Computing device and failure detection method thereof

Abstract

To provide a technique capable of detecting a failure without stopping normal operation of a computing device.SOLUTION: A computing device includes: a first register 21 in which input data for computation is held; a second register 22 in which input data for failure detection is held; a third register 23 in which comparison data for failure detection is held; a fourth register 24 in which computation result data for failure detection of a computation unit that is a failure detection target among a plurality of computation units is held; and a comparator 32 that compares the comparison data for failure detection with the computation result data for failure detection. A control circuit inputs the input data for computation from the first register to the computation unit selected from among the plurality of computation units on the basis of an instruction, and inputs the input data for failure detection from the second register to the computation unit that is the failure detection target from among the unselected computation units.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a computing device and a fault detection method therefor. [Background technology]

[0002] The arithmetic device includes an arithmetic circuit in which a plurality of arithmetic units are arranged, and a control circuit that controls the operation of each of the arithmetic units included in the arithmetic circuit. The control circuit inputs arithmetic input data to the arithmetic units based on instructions, causing them to perform arithmetic operations.

[0003] In order to meet high reliability and safety standards, a technology for detecting faults in multiple arithmetic units included in an arithmetic circuit is required. For example, as disclosed in Patent Document 1, a technology is known in which a test signal is input to an arithmetic circuit that is the target of fault detection, causing the circuit to execute an operation, and determining whether the operation result matches an expected value to detect a fault in the arithmetic circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-26647 Summary of the Invention [Problem to be solved by the invention]

[0005] The conventional technology has a problem in that normal operation is stopped during the test mode. This specification provides a technology that can perform fault detection without stopping the normal operation of the arithmetic device. [Means for solving the problem]

[0006] The arithmetic device (1, 2) disclosed in this specification may include an arithmetic circuit (12) in which a plurality of arithmetic units (12 a) are arranged, a control circuit (14) that controls the operation of each of the plurality of arithmetic units included in the arithmetic circuit, an instruction buffer (18) that stores instructions, a first register (21) that holds input data for arithmetic, a second register (22) that holds input data for fault detection, a third register (23) that holds comparison data for fault detection, a fourth register (24) that holds calculation result data for fault detection of a arithmetic unit that is a target of fault detection among the plurality of arithmetic units, and a comparator (32) that compares the comparison data for fault detection held in the third register with the calculation result data for fault detection held in the fourth register. The control circuit may be configured to input the calculation input data from the first register to a arithmetic unit selected from the plurality of arithmetic units based on an instruction, and to input the input data for fault detection from the second register to a arithmetic unit that is a target of fault detection among the non-selected arithmetic units.

[0007] In an arithmetic device, when an instruction is executed in a certain cycle, not all arithmetic units execute the operation, but an arithmetic unit selected from among the plurality of arithmetic units executes the instruction. Therefore, in a cycle in which an instruction is executed, there are arithmetic units that do not execute the instruction. In the above-mentioned arithmetic device, fault detection is performed on the arithmetic units that do not execute the instruction among the plurality of arithmetic units. Therefore, in the above-mentioned arithmetic device, fault detection can be performed without stopping normal operation of executing instructions.

[0008] This specification also discloses a fault detection method for an arithmetic device (1, 2) including an arithmetic circuit (12) in which a plurality of arithmetic units (12a) are arranged. This fault detection method may include the steps of inputting input data for calculation to an arithmetic unit selected from the plurality of arithmetic units based on an instruction, and inputting input data for fault detection to an arithmetic unit that is a target of fault detection from among the arithmetic units not selected, and comparing the calculation result of the arithmetic unit that is the target of fault detection with comparison data for fault detection. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an overview of a fault detection technique disclosed in this specification. [Figure 2] FIG. 1 is a diagram illustrating an outline of a configuration of a system-on-chip according to a first embodiment. [Figure 3] FIG. 10 is a diagram illustrating an outline of the configuration of a system-on-chip according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Before specifically describing the configuration of the arithmetic device of this embodiment, an overview of the fault detection technology disclosed in this specification will be provided. FIG. 1 illustrates four arithmetic units included in a arithmetic device. Time elapses from right to left on the page, and five cycles are shown in this example. In each cycle, an operation is performed based on an instruction. The hatched blocks indicate arithmetic units that perform an operation based on an instruction in that cycle. The unhatched blocks are arithmetic units that do not perform an operation based on an instruction in that cycle and are not operational based on a normal operation instruction. For example, in the first cycle, all four arithmetic units are operational, and in the second cycle, the first and second arithmetic units are operational, while the third and fourth arithmetic units are not operational. In this way, in a arithmetic device, not all arithmetic units are operational based on a normal operation instruction. As will be described later, in a arithmetic device such as an AI accelerator, the number of arithmetic units that operate based on a normal operation instruction may be approximately half of the multiple arithmetic units.

[0011] In the fault detection technology disclosed in this specification, fault detection is performed on non-operating computing units. For example, when detecting a fault in a third computing unit in a second cycle, the third computing unit is made to execute an operation identical to an operation executed by the second computing unit in a first cycle prior to the second cycle, and it is determined whether the result of the operation matches the result of the operation executed by the second computing unit in the first cycle. If the results do not match, a fault in at least one of the second computing unit and the third computing unit is suspected.

[0012] This fault detection technology can detect faults in arithmetic units that do not operate with normal operation instructions, so fault detection can be performed without stopping the normal operation of the arithmetic device. Below, we will explain a arithmetic device that embodies the above fault detection technology.

[0013] (First embodiment) Figure 2 shows an outline of the configuration of a system-on-chip. This system-on-chip includes a computing device 1 configured to perform massively parallel processing. The computing device 1 is not particularly limited, but may be, for example, an AI accelerator designed to perform high-speed neural network calculations.

[0014] The arithmetic unit 1 includes an arithmetic circuit 12 having an array of arithmetic units, a control circuit 14, a selector circuit 16, and an instruction buffer 18. The arithmetic circuit 12 includes a plurality of arithmetic units 12a, each capable of performing a sum-and-multiply operation. In this example, for clarity, only four arithmetic units 12a are shown in the arithmetic circuit 12. The control circuit 14 manages the overall processing of the arithmetic unit 1, including the processing sequence, data input / output, and the operation of each of the arithmetic units 12a included in the arithmetic circuit 12. The selector circuit 16 includes a plurality of selectors 16a, each of which corresponds to one of the arithmetic units 12a included in the arithmetic circuit 12. As described below, the selector circuit 16 selects one of the data held in a first register 21 and a second register 22 based on an instruction from the control circuit 14, and inputs the data to the arithmetic units 12a included in the arithmetic circuit 12. The instruction buffer 18 stores instructions to be executed by the arithmetic unit 1.

[0015] The arithmetic device 1 further includes a first register 21 , a second register 22 , a third register 23 , a fourth register 24 , a fifth register 25 , and a comparator 32 .

[0016] Input data for calculation corresponding to the instruction is held in the first register 21. The input data for calculation is transferred from the external memory 42 to the local memory 44 via DMA (Direct Memory Access), and then read from the local memory 44 and held in the first register 21.

[0017] The second register 22 holds input data for fault detection. In this example, the input data for fault detection is processed input data for operation that has been processed in the cycle before the fault is detected. That is, the input data for fault detection is data that is input from the first register 21 to the operation circuit 12 based on an instruction in the cycle before the fault is detected, and is also saved and held in the second register 22.

[0018] Fault detection comparison data is held in the third register 23. In this example, the fault detection comparison data is data resulting from the operation of the input data for operation performed by the arithmetic circuit 12 in the cycle before the fault is detected. That is, the fault detection comparison data is data that is saved in the third register 23 and held as a result of the operation of the input data for operation performed by the arithmetic circuit 12 based on an instruction in the cycle before the fault is detected. In other words, the fault detection comparison data is also data resulting from the operation of the input data for fault detection held in the second register 22 in the arithmetic circuit 12.

[0019] The fourth register 24 holds the calculation result data for fault detection of the calculation unit 12a that is the target of fault detection among the multiple calculation units 12a included in the arithmetic circuit 12. That is, the calculation result data for fault detection is data of the calculation result obtained by calculating the input data for fault detection held in the second register 22 by the calculation unit 12a that is the target of fault detection in the cycle of fault detection.

[0020] The fifth register 25 holds the result of an operation performed by the arithmetic circuit 12 based on an instruction. The data held in the fifth register 25 is written to the local memory 44 as needed, and then transferred to the external memory 42 via DMA.

[0021] The comparator 32 compares the fault detection comparison data held in the third register 23 with the fault detection calculation result data held in the fourth register 24. If the fault detection comparison data and the fault detection calculation result data do not match, the comparator 32 determines that a fault has been detected and notifies the outside of the comparator 32 of a fault detection signal.

[0022] The operation flow of the arithmetic device 1 will be described in detail below based on the function of the control circuit 14. First, the control circuit 14 retrieves an instruction stored in the instruction buffer 18. The control circuit 14 decodes the instruction and identifies an arithmetic unit 12a that executes an operation based on the instruction from among the multiple arithmetic units 12a included in the arithmetic circuit 12 (hereinafter referred to as an "arithmetic unit under normal operation"). The control circuit 14 further identifies an arithmetic unit 12a that is a target for fault detection from among the arithmetic units 12a that are under normal operation (hereinafter referred to as an "arithmetic unit under fault detection"). Note that the arithmetic units 12a that are the target for fault detection may be all arithmetic units 12a other than the arithmetic units 12a that are under normal operation, or may be some of the arithmetic units 12a other than the arithmetic units 12a that are under normal operation. Next, the control circuit 14 stores input data for operation required for executing the instruction in the first register 21. In addition, if the second register 22 does not store input data for fault detection, the control circuit 14 skips fault detection in this cycle, saves the input data for calculation from the first register 21 to the second register 22, and stores it as input data for fault detection.

[0023] Next, the control circuit 14 controls the selector circuit 16 to input the input data for calculation from the first register 21 to the arithmetic unit 12a subject to normal operation, and to input the input data for fault detection from the second register 22 to the arithmetic unit 12a subject to fault detection. The control circuit 14 causes the arithmetic unit 12a subject to normal operation to execute an operation corresponding to the input data for calculation, and causes the arithmetic unit 12a subject to fault detection to execute an operation corresponding to the input data for fault detection.

[0024] Next, the control circuit 14 stores the calculation result of the arithmetic unit 12a that is the target of normal operation in the fifth register 25, and stores the calculation result of the arithmetic unit 12a that is the target of fault detection in the fourth register 24. When the control circuit 14 skips fault detection in this cycle, that is, when it saves the input data for calculation in the second register 22, it saves the calculation result of the arithmetic unit 12a that is the target of normal operation in the third register 23 and stores it as comparison data for fault detection.

[0025] Next, the control circuit 14 compares the fault detection comparison data held in the third register 23 with the fault detection calculation result data held in the fourth register 24, and if the fault detection comparison data and the fault detection calculation result data do not match, it determines that a fault has been detected and notifies the outside of the control circuit 14 of a fault detection signal.

[0026] In this way, the calculation by the arithmetic unit 12a that is the target of normal operation and the calculation by the arithmetic unit 12a that is the target of failure are processed in parallel in the arithmetic device 1. Therefore, in the arithmetic device 1 described above, failure detection can be performed without stopping the normal operation of executing instructions.

[0027] (Second embodiment) An outline of the configuration of a system-on-chip of the modified example is shown in Fig. 3. Note that components that are essentially the same as those in the system-on-chip of Fig. 2 are given the same reference numerals, and their explanation will be omitted.

[0028] In the arithmetic unit 2 shown in FIG. 3, the fault detection input data held in the second register 22 and the fault detection comparison data held in the third register 23 are not data saved in the cycle before the fault is detected, but are predetermined data prepared in advance. The fault detection input data and the fault detection comparison data may be stored in the corresponding registers when the system-on-chip is started. In the example of the first embodiment, the fault detection input data depends on the instruction in the cycle before the fault is detected. On the other hand, in the example of the second embodiment, the fault detection input data can be prepared without depending on the instruction in the cycle before the fault is detected. Therefore, for example, by using data with a high fault detection rate, the accuracy of fault detection can be improved.

[0029] Although specific examples of the technology disclosed in this specification have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or in the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology exemplified in this specification or in the drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0030] 1, 2: arithmetic unit, 12: arithmetic circuit, 12a: arithmetic unit, 14: control circuit, 16: selector circuit, 16a: selector, 18: instruction buffer, 21: first register, 22: second register, 23: third register, 24: fourth register, 25: fifth register, 32: comparator

Claims

1. A computing device (1, 2), an arithmetic circuit (12) in which a plurality of arithmetic units (12a) are arranged; a control circuit (14) for controlling the operation of each of the plurality of arithmetic units included in the arithmetic circuit; an instruction buffer (18) in which instructions are stored; a first register (21) for holding input data for calculation; a second register (22) for holding input data for fault detection; a third register (23) for storing comparison data for fault detection; a fourth register (24) for holding failure detection calculation result data of a calculation unit that is a target of failure detection among the plurality of calculation units; a comparator (32) that compares the fault detection comparison data held in the third register with the fault detection operation result data held in the fourth register, the control circuit is configured to input the input data for operation from the first register to a computing unit selected from the plurality of computing units based on the instruction, and to input the input data for fault detection from the second register to a computing unit that is the target of fault detection from among the non-selected computing units.

2. the fault detection input data is the processed operation input data that has been processed in a cycle before the fault is detected, 2. The arithmetic device according to claim 1, wherein the fault detection comparison data is a result of arithmetic on the processed arithmetic input data.

3. 3. The arithmetic device according to claim 2, wherein the control circuit is configured to, when the fault detection input data is not stored in the second register, input the operation input data from the first register to an arithmetic unit selected from among the plurality of arithmetic units based on the instruction, store the operation input data in the second register as the fault detection input data, and further store a result of the operation of the selected arithmetic unit in the third register as the fault detection comparison data.

4. the fault detection input data is predetermined calculation input data, 2. The arithmetic device according to claim 1, wherein the fault detection comparison data is a result of arithmetic operation on predetermined arithmetic input data.

5. A fault detection method for an arithmetic device (1, 2) having an arithmetic circuit (12) in which a plurality of arithmetic units are arranged, comprising: a step of inputting input data for operation to a computing unit selected from the plurality of computing units based on an instruction, and inputting input data for fault detection to a computing unit that is a target of fault detection from among the non-selected computing units; a step of comparing a calculation result of the arithmetic unit that is the target of the fault detection with fault detection comparison data.

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