Semiconductor integrated circuit

Abstract

To provide a semiconductor integrated circuit which can be started up at a high speed.SOLUTION: A first transistor M1 is a PMOS transistor whose gate and drain are connected to each other and which is provided on a path of a constant current Ic1. A second transistor M2 is an NMOS transistor whose gate and source are connected to each other and which is provided on a path of a constant current. The first switch SW1 is connected between the gate of the first transistor M1 and the gate of the second transistor M2. A start-up circuit turns on the first switch SW1 for a predetermined time when a constant current circuit 200A is started up.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor integrated circuits. [Background technology]

[0002] In semiconductor integrated circuits, constant currents are used in various circuit blocks such as differential amplifiers, operational amplifiers, comparators, etc. Semiconductor integrated circuits are equipped with a reference current source (constant current circuit) that generates a reference current.

[0003] A current mirror circuit is used to generate constant current in multiple circuit blocks. Specifically, each circuit block is provided with an output transistor of the current mirror circuit. The gates of the multiple output transistors of the multiple circuit blocks are commonly connected to the gate of the current mirror circuit provided in the reference current source via wiring (called a gate bias line). As a result, the output transistor of each circuit block is provided with a gate bias voltage of the same level as that of the current mirror circuit of the reference current source, and a constant current proportional to the reference current flows through the output transistor.

[0004] The gate capacitance of the multiple MOS transistors that make up the current mirror circuit exists as parasitic capacitance on the gate bias line. This parasitic capacitance, along with the parasitic inductance and parasitic resistance of the gate bias line, forms a delay circuit. Therefore, when a semiconductor integrated circuit starts up, a non-negligible propagation delay occurs between the time when the gate bias voltage generated in the reference current source reaches the gates of the output transistors in the multiple circuit blocks. The propagation delay time increases as the gate wiring becomes longer and the number of circuit blocks increases. This means that the startup time of the semiconductor integrated circuit increases. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2023-73952 [Patent Document 2] Japanese Patent Application Publication No. 2017-62616 [Patent Document 3] Japanese Patent Application Laid-Open No. 2017-59056

[0006] [overview] The present disclosure has been made in light of such a situation, and one exemplary purpose of an embodiment thereof is to provide a semiconductor integrated circuit that can be started up quickly.

[0007] A semiconductor integrated circuit according to one embodiment of the present disclosure includes a constant current circuit that generates a constant current and outputs a P gate bias voltage and an N gate bias voltage, and a circuit block including a load transistor that is a P-channel Metal Oxide Semiconductor (PMOS) transistor that receives the P gate bias voltage at its gate, or a load transistor that is an NMOS transistor that receives the N gate bias voltage at its gate. The constant current circuit includes a first transistor that is a PMOS transistor with its gate and drain connected and located on the constant current path, a second transistor that is an NMOS transistor with its gate and source connected and located on the constant current path, a first switch whose gate is connected to the gate of the second transistor and connected between the gate of the first transistor and the gate of the second transistor, and a startup circuit that turns on the first switch for a predetermined time when the constant current circuit is started. The gate voltage of the first transistor is the P gate bias voltage, and the gate voltage of the second transistor is the N gate bias voltage.

[0008] Another embodiment of the present disclosure is also a semiconductor integrated circuit. The semiconductor integrated circuit includes a constant current circuit that generates a constant current and outputs a P gate bias voltage, and a circuit block including a load transistor that is a PMOS (P-channel Metal Oxide Semiconductor) transistor that receives the P gate bias voltage at its gate. The constant current circuit includes a first transistor that is a PMOS transistor and is provided on the constant current path with its gate and drain wired together, a first resistor and a second switch provided in series between the drain of the first transistor and a ground line, and a startup circuit that turns on the second switch for a predetermined time when the constant current circuit is started. The gate voltage of the first transistor is the P gate bias voltage.

[0009] Yet another embodiment of the present disclosure is also a semiconductor integrated circuit. This semiconductor integrated circuit includes a constant current circuit that generates a constant current and outputs a P gate bias voltage and an N gate bias voltage, and a circuit block including a load transistor that is an NMOS transistor that receives the N gate bias voltage at its gate. The constant current circuit includes a second transistor that is an NMOS transistor with its gate and source wired and arranged on the constant current path, a second resistor and a third switch arranged in series between the drain of the second transistor and a power supply line, and a startup circuit that turns on the third switch for a predetermined time when the constant current circuit is started. The gate voltage of the second transistor is the N gate bias voltage.

[0010] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc. are also valid aspects of the present invention. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram of a semiconductor integrated circuit according to a comparative technique. [Figure 2] FIG. 2 is a diagram illustrating the operation of the constant current circuit of FIG. [Figure 3]FIG. 3 is a circuit diagram of the semiconductor integrated circuit according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating the operation of the constant current circuit of FIG. [Figure 5] FIG. 5 is an equivalent circuit diagram of the constant current circuit when the first switch is on. [Figure 6] FIG. 6 is a circuit diagram of a modified example of the constant current circuit of FIG. [Figure 7] FIG. 7 is a circuit diagram of a constant current circuit according to the second embodiment. [Figure 8] FIG. 8 is an equivalent circuit diagram of the constant current circuit when the second switch is on. [Figure 9] FIG. 9 is a circuit diagram of a constant current circuit according to the third embodiment. [Figure 10] FIG. 10 is an equivalent circuit diagram of the constant current circuit when the third switch is on. [Figure 11] FIG. 11 is a circuit diagram showing an example of the configuration of the start-up circuit.

[0012] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not an exhaustive overview of all possible embodiments, nor does it limit essential elements of the embodiments. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0013] A semiconductor integrated circuit according to one embodiment includes a constant current circuit that generates a constant current and outputs a P gate bias voltage and an N gate bias voltage, and a circuit block including a load transistor that is a P-channel Metal Oxide Semiconductor (PMOS) transistor that receives the P gate bias voltage at its gate or an NMOS transistor that receives the N gate bias voltage at its gate. The constant current circuit includes a first transistor that is a PMOS transistor with its gate and drain connected and located on the path of the constant current, a second transistor that is an NMOS transistor with its gate and source connected and located on the path of the constant current, a first switch whose gate is connected to the gate of the second transistor and connected between the gate of the first transistor and the gate of the second transistor, and a startup circuit that turns on the first switch for a predetermined time when the constant current circuit is started. The gate voltage of the first transistor is the P gate bias voltage, and the gate voltage of the second transistor is the N gate bias voltage.

[0014] With this configuration, when the first switch is turned on during startup of the constant current circuit, the gate of the first transistor is shorted to the gate of the second transistor. In other words, the gate-source capacitance of the first transistor and the gate-source capacitance of the second transistor are connected in series between the power supply line and the ground line, and the current flowing through the first switch quickly charges the gate capacitance of the PMOS transistor and the gate capacitance of the NMOS transistor. This allows the operating points of the first and second transistors, i.e., the gate-source voltages, to transition to a stable point in a short time, shortening startup time.

[0015] In one embodiment, the constant current circuit may further include a reference current source that generates a reference current. The second transistor may be provided on a path of the reference current. The constant current circuit may further include a third transistor that is an NMOS transistor having a gate connected to the gate of the second transistor and a drain connected to the drain of the first transistor.

[0016] A semiconductor integrated circuit according to one embodiment includes a constant current circuit that generates a constant current and outputs a P-gate bias voltage, and a circuit block including a load transistor, which is a P-channel Metal Oxide Semiconductor (PMOS) transistor that receives the P-gate bias voltage at its gate. The constant current circuit includes a first transistor, which is a PMOS transistor and is provided on the path of the constant current, with its gate and drain wired together; a first resistor and a second switch provided in series between the drain of the first transistor and a ground line; and a startup circuit that turns on the second switch for a predetermined time when the constant current circuit is started. The gate voltage of the first transistor is the P-gate bias voltage.

[0017] With this configuration, when the constant current circuit starts up, the second switch is turned on, causing the pull-down path including the first resistor and the second switch to conduct and current to flow. This current charges the gate capacitance of the PMOS transistor, allowing the operating point of the first transistor, i.e., the gate-source voltage, to transition to a stable point in a short time, thereby shortening the startup time.

[0018] In one embodiment, the constant current circuit may further include a second transistor which is an NMOS transistor whose gate and source are connected and which is provided on the path of the constant current, and a third transistor which is an NMOS transistor whose gate is connected to the gate of the second transistor and whose drain is connected to the drain of the first transistor.

[0019] A semiconductor integrated circuit according to one embodiment includes a constant current circuit that generates a constant current and outputs a P gate bias voltage and an N gate bias voltage, and a circuit block including a load transistor, which is an NMOS transistor that receives the N gate bias voltage at its gate. The constant current circuit includes a second transistor, which is an NMOS transistor with its gate and source wired together and is provided on the path of the constant current, a second resistor and a third switch provided in series between the drain of the second transistor and a power supply line, and a startup circuit that turns on the third switch for a predetermined time when the constant current circuit is started. The gate voltage of the second transistor is the N gate bias voltage.

[0020] With this configuration, when the constant current circuit starts up, the third switch is turned on, causing the pull-up path including the second resistor and the third switch to conduct and current to flow. This current charges the gate capacitance of the NMOS transistor, allowing the operating point of the second transistor, i.e., the gate-source voltage, to transition to a stable point in a short time, thereby shortening the startup time.

[0021] In one embodiment, the constant current circuit may further include a first transistor which is a PMOS transistor whose gate and drain are connected and which is provided on the path of the constant current, and a third transistor which is an NMOS transistor whose gate is connected to the gate of the second transistor and whose drain is connected to the drain of the first transistor.

[0022] In one embodiment, the constant current circuit may further include a fourth transistor which is a PMOS transistor having a gate connected to the gate of the first transistor, and a fifth transistor which is an NMOS transistor having a gate connected to the gate of the second transistor and a drain connected to the drain of the fourth transistor.

[0023] In one embodiment, the constant current circuit may further include a sixth transistor which is an NMOS transistor having a gate connected to a gate of the second transistor and connected between the drain of the first transistor and the drain of the third transistor, and a seventh transistor which is an NMOS transistor having a gate-drain connection and connected between the drain of the fourth transistor and the drain of the fifth transistor.

[0024] In one embodiment, the constant current circuit may further include an eighth transistor which is a PMOS transistor having a gate connected to the gate of the first transistor and connected between the source of the first transistor and a power supply line, and a ninth transistor which is a PMOS transistor having a gate connected to the gate of the fourth transistor and connected between the source of the fourth transistor and a power supply line.

[0025] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0026] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0027] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0028] (Comparative Technology) First, with reference to FIG. 1, the basic configuration of a semiconductor integrated circuit equipped with a constant current circuit and the startup delay will be described.

[0029] 1 is a block diagram of a semiconductor integrated circuit 100R according to a comparative technique. The semiconductor integrated circuit 100R includes a constant current circuit 200R, one or more circuit blocks 110, and one or more circuit blocks 120. The circuit block 110 is provided on the power supply line 102 side and includes a current source CS1 that sources a constant current. The circuit block 120 is provided on the ground line 104 side and includes a current source CS2 that sinks a constant current.

[0030] The constant current circuit 200R and the multiple circuit blocks 110 are connected via a gate bias line 106. The constant current circuit 200R supplies a gate bias voltage Vbp to the current source CS1 of each circuit block 110. The constant current circuit 200R and the multiple circuit blocks 120 are connected via a gate bias line 108. The constant current circuit 200R supplies a gate bias voltage Vbn to the current source CS2 of each circuit block 120.

[0031] The constant current circuit 200R includes a reference current source 210 and an output stage 220. The reference current source 210 is connected to a power supply voltage V DD Reference current I that is independent of REF The configuration of the reference current source 210 is not particularly limited, and a known circuit can be used. The output stage 220 generates the reference current I REF The reference current I REF The gate bias voltages Vbp and Vbn are generated according to the

[0032] The output stage 220 includes a first transistor M1, which is a PMOS transistor, and a second transistor M2, which is an NMOS transistor. The gate and drain of the first transistor M1 are connected together, and a reference current I REFA gate bias line 106 is drawn from the gate of the first transistor M1, and the gate voltage of the first transistor M1 is the gate bias voltage Vbp.

[0033] The gate and drain of the second transistor M2 are connected, and a reference current I REF A gate bias line 108 is drawn from the gate of the second transistor M2, and the gate voltage of the second transistor M2 is the gate bias voltage Vbn.

[0034] The current source CS1 of the circuit block 110 includes a load transistor Mo1, which is a PMOS transistor. The first transistor M1 of the constant current circuit 200R and the multiple load transistors Mo1 form a current mirror circuit, and a current proportional to the constant current Ic1 flows through the multiple load transistors Mo1.

[0035] The current source CS2 of the circuit block 120 includes a load transistor Mo2, which is an NMOS transistor. The second transistor M2 of the constant current circuit 200R and the multiple load transistors Mo2 form a current mirror circuit, and a current proportional to the constant current Ic2 flows through the multiple load transistors Mo2.

[0036] The constant current circuit 200R can be switched between enabled and disabled in response to an enable signal EN, and is configured to be in an enabled state when the enable signal EN is asserted (high), and in a disabled state when the enable signal EN is negated (low). / indicates logical inversion.

[0037] To switch between the enabled state and the disabled state, the constant current circuit 200R is provided with a PMOS transistor Me1 and an NMOS transistor Me2. The PMOS transistor Me1 is connected between the power supply line 102 and the gate bias line 106. The NMOS transistor Me2 is connected between the gate bias line 108 and the ground line 104. The transistors Me1 and Me2 are on when the constant current circuit 200R is in the disabled state and off when it is in the enabled state.

[0038] The above is the configuration of the semiconductor integrated circuit 100R. Next, the startup of the semiconductor integrated circuit 100R will be described.

[0039] 2 is a diagram illustrating the operation of the constant current circuit 200R of FIG. 1. FIG. 2 shows the enable signal EN, the gate bias voltage Vbp, and the constant current Ic1. The power supply voltage V DD The potential difference between this and the gate bias voltage Vbp is the gate-source voltage V of the first transistor M1. GS is.

[0040] Before time t0, the constant current circuit 200R is in a disabled state. In the disabled state of the constant current circuit 200R, the gate bias voltage Vbp is DD Although not shown, the gate bias voltage Vbn is equal to the ground voltage V SS is equal to

[0041] At time t0, the enable signal EN is asserted. In order for the current sources CS1 and CS2 to generate constant currents of the designed values, the gate bias voltages Vbp and Vbn must transition to an appropriate voltage level Vop. However, the gate capacitance of the PMOS transistor connected to the gate bias line 106 prevents the gate bias voltage Vbp from transitioning quickly, resulting in a delay time τ1 before the voltage Vbp stabilizes at the target level Vop. Therefore, the constant current Ic1 flowing through the first transistor M1 and the constant current flowing through the load transistor Mo1 stabilize at time t1, after the delay time τ1 has elapsed since startup.

[0042] Similarly, the gate capacitance of the NMOS transistor connected to the gate bias line 108 prevents a high-speed transition of the gate bias voltage Vbn. Therefore, the constant current flowing through the load transistor Mo2 also stabilizes after a delay time has elapsed since the start of startup.

[0043] As described above, the semiconductor integrated circuit 100R of Fig. 1 has a problem of a long startup time. Next, a semiconductor integrated circuit according to an embodiment will be described.

[0044] (Embodiment 1) 3 is a circuit diagram of a semiconductor integrated circuit 100A according to embodiment 1. The semiconductor integrated circuit 100A includes circuit blocks 110 and 120 and a constant current circuit 200A.

[0045] The constant current circuit 200A includes a reference current source 210, an output stage 220A, and a start-up circuit 230.

[0046] Reference current source 210, reference current I REF The output stage 220A includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a first switch SW1.

[0047] The gate and drain of the first transistor M1 are connected, and a reference current I REF The gate and drain of the second transistor M2 are connected together, and the reference current I REF In this example, Ic2=I REF The third transistor M3 forms a current mirror circuit together with the second transistor M2, and the reference current I REF This means that the first transistor M1 also receives the reference current I REF The same amount of current flows.

[0048] The fourth transistor M4 forms a current mirror circuit together with the first transistor M1, and the fifth transistor M5 forms a current mirror circuit together with the second transistor M1. Note that the fourth transistor M4 and the fifth transistor M5 may be omitted.

[0049] The first switch SW1 is connected between the gate of the first transistor M1 and the gate of the second transistor M2. The first switch SW1 may be configured with a PMOS transistor, an NMOS transistor, or a CMOS switch.

[0050] The constant current circuit 200A can be switched between enabled and disabled in response to an enable signal EN, and is configured to be in an enabled state when the enable signal EN is asserted (high), and in a disabled state when the enable signal EN is negated (low). / indicates logical inversion.

[0051] To switch between an enabled state and a disabled state, the constant current circuit 200A is provided with PMOS transistors Me1 and Me3 and an NMOS transistor Me2. The PMOS transistor Me1 is connected between the power supply line 102 and the gate bias line 106. The NMOS transistor Me2 is connected between the gate bias line 108 and the ground line 104. The transistor Me3 is provided between the output of the reference current source 210 and the second transistor M2.

[0052] The transistors Me1 and Me2 are on when the constant current circuit 200A is disabled and off when it is enabled, while the transistor Me3 is off when the constant current circuit 200A is disabled and on when it is enabled.

[0053] When the constant current circuit 200A is started, the start-up circuit 230 turns on the first switch SW1 for a predetermined time Δt. Specifically, in response to the assertion of the enable signal EN, the start-up circuit 230 generates a start pulse START that remains at a predetermined level for the predetermined time Δt. The first switch SW1 remains on while the start pulse START remains at the predetermined level, and then turns off.

[0054] The above is the configuration of the constant current circuit 200A. Next, the operation of the constant current circuit 200A will be described.

[0055] Fig. 4 is a diagram for explaining the operation of the constant current circuit 200A of Fig. 3. Fig. 4 shows an enable signal EN, a start pulse START, a gate bias voltage Vbp, and a constant current Ic1.

[0056] Before time t0, the device is in a disabled state, and the gate bias voltage Vbp is equal to the power supply voltage V DD is equal to.

[0057] At time t0, the enable signal EN is asserted. In response to the assertion of the enable signal EN, the start pulse START goes high, turning on the first switch SW1.

[0058] FIG. 5 is an equivalent circuit diagram of the constant current circuit 200A when the first switch SW1 is on. GS1 represents the combined capacitance of the gate-source capacitances of the multiple PMOS transistors connected to the gate bias line 106, and C GS2 represents the combined capacitance of the gate-source capacitances of the multiple NMOS transistors connected to the gate bias line 108.

[0059] When the first switch SW1 is turned on, the gate of the first transistor M1 and the gate of the second transistor M2 are shorted. That is, a gate-source capacitance C GS1 and the gate-source capacitance C of the NMOS transistor GS2 are connected in series to form a capacitive voltage divider circuit.

[0060] Immediately after startup, two capacities C GS1 ,C GS2 Assuming that the law of conservation of charge holds between the two capacitances C GS1 ,C GS2 The voltages at the connection nodes of these, i.e., the gate bias voltages Vbp and Vbn, are V DD ×C GS1 / (C GS1 +C GS2 ) It changes sharply towards

[0061] Returning to Figure 4, the gate bias voltage Vbp drops sharply due to the short circuit between the gates of the first transistor M1 and the second transistor M2. As a result, the PMOS transistor turns on and drain current flows. When the first switch SW1 turns off, the gate capacitance C GS1 is discharged by the drain current of the PMOS transistor, and the gate bias voltage Vbp approaches the optimum voltage level Vop. Then, at time t2, after the delay time τ2 has elapsed since the start of startup, the gate bias voltage Vbp stabilizes at the optimum voltage level Vop.

[0062] In the constant current circuit 200A of FIG. 3, by optimizing the pulse width of the start pulse START, the delay time τ2 can be significantly reduced compared to the delay time τ1 in the constant current circuit 200R of FIG.

[0063] The delay time until the gate bias voltage Vbn is stabilized can also be reduced in the same way.

[0064] Fig. 6 is a circuit diagram of a modified example (200Aa) of the constant current circuit 200A of Fig. 3. In this modified example, the PMOS transistor and the NMOS transistor are cascode-connected in two stages.

[0065] In the circuit block 110a, the current source CS1 is configured by cascode connection of two stages of PMOS transistors Mo1a and Mo1b.

[0066] The output stage 220Aa further includes a sixth transistor M6 and a seventh transistor M7 which are NMOS transistors, and an eighth transistor M8 and a ninth transistor M9 which are PMOS transistors.

[0067] The first switch SW1 is configured as a CMOS switch (also called an analog switch or a transfer gate).

[0068] This modification also makes it possible to reduce the startup time, similar to the constant current circuit 200A of FIG.

[0069] To verify the effectiveness of the technology disclosed herein, a design tool was used to simulate the startup time of the constant current circuit 200Aa. Operation was verified by first fixing the first switch SW1 to OFF during startup. This is equivalent to the constant current circuit 200R in FIG. 1, and the startup time τ1 was 25 μs.

[0070] When the on-time of the first switch SW1 was optimized for the constant current circuit 200Aa in Figure 6, the start-up time τ2 was reduced to 2.2 μs, which is less than 1 / 10 of that of the comparative technology, demonstrating that extremely fast start-up is possible.

[0071] (Embodiment 2) 7 is a circuit diagram of a constant current circuit 200B according to the second embodiment. The output stage 220B includes a second switch SW2 and a first resistor R1 instead of the first switch SW1 in FIG. 3. The second switch SW2 and the first resistor R1 are connected in series to the gate of the first transistor M1, in other words, between the gate bias line 106 and the ground line 104. At startup, the second switch SW2 is on while the start pulse START is at a predetermined level (for example, high).

[0072] The transistors M5, M7, M4, and M9 can be omitted. As shown in FIG. 3, the NMOS transistor and the PMOS transistor may be configured in one stage.

[0073] The above is the configuration of the constant current circuit 200B. Next, the operation of the constant current circuit 200B will be described.

[0074] FIG. 8 is an equivalent circuit diagram of the constant current circuit 200B when the second switch SW2 is on. GS1 represents the combined capacitance of the gate-source capacitances of the multiple PMOS transistors connected to the gate bias line 106. When the second switch SW2 is on, the pull-down path 222 including the first resistor R1 and the second switch SW2 is conductive, and a current I CHG This current I CHG By this, the gate capacitance C GS1 is charged, the gate bias voltage Vbp can be transitioned to a stable point in a short time, and the start-up time can be shortened.

[0075] (Embodiment 3) 9 is a circuit diagram of a constant current circuit 200C according to a third embodiment. An output stage 220C includes a third switch SW3 and a second resistor R2 instead of the first switch SW1 in FIG. 3. The third switch SW3 and the second resistor R2 are connected in series to the gate of the second transistor M2, in other words, between the gate bias line 108 and the power supply line 102. At startup, the third switch SW3 is on while the start pulse START is at a predetermined level (for example, high).

[0076] The transistors M5, M7, M4, and M9 can be omitted. Furthermore, the transistors M3, M6, M1, and M8 can also be omitted. Furthermore, as shown in FIG. 3, the NMOS transistors and PMOS transistors may be configured in a single stage.

[0077] The above is the configuration of the constant current circuit 200B. Next, the operation of the constant current circuit 200B will be described.

[0078] FIG. 10 is an equivalent circuit diagram of the constant current circuit 200C when the third switch SW3 is on. GS2represents the combined capacitance of the gate-source capacitances of the multiple NMOS transistors connected to the gate bias line 108. When the third switch SW3 is on, the pull-up path 224 including the second resistor R2 and the third switch SW3 is conductive, and a current I CHG This current I CHG By this, the gate capacitance C GS2 is charged, the gate bias voltage Vbn can be transitioned to a stable point in a short time, and the start-up time can be shortened.

[0079] 11 is a circuit diagram showing an example configuration of the start-up circuit 230. The start-up circuit 230 includes inverters 232, 234, and 236, a low-pass filter 238, and a NOR gate 239. The inverter 232 inverts the enable signal EN. The low-pass filter 238 removes high-frequency components from the enable signal / EN inverted by the inverter 232, smoothing the waveform. The inverter 234 converts the output of the low-pass filter 238 into a binary signal. The output ENd of the inverter 234 is a signal obtained by delaying the positive edge of the enable signal EN. The inverter 236 inverts the enable signal EN. The NOR gate 239 takes a NOR of the output ENd of the inverter 234 and the output / EN of the inverter 236, and outputs the result as a start pulse START.

[0080] The configuration of the start-up circuit 230 is not limited to that shown in FIG. 11, and any known circuit such as a one-shot multivibrator circuit can be used.

[0081] The embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of the respective components and the respective treatment processes, and that such modifications are also within the scope of the present disclosure and the present invention. Such modifications will be described below.

[0082] The embodiments described using specific terms merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the spirit of the present invention as defined in the claims.

[0083] (Addendum) The present specification discloses the following techniques.

[0084] (Item 1) a constant current circuit that generates a constant current and outputs a P gate bias voltage and an N gate bias voltage; a circuit block including a load transistor, which is a PMOS (P-channel Metal Oxide Semiconductor) transistor receiving the P gate bias voltage at its gate, or a load transistor, which is an NMOS (N-channel Metal Oxide Semiconductor) transistor receiving the N gate bias voltage at its gate; Equipped with The constant current circuit is a first transistor, which is a PMOS transistor and has a gate and a drain connected together and is provided on a path of the constant current; a second transistor, which is an NMOS transistor whose gate and source are connected and which is provided on a path of the constant current; a first switch connected between the gate of the first transistor and the gate of the second transistor; a start-up circuit that turns on the first switch for a predetermined time when the constant current circuit is started; Including, the gate voltage of the first transistor is the P gate bias voltage; a gate voltage of the second transistor being the N gate bias voltage.

[0085] (Item 2) the constant current circuit further includes a reference current source that generates a reference current; the second transistor is provided on a path of the reference current; Item 1. The semiconductor integrated circuit of item 1, further comprising a third transistor that is an NMOS transistor having a gate connected to the gate of the second transistor and a drain connected to the drain of the first transistor.

[0086] (Item 3) a constant current circuit that generates a constant current and outputs a P gate bias voltage; a circuit block including a load transistor, which is a PMOS (P-channel Metal Oxide Semiconductor) transistor receiving the P gate bias voltage at its gate; Equipped with The constant current circuit is a first transistor, which is a PMOS transistor and is provided on the path of the constant current, with its gate and drain connected; a first resistor and a second switch connected in series between the drain of the first transistor and a ground line; a start-up circuit that turns on the second switch for a predetermined time when the constant current circuit is started; Including, a gate voltage of the first transistor being the P gate bias voltage;

[0087] (Item 4) The constant current circuit is a second transistor, which is an NMOS (N-channel Metal Oxide Semiconductor) transistor, whose gate and source are connected and which is provided on the path of the constant current; a third transistor, which is an NMOS transistor, the gate of which is connected to the gate of the second transistor and the drain of which is connected to the drain of the first transistor; Item 4. The semiconductor integrated circuit according to item 3, further comprising:

[0088] (Item 5) a constant current circuit that generates a constant current and outputs a P gate bias voltage and an N gate bias voltage; a circuit block including a load transistor, which is an NMOS transistor receiving the N gate bias voltage at its gate; Equipped with The constant current circuit is a second transistor, which is an NMOS transistor whose gate and source are connected and which is provided on a path of the constant current; a second resistor and a third switch connected in series between the drain of the second transistor and a power supply line; a start-up circuit that turns on the third switch for a predetermined time when the constant current circuit is started; Including, a gate voltage of the second transistor being the N gate bias voltage.

[0089] (Item 6) The constant current circuit is a first transistor, which is a PMOS transistor and has a gate and a drain connected together and is provided on a path of the constant current; a third transistor, which is an NMOS transistor, the gate of which is connected to the gate of the second transistor and the drain of which is connected to the drain of the first transistor; Item 6. The semiconductor integrated circuit according to item 5, further comprising:

[0090] (Item 7) The constant current circuit is a fourth transistor which is a PMOS transistor whose gate is connected to the gate of the first transistor; a fifth transistor, which is an NMOS transistor having a gate connected to the gate of the second transistor and a drain connected to the drain of the fourth transistor; Item 7. The semiconductor integrated circuit according to any one of items 2, 4, and 6, further comprising:

[0091] (Item 8) The constant current circuit is a sixth transistor, which is an NMOS transistor, the gate of which is connected to the gate of the second transistor and is connected between the drain of the first transistor and the drain of the third transistor; a seventh transistor, which is an NMOS transistor whose gate and drain are connected together and connected between the drain of the fourth transistor and the drain of the fifth transistor; 8. The semiconductor integrated circuit according to item 7, further comprising:

[0092] (Item 9) The constant current circuit is an eighth transistor, which is a PMOS transistor and has a gate connected to the gate of the first transistor and is connected between the source of the first transistor and a power supply line; a ninth transistor, which is a PMOS transistor and has a gate connected to the gate of the fourth transistor and is connected between the source of the fourth transistor and a power supply line; 8. The semiconductor integrated circuit according to item 7, further comprising:

[0093] (Item 10) The startup circuit an enable signal; a first inverter that inverts the enable signal; a low-pass filter that receives the output of the first inverter; a second inverter that inverts the output of the low-pass filter; a third inverter that inverts the enable signal; a logic gate that generates a NOR of the output of the first inverter and the output of the third inverter; 10. The semiconductor integrated circuit according to any one of items 1 to 9, comprising: [Explanation of symbols]

[0094] 100...semiconductor integrated circuit, 110, 120...circuit block, CS1, CS2...current source, 200...constant current circuit, 210...reference current source, 220...output stage, 230...start-up circuit, M1...first transistor, M2...second transistor, M3...third transistor, M4...fourth transistor, M5...fifth transistor, M6...sixth transistor, M7...seventh transistor, M8...eighth transistor, SW1...first switch, SW2...second switch, SW3...third switch, R1...first resistor, R2...second resistor, 102...power supply line, 104...ground line, 106, 108...gate bias lines.

Claims

1. a constant current circuit that generates a constant current and outputs a P gate bias voltage and an N gate bias voltage; a circuit block including a load transistor which is a PMOS (P-channel Metal Oxide Semiconductor) transistor receiving the P gate bias voltage at its gate, or a load transistor which is an NMOS (N-channel Metal Oxide Semiconductor) transistor receiving the N gate bias voltage at its gate; Equipped with The constant current circuit is a first transistor, which is a PMOS transistor and has a gate and a drain connected together and is provided on a path of the constant current; a second transistor, which is an NMOS transistor and has its gate and source connected together and is provided on a path of the constant current; a first switch connected between the gate of the first transistor and the gate of the second transistor; a start-up circuit that turns on the first switch for a predetermined time when the constant current circuit is started; Including, the gate voltage of the first transistor is the P gate bias voltage; a gate voltage of the second transistor being the N gate bias voltage;

2. the constant current circuit further includes a reference current source that generates a reference current; the second transistor is provided on a path of the reference current; 2. The semiconductor integrated circuit according to claim 1, further comprising a third transistor which is an NMOS transistor having a gate connected to the gate of said second transistor and a drain connected to the drain of said first transistor.

3. a constant current circuit that generates a constant current and outputs a P gate bias voltage; a circuit block including a load transistor, which is a PMOS (P-channel Metal Oxide Semiconductor) transistor receiving the P gate bias voltage at its gate; Equipped with The constant current circuit is a first transistor, which is a PMOS transistor and is provided on a path of the constant current, the first transistor having a gate and a drain connected together; a first resistor and a second switch connected in series between the drain of the first transistor and a ground line; a start-up circuit that turns on the second switch for a predetermined time when the constant current circuit is started; Including, a gate voltage of the first transistor being the P gate bias voltage;

4. The constant current circuit is a second transistor, which is an NMOS (N-channel Metal Oxide Semiconductor) transistor, whose gate and source are connected and which is provided on the path of the constant current; a third transistor, which is an NMOS transistor, having a gate connected to the gate of the second transistor and a drain connected to the drain of the first transistor; The semiconductor integrated circuit according to claim 3 , further comprising:

5. a constant current circuit that generates a constant current and outputs a P gate bias voltage and an N gate bias voltage; a circuit block including a load transistor, which is an NMOS transistor receiving the N gate bias voltage at its gate; Equipped with The constant current circuit is a second transistor, which is an NMOS transistor and has its gate and source connected together and is provided on a path of the constant current; a second resistor and a third switch connected in series between the drain of the second transistor and a power supply line; a start-up circuit that turns on the third switch for a predetermined time when the constant current circuit is started; Including, a gate voltage of the second transistor being the N gate bias voltage;

6. The constant current circuit is a first transistor, which is a PMOS transistor and has a gate and a drain connected together and is provided on a path of the constant current; a third transistor, which is an NMOS transistor, having a gate connected to the gate of the second transistor and a drain connected to the drain of the first transistor; The semiconductor integrated circuit according to claim 5 , further comprising:

7. The constant current circuit is a fourth transistor which is a PMOS transistor having a gate connected to the gate of the first transistor; a fifth transistor which is an NMOS transistor having a gate connected to the gate of the second transistor and a drain connected to the drain of the fourth transistor; 7. The semiconductor integrated circuit according to claim 2, further comprising:

8. The constant current circuit is a sixth transistor, which is an NMOS transistor, the gate of which is connected to the gate of the second transistor and which is connected between the drain of the first transistor and the drain of the third transistor; a seventh transistor, which is an NMOS transistor whose gate and drain are connected together and connected between the drain of the fourth transistor and the drain of the fifth transistor; The semiconductor integrated circuit according to claim 7 , further comprising:

9. The constant current circuit is an eighth transistor, which is a PMOS transistor, the gate of which is connected to the gate of the first transistor and which is connected between the source of the first transistor and a power supply line; a ninth transistor, which is a PMOS transistor and has a gate connected to the gate of the fourth transistor and is connected between the source of the fourth transistor and a power supply line; The semiconductor integrated circuit according to claim 7 , further comprising:

10. The startup circuit an enable signal; a first inverter that inverts the enable signal; a low-pass filter receiving an output of the first inverter; a second inverter that inverts the output of the low-pass filter; a third inverter that inverts the enable signal; a logic gate that generates a NOR of the output of the first inverter and the output of the third inverter; 7. The semiconductor integrated circuit according to claim 1, comprising:

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