A high-gain low-noise amplifier with transient overshoot optimization

Abstract

The application discloses a high-gain low-noise amplifier with transient overshoot optimization, which comprises a first low-noise amplification unit, a second low-noise amplification unit and a control unit, or comprises the first low-noise amplification unit or the second low-noise amplification unit and the control unit; the control unit is used for controlling the first low-noise amplification unit and the second low-noise amplification unit to be turned on and turned off; the first low-noise amplification unit is connected with the second low-noise amplification unit through a matching unit; and the application solves the problem of transient overshoot caused by the low-noise amplifier when being turned on or turned off.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of low noise amplifiers, and particularly relates to a high-gain low noise amplifier with transient overshoot optimization. BACKGROUND

[0002] The traditional current multiplexing low noise amplifier is composed of two common source stage radio frequency tubes, and a choke inductance is added between the common source tube and the common gate tube on the basis of the traditional cascode structure, and the signal at the drain of the input tube is coupled to the gate of the output tube through a capacitor. Therefore, for the direct current path, the two-stage common source tubes share the bias current, which can effectively reduce the power consumption compared with the two-stage common source tube amplification; for the alternating current path, the two-stage common source tube amplification can effectively improve the gain. However, due to the existence of the inter-stage choke inductance, the Miller effect suppression, high output impedance, high reverse isolation and other characteristics of the original cascode structure are invalid, which increases the reflected signal from the output end to the input end, resulting in potential instability of the circuit. For the low noise amplifier applied to 2G / 3G / 3G / 5G base station communication and WIFI communication, the opening and closing switching process (Power Down) of the amplifier needs to be performed at the gate of the output tube, at which time the output waveform will have an overshoot phenomenon. SUMMARY

[0003] In view of the above problems in the prior art, the present application provides a high-gain low noise amplifier with transient overshoot optimization, which solves the problem of transient overshoot caused by the opening or closing of the low noise amplifier.

[0004] In order to achieve the above-mentioned application purposes, the technical scheme adopted by the present application is as follows: a high-gain low noise amplifier with transient overshoot optimization, comprising: a first low noise amplification unit, a second low noise amplification unit and a control unit, or comprising: a first low noise amplification unit or a second low noise amplification unit, and a control unit.

[0005] The control unit is used for controlling the opening and closing of the first low noise amplification unit and the second low noise amplification unit; and the first low noise amplification unit and the second low noise amplification unit are connected through a matching unit.

[0006] Further, the first low noise amplification unit comprises: an inductor L g1 , a grounded inductor L S1 , a field effect tube M1, a capacitor C2, a capacitor C C1 , an inductor L d1 , a grounded capacitor C3, a resistor R1, a field effect tube M2, a resistor R2, a capacitor C4, an inductor L1, an inductor L2, a resistor R b3 , a grounded capacitor C P1 , a resistor R P1 , a resistor Rb1 and ground resistance R b2 ;

[0007] The source of the field effect transistor M1 is connected with the ground inductance L S1 , the gate is connected with one end of the inductance L g1 and one end of the resistance R1 respectively, and the drain is connected with one end of the capacitor C2, one end of the capacitor C C1 and one end of the inductance L d1 respectively; the other end of the resistance R1 is connected with the other end of the capacitor C2 and serves as a bias voltage terminal VB1; the source of the field effect transistor M2 is connected with the ground capacitor C3 and the other end of the inductance L d1 respectively, the gate is connected with one end of the resistance R2, one end of the resistance R b3 and the other end of the capacitor C C1 respectively, and the drain is connected with one end of the inductance L1; the other end of the resistance R b3 is connected with one end of the resistance R P1 , one end of the resistance R b1 and the ground resistance R b2 respectively and serves as a controlled terminal SD1; the other end of the resistance R P1 is connected with the ground capacitor C P1 ; the other end of the resistance R b1 is connected with one end of the inductance L2 and serves as a power supply terminal; the other end of the inductance L2 is connected with one end of the capacitor C4 and one end of the inductance L1 respectively and serves as an output terminal of the first low noise amplification unit; the other end of the capacitor C4 is connected with the other end of the resistance R2; the other end of the inductance L g1 serves as an input terminal of the first low noise amplification unit.

[0008] Further, the second low noise amplification unit comprises: a resistance R3, a capacitor C7, a field effect transistor M3, a ground inductance L S2 , a capacitor C C2 , an inductance L d2 , a ground capacitor C8, a field effect transistor M4, a resistance R b6 , a ground capacitor C p2 , a resistance R P2 , a ground resistance R b5 , a resistance R b4 and an inductance L4;

[0009] The source of the field effect transistor M3 is connected with the ground inductance L S2 , the gate is connected with one end of the resistance R3 and serves as an input terminal of the second low noise amplification unit; the drain of the field effect transistor M3 is connected with one end of the capacitor C7, one end of the inductance L d2 and the capacitor C C2One end of the resistor R3 is connected to the other end of the capacitor C7, and serves as the bias voltage terminal VB2; the source of the field-effect transistor M4 is connected to the ground capacitor C8 and the inductor L, respectively. d2 The other end is connected, and its gate is connected to capacitor C. C2 The other end and resistor R b6 One end of the resistor is connected to the inductor L4, and its drain is connected to one end of the inductor L4, serving as the output of the second low-noise amplifier unit; the resistor R b6 The other end is connected to resistor R respectively P2 One end, grounding resistance R b5 and resistance R b4 One end is connected and serves as the controlled terminal SD2; the resistor R b4 The other end is connected to the other end of inductor L4 and serves as the power supply terminal; the resistor R p2 The other end is connected to the grounding capacitor C p2 connect.

[0010] Furthermore, the control unit includes: a resistor R P3 Resistance R P4 Grounding resistance R P5 Resistance R P6 Resistance R P7 Resistance R P8 MOSFET M P1 MOSFET M P2 MOSFET M P3 MOSFET M P4 and field-effect transistor M P5 ;

[0011] The resistor R P3 One end is used as the level input terminal Vpd, and the other end is connected to the resistor R. P4 One end and grounding resistance R P5 Connection; the field-effect transistor M P1 Gate and resistor R P4 The other end is connected, its source is grounded, and its drain is connected to the field-effect transistor M. P2 Gate, field-effect transistor M P4 Gate and resistor R P6 One end is connected; the field-effect transistor M P2 The source is grounded, and its drain is respectively the field-effect transistor M P3 Gate and resistor R P7 One end is connected; the field-effect transistor M P3 The source of the field-effect transistor is grounded, and its drain is used as the control terminal SD1; the field-effect transistor M P4 The source is grounded, and its drain is connected to the field-effect transistor M. P5 Gate and resistor R P8one end of the resistor R P5 grounded, and its drain as a control end SD2; the resistor R P6 the other end of the resistor R P7 the other end of the resistor R P8 the other end of the resistor R

[0012] In summary, the beneficial effects of the present application are: the present application aims at the output signal wave overshoot problem of the existing low noise amplifier when it is turned on or turned off, and proposes to add RC series to ground circuit at voltage switching, to optimize the conduction state of the field effect tube through the RC circuit, and solve the problem of output waveform overshoot of the low noise amplifier during the turning on and turning off process. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 it is a circuit diagram of a high-gain low-noise amplifier with transient overshoot optimization;

[0014] Figure 2 it is a circuit diagram of a control unit;

[0015] Figure 3 it is a 0dBm transient output waveform diagram of the low-noise amplifier when the single-stage LNA1 works with the absence of the resistor R p1 and the capacitor C p1 ;

[0016] Figure 4 it is a 0dBm transient output waveform diagram of the low-noise amplifier of the present application when the single-stage LNA1 works;

[0017] Figure 5 it is a 0dBm transient output waveform diagram of the low-noise amplifier when the two-stage LNA1+LNA2 works with the absence of the resistor R p1 , the capacitor C p1 , the resistor R p2 and the capacitor C p2 ;

[0018] Figure 6 it is a 0dBm transient output waveform diagram of the low-noise amplifier of the two-stage LNA1+LNA2 when it works;

[0019] Figure 7 it is a gain diagram of the low-noise amplifier when the single-stage LNA1 is adopted in the present application;

[0020] Figure 8 it is a gain diagram of the low-noise amplifier when the two-stage LNA1+LNA2 is adopted in the present application. DETAILED DESCRIPTION

[0021] The specific embodiments of the present application are described below to enable those skilled in the art to understand the present application, but it should be clear that the present application is not limited to the scope of the specific embodiments, and that all the inventions utilizing the concept of the present application are within the scope of the present application as defined in the appended claims, which are obvious to those skilled in the art, as long as various changes are within the spirit and scope of the present application.

[0022] As shown in Figure 1 , a high-gain low-noise amplifier with transient overshoot optimization includes: a first low-noise amplification unit (LAN1), a second low-noise amplification unit (LAN2), and a control unit, or includes: a first low-noise amplification unit (LAN1) or a second low-noise amplification unit (LAN2), and a control unit.

[0023] The control unit is used to control the first low-noise amplification unit (LAN1) and the second low-noise amplification unit (LAN2) to turn on and turn off; the first low-noise amplification unit (LAN1) and the second low-noise amplification unit (LAN2) are connected through a matching unit.

[0024] The first low-noise amplification unit (LAN1) includes: an inductor L g1 , a ground inductor L S1 , a field effect transistor M1, a capacitor C2, a capacitor C C1 , an inductor L d1 , a ground capacitor C3, a resistor R1, a field effect transistor M2, a resistor R2, a capacitor C4, an inductor L1, an inductor L2, a resistor R b3 , a ground capacitor C P1 , a resistor R P1 , a resistor R b1 , and a ground resistor R b2 .

[0025] The source of the field effect transistor M1 is connected with the ground inductor L S1 , the gate is connected with one end of the inductor L g1 and one end of the resistor R1 respectively, and the drain is connected with one end of the capacitor C2, one end of the capacitor C C1 , and one end of the inductor L d1 respectively; the other end of the resistor R1 is connected with the other end of the capacitor C2, and serves as a bias voltage end VB1; the source of the field effect transistor M2 is connected with the ground capacitor C3 and the other end of the inductor L d1 respectively, the gate is connected with one end of the resistor R2, one end of the resistor R b3 , and the other end of the capacitor C C1 respectively, and the drain is connected with one end of the inductor L1; the other end of the resistor R b3 is connected with the other end of the resistor R P1one end of the resistor R b1 one end of the resistor R b2 is connected, and serves as a controlled end SD1; the resistor R P1 the other end of the resistor R P1 is connected; the other end of the resistor R b1 is connected to one end of the inductor L2, and serves as a power supply end; the other end of the inductor L2 is connected to one end of the capacitor C4 and one end of the inductor L1 respectively, and serves as an output end of the first low noise amplification unit (LAN1); the other end of the capacitor C4 is connected to the other end of the resistor R2; the other end of the inductor L g1 serves as an input end of the first low noise amplification unit (LAN1).

[0026] The first low noise amplification unit (LAN1) adds the resistor R1 and the capacitor C2 between the gate and the drain of the field effect transistor M1 for realizing wideband matching of the input end, and adds the resistor R2 and the capacitor C4 between the gate and the drain of the field effect transistor M2 for realizing bandwidth matching of the output end.

[0027] The second low noise amplification unit (LAN2) comprises: a resistor R3, a capacitor C7, a field effect transistor M3, a grounded inductor L S2 , a capacitor C C2 , an inductor L d2 , a grounded capacitor C8, a field effect transistor M4, a resistor R b6 , a grounded capacitor C p2 , a resistor R P2 , a grounded resistor R b5 , a resistor R b4 and an inductor L4.

[0028] The source of the field effect transistor M3 is connected to the grounded inductor L S2 , the gate of which is connected to one end of the resistor R3, and serves as an input end of the second low noise amplification unit (LAN2); the drain of the field effect transistor M3 is connected to one end of the capacitor C7, one end of the inductor L d2 and one end of the capacitor C C2 respectively; the other end of the resistor R3 is connected to the other end of the capacitor C7, and serves as a bias voltage end VB2; the source of the field effect transistor M4 is connected to the other end of the grounded capacitor C8 and the other end of the inductor L d2 respectively, the gate of which is connected to the other end of the capacitor C C2 and one end of the resistor R b6 respectively, and the drain of which is connected to one end of the inductor L4, and serves as an output end of the second low noise amplification unit (LAN2); the other end of the resistor R b6 is connected to one end of the resistor R P2 , a grounded resistor R b5 and the resistor R b4One end is connected and serves as the controlled terminal SD2; the resistor R b4 The other end is connected to the other end of inductor L4 and serves as the power supply terminal; the resistor R p2 The other end is connected to the grounding capacitor C p2 connect.

[0029] like Figure 2 As shown, the control unit includes: resistor R P3 Resistance R P4 Grounding resistance R P5 Resistance R P6 Resistance R P7 Resistance R P8 MOSFET M P1 MOSFET M P2 MOSFET M P3 MOSFET M P4 and field-effect transistor M P5 ;

[0030] The resistor R P3 One end is used as the level input terminal Vpd, and the other end is connected to the resistor R. P4 One end and grounding resistance R P5 Connection; the field-effect transistor M P1 Gate and resistor R P4 The other end is connected, its source is grounded, and its drain is connected to the field-effect transistor M. P2 Gate, field-effect transistor M P4 Gate and resistor R P6 One end is connected; the field-effect transistor M P2 The source is grounded, and its drain is respectively the field-effect transistor M P3 Gate and resistor R P7 One end is connected; the field-effect transistor M P3 The source of the field-effect transistor is grounded, and its drain is used as the control terminal SD1; the field-effect transistor M P4 The source is grounded, and its drain is connected to the field-effect transistor M. P5 Gate and resistor R P8 One end is connected; the field-effect transistor M P5 The source of the resistor is grounded, and its drain serves as the control terminal SD2; the resistor R P6 The other end is connected to resistor R respectively P7 The other end and resistor R P8 The other end is connected and serves as the power supply.

[0031] The control terminal SD1 is connected to the controlled terminal SD1, and the control terminal SD2 is connected to the controlled terminal SD2.

[0032] Figure 1In the middle, the switch SW1, switch SW2, switch SW3, can realize the single-stage LNA1 low noise amplifier, two-stage LNA1+LNA2 low noise amplifier.

[0033] In two-stage LNA1+LNA2 low noise amplifier, join the matching unit containing inductance L3 and capacitance C6.

[0034] In the first low noise amplification unit (LAN1) work, level input end Vpd is high and low level, high and low level through resistance R P3 , resistance R P4 and resistance R P5 get the appropriate voltage of control field effect tube M P1 , through the buffer inverter field effect tube M P1 and field effect tube M P2 , for the gate of field effect tube M P3 high and low level, control SD1 high and low level, so as to control the first low noise amplification unit (LAN1) start or shut down.

[0035] If there is no R p1 , C p1 series to the ground circuit, when the level input end Vpd by high level to low level, SD1 by low level to high level, constantly charging the gate-source parasitic capacitance C gs2 of field effect tube M2, in order to improve the gate voltage, due to the Miller effect, field effect tube M2 gate-drain equivalent parasitic capacitance C gd2 is larger, so that C gs2 charging to the Miller platform, the charging current of the gate will charge C gd2 , at this time the field effect tube M2 drain-source voltage changes rapidly, the output signal waveform will appear overshoot phenomenon, affect the transistor life.

[0036] If you add R p1 , C p1 series to the ground circuit, when SD1 by low level to high level, at the same time, charging the gate-source parasitic capacitance C gs2 of field effect tube M2, part of the charging current flows to the capacitor C p1 , so as to slow down the conduction time of field effect tube M2, so as to reduce the influence of the Miller effect. But the conduction of field effect tube M2 is too slow, that is, the drain-source resistance changes from the infinite resistance of the off state to the small resistance of the on state, which will lead to the time of the heat power of the field effect tube M2 during the conduction process being too long, so that the junction temperature of the field effect tube M2 is very high and burns out. Therefore, resistance R p1 can be used to control the conduction time of M2: the larger the resistance R p1 , the slower the charging of capacitor C p1 , and the slower the charging of capacitor C gs2Charging fast, field effect tube M2 turns on fast; resistance R p1 The smaller, the capacitor C p1 Charging fast, capacitor C gs2 Charging slow, field effect tube M2 turns on slow. Adjusting resistance R p1 , capacitor C p1 The value of the field effect tube M2 can be well optimized, thereby optimizing the output waveform of the first low noise amplifier unit (LAN1), and the specific adjustment process is: (1), only capacitor C p1 , the overshoot will decrease with the increase of capacitor C p1 , and the conduction time will be longer. In the circuit of the application, when the capacitor C p1 is about 15pF, the overshoot disappears, and the conduction time is greater than 140nS; when the capacitor C p1 is less than 15pF, the smaller the overshoot will be more obvious; when the capacitor C p1 is greater than 15pF, the greater the conduction time will gradually increase. (2), only resistance R p1 , the overshoot will not be optimized. (3), when resistance R p1 , capacitor C p1 exist at the same time, the overshoot will decrease with the increase of capacitor C p1 , and the conduction time will decrease with the increase of resistance R p1 . In the circuit of the application, when the resistance R p1 is 3kΩ, the capacitor C p1 is 15pF, the overshoot disappears, and the conduction time is less than 100nS; when the resistance R p1 is greater than 3kΩ and continuously increases, the overshoot will be more and more obvious; when the resistance R p1 is less than 3kΩ and continuously decreases, the conduction time will continuously increase.

[0037] Similarly, resistance R p2 , capacitor C p2 connected in series to the ground circuit at SD2 can optimize the output waveform of the second low noise amplifier unit (LAN2). Figure 3 is the 0dBm transient output waveform diagram when the single-stage LNA1 low noise amplifier is working without resistance R p1 and capacitor C p1 ; Figure 4 is the 0dBm transient output waveform diagram when the low noise amplifier of the application is working in single-stage LNA1; Figure 5 is the 0dBm transient output waveform diagram when the two-stage LNA1+LNA2 low noise amplifier is working without resistance R p1 , capacitor C p1 , resistance R p2 and capacitor C p2 ; Figure 6The 0dBm transient output waveform chart for the low noise amplifier of two-stage LNA1+LNA2 when working simultaneously; Figure 7 The gain chart of the low noise amplifier when the present application adopts single-stage LNA1; Figure 8 The gain chart of the low noise amplifier when the present application adopts two-stage LNA1+LNA2.

Claims

1. A high gain low noise amplifier optimized for transient overshoot, characterized by, The application relates to a low-noise amplifier, which comprises a first low-noise amplifier unit, a second low-noise amplifier unit and a control unit, or comprises a first low-noise amplifier unit or a second low-noise amplifier unit and a control unit. The control unit is used for controlling the first low-noise amplifier unit and the second low-noise amplifier unit to be turned on and turned off; the first low-noise amplifier unit and the second low-noise amplifier unit are connected through a matching unit. The first low-noise amplifier unit comprises an inductor Lg1, a ground inductor LS1, a field effect transistor M1, a capacitor C2, a capacitor CC1, an inductor Ld1, a ground capacitor C3, a resistor R1, a field effect transistor M2, a resistor R2, a capacitor C4, an inductor L1, an inductor L2, a resistor Rb3, a ground capacitor CP1, a resistor RP1, a resistor Rb1 and a ground resistor Rb2. The source of the field effect transistor M1 is connected with the ground inductor LS1, the gate is connected with one end of the inductor Lg1 and one end of the resistor R1 respectively, and the drain is connected with one end of the capacitor C2, one end of the capacitor CC1 and one end of the inductor Ld1 respectively; the other end of the resistor R1 is connected with the other end of the capacitor C2 and serves as a bias voltage end VB1; the source of the field effect transistor M2 is connected with the ground capacitor C3 and the other end of the inductor Ld1 respectively, the gate is connected with one end of the resistor R2, one end of the resistor Rb3 and the other end of the capacitor CC1 respectively, and the drain is connected with one end of the inductor L1; the other end of the resistor Rb3 is connected with one end of the resistor RP1, one end of the resistor Rb1 and the ground resistor Rb2 respectively and serves as a controlled end SD1; the other end of the resistor RP1 is connected with the ground capacitor CP1; the other end of the resistor Rb1 is connected with one end of the inductor L2 and serves as a power supply end; the other end of the inductor L2 is connected with one end of the capacitor C4 and one end of the inductor L1 respectively and serves as an output end of the first low-noise amplifier unit; the other end of the capacitor C4 is connected with the other end of the resistor R2; the other end of the inductor Lg1 serves as an input end of the first low-noise amplifier unit; The second low-noise amplifier unit comprises a resistor R3, a capacitor C7, a field effect transistor M3, a ground inductor LS2, a capacitor CC2, an inductor Ld2, a ground capacitor C8, a field effect transistor M4, a resistor Rb6, a ground capacitor Cp2, a resistor RP2, a ground resistor Rb5, a resistor Rb4 and an inductor L4. ​ The source of the field effect transistor M3 is connected with the ground inductor LS2, the gate is connected with one end of the resistor R3, and serves as the input end of the second low-noise amplification unit; the drain of the field effect transistor M3 is connected with one end of the capacitor C7, one end of the inductor Ld2 and one end of the capacitor CC2 respectively; the other end of the resistor R3 is connected with the other end of the capacitor C7, and serves as the bias voltage end VB2; the source of the field effect transistor M4 is connected with the ground capacitor C8 and the other end of the inductor Ld2 respectively, the gate is connected with the other end of the capacitor CC2 and one end of the resistor Rb6 respectively, the drain is connected with one end of the inductor L4, and serves as the output end of the second low-noise amplification unit; the other end of the resistor Rb6 is connected with one end of the resistor RP2, the ground resistor Rb5 and one end of the resistor Rb4 respectively, and serves as the controlled end SD2; the other end of the resistor Rb4 is connected with the other end of the inductor L4, and serves as the power supply end; the other end of the resistor RP2 is connected with the ground capacitor Cp2.

2. The transient overshoot optimized high gain low noise amplifier of claim 1, wherein, The control unit comprises a resistor RP3, a resistor RP4, a ground resistor RP5, a resistor RP6, a resistor RP7, a resistor RP8, a field effect transistor MP1, a field effect transistor MP2, a field effect transistor MP3, a field effect transistor MP4 and a field effect transistor MP5; One end of the resistor RP3 serves as the level input end Vpd, and the other end is connected with one end of the resistor RP4 and the ground resistor RP5 respectively; the gate of the field effect transistor MP1 is connected with the other end of the resistor RP4, the source is grounded, and the drain is connected with the gate of the field effect transistor MP2, the gate of the field effect transistor MP4 and one end of the resistor RP6 respectively; the source of the field effect transistor MP2 is grounded, and the drain is connected with the gate of the field effect transistor MP3 and one end of the resistor RP7 respectively; the source of the field effect transistor MP3 is grounded, and the drain serves as the control end SD1; the source of the field effect transistor MP4 is grounded, and the drain is connected with the gate of the field effect transistor MP5 and one end of the resistor RP8 respectively; the source of the field effect transistor MP5 is grounded, and the drain serves as the control end SD2; the other end of the resistor RP6 is connected with the other end of the resistor RP7 and the other end of the resistor RP8 respectively, and serves as the power supply end.

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