Semiconductor device and method for manufacturing the same

Abstract

To improve performance of a semiconductor device.SOLUTION: A semiconductor device 31 includes: semiconductor chips 5, 6, and 7; a sealing part 11 that seals the semiconductor chips 5, 6, and 7; bridge chips 18 and 19 and electronic components 15, 16, and 17 mounted on a main surface 11b of the sealing part 11; a sealing part 22 that is formed on the main surface 11b of the sealing part 11 and seals the bridge chips 18 and 19 and the electronic components 15, 16, and 17; and an external terminal of a solder ball 23 formed on a main surface 22a of the sealing part 22. Each of the electronic components 15, 16, and 17 is a passive component or voltage regulator.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] There are semiconductor devices that have multiple semiconductor chips built in. International Publication No. 2023 / 022179 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2022-140618 (Patent Document 2) describe a technique for electrically connecting two semiconductor chips built into a semiconductor device via a bridge chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 022179 [Patent Document 2] Japanese Patent Publication No. 2022-140618 Summary of the Invention [Problem to be solved by the invention]

[0004] It is also desirable to improve the performance of a semiconductor device that incorporates a plurality of semiconductor chips and a bridge chip that electrically connects the plurality of semiconductor chips. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a plurality of semiconductor chips, a first sealing portion sealing the plurality of semiconductor chips, a bridge chip and electronic components mounted on a main surface of the first sealing portion, a second sealing portion formed on the main surface of the first sealing portion and sealing the bridge chip and the electronic components, and external terminals formed on the main surface of the second sealing portion, wherein the electronic components are passive components or voltage regulators. [Effects of the Invention]

[0006] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor device during a manufacturing process according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 1. [Figure 3] 3 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 2. [Figure 4] 4 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 3. [Figure 5] 5 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 4. [Figure 6] 6 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 5. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 6. [Figure 8] FIG. 8 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 7. [Figure 9] 9 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. [Figure 11] 11 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 13. [Figure 15] FIG. 15 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 16] 1 is a cross-sectional view of a semiconductor device according to an embodiment; [Figure 17] 1 is a partially enlarged cross-sectional view showing a part of a semiconductor device according to an embodiment of the present invention; [Figure 18]1 is a partially enlarged cross-sectional view showing a part of a semiconductor device according to an embodiment of the present invention; [Figure 19] FIG. 10 is a cross-sectional view showing a semiconductor device according to a modified example. [Figure 20] FIG. 10 is a cross-sectional view showing a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0009] <About the structure and manufacturing process of semiconductor devices> 1 to 15 are cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment. Although each drawing shows only one package, multiple packages can be manufactured simultaneously with multiple packages connected in the planar direction.

[0010] To manufacture a semiconductor device, first, a substrate (support substrate) 1 is prepared as shown in FIG. 1. The substrate 1 is made of an insulating substrate such as a glass substrate. A seed layer (conductive layer) 2 is formed in advance on the upper surface of the substrate 1. The seed layer 2 is made of, for example, a copper (Cu) layer, and can be formed using a sputtering method or the like. A release layer (not shown) may also be formed between the upper surface of the substrate 1 and the seed layer 2. The release layer has the function of facilitating the release of the substrate 1 in the step of FIG. 6 described below.

[0011] 1, a resist mask 3 is formed on the upper surface of the substrate 1, i.e., on the seed layer 2. For example, a photoresist film can be used as the resist mask 3. A plurality of openings are formed in the resist mask 3 using, for example, photolithography technology.

[0012] Next, as shown in FIG. 2, a plurality of conductor portions (wiring portions) 4 are formed in the plurality of openings of the resist mask 3. The plurality of conductor portions 4 can be formed using a plating method (electrolytic plating method). The seed layer 2 exposed from the openings of the resist mask 3 functions as a base layer for plating. The conductor portions 4 are made of, for example, a simple copper (Cu) film, or a laminated film of a copper (Cu) film on the seed layer 2 and a gold (Au) film on the copper film.

[0013] Next, as shown in FIG. 3, the resist mask 3 is removed.

[0014] Next, as shown in FIG. 4, a plurality of semiconductor chips (semiconductor dies) 5, 6, and 7 are mounted on the substrate 1.

[0015] The semiconductor chip 5 has a front surface 5a which is one of the main surfaces, a back surface 5b which is the main surface located opposite to the front surface 5a, and a plurality of electrodes (columnar electrodes) 8 formed on the front surface 5a. The electrodes 8 are formed on the front surface 5a side of the semiconductor chip 5, and therefore can be considered as front surface electrodes. The plurality of electrodes 8 are electrically connected to semiconductor elements or circuits formed in the semiconductor chip 5.

[0016] The semiconductor chip 6 has a front surface 6a which is one of the main surfaces, a back surface 6b which is the main surface located opposite to the front surface 6a, and a plurality of electrodes (columnar electrodes) 9 formed on the front surface 6a. The electrodes 9 are formed on the front surface 6a side of the semiconductor chip 6, and therefore can be considered as front surface electrodes. The plurality of electrodes 9 are electrically connected to semiconductor elements or circuits formed in the semiconductor chip 6.

[0017] The semiconductor chip 7 has a front surface 7a which is one of the main surfaces, a back surface 7b which is the main surface located opposite the front surface 7a, and a plurality of electrodes (columnar electrodes) 10 formed on the front surface 7a. The electrodes 10 are formed on the front surface 7a side of the semiconductor chip 7 and can therefore be considered as front surface electrodes. The plurality of electrodes 10 are electrically connected to semiconductor elements or circuits formed within the semiconductor chip 7.

[0018] The electrodes 8, 9, and 10 are, for example, columnar electrodes (projecting electrodes) made of copper (Cu) or the like, and a solder layer (not shown) is formed on the surfaces (tip surfaces) of the electrodes 8, 9, and 10.

[0019] The semiconductor chips 5, 6, and 7 are mounted on the substrate 1 with the surfaces 5a, 6a, and 7a of the semiconductor chips 5, 6, and 7 facing the upper surface of the substrate 1, and with the multiple electrodes 8, 9, and 10 of the semiconductor chips 5, 6, and 7 facing the multiple conductor portions 4, respectively. A solder reflow process is then performed. This bonds the multiple electrodes 8, 9, and 10 of the semiconductor chips 5, 6, and 7 to the multiple conductor portions 4, respectively, via solder (not shown). That is, the multiple electrodes 8, 9, and 10 of the semiconductor chips 5, 6, and 7 are solder-connected to the multiple conductor portions 4. Therefore, each of the multiple electrodes 8, 9, and 10 of the semiconductor chips 5, 6, and 7 is electrically connected to the conductor portion 4 located underneath it.

[0020] 5, a sealing portion (sealing resin portion) 11 is formed to seal the semiconductor chips 5, 6, and 7 and the conductor portion 4. The sealing portion 11 is made of an insulating resin material such as a thermosetting resin, and may also contain a filler.

[0021] The encapsulating portion 11 is formed on the upper surface of the substrate 1, i.e., on the seed layer 2, so as to cover the semiconductor chips 5, 6, and 7 and the conductor portions 4. The semiconductor chips 5, 6, and 7 and the multiple conductor portions 4 are integrated by the encapsulating portion 11. The encapsulating portion 11 has a main surface 11a and a main surface 11b located opposite each other. The main surface 11b of the encapsulating portion 11 faces the seed layer 2 (substrate 1) and is in contact with the seed layer 2. In this embodiment, the semiconductor chips 5, 6, and 7 are not exposed from the main surface 11a of the encapsulating portion 11. After the encapsulating portion 11 is formed, the semiconductor chips 5, 6, and 7 may be exposed from the main surface 11a of the encapsulating portion 11 by polishing the main surface 11a of the encapsulating portion 11, for example.

[0022] Next, as shown in FIG. 6, the substrate 1 is removed by peeling it off from the sealing portion 11. For example, the substrate 1 can be easily peeled off by reducing the adhesive strength of a release layer (not shown) interposed between the substrate 1 and the seed layer 2, for example, by irradiating the release layer with a laser. Alternatively, the substrate 1 can be peeled off by mechanical stress. Note that the sealing portion 11 is upside down in FIGS. 5 and 6.

[0023] Next, a step of forming the through electrodes 13 is performed as shown in Figures 7 to 9. Hereinafter, the step of forming the through electrodes 13 will be specifically described with reference to Figures 7 to 9.

[0024] 7, a resist mask 12 is formed on the main surface 11b of the sealing portion 11, i.e., on the seed layer 2. For example, a photoresist film can be used as the resist mask 12. A plurality of openings are formed in the resist mask 12 using, for example, photolithography technology.

[0025] In this embodiment, after peeling off the substrate 1, the resist mask 12 is formed on the seed layer 2 without removing the seed layer 2, but it is also possible to remove the seed layer 2 after peeling off the substrate 1 to expose the main surface 11b of the sealing portion 11, and then form a seed layer on the main surface 11b of the sealing portion 11, and then form the resist mask 12 on the seed layer. In that case, the seed layer 2 shown in FIG. 7 is formed after peeling off the substrate 1.

[0026] Next, as shown in FIG. 8, a plurality of conductor portions 13a are formed in the plurality of openings of the resist mask 12. The plurality of conductor portions 13a can be formed using a plating method (electrolytic plating method). The seed layer 2 exposed from the openings of the resist mask 12 functions as a base layer for plating. The conductor portions 13a are made of, for example, a simple copper (Cu) film, or a laminated film of a copper (Cu) film on the seed layer 2 and a gold (Au) film on the copper film.

[0027] Next, as shown in FIG. 9, the resist mask 12 is removed. Thereafter, the seed layer 2 that is exposed and not covered with the conductor portion 13a is removed by etching or the like. The seed layer 2 that is covered with the conductor portion 13a remains without being etched. As a result, as shown in FIG. 9, a through electrode 13 is formed, which is composed of the conductor portion 13a and the seed layer 2 below the conductor portion 13a. The through electrode 13 is formed on the conductor portion 4 on the main surface 11b side of the sealing portion 11. The lower surface of the through electrode 13 is in contact with the conductor portion 4 located below the through electrode 13, and is electrically connected to the conductor portion 4 located below the through electrode 13.

[0028] 10 , solder 14 is placed (applied) on the main surface 11b of the sealing portion 11 on the conductor portion 4 on which electronic components 15, 16, and 17 are to be mounted. The solder 14 can be placed on the conductor portion 4 using, for example, a dispenser. When the solder 14 is placed using a printing method, there is a concern that the electronic components 15, 16, and 17 may get in the way of placing a printing mask. However, by placing the solder 14 on the conductor portion 4 using a dispenser without using a printing method, the solder 14 can be accurately placed on the conductor portion 4 without the electronic components 15, 16, and 17 getting in the way.

[0029] If a solder layer is formed on the electrodes of the electronic components 15, 16, and 17 in advance, the solder 14 does not need to be disposed on the conductor portion 4.

[0030] Next, as shown in FIG. 11 , electronic components 15, 16, and 17 are mounted on the main surface 11b of the sealing portion 11. The electronic components 15, 16, and 17 are mounted on the main surface 11b of the sealing portion 11 so that the multiple electrodes of the electronic components 15, 16, and 17 face the multiple conductor portions 4, respectively. Then, a solder reflow process is performed. As a result, the multiple electrodes of the electronic components 15, 16, and 17 are joined to the multiple conductor portions 4 via the solder 14, respectively. That is, the multiple electrodes of the electronic components 15, 16, and 17 are solder-connected to the multiple conductor portions 4. Therefore, each of the multiple electrodes of the electronic components 15, 16, and 17 is electrically connected to the conductor portion 4 located underneath it via the solder 14.

[0031] Each of electronic components 15, 16, and 17 is a passive component or a voltage regulator. Examples of passive components include a capacitor, an inductor, and a resistor. For example, in the case of FIG. 11, a passive component is used as electronic component 15, a voltage regulator is used as electronic component 16, and a passive component is used as electronic component 17.

[0032] Next, as shown in FIG. 12, bridge chips (bridge dies) 18 and 19 are mounted on the main surface 11b side of the sealing portion 11.

[0033] The bridge chip 18 has a front surface which is one of the main surfaces, a back surface which is the main surface located opposite the front surface, and a plurality of electrodes (columnar electrodes) 20 formed on the front surface. The bridge chip 19 has a front surface which is one of the main surfaces, a back surface which is the main surface located opposite the front surface, and a plurality of electrodes (columnar electrodes) 21 formed on the front surface.

[0034] The electrodes 20 and 21 are, for example, columnar electrodes (projecting electrodes) made of copper (Cu) or the like, and a solder layer (not shown) is formed on the surfaces (tip surfaces) of the electrodes 20 and 21.

[0035] The bridge chips 18, 19 are mounted on the main surface 11b of the sealing portion 11 so that the multiple electrodes 20, 21 of the bridge chips 18, 19 face the multiple conductor portions 4, respectively. Then, a solder reflow process is performed. As a result, the multiple electrodes 20, 21 of the bridge chips 18, 19 are joined to the multiple conductor portions 4 via solder (not shown). That is, the multiple electrodes 20, 21 of the bridge chips 18, 19 are solder-connected to the multiple conductor portions 4. Therefore, each of the multiple electrodes 20, 21 of the bridge chips 18, 19 is electrically connected to the conductor portion 4 located below it.

[0036] In this embodiment, the step of mounting electronic components 15, 16, and 17 on main surface 11b of sealing portion 11 is followed by the step of mounting bridge chips 18 and 19 on main surface 11b of sealing portion 11. However, the step of mounting electronic components 15, 16, and 17 can also be performed after the step of mounting bridge chips 18 and 19.

[0037] However, it is preferable to perform the step of mounting bridge chips 18 and 19 after the step of mounting electronic components 15, 16, and 17. The reason for this is as follows.

[0038] The electrodes 20 and 21 of the bridge chips 18 and 19 are smaller than the electrodes of the electronic components 15, 16, and 17. Therefore, if the mounting process of the electronic components 15, 16, and 17 is performed after the mounting process of the bridge chips 18 and 19, there is a risk that the electrodes 20 and 21 of the bridge chips 18 and 19 will be damaged by stress due to two solder reflow processes: one for mounting the bridge chips 18 and 19, and the other for mounting the electronic components 15, 16, and 17. If the electrodes 20 and 21 of the bridge chips 18 and 19 are damaged by stress, there is a concern that the connection strength between the electrodes 20 and 21 of the bridge chips 18 and 19 and the conductor portion 4 will be reduced.

[0039] In contrast, when the mounting process of the bridge chips 18 and 19 is performed after the mounting process of the electronic components 15, 16, and 17, as in the present embodiment, the solder reflow process accompanying the mounting process of the electronic components 15, 16, and 17 does not affect the electrodes 20 and 21 of the bridge chips 18 and 19. This reduces or prevents the electrodes 20 and 21 of the bridge chips 18 and 19 from being damaged by stress during the solder reflow process. This increases the connection strength between the electrodes 20 and 21 of the bridge chips 18 and 19 and the conductor 4. Furthermore, because the electrodes of the electronic components 15, 16, and 17 are larger than the electrodes 20 and 21 of the bridge chips 18 and 19, even if the electronic components 15, 16, and 17 are damaged by stress due to the two solder reflow processes, the connection strength between the electrodes of the electronic components 15, 16, and 17 and the conductor 4 can be sufficiently ensured.

[0040] 13, a sealing portion (sealing resin portion) 22 is formed to seal the plurality of through electrodes 13, the electronic components 15, 16, 17, and the bridge chips 18, 19. The sealing portion 22 is made of an insulating resin material such as a thermosetting resin, and may also contain a filler.

[0041] The sealing portion 22 is formed on the main surface 11b of the sealing portion 11 so as to cover the plurality of through electrodes 13, the electronic components 15, 16, and 17, and the bridge chips 18 and 19. The plurality of through electrodes 13, the electronic components 15, 16, and 17, and the bridge chips 18 and 19 are integrated by the sealing portion 22. The sealing portion 22 has main surfaces 22a and 22b located on opposite sides of each other. The main surface 22b of the sealing portion 22 faces the main surface 11b of the sealing portion 11 and is in contact with the main surface 11b of the sealing portion 11. At this stage, the plurality of through electrodes 13, the electronic components 15, 16, and 17, and the bridge chips 18 and 19 are not exposed from the main surface 22a of the sealing portion 22.

[0042] 14 , the main surface 22a of the sealing portion 22 is polished to reduce the thickness of the sealing portion 22. At this time, the sealing portion 22 is polished until the upper surfaces of the plurality of through electrodes 13 are exposed from the upper surface 22a of the sealing portion 22. As a result, the upper surfaces of the plurality of through electrodes 13 are exposed from the main surface 22a of the sealing portion 22.

[0043] In this embodiment, not only the upper surfaces of the plurality of through electrodes 13 but also the back surfaces of the bridge chips 18 and 19 are exposed from the main surface 22a of the sealing portion 22. In this case, the upper surfaces of the plurality of through electrodes 13 and the back surfaces of the bridge chips 18 and 19 are flush with the main surface 22a of the sealing portion 22. However, there may be cases where the upper surfaces of the plurality of through electrodes 13 are exposed from the main surface 22a of the sealing portion 22 but the bridge chips 18 and 19 are not exposed.

[0044] Furthermore, it is desirable that the electronic components 15, 16, and 17 are not exposed from the main surface 22a of the sealing portion 22. For this reason, the height (dimension in the height direction) of the through electrodes 13 is made larger than the height of the electronic components 15, 16, and 17. This makes the upper surfaces of the plurality of through electrodes 13 higher than the upper surfaces of the electronic components 15, 16, and 17. As a result, after polishing the sealing portion 22, the plurality of through electrodes 13 can be exposed from the main surface 22a of the sealing portion 22 without exposing the electronic components 15, 16, and 17.

[0045] Next, as shown in FIG. 15, a plurality of solder balls 23 are formed as external terminals on the surfaces of the plurality of through electrodes 13 exposed from the main surface 22a of the sealing portion 22 (top surfaces of the through electrodes 13 in FIG. 15).

[0046] Thereafter, the stack of sealing portion 11 and sealing portion 22 is cut between adjacent semiconductor packages using a dicing blade or the like to obtain semiconductor device 31 shown in Fig. 16. Fig. 16 is a cross-sectional view of semiconductor device 31 of this embodiment. Note that Fig. 15 and Fig. 16 are upside down.

[0047] 16, semiconductor device 31 of the present embodiment includes sealing portion 11 in which semiconductor chips 5, 6, and 7 and a plurality of conductor portions 4 are sealed, bridge chips 18 and 19 and electronic components 15, 16, and 17 mounted on main surface 11b of sealing portion 11, and sealing portion 22 formed on main surface 11b of sealing portion 11 and sealing bridge chips 18 and 19 and electronic components 15, 16, and 17. As shown in Fig. 16, semiconductor device 31 further includes a plurality of through electrodes 13 that penetrate through sealing portion 22 and a plurality of solder balls 23 arranged on main surface 22a of sealing portion 22. The plurality of solder balls 23 are respectively formed on surfaces of the plurality of through electrodes 13 exposed from main surface 22a of sealing portion 22 (lower surfaces of through electrodes 13 in Fig. 16).

[0048] The plurality of conductors 4 can function as internal wiring of the semiconductor device 31. The plurality of conductors 4 includes a conductor 4 interposed between the electrode 8 of the semiconductor chip 5 and the electrode 20 of the bridge chip 18 to electrically connect the electrode 8 and the electrode 20, and a conductor 4 interposed between the electrode 9 of the semiconductor chip 6 and the electrode 20 of the bridge chip 18 to electrically connect the electrode 9 and the electrode 20. The plurality of conductors 4 further includes a conductor 4 interposed between the electrode 9 of the semiconductor chip 6 and the electrode 21 of the bridge chip 19 to electrically connect the electrode 9 and the electrode 21, and a conductor 4 interposed between the electrode 10 of the semiconductor chip 7 and the electrode 21 of the bridge chip 19 to electrically connect the electrode 10 and the electrode 21. The plurality of conductor portions 4 further include a conductor portion 4 electrically connecting electrode 8 of semiconductor chip 5 and an electrode of electronic component 15, a conductor portion 4 electrically connecting electrode 9 of semiconductor chip 6 and an electrode of electronic component 16, a conductor portion 4 electrically connecting electrode 10 of semiconductor chip 7 and an electrode of electronic component 17, and a conductor portion 4 electrically connected to through electrode 13. The plurality of conductor portions 4 may further include a conductor portion 4 (not shown in FIG. 16) electrically connecting electrode 8 of semiconductor chip 5 and through electrode 13, a conductor portion 4 (not shown in FIG. 16) electrically connecting electrode 9 of semiconductor chip 6 and through electrode 13, and a conductor portion 4 (not shown in FIG. 16) electrically connecting electrode 10 of semiconductor chip 7 and through electrode 13.

[0049] The plurality of through electrodes 13 penetrate the sealing portion 22. A solder ball 23 formed on the lower surface of each through electrode 13 is electrically connected to the conductor portion 4 arranged on the upper surface of the through electrode 13 via the through electrode 13. The through electrode 13 is interposed between the solder ball 23 and the conductor portion 4 and can function as internal wiring that electrically connects the solder ball 23 and the conductor portion 4. The solder ball 23 functions as an external terminal of the semiconductor device 31.

[0050] Each of the electronic components 15, 16, and 17 is connected between an electrode of one of the semiconductor chips 5, 6, and 7 and an external terminal (here, the solder ball 23). That is, each of the electronic components 15, 16, and 17 is interposed in the middle of the conductive path between an electrode of one of the semiconductor chips 5, 6, and 7 and the external terminal (the solder ball 23).

[0051] Specifically, one electrode of electronic component 15 is electrically connected to electrode 8 of semiconductor chip 5 via solder 14 and conductor 4, and the other electrode of electronic component 15 is electrically connected to solder ball 23 via solder 14, conductor 4, and through electrode 13. In other words, electronic component 15 is located in the middle of the conductive path between electrode 8 of semiconductor chip 5 and solder ball 23. In addition, one electrode of electronic component 16 is electrically connected to electrode 9 of semiconductor chip 6 via solder 14 and conductor 4, and the other electrode of electronic component 16 is electrically connected to solder ball 23 via solder 14, conductor 4, and through electrode 13. In other words, electronic component 16 is located in the middle of the conductive path between electrode 9 of semiconductor chip 6 and solder ball 23. Furthermore, one electrode of electronic component 17 is electrically connected to electrode 10 of semiconductor chip 7 via solder 14 and conductor 4, and the other electrode of electronic component 17 is electrically connected to solder ball 23 via solder 14, conductor 4, and through electrode 13. In other words, electronic component 17 is located midway along the conductive path between electrode 10 of semiconductor chip 7 and solder ball 23.

[0052] The electrodes 20, 21 of the bridge chips 18, 19 are not electrically connected to the solder balls 23. In other words, the electrodes 20, 21 of the bridge chips 18, 19 are not connected to the solder balls 23 via a continuous conductive path.

[0053] Neither a semiconductor chip nor a bridge chip is mounted on the main surface 22a of the sealing portion 22, and no electronic components such as passive components or voltage regulators are mounted on the main surface 22a.

[0054] When mounting the semiconductor device 31 on a mounting substrate (wiring board), the semiconductor device 31 is mounted on the mounting substrate with the main surface 22a of the sealing portion 22 facing the mounting substrate, and multiple solder balls 23, which are external terminals of the semiconductor device 31, are connected to multiple terminals of the mounting substrate.

[0055] One of the main features of the semiconductor device 31 of this embodiment is that bridge chips 18, 19 and electronic components 15, 16, 17 are mounted on the main surface 11b of the sealing portion 11 that seals multiple semiconductor chips 5, 6, 7, and these are sealed with the sealing portion 22, and multiple external terminals (solder balls 23) are arranged on the main surface 22a of the sealing portion 22.

[0056] <About Bridge Chips 18 and 19> The semiconductor device 31 of this embodiment incorporates semiconductor chips 5, 6, and 7 and bridge chips 18 and 19. The bridge chip 18 is used to electrically connect the electrode 8 of the semiconductor chip 5 to the electrode 9 of the semiconductor chip 6 via wiring within the bridge chip 18. The bridge chip 19 is used to electrically connect the electrode 9 of the semiconductor chip 6 to the electrode 10 of the semiconductor chip 7 via wiring within the bridge chip 19. The connection relationship between the semiconductor chips 5, 6, and 7 and the bridge chips 18 and 19 will be specifically described with reference to FIGS. 17 and 18.

[0057] 17 and 18 are enlarged cross-sectional views showing a part of semiconductor device 31 of this embodiment. Note that sealing portions 11 and 22 are omitted from the illustration in FIGS.

[0058] 17, the semiconductor chip 5 has an IC chip 51, an insulating layer 52 formed on the IC chip 51, a wiring layer (rewiring) 53 formed on the insulating layer 52, and an insulating layer (uppermost protective film) 54 formed on the insulating layer 52 so as to cover the wiring layer 53. The electrodes 8 of the semiconductor chip 5 are formed on the wiring layer 53 exposed from the openings in the insulating layer 54. The electrodes 8 function as electrodes for connecting the semiconductor chip 5.

[0059] 17 and 18, the semiconductor chip 6 has an IC chip 61, an insulating layer 62 formed on the IC chip 61, a wiring layer (rewiring) 63 formed on the insulating layer 62, and an insulating layer (uppermost protective film) 64 formed on the insulating layer 62 so as to cover the wiring layer 63. The electrodes 9 of the semiconductor chip 6 are formed on the wiring layer 63 exposed from the openings in the insulating layer 64. The electrodes 9 function as electrodes for connecting the semiconductor chip 6.

[0060] 18, the semiconductor chip 7 has an IC chip 71, an insulating layer 72 formed on the IC chip 71, a wiring layer (rewiring) 73 formed on the insulating layer 72, and an insulating layer (uppermost protective film) 74 formed on the insulating layer 72 so as to cover the wiring layer 73. The electrodes 10 of the semiconductor chip 7 are formed on the wiring layer 73 exposed from the openings in the insulating layer 74. The electrodes 10 function as electrodes for connecting the semiconductor chip 7.

[0061] Each of the semiconductor chips 5, 6, and 7 has a semiconductor substrate constituting an IC chip and a multilayer wiring structure on the semiconductor substrate, with multiple semiconductor elements such as transistors formed in or on the semiconductor substrate. The multilayer wiring structure includes multiple wiring layers and multiple insulating films. The multiple semiconductor elements and multiple wirings in the IC chip form a predetermined circuit (IC circuit) within the IC chip.

[0062] Electrodes 8 of semiconductor chip 5 are electrically connected to the circuit (IC circuit) in IC chip 51 via wiring layer 53 and wiring in IC chip 51. Electrodes 9 of semiconductor chip 6 are electrically connected to the circuit (IC circuit) in IC chip 61 via wiring layer 63 and wiring in IC chip 61. Electrodes 10 of semiconductor chip 7 are electrically connected to the circuit (IC circuit) in IC chip 71 via wiring layer 73 and wiring in IC chip 71.

[0063] 17, the bridge chip 18 has a chip 81, an insulating layer 82 formed on the chip 81, a wiring layer 83 formed on the insulating layer 82, and an insulating layer (uppermost protective film) 84 formed on the insulating layer 82 so as to cover the wiring layer 83. The electrodes 20 of the bridge chip 18 are formed on the wiring layer 83 exposed from the openings in the insulating layer 84. The electrodes 20 function as connection electrodes for the bridge chip 18.

[0064] 18, the bridge chip 19 has a chip 91, an insulating layer 92 formed on the chip 91, a wiring layer 93 formed on the insulating layer 92, and an insulating layer (uppermost protective film) 94 formed on the insulating layer 92 so as to cover the wiring layer 93. The electrodes 21 of the bridge chip 19 are formed on the wiring layer 93 exposed from the openings in the insulating layer 94. The electrodes 21 function as connection electrodes for the bridge chip 19.

[0065] Each of chips 81 and 91 has a semiconductor substrate that constitutes an IC chip, but no semiconductor elements such as transistors are formed in or on the main surface of the semiconductor substrate. Furthermore, each of chips 81 and 91 does not necessarily have a multilayer wiring structure on the semiconductor substrate.

[0066] That is, semiconductor elements such as transistors are not formed in the bridge chips 18 and 19. The bridge chips 18 and 19 are chips (semiconductor chips) that do not have either active elements or passive elements.

[0067] The plurality of electrodes 8 of the semiconductor chip 5 includes a plurality of electrodes 8a (see FIG. 17). The plurality of electrodes 9 of the semiconductor chip 6 includes a plurality of electrodes 9a (see FIG. 17) and a plurality of electrodes 9b (see FIG. 18). The plurality of electrodes 10 of the semiconductor chip 7 includes a plurality of electrodes 10a (see FIG. 18). The plurality of electrodes 20 of the bridge chip 18 includes a plurality of electrodes 20a (see FIG. 17) and a plurality of electrodes 20b (see FIG. 17). The plurality of electrodes 21 of the bridge chip 19 includes a plurality of electrodes 21a (see FIG. 18) and a plurality of electrodes 21b (see FIG. 18).

[0068] The bridge chip 18 has internal wiring (wiring in the wiring layer 83) that electrically connects the electrodes 8a of the semiconductor chip 5 and the electrodes 9a of the semiconductor chip 6. The bridge chip 19 has internal wiring (wiring in the wiring layer 93) that electrically connects the electrodes 9b of the semiconductor chip 6 and the electrodes 10a of the semiconductor chip 7.

[0069] A plurality of electrodes 8a of the semiconductor chip 5 and a plurality of electrodes 20a of the bridge chip 18 face each other via the conductor portion 4 and are electrically connected to each other via the conductor portion 4 (see FIG. 17). A plurality of electrodes 9a of the semiconductor chip 6 and a plurality of electrodes 20b of the bridge chip 18 face each other via the conductor portion 4 and are electrically connected to each other via the conductor portion 4 (see FIG. 17). A plurality of electrodes 9b of the semiconductor chip 6 and a plurality of electrodes 21a of the bridge chip 19 face each other via the conductor portion 4 and are electrically connected to each other via the conductor portion 4 (see FIG. 18). A plurality of electrodes 10a of the semiconductor chip 7 and a plurality of electrodes 21b of the bridge chip 19 face each other via the conductor portion 4 and are electrically connected to each other via the conductor portion 4 (see FIG. 18).

[0070] The plurality of electrodes 20a and the plurality of electrodes 20b of the bridge chip 18 are electrically connected to each other via wiring (wiring layer 83) within the bridge chip 18 (see FIG. 17). Therefore, the electrode 8a of the semiconductor chip 5 and the electrode 9a of the semiconductor chip 6 are electrically connected to each other via the conductor portion 4 interposed between the electrode 8a and the electrode 20a, the conductor portion 4 interposed between the electrode 9a and the electrode 20b, the electrodes 20a and 20b of the bridge chip 18, and the wiring (wiring layer 83) within the bridge chip 18. In other words, the electrode 8a of the semiconductor chip 5 and the electrode 9a of the semiconductor chip 6 are electrically connected to each other via a continuous conductive path consisting of the conductor portion 4 and the conductor portions (electrodes 20a and 20b and wiring layer 83) within the bridge chip 18.

[0071] The plurality of electrodes 21a and the plurality of electrodes 21b of the bridge chip 19 are electrically connected to each other via wiring (wiring layer 83) within the bridge chip 19 (see FIG. 18). Therefore, the electrode 9b of the semiconductor chip 6 and the electrode 10a of the semiconductor chip 7 are electrically connected to each other via the conductor portion 4 interposed between the electrode 9b and the electrode 21a, the conductor portion 4 interposed between the electrode 10a and the electrode 21b, the electrodes 21a and 21b of the bridge chip 19, and the wiring (wiring layer 83) within the bridge chip 18. In other words, the electrode 9b of the semiconductor chip 6 and the electrode 10a of the semiconductor chip 7 are electrically connected to each other via a continuous conductive path consisting of the conductor portion 4 and the conductor portions (electrodes 21a and 21b and wiring layer 93) within the bridge chip 19.

[0072] In this way, the electrodes of the semiconductor chips 5, 6, and 7 built into the semiconductor device 31 can be electrically connected to each other using the bridge chips 18 and 19.

[0073] <About Electronic Components 15, 16, and 17> Semiconductor device 31 of this embodiment incorporates not only semiconductor chips 5, 6, and 7 and bridge chips 18 and 19, but also electronic components 15, 16, and 17. Each of electronic components 15, 16, and 17 is electrically connected to one of semiconductor chips 5, 6, and 7. In semiconductor device 31 of this embodiment, bridge chips 18 and 19 and electronic components 15, 16, and 17 are mounted on main surface 11b of sealing portion 11 that seals multiple semiconductor chips 5, 6, and 7, and these are sealed with sealing portion 22, and multiple external terminals (solder balls 23) are arranged on main surface 22a of sealing portion 22.

[0074] Unlike the present embodiment, it is assumed that the semiconductor device 31 does not include the electronic components 15, 16, and 17, and this case is referred to as a first example.

[0075] In the first study example, since the semiconductor device 31 does not include electronic components 15, 16, and 17, when manufacturing an electronic device using the semiconductor device 31, components corresponding to the electronic components 15, 16, and 17 must also be mounted on the mounting board on which the semiconductor device 31 is mounted.

[0076] In contrast, in the present embodiment, the semiconductor device 31 also incorporates the electronic components 15, 16, and 17, so when manufacturing an electronic device using the semiconductor device 31, it is not necessary to mount components equivalent to the electronic components 15, 16, and 17 on a mounting board on which the semiconductor device 31 is mounted. This makes it easier to manufacture an electronic device using the semiconductor device 31, and also simplifies the configuration of the electronic device using the semiconductor device 31. Furthermore, by incorporating the electronic components 15, 16, and 17, the performance of the semiconductor device 31 can be improved.

[0077] Also, unlike this embodiment, it is assumed that electronic components 15, 16, and 17 are mounted on main surface 22a of sealing portion 22, and this case is referred to as a second study example.

[0078] In the second study example, because electronic components 15, 16, and 17 are mounted on main surface 22a of sealing portion 22, the heights (dimensions in the height direction) of electronic components 15, 16, and 17 need to be smaller than the heights (dimensions in the height direction) of solder balls 23. This is because, in the second study example, if the heights of electronic components 15, 16, and 17 were larger than the heights of solder balls 23, electronic components 15, 16, and 17 would prevent connection of solder balls 23 of semiconductor device 31 to terminals of the mounting board.

[0079] In contrast, in this embodiment, not only bridge chips 18 and 19 but also electronic components 15, 16, and 17 are mounted on main surface 11b of sealing portion 11 that seals multiple semiconductor chips 5, 6, and 7. Bridge chips 18 and 19 and electronic components 15, 16, and 17 are then sealed with sealing portion 22, and external terminals (solder balls 23) are arranged on main surface 22a of sealing portion 22.

[0080] Therefore, in this embodiment, the heights (height dimensions) of the electronic components 15, 16, and 17 may be smaller than or larger than the heights (height dimensions) of the solder balls 23. That is, the heights of the electronic components 15, 16, and 17 can be selected without regard to the height of the solder balls 23. This increases the degree of freedom in selecting the electronic components 15, 16, and 17. Therefore, electronic components that fully meet the required characteristics can be used as the electronic components 15, 16, and 17 without regard to the heights of the electronic components 15, 16, and 17, thereby improving the performance of the semiconductor device 31. Alternatively, inexpensive electronic components can be used as the electronic components 15, 16, and 17 without regard to the heights of the electronic components 15, 16, and 17, thereby reducing the manufacturing cost of the semiconductor device 31.

[0081] Furthermore, in this embodiment, the height of the solder balls 23 can be selected without regard to the height of the electronic components 15, 16, and 17, and therefore the dimensions of the solder balls 23 can be set to dimensions suitable for mounting the semiconductor device 31 on an implementation board or the like.

[0082] Furthermore, in this embodiment, bridge chips 18 and 19 and electronic components 15, 16, and 17 are mounted on main surface 11b of sealing portion 11 that seals semiconductor chips 5, 6, and 7, and are then sealed with sealing portion 22. Therefore, the height (dimension in the height direction) of semiconductor device 31 is the same in the first study example in which electronic components 15, 16, and 17 are not built in, and in this embodiment in which electronic components 15, 16, and 17 are built in. Therefore, in this embodiment, it is possible to suppress or prevent an increase in the height of semiconductor device 31 that would otherwise occur due to the built-in electronic components 15, 16, and 17. Therefore, it is possible to achieve both improved performance of semiconductor device 31 and a smaller size of semiconductor device 31.

[0083] Furthermore, in the case of the second study example described above, because electronic components 15, 16, and 17 are mounted on main surface 22a of sealing portion 22, there is a concern that the length of the conductive paths electrically connecting the multiple electrodes of electronic components 15, 16, and 17 to the multiple electrodes of semiconductor chips 5, 6, and 7 will increase. This is because, in the case of the second study example, electronic components 15, 16, and 17 are mounted on main surface 22a of sealing portion 22, and therefore, in order to electrically connect the multiple electrodes of semiconductor chips 5, 6, and 7 to the multiple electrodes of electronic components 15, 16, and 17, the connection must be made via wiring or through electrodes within sealing portion 22.

[0084] In contrast, in the present embodiment, bridge chips 18, 19 and electronic components 15, 16, 17 are mounted on main surface 11b of sealing portion 11 that seals semiconductor chips 5, 6, 7, thereby reducing the length of the conductive paths between the multiple electrodes of semiconductor chips 5, 6, 7 and the multiple electrodes of electronic components 15, 16, 17. This is because, in the present embodiment, electronic components 15, 16, 17 are mounted on main surface 11b of sealing portion 11 that seals semiconductor chips 5, 6, 7, and therefore, in order to electrically connect the multiple electrodes of semiconductor chips 5, 6, 7 and the multiple electrodes of electronic components 15, 16, 17, it is not necessary to connect them via wiring or through electrodes within sealing portion 22, and the multiple electrodes of electronic components 15, 16, 17 can be connected to the multiple electrodes of semiconductor chips 5, 6, 7 via solder 14 and conductor portion 4. That is, in this embodiment, the wiring layer made of the conductor portion 4 can electrically connect the multiple electrodes of the electronic components 15, 16, and 17 to the multiple electrodes of the semiconductor chips 5, 6, and 7. In this embodiment, since the electronic components 15, 16, and 17 are mounted on the main surface 11b of the sealing portion 11 that seals the semiconductor chips 5, 6, and 7, the distances (intervals) between the multiple electrodes of the electronic components 15, 16, and 17 and the multiple electrodes of the semiconductor chips 5, 6, and 7 can be reduced, and therefore the length of the conductive paths electrically connecting the multiple electrodes of the electronic components 15, 16, and 17 to the multiple electrodes of the semiconductor chips 5, 6, and 7 can be reduced. This reduces the amount of parasitic capacitance and parasitic inductance generated, thereby improving the performance of the semiconductor device 31.

[0085] For example, in FIG. 16 , one electrode of electronic component 15 is electrically connected to electrode 8 of semiconductor chip 5 via solder 14 and conductor 4. The distance (gap) between the electrode of electronic component 15 and electrode 8 of semiconductor chip 5, which are electrically connected via solder 14 and conductor 4, can be, for example, about 10 to 40 μm. One electrode of electronic component 16 is electrically connected to electrode 9 of semiconductor chip 6 via solder 14 and conductor 4. The distance (gap) between the electrode of electronic component 16 and electrode 9 of semiconductor chip 6, which are electrically connected via solder 14 and conductor 4, can be, for example, about 10 to 40 μm. One electrode of electronic component 17 is electrically connected to electrode 10 of semiconductor chip 7 via solder 14 and conductor 4. The distance (gap) between the electrode of electronic component 17 and electrode 10 of semiconductor chip 7, which are electrically connected via solder 14 and conductor 4, can be, for example, about 10 to 40 μm.

[0086] 16, three electronic components 15, 16, and 17 are mounted on the main surface 11b of the sealing portion 11 constituting the semiconductor device 31, but the number of electronic components (passive components or voltage regulators) mounted on the main surface 11b of the sealing portion 11 is not limited to three. However, one or more electronic components (passive components or voltage regulators) are mounted on the main surface 11b of the sealing portion 11 constituting the semiconductor device 31. The number of electronic components mounted on the main surface 11b of the sealing portion 11 and the number of semiconductor chips sealed in the sealing portion 11 may be the same or different.

[0087] 16, two bridge chips 18 and 19 are mounted on the main surface 11b of the sealing portion 11 constituting the semiconductor device 31, but the number of bridge chips mounted on the main surface 11b of the sealing portion 11 is not limited to two. However, one or more bridge chips may be mounted on the main surface 11b of the sealing portion 11 constituting the semiconductor device 31.

[0088] 16, three semiconductor chips 5, 6, and 7 are sealed in sealing portion 11, but the number of semiconductor chips (IC chips) sealed in sealing portion 11 is not limited to three. However, two or more semiconductor chips (IC chips) are sealed in sealing portion 11 constituting semiconductor device 31. For example, in semiconductor device 31 shown in FIG. 16, if the number of semiconductor chips sealed in sealing portion 11 is two, semiconductor chips 5 and 6, semiconductor chip 7, bridge chip 19, and electronic component 17 are omitted.

[0089] Furthermore, within semiconductor device 31, multiple electronic components may be connected in series or parallel to one semiconductor chip. Figures 19 and 20 are cross-sectional views showing modifications of semiconductor device 31 of the present embodiment. In semiconductor device 31a (a modification of semiconductor device 31) shown in Figure 19, multiple electronic components 16 and 17 are connected in series to semiconductor chip 7. Specifically, multiple electronic components 16 and 17 are connected in series between electrodes 10 of semiconductor chip 7 and solder balls 23. In semiconductor device 31b (a modification of semiconductor device 31) shown in Figure 20, multiple electronic components 16 and 17 are connected in parallel to semiconductor chip 6.

[0090] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0091] 1 board 2. Seed layer 3. Resist mask 4 Conductor part 5,6,7 Semiconductor chips 5a,6a,7a surface 5b,6b,7b Back side 8,8a,9,9a,9b,10,10a electrode 11 Sealing part 11a,11b Main surface 12 Resist mask 13 Through electrode 13a Conductor part 14 Solder 15, 16, 17 Electronic Components 18,19 Bridge chip 20,20a,20b,21,21a,21b electrode 22 Sealing part 22a,22b main surface 23 Solder ball 31 Semiconductor devices 51, 61, 71 IC chip 52,54,62,64,72,74,82,84,92,94 Insulation layer 53,63,73,83,93 wiring layer 81,91 chips

Claims

1. a first semiconductor chip; a second semiconductor chip; a first sealing portion that seals the first semiconductor chip and the second semiconductor chip and has a first main surface and a second main surface located opposite to each other; a bridge chip disposed on the first main surface of the first sealing portion; an electronic component disposed on the first main surface of the first sealing portion; a second sealing portion formed on the first main surface of the first sealing portion, sealing the bridge chip and the electronic component, and having a third main surface opposite to the side facing the first sealing portion; an external terminal disposed on the third main surface of the second sealing portion; Including, the first semiconductor chip has a first electrode; the second semiconductor chip has a second electrode; the bridge chip has internal wiring that electrically connects first electrodes of the first semiconductor chip and second electrodes of the second semiconductor chip; The semiconductor device, wherein the electronic component is a passive component or a voltage regulator.

2. 2. The semiconductor device according to claim 1, Further including a through electrode that penetrates the second sealing portion, The semiconductor device, wherein the external terminal is formed on the through electrode on the third main surface.

3. 3. The semiconductor device according to claim 2, further including a first conductor portion and a second conductor portion sealed in the first sealing portion; the bridge chip has a third electrode and a fourth electrode; the first electrode of the first semiconductor chip and the third electrode of the bridge chip are electrically connected to each other via the first conductor portion; the second electrode of the second semiconductor chip and the fourth electrode of the bridge chip are electrically connected to each other via the second conductor portion; the third electrode and the fourth electrode of the bridge chip are electrically connected to each other via the internal wiring.

4. 4. The semiconductor device according to claim 3, further including a third conductor portion and a fourth conductor portion sealed in the first sealing portion; the second semiconductor chip further includes a fifth electrode; the electronic component has a sixth electrode and a seventh electrode; the fifth electrode of the second semiconductor chip and the sixth electrode of the electronic component are electrically connected to each other via the third conductor portion; the seventh electrode of the electronic component is electrically connected to the through electrode via the fourth conductor portion.

5. a first semiconductor chip; a second semiconductor chip; a first sealing portion that seals the first semiconductor chip and the second semiconductor chip and has a first main surface and a second main surface located opposite to each other; a bridge chip disposed on the first main surface of the first sealing portion; an electronic component disposed on the first main surface of the first sealing portion; a second sealing portion formed on the first main surface of the first sealing portion, sealing the bridge chip and the electronic component, and having a third main surface opposite to the side facing the first sealing portion; an external terminal disposed on the third main surface of the second sealing portion; Including, the first semiconductor chip has a first electrode; the second semiconductor chip has a second electrode and a third electrode; the bridge chip has internal wiring that electrically connects first electrodes of the first semiconductor chip and second electrodes of the second semiconductor chip; The electronic component is interposed in the middle of a conductive path between the third electrode of the second semiconductor chip and the external terminal.

6. 6. The semiconductor device according to claim 5, The semiconductor device, wherein the electronic component is a passive component or a voltage regulator.

7. 6. The semiconductor device according to claim 5, a first conductor portion, a second conductor portion, a third conductor portion, and a fourth conductor portion sealed in the first sealing portion; a through electrode that penetrates the second sealing portion; Further comprising: the external terminal is formed on the through electrode on the third principal surface; the bridge chip has a fourth electrode and a fifth electrode; the electronic component has a sixth electrode and a seventh electrode; the first electrode of the first semiconductor chip and the fourth electrode of the bridge chip are electrically connected to each other via the first conductor portion; the second electrode of the second semiconductor chip and the fifth electrode of the bridge chip are electrically connected to each other via the second conductor portion; the fourth electrode and the fifth electrode of the bridge chip are electrically connected to each other via the internal wiring; the sixth electrode of the electronic component is electrically connected to the third electrode of the second semiconductor chip via the third conductor portion; the seventh electrode of the electronic component is electrically connected to the through electrode via the fourth conductor portion.

8. A method for manufacturing a semiconductor device, comprising the steps of: (a) preparing a first sealing portion that seals a first semiconductor chip and a second semiconductor chip and has a first main surface and a second main surface positioned opposite to each other; (b) mounting an electronic component on the first main surface of the first sealing portion; (c) mounting a bridge chip on the first main surface of the first sealing portion; (d) forming a second sealing portion on the first main surface of the first sealing portion to seal the bridge chip and the electronic component; (e) forming an external terminal on a third main surface of the second sealing portion opposite to the side facing the first sealing portion; where: the first semiconductor chip has a first electrode; the second semiconductor chip has a second electrode; the bridge chip has internal wiring that electrically connects first electrodes of the first semiconductor chip and second electrodes of the second semiconductor chip; The electronic component is a passive component or a voltage regulator.

9. 9. The method for manufacturing a semiconductor device according to claim 8, The method for manufacturing a semiconductor device, wherein the step (c) is carried out after the step (b).

10. 9. The method for manufacturing a semiconductor device according to claim 8, (a1) forming a through electrode on the first main surface of the first sealing portion after the step (a) and before the step (d); and The step (d) (d1) forming the second sealing portion on the first main surface of the first sealing portion so as to cover the bridge chip, the electronic component, and the through electrode; (d2) after the step (d1), polishing the third main surface of the second sealing portion to expose the through electrode from the third main surface of the second sealing portion; and In the step (e), the external terminal is formed on the through electrode exposed from the third main surface of the second sealing portion.

11. A method for manufacturing a semiconductor device, comprising the steps of: (a) preparing a first sealing portion that seals a first semiconductor chip and a second semiconductor chip and has a first main surface and a second main surface positioned opposite to each other; (b) mounting an electronic component on the first main surface of the first sealing portion; (c) mounting a bridge chip on the first main surface of the first sealing portion; (d) forming a second sealing portion on the first main surface of the first sealing portion to seal the bridge chip and the electronic component; (e) forming an external terminal on a third main surface of the second sealing portion opposite to the side facing the first sealing portion; where: the first semiconductor chip has a first electrode; the second semiconductor chip has a second electrode and a third electrode; the bridge chip has internal wiring that electrically connects first electrodes of the first semiconductor chip and second electrodes of the second semiconductor chip; When the step (e) is performed, the electronic component is interposed in the middle of the conductive path between the third electrode of the second semiconductor chip and the external terminal.

12. 12. The method for manufacturing a semiconductor device according to claim 11, The method for manufacturing a semiconductor device, wherein the electronic component is a passive component or a voltage regulator.

13. 12. The method for manufacturing a semiconductor device according to claim 11, The method for manufacturing a semiconductor device, wherein the step (c) is carried out after the step (b).

14. 12. The method for manufacturing a semiconductor device according to claim 11, (a1) forming a through electrode on the first main surface of the first sealing portion after the step (a) and before the step (d); and The step (d) (d1) forming the second sealing portion on the first main surface of the first sealing portion so as to cover the bridge chip, the electronic component, and the through electrode; (d2) after the step (d1), polishing the third main surface of the second sealing portion to expose the through electrode from the third main surface of the second sealing portion; and In the step (e), the external terminal is formed on the through electrode exposed from the third main surface of the second sealing portion.

Images