Semiconductor device

Abstract

To provide a novel display device.SOLUTION: A display device includes a first layer including a driving circuit, a second layer including a plurality of pixel circuits, and a third layer including a plurality of light-emitting elements. The second layer is provided on the first layer, the third layer is provided on the second layer, and a conductive layer is provided between the driving circuit and the pixel circuits. The driving circuit has a function of controlling the operation of the pixel circuits. One of the pixel circuits is electrically connected to one of the light-emitting elements. The pixel circuit has a function of controlling the emission luminance of the light-emitting element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] In recent years, electronic devices equipped with display devices, such as smartphones and tablet terminals, have become widespread. Representative examples of display devices include liquid crystal display devices, organic electroluminescence (EL) elements, light-emitting devices equipped with light-emitting elements such as light-emitting diodes (LEDs), and electronic paper that displays images using electrophoresis or the like.

[0004] For example, the basic structure of an organic EL element is a layer containing a light-emitting organic compound sandwiched between a pair of electrodes. By applying a voltage to this element, light can be emitted from the light-emitting organic compound. A display device using such an organic EL element does not require a backlight, which is necessary in liquid crystal display devices and the like, and therefore can realize a thin, lightweight, high-contrast, and low-power display device. For example, an example of a display device using an organic EL element is described in Patent Document 1.

[0005] Furthermore, Patent Document 2 discloses a circuit configuration that corrects variations in threshold voltage of transistors for each pixel in a pixel circuit that controls the light emission brightness of an organic EL element, thereby improving the display quality of a display device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-324673 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-132816 Summary of the Invention [Problem to be solved by the invention]

[0007] However, depending on the configuration of the organic EL element, a high voltage may be required to drive it, and in order to drive such an organic EL element, a power supply must be provided to generate the high voltage.

[0008] An object of one embodiment of the present invention is to provide a miniaturized display device.An object of one embodiment of the present invention is to provide a display device with high color reproducibility.An object of one embodiment of the present invention is to provide a high-resolution display device.An object of one embodiment of the present invention is to provide a highly reliable display device.An object of one embodiment of the present invention is to provide a display device with reduced power consumption.An object of one embodiment of the present invention is to provide a novel display device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] (1) One embodiment of the present invention is a semiconductor device including first and second transistors, first to fifth switches, first to third capacitors, and a display element, in which the first transistor has a back gate, a gate of the first transistor is electrically connected to the first switch, a second switch and a first capacitor are provided between the gate and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch, a second capacitor is provided between the back gate and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch and a drain of the second transistor, a gate of the second transistor is electrically connected to the fifth switch, a third capacitor is provided between the gate and source of the second transistor, and the source of the second transistor is electrically connected to one terminal of the display element.

[0011] In (1), the first switch may have a function of selecting conduction or non-conduction between the first wiring and the gate of the first transistor. The second switch may have a function of selecting conduction or non-conduction between the gate and source of the first transistor. The third switch may have a function of selecting conduction or non-conduction between the second wiring and the back gate of the first transistor. The fourth switch may have a function of selecting conduction or non-conduction between the third wiring and the source of the first transistor. The fifth switch may have a function of selecting conduction or non-conduction between the fourth wiring and the gate of the second transistor.

[0012] In (1), the first to fifth switches may be transistors. The fourth switch and the fifth switch may be p-channel transistors. The fourth switch and the fifth switch may be transistors containing silicon in a semiconductor layer in which a channel is formed.

[0013] (2) Another embodiment of the present invention is a semiconductor device including first and second transistors, first to fifth switches, first to third capacitors, a first display element, and a second display element, wherein the first transistor has a back gate, the gate of the first transistor is electrically connected to the first switch, a second switch and a first capacitor are provided between the gate and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch, a second capacitor is provided between the back gate and a source of the first transistor, the source of the first transistor is electrically connected to the fourth switch and the drain of the second transistor, the gate of the second transistor is electrically connected to the fifth switch, a third capacitor is provided between the gate and a source of the second transistor, and the source of the second transistor is electrically connected to one terminal of the first display element and one terminal of the second display element.

[0014] In addition, in (2), the first switch may have a function of selecting conduction or non-conduction between the first wiring and the gate of the first transistor. The second switch may have a function of selecting conduction or non-conduction between the gate and source of the first transistor. The third switch may have a function of selecting conduction or non-conduction between the second wiring and the back gate of the first transistor. The fourth switch may have a function of selecting conduction or non-conduction between the third wiring and the source of the first transistor. The fifth switch may have a function of selecting conduction or non-conduction between the fourth wiring and the gate of the second transistor.

[0015] In (2), the first capacitance may have a function of maintaining a potential difference between the gate and source of the first transistor, the second capacitance may have a function of maintaining a potential difference between the back gate and source of the first transistor, and the third capacitance may have a function of maintaining a potential difference between the gate and source of the second transistor.

[0016] In addition, in (2), the drain of the first transistor may be electrically connected to the fifth wiring. For example, the other terminal of the first display element may be electrically connected to the sixth wiring, and the other terminal of the second display element may be electrically connected to the seventh wiring.

[0017] A display device may also be constructed by arranging a plurality of the semiconductor devices described in (2) in a matrix. For example, first display elements may be arranged in odd-numbered rows, and second display elements may be arranged in even-numbered rows. By causing the first display elements to emit light during odd-numbered frame periods and the second display elements to emit light during even-numbered frame periods, a display device having an interlaced driving function can be realized.

[0018] (3) Another embodiment of the present invention includes first to eighth transistors, first to third capacitors, and a display element. A gate of the first transistor and a gate of the sixth transistor are electrically connected to a first wiring. A gate of the third transistor and a gate of the fourth transistor are electrically connected to a second wiring. A gate of the seventh transistor is electrically connected to a third wiring. A gate of the eighth transistor is electrically connected to a fourth wiring. One of a source or a drain of the first transistor is electrically connected to a fifth wiring. The other of the source or the drain of the first transistor is electrically connected to a gate of a second transistor, one of a source or a drain of the third transistor, and one terminal of the first capacitor. One of the source or the drain of the second transistor is electrically connected to a sixth wiring. One of the source or the drain of the fourth transistor is electrically connected to a seventh wiring. The other of the source or the drain of the fourth transistor is electrically connected to one terminal of the second capacitor. one of the source and drain of the seventh transistor is electrically connected to the other of the source or drain of the third transistor, the other terminal of the first capacitor, the other terminal of the second capacitor, one of the source or drain of the fifth transistor, and one of the source or drain of the sixth transistor; one of the source or drain of the seventh transistor is electrically connected to a seventh wiring; a gate of the fifth transistor is electrically connected to the other of the source or drain of the seventh transistor, one of the source or drain of the eighth transistor, and one terminal of the third capacitor; the other of the source or drain of the sixth transistor and the other of the source or drain of the eighth transistor are electrically connected to an eighth wiring; the other of the source or drain of the fifth transistor is electrically connected to the other terminal of the third capacitor and one terminal of a display element; and the other terminal of the display element is electrically connected to a ninth wiring; and the second transistor has a back gate, and the back gate is electrically connected to the other of the source or drain of the fourth transistor and one terminal of the second capacitor.

[0019] In (3), the second transistor may be a transistor in which a semiconductor in which a channel is formed contains an oxide semiconductor. The second transistor includes one of a source and a drain, the other of the source and the drain, a gate, and a backgate. The second transistor may have a function of changing the gate potential and the backgate potential in response to a change in the potential of the other of the source and the drain.

[0020] In (3), the fifth transistor may be a transistor in which a semiconductor in which a channel is formed contains an oxide semiconductor. The fifth transistor includes one of a source or a drain, the other of the source or the drain, and a gate. The fifth transistor may have a function of changing the gate potential in response to a change in the potential of the other of the source or the drain.

[0021] (4) Another embodiment of the present invention is a semiconductor device including first and second transistors, first to sixth switches, first to third capacitors, and a display element, wherein the first transistor has a back gate, a gate of the first transistor is electrically connected to the first switch, a second switch and a first capacitor are provided between the gate and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch, a second capacitor is provided between the back gate and a source of the first transistor, the source of the first transistor is electrically connected to the fourth switch and a drain of the second transistor, a gate of the second transistor is electrically connected to the fifth switch and a sixth switch, a third capacitor is provided between the gate and a source of the second transistor, and the source of the second transistor is electrically connected to the display element.

[0022] Also, in (4), the first switch may have a function of selecting conduction or non-conduction between the first wiring and the gate of the first transistor, the second switch may have a function of selecting conduction or non-conduction between the gate and source of the first transistor, the third switch may have a function of selecting conduction or non-conduction between the second wiring and the back gate of the first transistor, the fourth switch may have a function of selecting conduction or non-conduction between the third wiring and the source of the first transistor, the fifth switch may have a function of selecting conduction or non-conduction between the second wiring and the gate of the second transistor, and the sixth switch may have a function of selecting conduction or non-conduction between the third wiring and the gate of the second transistor.

[0023] Also, in (4), the first capacitance may have a function of maintaining a potential difference between the gate and source of the first transistor, the second capacitance may have a function of maintaining a potential difference between the back gate and source of the first transistor, and the third capacitance may have a function of maintaining a potential difference between the gate and source of the second transistor.

[0024] In addition, in (1), (2), (3), and (4), the oxide semiconductor preferably contains at least one of indium and zinc. The display element may be a single-structure organic EL element or a tandem-structure organic EL element.

[0025] (5) Another embodiment of the present invention is a display device including a first layer including a driver circuit, a second layer including a plurality of pixel circuits, and a third layer including a plurality of light-emitting elements, the second layer being provided over the first layer, the third layer being provided over the second layer, the driver circuit having a function of controlling the operation of the plurality of pixel circuits, one of the plurality of pixel circuits being electrically connected to one of the plurality of light-emitting elements, the pixel circuit having a function of controlling the light-emitting luminance of the light-emitting element, and a conductive layer being provided between the driver circuit and the plurality of pixel circuits.

[0026] In addition, in (5), it is preferable that the conductive layer and the plurality of pixel circuits have overlapping regions. The conductive layer may be in a mesh pattern.

[0027] In (5), the driving circuit may include, for example, a Si transistor. The pixel circuit may include, for example, an OS transistor. The light-emitting element may be, for example, an organic EL element. The light-emitting element may have a tandem structure. [Effects of the Invention]

[0028] According to one embodiment of the present invention, a miniaturized display device can be provided. Alternatively, a display device with high color reproducibility can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, according to one embodiment of the present invention, a display device with reduced power consumption can be provided. Alternatively, a novel display device can be provided.

[0029] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 is a diagram illustrating a semiconductor device. [Figure 2] FIG. 2 is a diagram illustrating the semiconductor device. [Figure 3] FIG. 3 is a diagram illustrating a semiconductor device. [Figure 4] FIG. 4 is a diagram illustrating a semiconductor device. [Figure 5] FIG. 5 is a diagram illustrating a semiconductor device. [Figure 6] FIG. 6 is a diagram illustrating a planar layout of the semiconductor device. [Figure 7] FIG. 7 is a diagram illustrating a semiconductor device. [Figure 8] FIG. 8 is a diagram illustrating a semiconductor device. [Figure 9] FIG. 9 is a diagram illustrating a semiconductor device. [Figure 10]FIG. 10 is a diagram illustrating a semiconductor device. [Figure 11] FIG. 11 is a diagram illustrating a semiconductor device. [Figure 12] FIG. 12 is a diagram illustrating a semiconductor device. [Figure 13] FIG. 13 is a diagram illustrating a semiconductor device. [Figure 14] FIG. 14 is a diagram illustrating a semiconductor device. [Figure 15] FIG. 15 is a diagram illustrating a semiconductor device. [Figure 16] 16A to 16C are diagrams showing circuit symbols for transistors. [Figure 17] FIG. 17 is a timing chart illustrating the operation of the semiconductor device. [Figure 18] FIG. 18 is a diagram illustrating the operation of the semiconductor device. [Figure 19] FIG. 19 is a diagram illustrating the operation of the semiconductor device. [Figure 20] FIG. 20 is a diagram illustrating the operation of the semiconductor device. [Figure 21] FIG. 21 is a diagram illustrating the operation of the semiconductor device. [Figure 22] FIG. 22 is a diagram illustrating the operation of the semiconductor device. [Figure 23] FIG. 23 is a diagram illustrating the operation of the semiconductor device. [Figure 24] FIG. 24 is a diagram illustrating the operation of the semiconductor device. [Figure 25] FIG. 25 is a diagram illustrating a semiconductor device. [Figure 26] FIG. 26 is a timing chart illustrating the operation of the semiconductor device. [Figure 27] FIG. 27 is a diagram illustrating the operation of the semiconductor device. [Figure 28] FIG. 28 is a diagram illustrating the operation of the semiconductor device. [Figure 29] FIG. 29 is a diagram illustrating the operation of the semiconductor device. [Figure 30]FIG. 30 is a diagram illustrating the operation of the semiconductor device. [Figure 31] FIG. 31 is a diagram illustrating the operation of the semiconductor device. [Figure 32] FIG. 32 is a diagram illustrating the operation of the semiconductor device. [Figure 33] FIG. 33 is a diagram illustrating a semiconductor device. [Figure 34] FIG. 34 is a diagram illustrating a semiconductor device. [Figure 35] FIG. 35 is a timing chart illustrating the operation of the semiconductor device. [Figure 36] FIG. 36 is a diagram illustrating the operation of the semiconductor device. [Figure 37] FIG. 37 is a diagram illustrating the operation of the semiconductor device. [Figure 38] FIG. 38 is a diagram illustrating the operation of the semiconductor device. [Figure 39] FIG. 39 is a diagram illustrating the operation of the semiconductor device. [Figure 40] FIG. 40 is a diagram illustrating the operation of the semiconductor device. [Figure 41] FIG. 41 is a diagram illustrating the operation of the semiconductor device. [Figure 42] FIG. 42 is a diagram illustrating a semiconductor device. [Figure 43] FIG. 43 is a diagram illustrating the operation of the semiconductor device. [Figure 44] FIG. 44 is a diagram illustrating a semiconductor device. [Figure 45] FIG. 45 is a diagram illustrating a semiconductor device. [Figure 46] FIG. 46 is a diagram illustrating a semiconductor device. [Figure 47] FIG. 47 is a diagram illustrating a semiconductor device. [Figure 48] FIG. 48 is a diagram illustrating a semiconductor device. [Figure 49] 49A and 49B are diagrams illustrating a semiconductor device. [Figure 50] 50A and 50B are diagrams illustrating a semiconductor device. [Figure 51] FIG. 51 is a diagram illustrating a semiconductor device. [Figure 52] FIG. 52 is a diagram illustrating a semiconductor device. [Figure 53] FIG. 53 is a diagram illustrating a semiconductor device. [Figure 54] FIG. 54 is a diagram illustrating a semiconductor device. [Figure 55] Fig. 55A is a diagram illustrating a display device, and Fig. 55B1 to Fig. 55B7 are diagrams illustrating examples of pixel configurations. [Figure 56] FIG. 56 is a diagram illustrating an example of the configuration of a pixel. [Figure 57] 57A1, 57A2, 57B, and 57C are diagrams for explaining examples of pixel configurations. [Figure 58] 58A to 58D are diagrams illustrating configuration examples of light-emitting elements. [Figure 59] 59A to 59D are diagrams showing configuration examples of light-emitting elements. [Figure 60] 60A to 60D are diagrams showing configuration examples of light-emitting elements. [Figure 61] 61A and 61B are diagrams showing configuration examples of a light-emitting element. [Figure 62] 62A to 62C are diagrams showing configuration examples of light-emitting elements. [Figure 63] 63A and 63B are perspective views of the display device. [Figure 64] Fig. 64A is a perspective view of the display device, and Fig. 64B is a plan view of the display device. [Figure 65] FIG. 65 is a perspective view of the display device. [Figure 66] Fig. 66A is a perspective view of a display device, and Fig. 66B and Fig. 66C are diagrams showing an example of a conductive layer. [Figure 67] FIG. 67 is a perspective view of a display device. [Figure 68] 68A and 68B are perspective views of the display device. [Figure 69]69A to 69C are perspective schematic diagrams of a display module. [Figure 70] FIG. 70 is a cross-sectional view showing an example of a display device. [Figure 71] FIG. 71 is a cross-sectional view showing an example of a display device. [Figure 72] FIG. 72 is a cross-sectional view showing an example of a display device. [Figure 73] FIG. 73 is a cross-sectional view showing an example of a display device. [Figure 74] FIG. 74 is a cross-sectional view showing an example of a display device. [Figure 75] FIG. 75 is a cross-sectional view showing an example of a display device. [Figure 76] Fig. 76A is a block diagram of a display device, and Fig. 76B is a timing chart illustrating the operation of the display device. [Figure 77] Fig. 77A is a block diagram of a display device, and Fig. 77B is a timing chart illustrating the operation of the display device. [Figure 78] Fig. 78A is a block diagram of a display device, and Fig. 78B is a timing chart illustrating the operation of the display device. [Figure 79] Fig. 79A is a top view showing an example of the configuration of a transistor, and Fig. 79B and Fig. 79C are cross-sectional views showing an example of the configuration of a transistor. [Figure 80] Fig. 80A is a diagram explaining the classification of crystal structures, Fig. 80B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Fig. 80C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 81] 81A to 81F are diagrams illustrating an example of an electronic device. [Figure 82] 82A to 82F are diagrams illustrating an example of an electronic device. [Figure 83] 83A and 83B are diagrams illustrating an example of an electronic device. [Figure 84] FIG. 84 is a diagram illustrating an example of an electronic device. [Figure 85]85A to 85C are diagrams showing the evaluation results of the Id-Vd characteristics of the transistors. [Figure 86] FIG. 86 is a diagram showing the evaluation results of the dielectric strength voltage of the transistor. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0032] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0033] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0034] As an example of the case where X and Y are electrically connected, one or more elements (e.g., switches, transistors, capacitance elements, inductors, resistance elements, diodes, display devices, light-emitting devices, loads, etc.) that enable the electrical connection between X and Y can be connected between X and Y.

[0035] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0036] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0037] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0038] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "electrically connected" also includes such cases where one conductive film has the functions of multiple components.

[0039] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value greater than 0 F, a region of wiring having a capacitance value greater than 0 F, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also parasitic capacitance occurring between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0040] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the amount of current flowing between the source and the drain. The two terminals that function as a source or a drain are the input / output terminals of the transistor. One of the two input / output terminals functions as a source and the other as a drain depending on the transistor's conductivity type (n-channel or p-channel) and the level of the potential applied to the three terminals. Therefore, in this specification, the terms source and drain are interchangeable. In addition, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the transistor's structure, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as the first gate, and the other of the gate or backgate of the transistor may be referred to as the second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0041] Furthermore, in this specification and the like, the term "node" can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Furthermore, the term "node" can be rephrased as a terminal, wiring, etc.

[0042] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment, in the claims, etc. Furthermore, for example, a component referred to as "first" in one embodiment of this specification, etc. may be omitted in another embodiment, in the claims, etc.

[0043] Furthermore, in this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "an insulator located on the upper surface of a conductor" can be rephrased as "an insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0044] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0045] Furthermore, in this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0046] Furthermore, in this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0047] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, depending on the situation, terms such as "film" and "layer" may be replaced with other terms without using terms such as "film" and "layer." For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, the term "conductor" may be changed to the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator." Or, the term "insulator" may be changed to the term "insulating layer" or "insulating film."

[0048] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0049] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0050] In addition, in this specification, a "switch" has multiple terminals and has the function of switching (selecting) between conduction and non-conduction between the terminals. For example, when a switch has two terminals and both terminals are conductive, the switch is said to be in a "conductive state" or "on state." When both terminals are non-conductive, the switch is said to be in a "non-conductive state" or "off state." Note that switching between a conductive state or a non-conductive state, or maintaining one of a conductive state or a non-conductive state, is sometimes referred to as "controlling the conductive state."

[0051] In other words, a switch is a device that has the function of controlling whether or not a current flows. Alternatively, a switch is a device that has the function of selecting and switching the path through which a current flows. As an example, an electrical switch, a mechanical switch, etc. can be used. In other words, a switch is not limited to a specific type as long as it can control a current.

[0052] Examples of switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0053] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. Such a switch has a mechanically movable electrode, and the movement of the electrode determines whether the switch is conductive or non-conductive.

[0054] As used herein, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. This therefore includes cases in which the angle is -5° or more and 5° or less. "Substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This therefore includes cases in which the angle is 85° or more and 95° or less. "Substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0055] In this specification, when referring to counting values ​​and measurement values, terms such as "same," "equal," or "uniform" (including synonyms thereof) are used, they are considered to include an error of plus or minus 20%, unless otherwise specified.

[0056] The embodiments described in this specification will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and those skilled in the art will readily understand that various changes in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, top views, etc.

[0057] In addition, in the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited. Note that the drawings are schematic illustrations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations, etc. may be included.

[0058] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0059] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m,n]” may be added to the symbol.

[0060] (Embodiment 1) A semiconductor device 100A according to one embodiment of the present invention will be described. The semiconductor device 100A according to one embodiment of the present invention can be used for a pixel of a display device, for example.

[0061] <Configuration example> An example circuit configuration of the semiconductor device 100A is shown in FIG. 1. The semiconductor device 100A includes a pixel circuit 51A and a light-emitting element 61. The pixel circuit 51A includes transistors M1 to M8 and capacitors C1 to C3. In this embodiment and the like, the transistors M1 to M8 are enhancement-type (normally-off) n-channel field-effect transistors unless otherwise specified. Therefore, their threshold voltages (also referred to as "Vth") are assumed to be greater than 0 V.

[0062] The gate of the transistor M1 is electrically connected to the wiring GLa, one of the source and the drain is electrically connected to the wiring DL, and the other of the source and the drain is electrically connected to the gate of the transistor M2. The transistor M1 has a function of selecting whether to bring the gate of the transistor M2 and the wiring DL into a conductive state or a non-conductive state.

[0063] The gate of the transistor M2 is electrically connected to one terminal of the capacitor C1, one of the source and the drain is electrically connected to the wiring 101, and the other of the source and the drain is electrically connected to the other terminal of the capacitor C1. The transistor M2 also has a backgate. The backgate of the transistor M2 is electrically connected to one terminal of the capacitor C2. The other terminal of the capacitor C2 is electrically connected to the other of the source and the drain of the transistor M2.

[0064] The gate of the transistor M3 is electrically connected to the wiring GLb, one of the source and the drain is electrically connected to one terminal of the capacitor C1, and the other of the source and the drain is electrically connected to the other terminal of the capacitor C1. The transistor M3 has a function of selecting whether to bring the gate and the source of the transistor M2 into a conductive state or a non-conductive state.

[0065] The gate of the transistor M4 is electrically connected to the wiring GLb, one of the source and the drain is electrically connected to the wiring 102, and the other of the source and the drain is electrically connected to one terminal of the capacitor C2. The transistor M4 has a function of selecting whether to establish electrical continuity or non-conduction between the wiring 102 and the one terminal of the capacitor C2.

[0066] The gate of the transistor M5 is electrically connected to one terminal of the capacitor C3, and one of the source and drain is electrically connected to the other of the source and drain of the transistor M2. The other of the source and drain of the transistor M5 is electrically connected to the other terminal of the capacitor C3 and one terminal (e.g., an anode terminal) of the light-emitting element 61. The other terminal (e.g., a cathode terminal) of the light-emitting element 61 is electrically connected to the wiring 104.

[0067] The gate of the transistor M6 is electrically connected to the wiring GLa, one of the source and the drain is electrically connected to the other of the source and the drain of the transistor M2, and the other of the source and the drain is electrically connected to the wiring 103. The transistor M6 has a function of selecting whether to bring the other of the source and the drain of the transistor M2 and the wiring 103 into an electrically conductive state or a non-conductive state.

[0068] The gate of the transistor M7 is electrically connected to the wiring GLc, one of the source and the drain is electrically connected to the wiring 102, and the other of the source and the drain is electrically connected to the gate of the transistor M5. The transistor M7 has a function of selecting whether to bring the gate of the transistor M5 and the wiring 102 into a conductive state or a non-conductive state.

[0069] The gate of the transistor M8 is electrically connected to the wiring GLd, one of the source and the drain is electrically connected to the gate of the transistor M5, and the other of the source and the drain is electrically connected to the wiring 103. The transistor M8 has a function of selecting whether to bring the gate of the transistor M5 and the wiring 103 into an electrically conductive state or a non-conductive state.

[0070] In addition, the region where the other terminals of capacitors C1 and C2, the other of the source or drain of transistor M2, the other of the source or drain of transistor M3, one of the source or drain of transistor M5, and one of the source or drain of transistor M6 are electrically connected is also referred to as node ND1.

[0071] A region where one terminal of the capacitor C2, the back gate of the transistor M2, and the other of the source and drain of the transistor M4 are electrically connected is also referred to as a node ND2.

[0072] A region where the other of the source and the drain of the transistor M1, one of the source and the drain of the transistor M3, one terminal of the capacitor C1, and the gate of the transistor M2 are electrically connected is also referred to as a node ND3.

[0073] A region where the gate of the transistor M5, one terminal of the capacitor C3, the other of the source or drain of the transistor M7, and the one of the source or drain of the transistor M8 are electrically connected is also referred to as a node ND4.

[0074] Capacitor C1 has a function of maintaining the potential difference between the other of the source or drain of transistor M2 and the gate of transistor M2 when node ND3 is floating. Capacitor C2 has a function of maintaining the potential difference between the other of the source or drain of transistor M2 and the back gate of transistor M2 when node ND2 is floating. Capacitor C3 has a function of maintaining the potential difference between the other of the source or drain of transistor M5 and the gate of transistor M5 when node ND4 is floating.

[0075] The pixel circuit 51A according to one embodiment of the present invention can use transistors including various semiconductors. For example, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used. Furthermore, the semiconductor is not limited to a simple semiconductor whose main component is a single element (e.g., silicon (Si) or germanium (Ge)), but can also be a compound semiconductor (e.g., silicon germanium (SiGe) or gallium arsenide (GaAs)), an oxide semiconductor, or the like.

[0076] Although the semiconductor device 100A is configured using n-channel transistors in this embodiment and the like, one embodiment of the present invention is not limited thereto. Some or all of the transistors constituting the semiconductor device 100A may be p-channel transistors.

[0077] 2 shows an example of a circuit configuration of a semiconductor device 100A in which p-channel transistors are used as the transistors M6 to M8 among the transistors included in the pixel circuit 51A. In the circuit configuration shown in FIG. 2, the gate of the transistor M6 is electrically connected to the wiring GLe.

[0078] In addition, the pixel circuit 51A according to one embodiment of the present invention can use transistors with various structures. For example, transistors with various structures such as planar type, FIN type, TRI-GATE type, top gate type, bottom gate type, and double gate type (structure in which gates are arranged above and below a channel) can be used. In addition, as the transistor according to one embodiment of the present invention, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used.

[0079] For example, an OS transistor (a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed) may be used as a transistor included in the pixel circuit 51 A. Since an oxide semiconductor has a band gap of 2 eV or more, its off-state current is significantly small.

[0080] The off-state current of an OS transistor per 1 μm of channel width at room temperature is 1 aA (1 × 10 -18 A) Below, 1zA(1×10 -21 A) or less, or 1yA (1 x 10 -24 The off-state current of a Si transistor (a transistor containing silicon in a semiconductor layer in which a channel is formed) per 1 μm of channel width at room temperature can be 1 fA (1×10 -15 A) More than 1pA (1×10 -12 Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0081] Using OS transistors as the transistors constituting the pixel circuit 51A allows the charge written to each node to be retained for a long period of time. For example, when displaying a still image that does not require rewriting for each frame, it is possible to continue displaying the image even if the operation of the peripheral driving circuit is stopped. This driving method of stopping the operation of the peripheral driving circuit while displaying a still image is also called "idling stop driving." By performing idling stop driving, the power consumption of the display device can be reduced.

[0082] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A semiconductor device including an OS transistor operates stably and has high reliability even in a high-temperature environment.

[0083] Furthermore, OS transistors have a high dielectric strength between the source and drain. By using OS transistors as the transistors constituting the pixel circuit 51A, operation is stable even when there is a large potential difference between the potentials Va and Vc, and a highly reliable semiconductor device can be realized. In particular, it is preferable to use OS transistors as one or both of the transistors M2 and M5.

[0084] The semiconductor layer of the OS transistor preferably contains, for example, indium, M (M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0085] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO") as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used as the semiconductor layer.

[0086] When the semiconductor layer is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. The atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:1:1 or a composition thereabout, In:M:Zn=1:1:1.2 or a composition thereabout, In:M:Zn=1:3:2 or a composition thereabout, In:M:Zn=1:3:4 or a composition thereabout, In:M:Zn=2:1:3 or a composition thereabout, In:M:Zn=3:1:2 or a composition thereabout, or In:M:Zn=4:2:3. or a composition in the vicinity thereof, In:M:Zn=4:2:4.1 or a composition in the vicinity thereof, In:M:Zn=5:1:3 or a composition in the vicinity thereof, In:M:Zn=5:1:6 or a composition in the vicinity thereof, In:M:Zn=5:1:7 or a composition in the vicinity thereof, In:M:Zn=5:1:8 or a composition in the vicinity thereof, In:M:Zn=6:1:6 or a composition in the vicinity thereof, In:M:Zn=5:2:5 or a composition in the vicinity thereof, etc. Note that a composition in the vicinity thereof includes a range of ±30% of the desired atomic ratio.

[0087] For example, when describing a composition with an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, this includes a case where, when the atomic ratio of In is 4, the atomic ratio of Ga is 1 to 3 and the atomic ratio of Zn is 2 to 4. Furthermore, when describing a composition with an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, this includes a case where, when the atomic ratio of In is 5, the atomic ratio of Ga is greater than 0.1 and less than 2 and the atomic ratio of Zn is greater than 5 and less than 7. Furthermore, when describing a composition with an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, this includes a case where, when the atomic ratio of In is 1, the atomic ratio of Ga is greater than 0.1 and less than 2 and the atomic ratio of Zn is greater than 0.1 and less than 2.

[0088] The transistor M2 has a function of controlling the amount of current Ie flowing through the light emitting element 61. That is, the transistor M2 has a function of controlling the amount of light emitted by the light emitting element 61. Therefore, the transistor M2 is also called a "drive transistor."

[0089] Furthermore, the transistor M5 has the function of switching between conduction and non-conduction between the transistor M2 and the light-emitting element 61. When the transistor M5 is in the off state, the light-emitting element 61 does not emit light, and when the transistor M5 is in the on state, the light-emitting element 61 can emit light. Therefore, the transistor M5 is also called a "light-emitting transistor." To ensure that the amount of current determined by the drive transistor flows to the light-emitting element 61, the transistor M5 must be reliably in the on state regardless of the values ​​of the source potential and drain potential.

[0090] Among the transistors that make up the pixel circuit 51A, the transistor M1, the transistor M3, the transistor M4, the transistor M6, the transistor M7, and the transistor M8 function as switches. Therefore, the semiconductor device 100A can be shown as in FIG.

[0091] The transistor M5 also functions as a switch. Therefore, the semiconductor device 100A can also be shown as shown in Figure 4. The transistor M1 and the transistors M3 to M8 can be replaced with elements that can implement the function of a switch.

[0092] The transistors included in the pixel circuit 51A may have a back gate. By providing a back gate, an electric field generated outside the transistor is less likely to affect the channel formation region, thereby stabilizing the operation of the semiconductor device and improving the reliability of the semiconductor device. Furthermore, the threshold voltage of the transistor can be changed by controlling the potential of the back gate.

[0093] 5 shows an example of a circuit configuration of a semiconductor device 100A in which not only the transistor M2 but also the transistor M1 and the transistors M3 to M8 are configured as transistors having back gates. In FIG. 5, the gate and the back gate are electrically connected in the transistor M1 and the transistors M3 to M8. However, it is not necessary to provide a back gate in all the transistors that configure the semiconductor device.

[0094] Alternatively, the gate and the back gate may not be electrically connected, and an arbitrary potential may be supplied to the back gate. Note that the potential supplied to the back gate is not limited to a fixed potential. The potential supplied to the back gate of each transistor included in the semiconductor device may be different or the same for each transistor.

[0095] 6 shows a planar layout diagram of the semiconductor device 100A shown in FIG. 6. In the planar layout diagram shown in FIG. 6, a semiconductor layer 111 of the transistor M1 is provided on a wiring GLa. The wiring GLa and the semiconductor layer 111 have an overlapping region. A part of the wiring GLa functions as a back gate of the transistor M1. A conductor 112 functions as a gate of the transistor M1 and is electrically connected to the wiring GLa through a contact hole 113.

[0096] A semiconductor layer 114 of the transistor M3 is provided over the wiring GLb. The wiring GLb and the semiconductor layer 114 overlap each other. A part of the wiring GLb functions as a back gate of the transistor M3. A conductor 115 functions as a gate of the transistor M3 and is electrically connected to the wiring GLb through a contact hole 116.

[0097] A semiconductor layer 117 of the transistor M4 is provided on the wiring GLb. The wiring GLb and the semiconductor layer 117 overlap each other. A part of the wiring GLb functions as the back gate of the transistor M4. A conductor 118 functions as the gate of the transistor M4 and is electrically connected to the wiring GLb through a contact hole 119.

[0098] A semiconductor layer 121 of the transistor M6 is provided over the wiring GLa. The wiring GLa and the semiconductor layer 121 overlap each other. A part of the wiring GLa functions as the back gate of the transistor M6. A conductor 122 functions as the gate of the transistor M6 and is electrically connected to the wiring GLa through a contact hole 123.

[0099] A semiconductor layer 124 of the transistor M7 is provided over the wiring GLc. The wiring GLc and the semiconductor layer 124 overlap each other. A part of the wiring GLc functions as the back gate of the transistor M7. A conductor 125 functions as the gate of the transistor M7 and is electrically connected to the wiring GLc through a contact hole 126.

[0100] A semiconductor layer 127 of the transistor M8 is provided over the wiring GLd. The wiring GLd and the semiconductor layer 127 overlap each other. A part of the wiring GLd functions as the back gate of the transistor M8. A conductor 128 functions as the gate of the transistor M8 and is electrically connected to the wiring GLd through a contact hole 129.

[0101] One of the source and the drain of the transistor M1 is electrically connected to the wiring DL through a conductive layer 131. The other of the source and the drain of the transistor M1 is electrically connected to a conductive layer 133 through a conductive layer 132.

[0102] A semiconductor layer 134 of the transistor M2 is provided over the conductive layer 136. The conductive layer 136 and the semiconductor layer 134 overlap each other. A part of the conductive layer 136 functions as a back gate of the transistor M2. A conductive layer 135 electrically connected to the conductive layer 133 functions as a gate of the transistor M2.

[0103] One of the source and the drain of the transistor M2 is electrically connected to the wiring 101 through a conductive layer 137. The other of the source and the drain of the transistor M2 is electrically connected to a conductive layer 138. A region where the conductive layer 133 and the conductive layer 138 overlap functions as a capacitor C1. A region where the conductive layer 136 and the conductive layer 138 overlap functions as a capacitor C2.

[0104] In addition, a semiconductor layer 142 of the transistor M5 is provided on the conductive layer 141. The conductive layer 141 and the semiconductor layer 142 have an overlapping region. A part of the conductive layer 141 functions as a back gate of the transistor M5. A conductor 143 functions as a gate of the transistor M5 and is electrically connected to a wiring GLc through a contact hole 144.

[0105] One of the source and the drain of the transistor M5 is electrically connected to the conductive layer 138. The other of the source and the drain of the transistor M5 is electrically connected to the conductive layer 145. The region where the conductive layer 141 and the conductive layer 145 overlap functions as a capacitor C3. The conductive layer 145 is electrically connected to the light-emitting element 61.

[0106] One of the source and the drain of the transistor M5 is electrically connected to the wiring 102 through a conductive layer 146. The other of the source and the drain of the transistor M5 and the other of the source and the drain of the transistor M8 are electrically connected to the conductive layer 141 through a conductive layer 147. The other of the source and the drain of the transistor M8 is electrically connected to the wiring 103 through a conductive layer 148.

[0107] The conductive layer 138 functions as a node ND1, the conductive layer 136 functions as a node ND2, the conductive layer 133 functions as a node ND3, and the conductive layer 141 functions as a node ND4.

[0108] 7, a wiring GLe may be provided to electrically connect the gate of the transistor M6 to the wiring GLe. A wiring GLf may be provided to electrically connect the gate of the transistor M4 to the wiring GLf. By providing the wiring GLe and the wiring GLf, the on and off states of the transistors M1 to M8 can be controlled independently.

[0109] 8, one of the source or drain of the transistor M2 and one of the source or drain of the transistor M7 may be electrically connected to a wiring 101. The wiring 103 and the wiring 104 may be electrically connected. That is, the cathode of the light-emitting element 61 and the wiring 103 may be electrically connected.

[0110] Furthermore, if the gate capacitance of transistor M2 is sufficiently large, capacitor C1 may not be formed. If the back-gate capacitance of transistor M2 is sufficiently large, capacitor C2 may not be formed. If the gate capacitance of transistor M5 is sufficiently large, capacitor C3 may not be formed.

[0111] 9, one of the source or drain of the transistor M2, one of the source or drain of the transistor M4, and one of the source or drain of the transistor M7 may be electrically connected to a wiring 101.

[0112] 10, one of the source or the drain of the transistor M2, one of the source or the drain of the transistor M7, and the other of the source or the drain of the transistor M6 may be electrically connected to a wiring 101.

[0113] 11, one of the source or the drain of the transistor M2, one of the source or the drain of the transistor M4, one of the source or the drain of the transistor M7, and the other of the source or the drain of the transistor M6 may be electrically connected to a wiring 101. In the circuit configurations shown in FIGS. 10 and 11, the formation of the transistor M8 and the wiring GLd can be omitted.

[0114] 12, one of the source and the drain of the transistor M4 may be electrically connected to a wiring 102, and one of the source and the drain of the transistor M7 may be electrically connected to a wiring 106. The other of the source and the drain of the transistor M6 may be electrically connected to a wiring 103, and one of the source and the drain of the transistor M8 may be electrically connected to a wiring 107.

[0115] 13, some or all of the transistors M6, M7, and M8 may be replaced with diodes. By replacing the transistor M7 with a diode, the formation of the wiring GLc can be omitted. By replacing the transistor M8 with a diode, the formation of the wiring GLd can be omitted.

[0116] Also, as shown in FIG. 14, some or all of the transistors M4, M6, M7, and M8 may be replaced with diodes.

[0117] 15, a transistor M9 may be provided between the gate of the transistor M2 and the wiring 103.

[0118] The transistors constituting pixel circuit 51A may be single-gate transistors having one gate between the source and drain, or may be double-gate transistors. Fig. 16A shows an example of a circuit symbol for double-gate transistor 180A.

[0119] The transistor 180A has a configuration in which a transistor Tr1 and a transistor Tr2 are connected in series. Fig. 16A shows a state in which one of the source or drain of the transistor Tr1 is electrically connected to a terminal S, the other of the source or drain of the transistor Tr1 is electrically connected to one of the source or drain of the transistor Tr2, and the other of the source or drain of the transistor Tr2 is electrically connected to a terminal D. Fig. 16A also shows a state in which the gates of the transistors Tr1 and Tr2 are electrically connected and also electrically connected to a terminal G.

[0120] 16A has a function of switching conduction or non-conduction between terminals S and D by changing the potential of terminal G. Thus, the transistor 180A, which is a double-gate transistor, includes transistors Tr1 and Tr2 and functions as a single transistor. That is, in FIG. 16A, one of the source or drain of the transistor 180A is electrically connected to terminal S, the other of the source or drain is electrically connected to terminal D, and the gate is electrically connected to terminal G.

[0121] The transistors that make up pixel circuit 51A may be triple-gate transistors. An example of the circuit symbol for triple-gate transistor 180B is shown in Figure 16B.

[0122] The transistor 180B has a configuration in which a transistor Tr1, a transistor Tr2, and a transistor Tr3 are connected in series. Fig. 16B shows a state in which one of the source or drain of the transistor Tr1 is electrically connected to a terminal S, the other of the source or drain of the transistor Tr1 is electrically connected to one of the source or drain of the transistor Tr2, the other of the source or drain of the transistor Tr2 is electrically connected to one of the source or drain of the transistor Tr3, and the other of the source or drain of the transistor Tr3 is electrically connected to a terminal D. Fig. 16B also shows a state in which the gates of the transistors Tr1, Tr2, and Tr3 are electrically connected and also electrically connected to a terminal G.

[0123] 16B has a function of switching conduction or non-conduction between terminals S and D by changing the potential of terminal G. Thus, the triple-gate transistor 180B includes transistors Tr1, Tr2, and Tr3 and functions as a single transistor. That is, in FIG. 16B, one of the source and drain of the transistor 180B is electrically connected to terminal S, the other of the source and drain is electrically connected to terminal D, and the gate is electrically connected to terminal G.

[0124] Furthermore, the transistors constituting the pixel circuit 51A may be configured such that four or more transistors are connected in series. The transistor 180C shown in Fig. 16C shows a state in which six transistors (transistors Tr1 to Tr6) are connected in series. The gates of the six transistors are also electrically connected to the terminal G.

[0125] 16C has a function of switching conduction or non-conduction between terminal S and terminal D by changing the potential of terminal G. Thus, transistor 180C includes transistors Tr1 to Tr6 and functions as a single transistor. That is, in FIG. 16C, one of the source and drain of transistor 180C is electrically connected to terminal S, the other of the source and drain is electrically connected to terminal D, and the gate is electrically connected to terminal G.

[0126] A transistor having multiple gates electrically connected to each other, such as transistor 180A, transistor 180B, and transistor 180C, may be referred to as a "multi-gate transistor" or a "multi-gate transistor."

[0127] For example, when a transistor is operated in a saturation region, the channel length of the transistor may be increased to improve electrical characteristics in the saturation region. A multi-gate transistor may be used to realize a transistor with a long channel length.

[0128] As the light-emitting element 61, various display elements can be used, such as EL elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), micro LEDs, QLEDs (Quantum-dot Light Emitting Diodes), electron-emitting elements, etc.

[0129] <Example of operation> Next, an operation example of the semiconductor device 100A shown in Fig. 1 will be described with reference to the drawings. Fig. 17 is a timing chart for describing the operation example of the semiconductor device 100A. Figs. 18 to 24 are circuit diagrams for describing the operation example of the semiconductor device 100A.

[0130] A video signal Vdata is supplied to the wiring DL. A potential Va is supplied to the wiring 101, a potential V1 is supplied to the wiring 102, a potential V0 is supplied to the wiring 103, and a potential Vc is supplied to the wiring 104. Either a potential H or a potential L is supplied to each of the wirings GLa, GLb, GLc, and GLd.

[0131] The potential Va is an anode potential, and the potential Vc is a cathode potential. The potential V1 is a potential higher than the potential V0, and is a potential at which a transistor can be turned on by supplying the potential V1 to the gate of the transistor. The potential V0 is a potential at which a transistor can be turned off by supplying the potential V0 to the gate of the transistor. The potential V0 is, for example, 0 V or a potential L. In this embodiment, the potential V0 is set to 0 V, and the potential V1 is set to 3 V. The potential Va is set to 15 V, and the potential Vc is set to 0 V.

[0132] The semiconductor device 100A has a function of controlling, in response to a video signal Vdata supplied from a wiring DL, the magnitude of a current Ie (see FIG. 23) flowing through the light-emitting element 61. The light emission brightness of the light-emitting element 61 is controlled by the magnitude of the current Ie.

[0133] In the drawings, symbols indicating potential such as "H", "L", "V0", or "V1" (also called "potential symbols") may be written adjacent to terminals, wiring, etc. To make it easier to understand potential changes in terminals, wiring, etc., potential symbols attached to terminals, wiring, etc. where potential changes have occurred may be written in boxes. An "x" symbol may also be placed over a transistor in an off state.

[0134] The current Ie flowing through the light-emitting element 61 is mainly determined by the video signal Vdata and the Vth of the transistor M2. Therefore, even if the same video signal Vdata is supplied to multiple pixel circuits, if the Vth of the transistor M2 provided in each pixel circuit differs, the current Ie will differ for each pixel. Therefore, variations in the Vth of the transistor M2 are one cause of deterioration in display quality.

[0135] Therefore, the variation in the current Ie is reduced by obtaining the Vth of the transistor M2 for each pixel. Note that the operation of obtaining the Vth of the transistor M2 is sometimes called a "threshold voltage compensation operation."

[0136] [Vth compensation operation] First, in a period T11, a reset operation is performed. Specifically, a potential H is supplied to the wirings GLa, GLb, and GLd, and a potential L is supplied to the wiring GLc (see FIG. 18). Note that in this specification and elsewhere, "potential H" refers to a potential that turns on an n-channel transistor and turns off a p-channel transistor. Also, "potential L" refers to a potential that turns off an n-channel transistor and turns on a p-channel transistor.

[0137] Therefore, the transistors M1, M3, M4, M6, and M8 are turned on, and the transistor M7 is turned off.

[0138] Furthermore, the potential V0 is supplied to the node ND1 via the transistor M6. Furthermore, the potential V0 is supplied to the node ND3 via the transistors M6 and M3. Furthermore, the potential V1 is supplied to the node ND2 via the transistor M4. Furthermore, the potential V0 is supplied to the node ND4 via the transistor M8. Therefore, the transistor M5 is turned off.

[0139] In the period T11, the wiring DL and the wiring 103 are brought into electrical continuity through the transistors M1, M3, and M6. Therefore, in the period T11, it is preferable that the wiring DL and the wiring 103 be set to the same potential or that the wiring DL be set in a floating state. In addition, when the pixel circuit 51A has the configuration shown in FIG. 7, the wiring GLa and the wiring GLe are separated from each other, and therefore, a reset operation can be performed in the period T11 by supplying a potential L to the wiring GLa and a potential H to the wiring GLe.

[0140] Next, in a period T12, a potential L is supplied to the wiring GLa (see FIG. 19), which turns off the transistor M1 and the transistor M6.

[0141] Because the potential of the node ND2 is the potential V1, the transistor M2 is on. Therefore, the potential of the node ND1 increases through the wiring 101 and the transistor M2. In addition, because the transistor M3 is also on, the potential of the node ND3 also increases. Specifically, the potentials of the nodes ND1 and ND3 increase to a value obtained by subtracting the Vth of the transistor M2 from the potential V1.

[0142] Next, in a period T13, a potential L is supplied to the wiring GLb (see FIG. 20). As a result, the transistors M3 and M4 are turned off. Therefore, the nodes ND1, ND2, and ND3 are brought into a floating state, and the charges supplied to the respective nodes are held.

[0143] [Data write operation] In a period T14, a potential H is supplied to the wiring GLa, a potential H is supplied to the wiring GLc, and a potential L is supplied to the wiring GLd (see FIG. 21). Then, the transistor M1 is turned on, and the video signal Vdata is supplied to the node ND3. In addition, the transistor M6 is turned on, and the potential V0 is supplied to the node ND1.

[0144] Because the nodes ND1 and ND2 are capacitively coupled via the capacitor C2, when the potential of the node ND1 changes from V1-Vth to V0, the potential of the node ND2 also changes in the same way. In this embodiment and the like, the potential V0 is 0 V, so the potential of the node ND2 is expressed as the potential V1-(potential V1-Vth). That is, the potential of the node ND2 becomes Vth.

[0145] Furthermore, the transistor M7 is turned on and the transistor M8 is turned off, so that the potential V1 is supplied to the node ND4, and the transistor M5 is turned on, so that the potential of the anode terminal of the light-emitting element 61 becomes the potential V0.

[0146] Next, in a period T15, the potential L is supplied to the wiring GLc (see FIG. 22), which turns off the transistor M7 and puts the node ND4 in a floating state.

[0147] [Light Emitting Operation] In period T16, a potential L is supplied to the wiring GLa (see FIG. 23). This turns off the transistors M1 and M6. A current flows from the wiring 101 to the wiring 104. That is, the current Ie flows to the light-emitting element 61, and the light-emitting element 61 emits light with a luminance corresponding to the current Ie. Furthermore, when a current flows from the wiring 101 to the wiring 104, the potentials of the node ND1 and the anode terminal of the light-emitting element 61 increase.

[0148] Furthermore, nodes ND2 and ND3 are floating. Nodes ND1 and ND3 are capacitively coupled via capacitor C1. During period T16, when the potential of node ND1 changes from potential V0 to potential Va1, the potential of node ND3 also changes. Here, the potential of node ND3 becomes the video signal Vdata plus potential Va1. That is, even if the source potential of transistor M2 changes, the potential difference (voltage) between the gate and source of transistor M2 remains the video signal Vdata.

[0149] Similarly, the potential of the node ND2 becomes Vth+potential Va1 following the change in the potential of the node ND1, so that the potential difference between the back gate and source of the transistor M2 remains Vth.

[0150] Furthermore, the anode terminal of the light-emitting element 61 and node ND4 are capacitively coupled via capacitor C3. Therefore, when the potential of the anode terminal of the light-emitting element 61 changes from potential V0 to potential Va2, the potential of node ND4 also changes similarly. Here, the potential of node ND4 becomes potential V1 + potential Va2. That is, even if the potential of the anode terminal of the light-emitting element 61 changes, the potential difference (voltage) between the gate and source of transistor M5 is maintained at potential V1 - potential V0.

[0151] For example, if the gate of transistor M5 is at a fixed potential, increasing the source potential of transistor M5 reduces the potential difference between the gate and source. When the potential difference between the gate and source falls below the threshold voltage of transistor M5, transistor M5 turns off. Therefore, if the anode potential is increased, a high potential must also be supplied to the gate, which requires an additional power supply or power circuit.

[0152] In the semiconductor device 100A according to one embodiment of the present invention, by providing a capacitor C3 between the gate and source of the transistor M5 to form a bootstrap circuit, the transistor M5 can be maintained in an on state without adding a power supply circuit even when the anode potential is increased. This allows a stable supply of the current Ie to the light-emitting element 61. The capacitor C3 may also be referred to as a "bootstrap capacitor." Furthermore, the capacitors C1 and C2 each function as a bootstrap capacitor.

[0153] The semiconductor device 100A according to one embodiment of the present invention can be suitably used not only for a light-emitting element having a single structure but also for a light-emitting element having a tandem structure that requires a higher driving voltage than a light-emitting element having a single structure. The structure of the light-emitting element will be described later.

[0154] As described above, the amount of current Ie flowing through the light-emitting element 61 is determined by the video signal Vdata and the Vth of the transistor M2. In the semiconductor device 100A according to one aspect of the present invention, the amount of current Ie flowing through the light-emitting element 61 can be controlled by the video signal Vdata by performing a threshold compensation operation.

[0155] Since the light emission luminance of the light-emitting element 61 is controlled by the video signal Vdata, it is necessary to reliably keep the transistor M5 in the on state during light emission. In the semiconductor device 100A according to one embodiment of the present invention, the transistor M5 can be reliably kept in the on state during light emission. When the semiconductor device 100A according to one embodiment of the present invention is used in a display device, accurate control of the current Ie becomes possible, thereby improving color reproducibility of intermediate tones. Therefore, the display quality of the display device can be improved.

[0156] [Quenching operation] In period T17, a potential H is supplied to the wiring GLd (see FIG. 24). This turns on the transistor M8. This causes the potential V0 to be supplied to the node ND4 from the wiring 103, turning off the transistor M5. When the transistor M5 turns off, no current flows through the light-emitting element 61, and the light-emitting element 61 stops emitting light.

[0157] Display devices that use light-emitting elements such as EL elements as display elements can keep the light-emitting elements lit during one frame period. This type of driving method is also called "hold type" or "hold type driving." By using hold type driving as the driving method for a display device, it is possible to reduce flickering on the display screen. On the other hand, hold type driving is prone to causing afterimages and blurred images when displaying moving images. The resolution perceived by humans when displaying moving images is also called "video resolution." In other words, hold type driving is prone to reducing video resolution.

[0158] There is also a known "black insertion drive" that can improve image blur and afterimages in moving image displays. "Black insertion drive" is also called "pseudo-impulse type" or "pseudo-impulse type drive." Black insertion drive is a drive method that displays black every other frame or for a certain period of time within one frame.

[0159] The semiconductor device 100A according to one embodiment of the present invention can easily realize black insertion driving by performing a light-extinguishing operation. A display device using the semiconductor device 100A according to one embodiment of the present invention is less likely to experience a decrease in moving image resolution, and can realize high-quality moving image display.

[0160] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0161] (Embodiment 2) In this embodiment, a semiconductor device 100B according to one embodiment of the present invention will be described. The semiconductor device 100B is a modified example of the semiconductor device 100A. Therefore, to avoid repetition of the description, differences between the semiconductor device 100B and the semiconductor device 100A will be mainly described.

[0162] <Configuration example> 25 shows an example of a circuit configuration of the semiconductor device 100B. The semiconductor device 100B includes a pixel circuit 51B and a light-emitting element 61. The pixel circuit 51B has a configuration in which the transistor M8 is removed from the pixel circuit 51A. This allows the wiring GLd electrically connected to the gate of the transistor M8 to be eliminated. In addition, one of the source and drain of the transistor M7 is electrically connected to the wiring GLc, and the gate of the transistor M7 is electrically connected to the wiring 105.

[0163] <Example of operation> Next, an example of the operation of the semiconductor device 100B will be described with reference to the drawings. Fig. 26 is a timing chart for explaining the example of the operation of the semiconductor device 100B. Figs. 27 to 32 are circuit diagrams for explaining the example of the operation of the semiconductor device 100B.

[0164] A potential V2 is supplied to the wiring 105. The potential V2 is higher than the potential V1. The potential V2 is lower than or equal to the potential H. In this embodiment and the like, the potential V2 is set to 6V.

[0165] [Vth compensation operation] First, in a period T21, a reset operation is performed. Specifically, a potential H is supplied to the wiring GLa and the wiring GLb, and a potential L is supplied to the wiring GLc (see FIG. 27). Therefore, the transistors M1, M3, M4, M6, and M7 are turned on.

[0166] Furthermore, the potential V0 is supplied to the node ND1 via the transistor M6. Furthermore, the potential V0 is supplied to the node ND3 via the transistors M6 and M3. Furthermore, the potential V1 is supplied to the node ND2 via the transistor M4. Furthermore, the potential L is supplied to the node ND4 via the transistor M7. Therefore, the transistor M5 is turned off.

[0167] In addition, similarly to the period T11 described above, also in the period T21, it is preferable that the wiring DL and the wiring 103 have the same potential or the wiring DL be in a floating state.

[0168] Next, in period T22, potential L is supplied to the wiring GLa (see FIG. 28). As a result, the transistors M1 and M6 are turned off. As in period T12, the potentials of the nodes ND1 and ND3 increase to a value obtained by subtracting the Vth of the transistor M2 from the potential V1.

[0169] Next, in a period T23, a potential L is supplied to the wiring GLb (see FIG. 29). As a result, the transistors M3 and M4 are turned off. The nodes ND1, ND2, and ND3 are brought into a floating state, and the charges supplied to the respective nodes are held.

[0170] [Data write operation] In period T24, a potential H is supplied to the wiring GLa, and a potential H is supplied to the wiring GLc (see FIG. 30). Then, the transistor M1 is turned on, and the video signal Vdata is supplied to the node ND3. The transistor M6 is turned on, and the potential V0 is supplied to the node ND1. As in the period T14 described above, the potential of the node ND2 becomes Vth.

[0171] Furthermore, because the transistor M7 is on, charge is supplied from the wiring GLc to the node ND4. The potential of the node ND4 rises to a value obtained by subtracting the Vth of the transistor M7 from the potential H. In this embodiment and other cases, the potential H is 6 V. If the Vth of the transistors M5 and M7 is 1 V, the potential of the node ND4 (potential H - Vth) becomes 5 V. Therefore, the transistor M5 is turned on.

[0172] [Light Emitting Operation] In period T25, potential L is supplied to the wiring GLa (see FIG. 31). This turns off the transistors M1 and M6. As in the previously described period T16, current flows from the wiring 101 to the wiring 104, causing the light-emitting element 61 to emit light with a luminance corresponding to the current Ie. Furthermore, the potentials of the node ND1 and the anode terminal of the light-emitting element 61 increase. The potential of the node ND1 becomes potential Va1, and the potential of the anode terminal becomes potential Va2. Furthermore, the potential of the node ND3 becomes video signal Vdata+potential Va1, and the potential of the node ND2 becomes Vth+potential Va1.

[0173] The node ND4 is in a floating state, and a potential difference between the node ND4 and the anode terminal is maintained via the capacitor C3. Therefore, the potential of the node ND4 changes in accordance with the change in the potential of the anode terminal of the light-emitting element 61. When the potential of the anode terminal rises from potential V0 to potential Va2, the potential of the node ND4 becomes potential H-Vth+potential Va2. In other words, even if the potential of the anode terminal, which corresponds to the source side of the transistor M5, rises, the on state of the transistor M5 is reliably maintained.

[0174] In this embodiment, the potential H and the potential V2 are both 6 V (the same potential). Therefore, the potential of the node ND4 becomes higher than the potential of one of the source and drain of the transistor M7 and the potential of the gate, turning off the transistor M7.

[0175] [Quenching operation] In a period T26, a potential L is supplied to the wiring GLc (see FIG. 32). Then, the transistor M7 is turned on, and the potential of the node ND4 becomes L. When the potential of the node ND4 becomes L, the transistor M5 is turned off, and the light-emitting element 61 stops emitting light.

[0176] Like the semiconductor device 100A, the semiconductor device 100B can be suitably used not only for light-emitting elements with a single structure but also for light-emitting elements with a tandem structure that require a higher driving voltage than a single structure. Furthermore, like the semiconductor device 100A, the semiconductor device 100B can perform black insertion driving. A display device using the semiconductor device 100B according to one embodiment of the present invention is less likely to experience a decrease in video resolution, and can display videos with high display quality.

[0177] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0178] (Embodiment 3) In this embodiment, a semiconductor device 100C according to one embodiment of the present invention will be described. The semiconductor device 100C is a modified example of the semiconductor device 100B. Therefore, the semiconductor device 100C is also a modified example of the semiconductor device 100A. To reduce repetition of the description, differences between the semiconductor device 100C and the semiconductor device 100A and the semiconductor device 100B will be mainly described.

[0179] <Configuration example> An example circuit configuration of the semiconductor device 100C is shown in FIG. 33. The semiconductor device 100C includes a pixel circuit 51C and a light-emitting element 61. The pixel circuit 51C differs from the pixel circuit 51B in that the gate of the transistor M7 is electrically connected to the wiring GLa. Therefore, the wiring 105 shown in FIG. 25 does not need to be provided. Therefore, the formation of the wiring 105 can be omitted.

[0180] Among the transistors constituting the pixel circuit 51C, the transistor M1, the transistor M3, the transistor M4, the transistor M6, and the transistor M7 function as switches. Therefore, the semiconductor device 100C can be shown as in FIG.

[0181] <Example of operation> Next, an example of the operation of the semiconductor device 100C will be described with reference to the drawings. Fig. 35 is a timing chart for explaining the example of the operation of the semiconductor device 100C. Figs. 36 to 41 are circuit diagrams for explaining the example of the operation of the semiconductor device 100C.

[0182] [Vth compensation operation] First, in period T31, the same reset operation as in period T21 is performed. Specifically, a potential H is supplied to the wiring GLa and wiring GLb, and a potential L is supplied to the wiring GLc (see FIG. 36). In period T31, transistors M1, M3, M4, M6, and M7 are turned on.

[0183] Furthermore, the potential V0 is supplied to the node ND1 via the transistor M6. Furthermore, the potential V0 is supplied to the node ND3 via the transistors M6 and M3. Furthermore, the potential V1 is supplied to the node ND2 via the transistor M4. Furthermore, the potential L is supplied to the node ND4 via the transistor M7. Therefore, the transistor M5 is turned off.

[0184] Also in the period T31, similarly to the period T21 described above, it is preferable that the wiring DL and the wiring 103 have the same potential or the wiring DL be in a floating state.

[0185] Next, in period T32, potential L is supplied to the wiring GLa (see FIG. 37). This turns off the transistors M1, M6, and M7. As in the aforementioned period T12, the potentials of the nodes ND1 and ND3 increase to a value obtained by subtracting the Vth of the transistor M2 from the potential V1. Furthermore, the node ND4 is brought into a floating state, and the charge supplied to the node ND4 is held.

[0186] Next, in a period T33, a potential L is supplied to the wiring GLb (see FIG. 38). As a result, the transistors M3 and M4 are turned off. The nodes ND1, ND2, and ND3 are brought into a floating state, and the charges supplied to the respective nodes are held.

[0187] [Data write operation] In period T34, a potential H is supplied to the wiring GLa, and a potential H is supplied to the wiring GLc (see FIG. 39). Then, the transistor M1 is turned on, and the video signal Vdata is supplied to the node ND3. The transistor M6 is turned on, and the potential V0 is supplied to the node ND1. As in the period T24 described above, the potential of the node ND2 becomes Vth.

[0188] Furthermore, the transistor M7 is turned on, and charge is supplied to the node ND4 from the wiring GLc. The potential of the node ND4 rises to a value obtained by subtracting the Vth of the transistor M7 from the potential H. In this embodiment and other cases, if the potential H is 6 V and the Vth of the transistors M5 and M7 is 1 V, the potential of the node ND4 (potential H - Vth) becomes 5 V. Therefore, the transistor M5 is turned on.

[0189] [Light Emitting Operation] In period T35, potential L is supplied to the wiring GLa (see FIG. 40). This turns off the transistors M1 and M6. As in the previously described period T25, current flows from the wiring 101 to the wiring 104, causing the light-emitting element 61 to emit light with a luminance corresponding to the current Ie. At this time, the potentials of the node ND1 and the anode terminal of the light-emitting element 61 increase. The potential of the node ND1 becomes potential Va1, and the potential of the anode terminal becomes potential Va2. The potential of the node ND3 becomes video signal Vdata+potential Va1, and the potential of the node ND2 becomes Vth+potential Va1.

[0190] The node ND4 is in a floating state, and the potential difference between the node ND4 and the anode terminal is maintained via the capacitor C3. Therefore, the potential of the node ND4 changes in accordance with the change in the potential of the anode terminal. When the potential of the anode terminal rises from potential V0 to potential Va2, the potential of the node ND4 becomes potential H-Vth+potential Va2. In other words, even if the potential of the anode terminal, which corresponds to the source side of the transistor M5, rises, the on state of the transistor M5 is reliably maintained.

[0191] [Quenching operation] In a period T36, a potential H is supplied to the wiring GLa, and a potential L is supplied to the wiring GLc (see FIG. 41). Then, the transistors M1, M6, and M7 are turned on, the potential of the node ND1 becomes the potential V0, and the potential of the node ND4 becomes the L potential. When the potential of the node ND4 becomes the L potential, the transistor M5 is turned off, and the light-emitting element 61 stops emitting light.

[0192] During period T36, a video signal Vdata to be written to another semiconductor device 100C electrically connected to the wiring DL may be supplied to node ND3 via transistor M1, but since transistor M5 is in the off state, this does not affect the extinction operation.

[0193] Like the semiconductor devices 100A and 100B, the semiconductor device 100C can be suitably used not only for light-emitting devices with a single structure but also for light-emitting devices with a tandem structure that require a higher driving voltage than a single structure. Furthermore, like the semiconductor devices 100A and 100B, the semiconductor device 100C can perform black insertion driving. A display device using the semiconductor device 100C according to one embodiment of the present invention is less likely to experience a decrease in video resolution, and can display videos with high display quality.

[0194] <Variation 1> Fig. 42 shows a semiconductor device 100Ca, which is a modified example of the semiconductor device 100C. The semiconductor device 100Ca shown in Fig. 42 includes a pixel circuit 51Ca. The pixel circuit 51Ca differs from the pixel circuit 51C shown in Fig. 33 in that a transistor M8 is provided between the line GLc and the node ND4.

[0195] Specifically, the gate of the transistor M8 is electrically connected to the wiring GLb, one of the source and the drain is electrically connected to the wiring GLc, and the other of the source and the drain is electrically connected to the node ND4.

[0196] In the circuit configuration example shown in FIG. 33, during the period T32 in which the Vth compensation operation is performed, the node ND4 is in a floating state, so the potential of the node ND4 may fluctuate, causing the transistor M5 to approach an on state.

[0197] 43 is a circuit diagram showing the operating state of the semiconductor device 100Ca shown in FIG. 42 during period T32. By providing transistor M8, node ND4 is prevented from floating during period T32 when the Vth compensation operation is performed, and the potential of node ND4 can be fixed to potential L. By providing transistor M8, an accurate Vth compensation operation can be achieved. This improves the display quality of the semiconductor device 100Ca.

[0198] <Variation 2> FIG. 44 shows a semiconductor device 100Cb, which is a modification of the semiconductor device 100C shown in FIG. 33. The semiconductor device 100Cb includes a pixel circuit 51Cb. The pixel circuit 51Cb differs from the pixel circuit 51C in that p-channel transistors are used for the transistors M6 and M7. The gates of the transistors M6 and M7 are electrically connected to the wiring GLd. As described in the above embodiment, p-channel transistors may be used for at least some of the transistors constituting the semiconductor device 100C.

[0199] As described in the above embodiment, transistors including various semiconductors can be used as transistors constituting a semiconductor device. For example, single crystal silicon or polycrystalline silicon may be used as a p-channel transistor. Low temperature polysilicon (LTPS) may be used as polycrystalline silicon.

[0200] When transistors M1 to M5 are formed as n-channel transistors and transistors M6 and M7 are formed as p-channel transistors, for example, an n-channel OS transistor may be stacked on top of a p-channel Si transistor using single crystal silicon for its semiconductor layer.

[0201] In FIG. 44, a region 51a including a Si transistor and a region 51b including an OS transistor in a pixel circuit 51Cb are indicated by two-dot chain lines.

[0202] For example, the semiconductor device 100Cb may have a stacked structure of layers 40, 50, and 60. FIG. 45 is a perspective schematic diagram of the semiconductor device 100Cb having a stacked structure of layers 40, 50, and 60. FIG. 45 illustrates an example in which p-channel Si transistors M6 and M7 are formed in the layer 40, and n-channel OS transistors M1 to M5 are formed in the layer 50. Thus, a region 51a is formed in the layer 40, and a region 51b is formed in the layer 50 (not shown in FIG. 45). That is, the regions 51a and 51b can be provided overlapping each other. FIG. 45 also illustrates an example in which a light-emitting element 61 is formed in the layer 60.

[0203] In FIG. 45, some of the transistors constituting the pixel circuit 51Cb are provided on layer 40, and the other part is provided on layer 50. By stacking the transistors constituting the pixel circuit 51Cb, the area occupied by the semiconductor device 100Cb can be reduced. This allows for an increase in the packaging density of the semiconductor device 100Cb. Furthermore, restrictions on the arrangement and size of the transistors constituting the semiconductor device 100Cb are relaxed, thereby increasing the degree of freedom in designing the semiconductor device. This allows for an increase in the reliability of the semiconductor device.

[0204] Furthermore, by using a combination of a Si transistor, which operates faster than an OS transistor, and an OS transistor, which has a low off-state current, in the semiconductor device 100Cb, it is possible to improve the operating speed and reduce power consumption.

[0205] For example, in the semiconductor device 100Cb, a high-speed reset operation can be achieved by using a Si transistor. Furthermore, the video signal Vdata written to the node ND3 can be retained for a long time by using an OS transistor. Therefore, in a display device using the semiconductor device 100Cb or the like as a pixel, power consumption can be reduced by performing idling stop driving when displaying a still image or by reducing the frame frequency. By using an OS transistor, the gradation of the pixel can be maintained even if the frame frequency is significantly reduced (for example, 1 fps or less).

[0206] Furthermore, when the light emitting element 61 is a bottom emission type light emitting element, the layer 60 may be provided below the layers 40 and 50. The layer 40 may also be formed on the layer 50.

[0207] <Variation 3> 46 shows a semiconductor device 100Cc, which is a variation of the semiconductor device 100C. The semiconductor device 100Cc includes a pixel circuit 51Cc. Of the transistors M1 to M7 included in the pixel circuit 51C, the pixel circuit 51Cc uses n-channel OS transistors for the transistors M2 and M5, and p-channel Si transistors for the other transistors.

[0208] <Variation 4> FIG. 47 shows a semiconductor device 100Cd, which is a modification of the semiconductor device 100C. The semiconductor device 100Cd includes a pixel circuit 51Cd. Among the transistors M1 to M7 included in the pixel circuit 51C, the pixel circuit 51Cd uses p-channel Si transistors for the transistors M5 and M6, and n-channel OS transistors for the transistors M1 to M4. The gate of the transistor M6 is electrically connected to a wiring GLd. The transistor M7 and the capacitor C3 are not provided. By using a p-channel transistor for the transistor M5, the transistor M7 and the capacitor C3 can be omitted.

[0209] <Variation 5> 48 shows a semiconductor device 100Ce, which is a modification of the semiconductor device 100Cd. As shown in FIG. 48, a p-channel Si transistor may be used as the transistor M5, and n-channel OS transistors may be used as the transistors M1 to M4 and the transistor M6. The gate of the transistor M6 is electrically connected to the wiring GLa.

[0210] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0211] (Fourth embodiment) In this embodiment, a semiconductor device 100D including four transistors, one capacitor, and one light-emitting element will be described. An example circuit configuration of the semiconductor device 100D is shown in Fig. 49A. The semiconductor device 100D includes a pixel circuit 51D and a light-emitting element 61. The pixel circuit 51D includes transistors M1 to M4 and a capacitor C1.

[0212] The gate of the transistor M1 is electrically connected to the wiring GLa, one of the source and the drain is electrically connected to the wiring DL, and the other of the source and the drain is electrically connected to the gate of the transistor M2. The transistor M1 has a function of selecting whether to bring the gate of the transistor M2 and the wiring DL into a conductive state or a non-conductive state.

[0213] The gate of the transistor M2 is electrically connected to one terminal of the capacitor C1, one of the source and the drain is electrically connected to the wiring 101, and the other of the source and the drain is electrically connected to the other terminal of the capacitor C1. The transistor M2 also has a backgate. The backgate of the transistor M2 is electrically connected to the other terminal of the capacitor C1.

[0214] The gate of the transistor M3 is electrically connected to the wiring GLc, one of the source and the drain is electrically connected to one terminal of the capacitor C1, and the other of the source and the drain is electrically connected to the wiring 103. The transistor M3 has a function of selecting whether to bring the gate of the transistor M2 and the wiring 103 into a conductive state or a non-conductive state.

[0215] The gate of the transistor M4 is electrically connected to the wiring GLb, and one of the source and the drain of the transistor M4 is electrically connected to the other of the source and the drain of the transistor M2. The other of the source and the drain of the transistor M4 is electrically connected to the wiring 103. The transistor M4 has a function of selecting whether to bring the wiring 103 and the other of the source and the drain of the transistor M2 into a conductive state or a non-conductive state.

[0216] The other of the source and drain of the transistor M2 is electrically connected to one terminal (for example, an anode terminal) of the light emitting element 61. The other terminal (for example, a cathode terminal) of the light emitting element 61 is electrically connected to the wiring 104.

[0217] A region where one terminal of the capacitor C1, the other of the source and the drain of the transistor M1, the gate of the transistor M2, and the one of the source and the drain of the transistor M3 are electrically connected is also referred to as a node ND1.

[0218] A region where the other terminal of the capacitor C1, the other of the source or drain of the transistor M2, and one terminal of the light-emitting element 61 are electrically connected is also referred to as a node ND2.

[0219] 49B, a p-channel transistor may be used as the transistor M2. In this case, the other terminal of the capacitor C1 is electrically connected to the wiring 101.

[0220] According to the semiconductor device 100D of this embodiment, the number of transistors can be reduced, and therefore the occupied area can be reduced.

[0221] 50A, a semiconductor device 100E may be provided which includes four p-channel transistors, two capacitors, and one light-emitting element. The semiconductor device 100E includes a pixel circuit 51E and a light-emitting element 61. The pixel circuit 51E includes transistors M1 to M4, a capacitor C1, and a capacitor C2.

[0222] The gate of the transistor M1 is electrically connected to the wiring GLa, one of the source and the drain is electrically connected to the wiring DL, and the other of the source and the drain is electrically connected to the gate of the transistor M3. The transistor M1 has a function of selecting whether to bring the gate of the transistor M3 and the wiring DL into a conductive state or a non-conductive state.

[0223] The gate of the transistor M2 is electrically connected to the wiring GLb, one of the source and the drain is electrically connected to the wiring 101, and the other of the source and the drain is electrically connected to the one of the source and the drain of the transistor M3.

[0224] The other of the source and the drain of the transistor M3 is electrically connected to the other of the source and the drain of the transistor M4. The gate of the transistor M4 is electrically connected to the wiring GLc, and the other of the source and the drain is electrically connected to the wiring 103.

[0225] The other of the source and the drain of the transistor M3 is electrically connected to one terminal of the light-emitting element 61. The other terminal of the light-emitting element 61 is electrically connected to the wiring 104.

[0226] One terminal of the capacitor C1 is electrically connected to one of the source and drain of the transistor M3. The other terminal of the capacitor C1 is electrically connected to the gate of the transistor M3. One terminal of the capacitor C2 is electrically connected to the wiring 101. The other terminal of the capacitor C2 is electrically connected to one terminal of the capacitor C1.

[0227] As shown in FIG. 50B, n-channel transistors may be used for the transistors M1 and M4.

[0228] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0229] (Embodiment 5) In this embodiment, a semiconductor device 100F according to one embodiment of the present invention will be described. The semiconductor device 100F is a modified example of the semiconductor device 100C shown in Fig. 41. To avoid repetition of the description, differences between the semiconductor device 100F and the semiconductor device 100C shown in Fig. 41 will be mainly described.

[0230] <Configuration example> An example circuit configuration of the semiconductor device 100F is shown in Fig. 51. The semiconductor device 100F includes a pixel circuit 51F, a light-emitting element 61a, and a light-emitting element 61b. The pixel circuit 51F has the same configuration as the pixel circuit 51C shown in Fig. 41, except that the other of the source or the drain of the transistor M5 is electrically connected to one terminal (e.g., the anode terminal) of the light-emitting element 61a and one terminal (e.g., the anode terminal) of the light-emitting element 61b.

[0231] The other terminal (for example, cathode terminal) of the light emitting element 61a is electrically connected to the wiring 104a, and the other terminal (for example, cathode terminal) of the light emitting element 61b is electrically connected to the wiring 104b.

[0232] Among the transistors constituting the pixel circuit 51F, the transistor M1, the transistor M3, the transistor M4, the transistor M6, and the transistor M7 function as switches. Therefore, the semiconductor device 100F can be shown as in FIG.

[0233] <Example of operation> The semiconductor device 100F can control the light emission of the light-emitting elements 61a and 61b by controlling the potentials of the wirings 104a and 104b. For example, to make the light-emitting element 61a emit light, a potential Vc is supplied to the wiring 104a and a potential equal to or greater than the potential Va is supplied to the wiring 104b. To make the light-emitting element 61b emit light, a potential Vc is supplied to the wiring 104b and a potential equal to or greater than the potential Va is supplied to the wiring 104a.

[0234] In addition, when it is desired to make both the light-emitting element 61a and the light-emitting element 61b emit light, the potential Vc may be supplied to both the wiring 104a and the wiring 104b.

[0235] In the semiconductor device 100F, one pixel circuit 51F can control the emission of two light-emitting elements 61 (light-emitting element 61a and light-emitting element 61b). This reduces the area occupied by the pixel circuit per pixel, making it easier to improve the pixel density of the display device. Furthermore, the reduction in the area required for one pixel circuit increases the design freedom of the semiconductor device and the display device. This makes it easier to achieve high functionality and improved reliability of the semiconductor device and the display device.

[0236] The configuration shown in this embodiment is also applicable to the semiconductor device 100A and the semiconductor device 100B.

[0237] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0238] (Embodiment 6) In this embodiment, a semiconductor device 100G according to one embodiment of the present invention will be described. The semiconductor device 100G is a modified example of the semiconductor device 100C shown in FIG. 41 . Therefore, the semiconductor device 100G is also a modified example of the semiconductor device 100F. To reduce repetition of the description, differences between the semiconductor device 100G and the semiconductor device 100C shown in FIG. 41 will be mainly described.

[0239] <Configuration example> An example of the circuit configuration of the semiconductor device 100G is shown in Fig. 53. The semiconductor device 100G includes a pixel circuit 51G, a light emitting element 61a, and a light emitting element 61b. The pixel circuit 51G also includes a circuit 52a and a circuit 52b.

[0240] The circuit 52a includes a transistor M5a, a transistor M7a, and a capacitor C3a. The gate of the transistor M5a is electrically connected to one terminal of the capacitor C3a, and one of the source and the drain is electrically connected to the other of the source and the drain of the transistor M2. The other of the source and the drain of the transistor M5a is electrically connected to the other terminal of the capacitor C3a and one terminal (e.g., an anode terminal) of the light-emitting element 61a. The other terminal (e.g., a cathode terminal) of the light-emitting element 61a is electrically connected to the wiring 104a. The gate of the transistor M7a is electrically connected to the wiring GLa, one of the source and the drain is electrically connected to the wiring GLc, and the other of the source and the drain is electrically connected to the gate of the transistor M5a.

[0241] A region where the gate of the transistor M5a, one terminal of the capacitor C3a, and the other of the source and drain of the transistor M7a are electrically connected is also referred to as a node ND4a.

[0242] The circuit 52b includes a transistor M5b, a transistor M7b, and a capacitor C3b. The gate of the transistor M5b is electrically connected to one terminal of the capacitor C3b, and one of the source and the drain is electrically connected to the other of the source and the drain of the transistor M2. The other of the source and the drain of the transistor M5b is electrically connected to the other terminal of the capacitor C3b and one terminal (e.g., an anode terminal) of the light-emitting element 61b. The other terminal (e.g., a cathode terminal) of the light-emitting element 61b is electrically connected to the wiring 104b. The gate of the transistor M7b is electrically connected to the wiring GLa, one of the source and the drain is electrically connected to the wiring GLc, and the other of the source and the drain is electrically connected to the gate of the transistor M5b.

[0243] A region where the gate of the transistor M5b, one terminal of the capacitor C3b, and the other of the source and drain of the transistor M7b are electrically connected is also referred to as a node ND4b.

[0244] That is, the transistors M5a and M5b correspond to the transistor M5. The transistors M7a and M7b correspond to the transistor M7. The capacitances C3a and C3b correspond to the capacitance C3. The nodes ND4a and ND4b correspond to the node ND4. The light-emitting element 61a and the light-emitting element 61b correspond to the light-emitting element 61, and the wiring 104a and the wiring 104b correspond to the wiring 104.

[0245] <Example of operation> The semiconductor device 100G can control the light emission of the light-emitting elements 61a and 61b by controlling the potentials of the wirings 104a and 104b. For example, to make the light-emitting element 61a emit light, a potential Vc is supplied to the wiring 104a and a potential equal to or greater than the potential Va is supplied to the wiring 104b. To make the light-emitting element 61b emit light, a potential Vc is supplied to the wiring 104b and a potential equal to or greater than the potential Va is supplied to the wiring 104a.

[0246] In addition, when it is desired to make both the light-emitting element 61a and the light-emitting element 61b emit light, the potential Vc may be supplied to both the wiring 104a and the wiring 104b.

[0247] The semiconductor device 100G can control the emission of two light-emitting elements 61 (light-emitting element 61a and light-emitting element 61b) using a set of transistors M1, M2, M3, M4, M6, capacitors C1, and C2. This reduces the area occupied by the pixel circuit per pixel, making it easier to improve the pixel density of the display device. Furthermore, the reduction in the area required for one pixel circuit increases the design freedom of the semiconductor device and the display device. This makes it easier to achieve high functionality and improved reliability of the semiconductor device and the display device.

[0248] The configuration shown in this embodiment is also applicable to the semiconductor device 100A and the semiconductor device 100B.

[0249] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0250] (Embodiment 7) In this embodiment, a semiconductor device 100H according to one embodiment of the present invention will be described. The semiconductor device 100H is a variation of the semiconductor device 100G shown in Fig. 53. To avoid repetition of the description, differences between the semiconductor device 100H and the semiconductor device 100G will be mainly described.

[0251] <Configuration example> An example of the circuit configuration of the semiconductor device 100H is shown in Fig. 54. The semiconductor device 100H includes a pixel circuit 51H, a light-emitting element 61a, and a light-emitting element 61b. The pixel circuit 51H also includes a circuit 52a and a circuit 52b.

[0252] The semiconductor device 100H differs from the semiconductor device 100G in that one of the source and drain of the transistor M7b included in the circuit 52b is electrically connected to the wiring GLd. In addition, both the cathode of the light-emitting element 61a and the cathode of the light-emitting element 61b are electrically connected to the wiring 104.

[0253] <Example of operation> The semiconductor device 100H can control the light emission of the light-emitting elements 61a and 61b by controlling the potentials of the wirings GLc and GLd. For example, to make only the light-emitting element 61a emit light, a potential H may be supplied to the wiring GLc and a potential L may be supplied to the wiring GLd during the period T34 described in the above embodiment. On the other hand, to make only the light-emitting element 61b emit light, a potential L may be supplied to the wiring GLc and a potential H may be supplied to the wiring GLd during the period T34 described in the above embodiment.

[0254] In addition, when both the light-emitting elements 61a and 61b are to emit light, the potential H may be supplied to both the wirings GLc and GLd during the period T34 shown in the above embodiment.

[0255] As with the semiconductor device 100G, the semiconductor device 100H can also control the light emission of two light-emitting elements 61 (light-emitting element 61a and light-emitting element 61b) using a set of transistors M1, M2, M3, M4, M6, capacitors C1, and C2. This reduces the area occupied by the pixel circuit per pixel, making it easier to improve the pixel density of the display device. Furthermore, the reduction in the area required for one pixel circuit increases the design freedom of the semiconductor device and the display device. This makes it easier to achieve high functionality and improved reliability of the semiconductor device and the display device.

[0256] The configuration shown in this embodiment is also applicable to the semiconductor device 100A and the semiconductor device 100B.

[0257] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0258] (Embodiment 8) In this embodiment, a configuration example of a display device 10 using a semiconductor device 100 (semiconductor device 100A, semiconductor device 100B, semiconductor device 100C, semiconductor device 100Ca, semiconductor device 100Cb, semiconductor device 100Cc, semiconductor device 100Cd, semiconductor device 100Ce, semiconductor device 100D, semiconductor device 100E, semiconductor device 100F, semiconductor device 100G, or semiconductor device 100H) will be described. FIG. 55A is a block diagram illustrating the display device 10. The display device 10 has a display region 235, a first driver circuit unit 231, and a second driver circuit unit 232. The display region 235 has a plurality of pixels 230 arranged in a matrix. The semiconductor device 100 according to one embodiment of the present invention can be used for the pixels 230.

[0259] The circuit included in the first drive circuit unit 231 functions as, for example, a scanning line drive circuit. The circuit included in the second drive circuit unit 232 functions as, for example, a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 231 across the display area 235. Note that some kind of circuit may be provided at a position facing the second drive circuit unit 232 across the display area 235. Note that the circuits included in the first drive circuit unit 231 and the second drive circuit unit 232 may be collectively referred to as a "peripheral drive circuit" or a "drive circuit."

[0260] The peripheral driver circuit can include various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, and a logic circuit. The peripheral driver circuit can include a transistor, a capacitor, and the like. The transistors included in the peripheral driver circuit can be formed in the same process as the transistors included in the pixel 230.

[0261] For example, OS transistors may be used as transistors constituting the pixel 230, and Si transistors may be used as transistors constituting the peripheral driver circuit. OS transistors have a low off-state current, which allows for reduced power consumption. Si transistors have a faster operating speed than OS transistors, so they are suitable for use in the peripheral driver circuit. Depending on the display device, OS transistors may be used as both the transistors constituting the pixel 230 and the transistors constituting the peripheral driver circuit. Depending on the display device, Si transistors may be used as both the transistors constituting the pixel 230 and the transistors constituting the peripheral driver circuit. Alternatively, depending on the display device, Si transistors may be used as transistors constituting the pixel 230, and OS transistors may be used as transistors constituting the peripheral driver circuit.

[0262] Furthermore, both Si transistors and OS transistors may be used as transistors forming the pixel 230. Furthermore, both Si transistors and OS transistors may be used as transistors forming the peripheral driver circuits.

[0263] The display device 10 also has m (m is an integer greater than or equal to 1) wires 236 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the first drive circuit section 231, and n (n is an integer greater than or equal to 1) wires 237 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the second drive circuit section 232.

[0264] 55A shows an example in which wiring 236 and wiring 237 are connected to pixel 230. However, wiring 236 and wiring 237 are just an example, and wirings connected to pixel 230 are not limited to wiring 236 and wiring 237.

[0265] The display region 235 includes a plurality of pixels 230 arranged in a matrix of m rows and n columns. For example, the pixel 230 arranged in the r-th row (r is any number and is an integer of 1 to m inclusive in this embodiment and the like) is electrically connected to the first drive circuit unit 231 via the r-th wiring 236. The pixel 230 arranged in the s-th column (s is any number and is an integer of 1 to n inclusive in this embodiment and the like) is electrically connected to the second drive circuit unit 232 via the s-th wiring 237.

[0266] A pixel 230 that controls red light, a pixel 230 that controls green light, and a pixel 230 that controls blue light are arranged in a stripe pattern, and these pixels function as a single pixel 240. By controlling the light emission amount (light emission brightness) of each pixel 230, a full-color display can be achieved. Thus, each of the three pixels 230 functions as a sub-pixel. That is, each of the three sub-pixels controls the light emission amount of red light, green light, or blue light (see FIG. 55B1). Note that the color of light controlled by each of the three sub-pixels is not limited to a combination of red (R), green (G), and blue (B), but may also be cyan (C), magenta (M), or yellow (Y) (see FIG. 55B2).

[0267] Furthermore, the three pixels 230 that make up one pixel 240 may be arranged in a delta arrangement (see FIG. 55B3). Specifically, the three pixels 230 that make up one pixel 240 may be arranged so that the lines connecting the center points of each pixel 230 form a triangle.

[0268] Furthermore, the areas of the three sub-pixels (pixels 230) do not have to be the same. If the luminous efficiency and reliability differ depending on the luminous color, the area of ​​the sub-pixels may be changed for each luminous color (see FIG. 55B4). The sub-pixel arrangement shown in FIG. 55B4 may also be called an "S-stripe arrangement," for example.

[0269] Furthermore, four subpixels may be combined to function as one pixel. For example, a subpixel that controls white light may be added to three subpixels that control red, green, and blue light, respectively (see FIG. 55B5). Adding a subpixel that controls white light can increase the brightness of the display area. A subpixel that controls yellow light may be added to three subpixels that control red, green, and blue light, respectively (see FIG. 55B6). A subpixel that controls white light may be added to three subpixels that control cyan, magenta, and yellow light, respectively (see FIG. 55B7).

[0270] By increasing the number of sub-pixels that function as one pixel and by appropriately combining sub-pixels that control red, green, blue, cyan, magenta, and yellow light, it is possible to improve the reproducibility of intermediate tones, thereby improving display quality.

[0271] Furthermore, as shown in FIG. 56, sub-pixels (pixels 230) in an S-stripe arrangement may be arranged so that sub-pixels of the same luminescent color are adjacent between adjacent pixels 240.

[0272] Furthermore, as shown in FIGS. 57A1 and 57A2, in the pixels 240 in which the pixels 230 are arranged in a stripe pattern, the pixels 230 that control the same luminescent color may be provided adjacent to each other between adjacent pixels 240.

[0273] In Figures 57A1 and 57A2, the pixels 230a and 230b that control red light are adjacent in the row direction, the pixels 230a and 230b that control green light are adjacent in the row direction, and the pixels 230a and 230b that control blue light are adjacent in the row direction. The pixel 240 shown in Figures 57A1 and 57A2 can be said to be configured by dividing one pixel 230 into two along the column direction. Note that three or more pixels 230 of the same luminescent color may be adjacent. In other words, one pixel 230 may be divided into three or more.

[0274] As shown in Fig. 57A1, a pixel 230a that controls red light, a pixel 230a that controls green light, and a pixel 230a that controls blue light may constitute one pixel 240. Alternatively, as shown in Fig. 57A2, one pixel 240 may be constituted by a pixel 230a and a pixel 230b that control red light, a pixel 230a and a pixel 230b that control green light, and a pixel 230a and a pixel 230b that control blue light.

[0275] By providing a plurality of sub-pixels that control the same emitted light color in one pixel 240, it is possible to increase the number of gradations that can be reproduced by the display device 10. This makes it possible to improve the display quality of the display device.

[0276] Furthermore, as shown in Fig. 57B, pixel 230a and pixel 230b that control the same emission color may be arranged adjacent to each other in the column direction. The pixel configuration shown in Fig. 57B can be said to be a configuration in which pixel 240 shown in Fig. 55B1 is divided into two in the row direction. By dividing pixel 240, the pixel density of display area 235 can be increased. This allows for higher-resolution image display.

[0277] 57A1 and 57A2, in the pixel 240 of the S-stripe arrangement, the pixel 230, which is a sub-pixel, may be divided into multiple sub-pixels (see FIG. 57C). The pixel 240 shown in FIG. 57C can function in the same way as the pixel 240 shown in FIG. 57A1 and 57A2.

[0278] The display device of one embodiment of the present invention can reproduce color gamuts of various standards, such as the PAL (Phase Alternating Line) standard and the NTSC (National Television System Committee) standard used in television broadcasting, the sRGB (standard RGB) standard and the Adobe RGB standard widely used in display devices used in electronic devices such as personal computers, digital cameras, and printers, the ITU-R BT.709 (International Telecommunication Union Radiocommunication Sector Broadcasting Service (Television) 709) standard used in HDTV (High Definition Television, also called Hi-Vision), the DCI-P3 (Digital Cinema Initiatives P3) standard used in digital cinema projection, and the ITU-R BT.2020 (REC.2020 (Recommendation 2020)) standard used in UHDTV (Ultra High Definition Television, also called Super Hi-Vision).

[0279] Furthermore, by arranging the pixels 240 in a 1920 × 1080 matrix, it is possible to realize a display device 10 capable of full-color display at a resolution of so-called full high-definition (also referred to as "2K resolution," "2K1K," or "2K"). Furthermore, by arranging the pixels 240 in a 3840 × 2160 matrix, it is possible to realize a display device 10 capable of full-color display at a resolution of so-called ultra high-definition (also referred to as "4K resolution," "4K2K," or "4K"). Furthermore, by arranging the pixels 240 in a 7680 × 4320 matrix, it is possible to realize a display device 10 capable of full-color display at a resolution of so-called super high-definition (also referred to as "8K resolution," "8K4K," or "8K"). By increasing the number of pixels 240, it is also possible to realize a display device 10 capable of full-color display at a resolution of 16K or 32K.

[0280] The pixel density of the display area 235 is preferably 100 ppi to 10,000 ppi, and more preferably 1,000 ppi to 10,000 ppi. For example, it may be 2,000 ppi to 6,000 ppi, or 3,000 ppi to 5,000 ppi.

[0281] There is no particular limitation on the aspect ratio of the display area 235. The display area 235 of the display device 10 can accommodate various aspect ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.

[0282] The diagonal size of the display area 235 may be 0.1 inches or more and 100 inches or less, and may be 100 inches or more.

[0283] When the display device 10 is used as a display device for virtual reality (VR) or augmented reality (AR), the diagonal size of the display area 235 can be set to 0.1 inches or more and 5.0 inches or less, preferably 0.5 inches or more and 2.0 inches or less, and more preferably 1 inch or more and 1.7 inches or less. For example, the diagonal size of the display area 235 may be set to 1.5 inches or approximately 1.5 inches. Setting the diagonal size of the display area 235 to 2.0 inches or less, preferably approximately 1.5 inches, enables the exposure process to be performed in an exposure device (typically a scanner device) in just one step, thereby improving the productivity of the manufacturing process.

[0284] The configuration of the transistors used in the display region 235 may be selected appropriately depending on the diagonal size of the display region 235. For example, when single-crystal Si transistors are used in the display region 235, the diagonal size of the display region 235 is preferably 0.1 inches to 3 inches. When LTPS transistors are used in the display region 235, the diagonal size of the display region 235 is preferably 0.1 inches to 30 inches, and more preferably 1 inch to 30 inches. When LTPO (a combination of LTPS transistors and OS transistors) is used in the display region 235, the diagonal size of the display region 235 is preferably 0.1 inches to 50 inches, and more preferably 1 inch to 50 inches. When OS transistors are used in the display region 235, the diagonal size of the display region 235 is preferably 0.1 inches to 200 inches, and more preferably 50 inches to 100 inches.

[0285] Single-crystal silicon transistors are extremely difficult to enlarge due to the size of single-crystal silicon substrates. Furthermore, LTPS transistors are manufactured using a laser crystallization apparatus, making it difficult to accommodate larger screen sizes (typically, screen sizes exceeding 30 inches diagonally). On the other hand, OS transistors are not restricted by the need for a laser crystallization apparatus or can be manufactured at relatively low process temperatures (typically, 450°C or lower), making them suitable for display panels with relatively large areas (typically, diagonal sizes of 50 to 100 inches). Furthermore, LTPO transistors can be applied to display panel sizes between those using LTPS transistors and those using OS transistors (typically, diagonal sizes of 1 to 50 inches).

[0286] <Configuration example of light-emitting element> A light-emitting element (also referred to as a light-emitting device) that can be used in a semiconductor device according to one embodiment of the present invention will be described.

[0287] As shown in FIG. 58A, the light-emitting element 61 includes an EL layer 172 between a pair of electrodes (conductive layers 171 and 173). The EL layer 172 can be composed of multiple layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can include, for example, a layer containing a substance with high electron injection properties (electron injection layer) and a layer containing a substance with high electron transport properties (electron transport layer). The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 can include, for example, a layer containing a substance with high hole injection properties (hole injection layer) and a layer containing a substance with high hole transport properties (hole transport layer).

[0288] A structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 58A is referred to as a single structure in this specification and the like.

[0289] 58B shows a modified example of the EL layer 172 included in the light-emitting element 61 shown in Fig. 58A. Specifically, the light-emitting element 61 shown in Fig. 58B includes a layer 4430-1 on the conductive layer 171, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductive layer 173 on the layer 4420-2. For example, when the conductive layer 171 is an anode and the conductive layer 173 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductive layer 171 is used as a cathode and the conductive layer 173 is used as an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. By using such a layer structure, it is possible to efficiently inject carriers into the light-emitting layer 4411 and increase the efficiency of carrier recombination in the light-emitting layer 4411.

[0290] Note that a configuration in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 as shown in FIG. 58C is also an example of a single structure.

[0291] 58D, a configuration in which multiple light-emitting units (EL layer 172a, EL layer 172b) are connected in series via an intermediate layer (charge generating layer) 4440 is referred to as a tandem structure or a stack structure in this specification and elsewhere. Note that a tandem structure can realize a light-emitting element capable of emitting light with high brightness.

[0292] Furthermore, when the light-emitting element 61 has a tandem structure as shown in FIG. 58D , the EL layer 172a and the EL layer 172b may emit the same light. For example, the EL layer 172a and the EL layer 172b may both emit green light. When the display region 235 includes three subpixels, R, G, and B, each of which has a light-emitting element, the light-emitting elements of the subpixels may be configured in tandem. Specifically, the EL layer 172a and the EL layer 172b of the R subpixel each contain a material capable of emitting red light, the EL layer 172a and the EL layer 172b of the G subpixel each contain a material capable of emitting green light, and the EL layer 172a and the EL layer 172b of the B subpixel each contain a material capable of emitting blue light. In other words, the light-emitting layer 4411 and the light-emitting layer 4412 may be made of the same material. By making the EL layers 172a and 172b emit light of the same color, the current density per unit of emitted light luminance can be reduced, thereby improving the reliability of the light emitting element 61.

[0293] The light-emitting element can emit light in red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 172. Furthermore, the color purity can be further improved by providing the light-emitting element with a microcavity structure.

[0294] The light-emitting layer may contain two or more light-emitting materials that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). A light-emitting element that emits white light preferably has a configuration in which the light-emitting layer contains two or more types of light-emitting materials. To obtain white light emission using two types of light-emitting materials, light-emitting materials may be selected such that the emission colors of the respective light-emitting materials are complementary to each other. Alternatively, for example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a light-emitting element that emits white light as a whole can be obtained. The same applies to a light-emitting element having three or more light-emitting layers.

[0295] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0296] Examples of light-emitting materials include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials). TADF materials may also be materials that are in thermal equilibrium between the singlet excited state and the triplet excited state. Because such TADF materials have a short emission lifetime (excitation lifetime), they can suppress a decrease in efficiency in the high-brightness region of light-emitting elements.

[0297] <Method for forming light-emitting element> An example of a method for forming the light emitting element 61 will be described below.

[0298] FIG. 59A shows a schematic top view of a light-emitting element 61. In FIG. 59A and other figures, a light-emitting element 61 that emits red light is designated as light-emitting element 61R, a light-emitting element 61 that emits green light is designated as light-emitting element 61G, and a light-emitting element 61 that emits blue light is designated as light-emitting element 61B. In FIG. 59A, the symbols R, G, and B are assigned within the light-emitting region of each light-emitting element to easily distinguish between the light-emitting elements. The configuration of light-emitting element 61 shown in FIG. 59A may be referred to as an SBS (Side By Side) structure. Although FIG. 59A illustrates a configuration having three emitted colors, red (R), green (G), and blue (B), the present invention is not limited to this. For example, a configuration having four or more colors may also be used.

[0299] The light-emitting elements 61R, 61G, and 61B are arranged in a matrix. Fig. 59A shows a stripe arrangement in which light-emitting elements of the same color are arranged in one direction, but the arrangement of the light-emitting elements is not limited to this. The light-emitting elements may be arranged in a delta arrangement, a zigzag arrangement, an S-stripe arrangement, a pentile arrangement, or the like.

[0300] As the light-emitting elements 61R, 61G, and 61B, it is preferable to use organic EL devices such as OLEDs (Organic Light Emitting Diodes) or QOLEDs (Quantum-dot Organic Light Emitting Diodes). Examples of light-emitting materials that the light-emitting elements have include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials).

[0301] FIG. 59B is a schematic cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 59A. FIG. 59B shows cross sections of light-emitting elements 61R, 61G, and 61B. Light-emitting elements 61R, 61G, and 61B are each provided on an insulating layer 363 and include a conductive layer 171 functioning as a pixel electrode and a conductive layer 173 functioning as a common electrode. The insulating layer 363 can be an inorganic insulating film or an organic insulating film, or both. It is preferable to use an inorganic insulating film as the insulating layer 363. Examples of inorganic insulating films include oxide insulating films and nitride insulating films, such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.

[0302] The light-emitting element 61R has an EL layer 172R between the conductive layer 171 functioning as a pixel electrode and the conductive layer 173 functioning as a common electrode. The EL layer 172R contains a light-emitting organic compound that emits light having an intensity at least in the red wavelength range. The EL layer 172G of the light-emitting element 61G contains a light-emitting organic compound that emits light having an intensity at least in the green wavelength range. The EL layer 172B of the light-emitting element 61B contains a light-emitting organic compound that emits light having an intensity at least in the blue wavelength range.

[0303] The EL layer 172R, the EL layer 172G, and the EL layer 172B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0304] The conductive layer 171 functioning as a pixel electrode is provided for each light-emitting element. The conductive layer 173 functioning as a common electrode is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductive layer 171 functioning as a pixel electrode or the conductive layer 173 functioning as a common electrode, and a conductive film that is reflective is used for the other. By making the conductive layer 171 functioning as a pixel electrode light-transmitting and the conductive layer 173 functioning as a common electrode light-reflective, a bottom-emission display device can be obtained. Conversely, by making the conductive layer 171 functioning as a pixel electrode light-transmitting and the conductive layer 173 functioning as a common electrode light-transmitting, a top-emission display device can be obtained. Note that by making both the conductive layer 171 functioning as a pixel electrode and the conductive layer 173 functioning as a common electrode light-transmitting, a dual-emission display device can also be obtained.

[0305] For example, when the light emitting element 61R is a top emission type, the light 175R emitted from the light emitting element 61R is emitted toward the conductive layer 173. When the light emitting element 61G is a top emission type, the light 175G emitted from the light emitting element 61G is emitted toward the conductive layer 173. When the light emitting element 61B is a top emission type, the light 175B emitted from the light emitting element 61B is emitted toward the conductive layer 173.

[0306] An insulating layer 272 is provided to cover an edge portion of the conductive layer 171 functioning as a pixel electrode. The edge portion of the insulating layer 272 preferably has a tapered shape. The insulating layer 272 can be formed using a material similar to that of the insulating layer 363.

[0307] The insulating layer 272 is provided to prevent erroneous light emission due to unintentional electrical short circuit between adjacent light-emitting elements 61. In addition, when a metal mask is used to form the EL layer 172, the insulating layer 272 also functions to prevent the metal mask from coming into contact with the conductive layer 171.

[0308] The EL layer 172R, the EL layer 172G, and the EL layer 172B each have a region in contact with the upper surface of the conductive layer 171 that functions as a pixel electrode, and a region in contact with the surface of the insulating layer 272. In addition, the ends of the EL layer 172R, the EL layer 172G, and the EL layer 172B are located on the insulating layer 272.

[0309] As shown in Figure 59B, a gap is provided between the EL layers of the light-emitting elements that emit two different colors. In this way, it is preferable that the EL layers 172R, 172G, and 172B are arranged so that they do not come into contact with each other. This effectively prevents current from flowing through two adjacent EL layers, resulting in unintended light emission (also known as crosstalk). This improves contrast, enabling the realization of a display device with high display quality.

[0310] The EL layer 172R, the EL layer 172G, and the EL layer 172B can be separately fabricated by vacuum deposition using a shadow mask such as a metal mask. Alternatively, they may be separately fabricated by photolithography. By using photolithography, it is possible to realize a high-definition display device that is difficult to achieve using a metal mask.

[0311] In this specification, etc., a device fabricated using a metal mask or FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure. Because a display device with an MML structure is fabricated without using a metal mask, it has a higher degree of design freedom for pixel arrangement, pixel shape, etc. than a display device with an MM structure.

[0312] Moreover, a protective layer 271 is provided on the conductive layer 173, which functions as a common electrode, to cover the light-emitting elements 61R, 61G, and 61B. The protective layer 271 has a function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0313] The protective layer 271 may have, for example, a single-layer structure or a laminated structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide (IGZO) may be used for the protective layer 271. Note that the protective layer 271 may be formed by an ALD method, a CVD method, or a sputtering method. Note that, although the protective layer 271 includes an inorganic insulating film, the present invention is not limited to this. For example, the protective layer 271 may have a laminated structure of an inorganic insulating film and an organic insulating film.

[0314] In this specification, "nitride oxide" refers to a compound containing more nitrogen than oxygen. "Oxynitride" refers to a compound containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford Backscattering Spectrometry (RBS).

[0315] When indium gallium zinc oxide is used as the protective layer 271, it can be processed using a wet etching method or a dry etching method. For example, when IGZO is used as the protective layer 271, a chemical solution such as oxalic acid, phosphoric acid, or a mixed chemical solution (for example, a mixed chemical solution of phosphoric acid, acetic acid, nitric acid, and water (also called a mixed acid aluminum etching solution)) can be used. The mixed acid aluminum etching solution can have a volume ratio of phosphoric acid:acetic acid:nitric acid:water of approximately 53.3:6.7:3.3:36.7.

[0316] Fig. 59C shows a different example. Specifically, Fig. 59C shows a light-emitting element 61W that emits white light. The light-emitting element 61W has an EL layer 172W that emits white light between a conductive layer 171 that functions as a pixel electrode and a conductive layer 173 that functions as a common electrode.

[0317] The EL layer 172W may be configured by stacking two light-emitting layers selected so that the emitted light colors are complementary to each other. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between the light-emitting layers. Alternatively, the EL layer 172W may have three or more light-emitting layers.

[0318] FIG. 59C shows three light-emitting elements 61W lined up. A colored layer 264R is provided on the top of the left light-emitting element 61W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 61W. This allows the display device to display color images.

[0319] Here, the EL layer 172W and the conductive layer 173 functioning as a common electrode are separated between two adjacent light-emitting elements 61W. This prevents unintended light emission due to current flowing through the EL layer 172W between the two adjacent light-emitting elements 61W. In particular, when a stacked EL layer in which a charge-generating layer is provided between two light-emitting layers is used as the EL layer 172W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using this configuration, a display device that combines high resolution and high contrast can be realized.

[0320] The EL layer 172W and the conductive layer 173 functioning as a common electrode are preferably separated by photolithography, which allows the distance between the light-emitting elements to be narrowed, thereby achieving a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0321] In the case of a bottom-emission light-emitting element, a colored layer may be provided between the conductive layer 171 functioning as a pixel electrode and the insulating layer 363 .

[0322] FIG. 59D shows an example different from the above. Specifically, FIG. 59D shows a configuration in which an insulating layer 272 is not provided between the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. This configuration allows a display device with a high aperture ratio. Furthermore, by not providing the insulating layer 272, the unevenness of the light-emitting element 61 is reduced, thereby improving the viewing angle of the display device. Specifically, the viewing angle can be set to 150° or more and less than 180° degrees, preferably 160° or more and less than 180° degrees, and more preferably 160° or more and less than 180° degrees.

[0323] Furthermore, the protective layer 271 covers the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. This configuration can suppress impurities (typically, water, etc.) that can enter from the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. Furthermore, since the leakage current between adjacent light-emitting elements 61 is reduced, the color saturation and contrast ratio are improved and power consumption is reduced.

[0324] 59D, the top surfaces of conductive layer 171, EL layer 172R, and conductive layer 173 generally coincide with each other. This structure can be formed all at once by using a resist mask or the like after forming conductive layer 171, EL layer 172R, and conductive layer 173. This process can also be called self-aligned patterning, since EL layer 172R and conductive layer 173 are processed using conductive layer 173 as a mask. Note that although the EL layer 172R has been described here, the EL layer 172G and EL layer 172B can also have a similar structure.

[0325] 59D shows a structure in which protective layer 273 is further provided on protective layer 271. For example, protective layer 271 is formed using an apparatus (typically, an ALD apparatus) capable of depositing a film with high coverage, and protective layer 273 is formed using an apparatus (typically, a sputtering apparatus) capable of depositing a film with lower coverage than protective layer 271, thereby making it possible to provide region 275 between protective layer 271 and protective layer 273. In other words, region 275 is located between EL layer 172R and EL layer 172G, and between EL layer 172G and EL layer 172B.

[0326] The region 275 contains, for example, one or more selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, krypton, etc.). The region 275 may also contain, for example, a gas used when forming the protective layer 273. For example, when the protective layer 273 is formed by sputtering, the region 275 may contain one or more of the above Group 18 elements. When the region 275 contains a gas, the gas can be identified by gas chromatography or the like. Alternatively, when the protective layer 273 is formed by sputtering, the gas used during sputtering may also be contained in the film of the protective layer 273. In this case, when the protective layer 273 is analyzed by energy dispersive X-ray analysis (EDX analysis) or the like, elements such as argon may be detected.

[0327] Furthermore, when the refractive index of region 275 is lower than the refractive index of protective layer 271, light emitted from EL layer 172R, EL layer 172G, or EL layer 172B is reflected at the interface between protective layer 271 and region 275. This may prevent light emitted from EL layer 172R, EL layer 172G, or EL layer 172B from entering adjacent pixels. This prevents light of different colors from being mixed in with neighboring pixels, thereby improving the display quality of the display device.

[0328] 59D, the area between light-emitting element 61R and light-emitting element 61G or the area between light-emitting element 61G and light-emitting element 61B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be set to 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of EL layer 172R and the side surface of EL layer 172G or the distance between the side surface of EL layer 172G and the side surface of EL layer 172B has an area of ​​1 μm or less, preferably an area of ​​0.5 μm (500 nm) or less, and more preferably an area of ​​100 nm or less.

[0329] Furthermore, for example, when the region 275 contains gas, it is possible to isolate the light emitting elements while suppressing color mixing or crosstalk of the light from each light emitting element.

[0330] Alternatively, the region 275 may be filled with a filler. Examples of the filler include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Alternatively, a photoresist may be used as the filler. The photoresist used as the filler may be a positive photoresist or a negative photoresist.

[0331] Furthermore, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) with a light-emitting device with an SBS structure, the light-emitting device with an SBS structure can consume less power than the white light-emitting device. If you want to keep power consumption low, it is preferable to use a light-emitting device with an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device with an SBS structure, so it is preferable because it can reduce manufacturing costs or increase manufacturing yields.

[0332] FIG. 60A shows a different example. Specifically, the configuration shown in FIG. 60A differs from the configuration shown in FIG. 59D in the configuration of the insulating layer 363. The insulating layer 363 has a recess formed by removing a portion of its upper surface during processing of the light-emitting elements 61R, 61G, and 61B. A protective layer 271 is formed in the recess. In other words, the insulating layer 363 has a region where the lower surface of the protective layer 271 is located lower than the lower surface of the conductive layer 171 in a cross-sectional view. By providing this region, impurities (typically, water, etc.) that may enter the light-emitting elements 61R, 61G, and 61B from below can be effectively suppressed. The recess can be formed when impurities (also referred to as residue) that may adhere to the side surfaces of the light-emitting elements 61R, 61G, and 61B are removed by wet etching or the like during processing. After removing the residue, the side surfaces of the light-emitting elements are covered with the protective layer 271, resulting in a highly reliable display device.

[0333] FIG. 60B shows a different example. Specifically, the configuration shown in FIG. 60B includes an insulating layer 276 and a microlens array 277 in addition to the configuration shown in FIG. 60A. The insulating layer 276 functions as an adhesive layer. If the refractive index of the insulating layer 276 is lower than that of the microlens array 277, the microlens array 277 can condense light emitted from the light-emitting elements 61R, 61G, and 61B. This improves the light extraction efficiency of the display device. This is particularly advantageous because it allows a bright image to be viewed when a user views the display surface from directly in front of the display surface. The insulating layer 276 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet-curable adhesive), a reactive-curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, materials with low moisture permeability, such as epoxy resin, are preferred. Two-component resins may also be used. Adhesive sheets may also be used.

[0334] FIG. 60C shows a different example. Specifically, the configuration shown in FIG. 60C has three light-emitting elements 61W instead of the light-emitting elements 61R, 61G, and 61B in the configuration shown in FIG. 60A. An insulating layer 276 is provided above the three light-emitting elements 61W, and colored layers 264R, 264G, and 264B are provided above the insulating layer 276. Specifically, a colored layer 264R that transmits red light is provided at a position overlapping the left light-emitting element 61W, a colored layer 264G that transmits green light is provided at a position overlapping the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided at a position overlapping the right light-emitting element 61W. This allows the display device to display a color image. The configuration shown in FIG. 60C is also a variation of the configuration shown in FIG. 59C.

[0335] Fig. 60D shows another example. Specifically, in the configuration shown in Fig. 60D, protective layer 271 is provided adjacent to the side surfaces of conductive layer 171 and EL layer 172. Conductive layer 173 is provided as a continuous layer common to each light-emitting element. In the configuration shown in Fig. 60D, region 275 is preferably filled with a filler material.

[0336] The color purity of the emitted color can be improved by providing a micro-optical resonator (microcavity) structure to the light-emitting element 61. To provide a microcavity structure to the light-emitting element 61, the product (optical path length) of the distance d between the conductive layers 171 and 173 and the refractive index n of the EL layer 172 should be configured to be m times half the wavelength λ (m is an integer equal to or greater than 1). The distance d can be calculated using Equation 1.

[0337] d=m×λ / (2×n) ··· Equation 1.

[0338] According to Equation 1, the distance d of the light emitting element 61 having a microcavity structure is determined according to the wavelength (emission color) of the emitted light. The distance d corresponds to the thickness of the EL layer 172. Therefore, the EL layer 172G may be provided thicker than the EL layer 172B, and the EL layer 172R may be provided thicker than the EL layer 172G.

[0339] Strictly speaking, distance d is the distance from the reflective region of conductive layer 171, which functions as a reflective electrode, to the reflective region of conductive layer 173, which functions as a semi-transmissive and semi-reflective electrode. For example, if conductive layer 171 is a laminate of silver and a transparent conductive film, ITO (Indium Tin Oxide), and the ITO is on the EL layer 172 side, distance d can be set according to the emitted color by adjusting the film thickness of the ITO. In other words, even if EL layer 172R, EL layer 172G, and EL layer 172B have the same thickness, distance d appropriate for the emitted color can be obtained by changing the thickness of the ITO.

[0340] However, it may be difficult to precisely determine the positions of the reflective regions in the conductive layers 171 and 173. In this case, it is assumed that the microcavity effect can be fully obtained by assuming that any position on the conductive layers 171 and 173 is the reflective region.

[0341] The light-emitting element 61 is composed of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, etc. Detailed configuration examples of the light-emitting element 61 will be described in other embodiments. To increase the light extraction efficiency in the microcavity structure, it is preferable to set the optical distance from the conductive layer 171, which functions as a reflective electrode, to the light-emitting layer to an odd multiple of λ / 4. To achieve this optical distance, it is preferable to appropriately adjust the thickness of each layer that constitutes the light-emitting element 61.

[0342] Furthermore, when light is emitted from the conductive layer 173 side, it is preferable that the reflectance of the conductive layer 173 is greater than the transmittance. The light transmittance of the conductive layer 173 is preferably 2% to 50%, more preferably 2% to 30%, and even more preferably 2% to 10%. By reducing the transmittance of the conductive layer 173 (increasing the reflectance), the effect of the microcavity can be enhanced.

[0343] Fig. 61A shows an example different from the above. Specifically, in the configuration shown in Fig. 61A, the EL layer 172 extends beyond the edge of the conductive layer 171 in each of the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. For example, in the light-emitting element 61R, the EL layer 172R extends beyond the edge of the conductive layer 171. In the light-emitting element 61G, the EL layer 172G extends beyond the edge of the conductive layer 171. In the light-emitting element 61B, the EL layer 172B extends beyond the edge of the conductive layer 171.

[0344] In each of the light-emitting elements 61R, 61G, and 61B, the EL layer 172 and the protective layer 271 have an overlapping region with the insulating layer 270 interposed therebetween. In addition, an insulating layer 278 is provided on the protective layer 271 in the region between adjacent light-emitting elements 61.

[0345] Examples of materials for the insulating layer 278 include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Photoresist may also be used for the insulating layer 278. The photoresist used for the insulating layer 278 may be a positive photoresist or a negative photoresist.

[0346] Furthermore, a common layer 174 is provided on the light-emitting elements 61R, 61G, and 61B and the insulating layer 278, and a conductive layer 173 is provided on the common layer 174. The common layer 174 has a region in contact with the EL layer 172R, a region in contact with the EL layer 172G, and a region in contact with the EL layer 172B. The common layer 174 is shared by the light-emitting elements 61R, 61G, and 61B.

[0347] The common layer 174 may be one or more of a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electron transport layer, and an electron injection layer. For example, the common layer 174 may be a carrier injection layer (hole injection layer or electron injection layer). The common layer 174 may also be considered a part of the EL layer 172. The common layer 174 may be provided as needed. When the common layer 174 is provided, it is not necessary to provide a layer having the same function as the common layer 174 among the layers included in the EL layer 172.

[0348] In addition, a protective layer 273 is provided over the conductive layer 173 , and an insulating layer 276 is provided over the protective layer 273 .

[0349] FIG. 61B shows a different example. Specifically, the configuration shown in FIG. 61B has three light-emitting elements 61W instead of the light-emitting elements 61R, 61G, and 61B in the configuration shown in FIG. 61A. An insulating layer 276 is provided above the three light-emitting elements 61W, and colored layers 264R, 264G, and 264B are provided above the insulating layer 276. Specifically, a colored layer 264R that transmits red light is provided at a position overlapping the left light-emitting element 61W, a colored layer 264G that transmits green light is provided at a position overlapping the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided at a position overlapping the right light-emitting element 61W. This allows the display device to display a color image. The configuration shown in FIG. 61B is also a variation of the configuration shown in FIG. 60C.

[0350] FIG. 62A shows a schematic top view of a light-emitting element 61. Similar to FIG. 57A1, FIG. 62A shows an example in which multiple light-emitting elements 61 of the same emission color are arranged adjacent to each other. In FIG. 62A, two light-emitting elements 61R are adjacent to each other, two light-emitting elements 61G are adjacent to each other, and two light-emitting elements 61B are adjacent to each other. Note that three or more light-emitting elements 61 of the same emission color may be adjacent to each other. Also, FIG. 62A illustrates a configuration having three emission colors, red (R), green (G), and blue (B), but this is not limiting. For example, a configuration having four or more emission colors may be used.

[0351] 62A, the arrangement of the light emitting elements 61 is shown in a stripe arrangement, but the arrangement method of the light emitting elements 61 is not limited to this. The arrangement method of the light emitting elements 61 can be a delta arrangement, a zigzag arrangement, an S-stripe arrangement, a pentile arrangement, or the like.

[0352] Figures 62B and 62C are cross-sectional schematic views corresponding to the dashed dotted line A3-A4 in Figure 62A. Figure 62B corresponds to a modified example of the configuration shown in Figure 60C. Figure 62C corresponds to a modified example of the configuration shown in Figure 60D.

[0353] By grouping a plurality of light emitting elements 61 of the same luminescent color together and using them as one sub-pixel, the number of reproducible gradations can be increased, thereby improving the display quality of the display device.

[0354] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0355] (Embodiment 9) In this embodiment, an example of a stacked structure of the display device 10 will be described.

[0356] Figures 63A and 63B show perspective views of display device 10. Display device 10 shown in Figure 63A includes layer 60 stacked on layer 50. Layer 50 includes a plurality of pixel circuits 51 arranged in a matrix, a first drive circuit section 231, a second drive circuit section 232, and an input / output terminal section 29. Layer 60 includes a plurality of light-emitting elements 61 arranged in a matrix.

[0357] In the display device 10 shown in Figures 63A and 63B, one pixel circuit 51 and one light-emitting element 61 are electrically connected to each other, and function as one pixel 230. Therefore, the area where the multiple pixel circuits 51 included in the layer 50 and the multiple light-emitting elements 61 included in the layer 60 overlap functions as a display area 235. As the pixel 230 included in the display device 10 shown in Figures 63A and 63B, for example, the semiconductor device 100A, the semiconductor device 100B, or the semiconductor device 100C described in the above embodiment can be used.

[0358] Power, signals, and the like required for the operation of the display device 10 are supplied to the display device 10 via the input / output terminal unit 29. In the display device 10 shown in Fig. 63A, the transistors included in the peripheral driving circuit and the transistors included in the pixels 230 can be formed in the same process.

[0359] 63B, display device 10 may be configured such that layers 40, 50, and 60 are stacked one on top of the other. In FIG. 63B, a plurality of pixel circuits 51 arranged in a matrix are provided on layer 50, and first drive circuit section 231 and second drive circuit section 232 are provided on layer 40. By providing first drive circuit section 231 and second drive circuit section 232 on a different layer from pixel circuits 51, the width of the frame around display region 235 can be narrowed, and the area occupied by display region 235 can be expanded.

[0360] By increasing the occupied area of ​​the display region 235, the resolution of the display region 235 can be increased. When the resolution of the display region 235 is constant, the occupied area per pixel can be increased. This can increase the luminance of the light emitted from the display region 235. Furthermore, the ratio of the light-emitting area to the occupied area of ​​one pixel (also referred to as the "aperture ratio") can be increased. For example, the aperture ratio of the pixel can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, by increasing the occupied area per pixel, the current density supplied to the light-emitting element 61 can be reduced. This reduces the load on the light-emitting element 61, thereby improving the reliability of the semiconductor device 100. This can improve the reliability of the display device 10 including the semiconductor device 100.

[0361] Furthermore, by stacking the display region 235 and the peripheral driving circuits, etc., it is possible to shorten the wiring that electrically connects them. This reduces the wiring resistance and parasitic capacitance, and increases the operating speed of the semiconductor device 100. Furthermore, the power consumption of the semiconductor device 100 is reduced.

[0362] Furthermore, the layer 40 may include not only the peripheral drive circuits but also a CPU 23 (Central Processing Unit), a GPU 24 (Graphics Processing Unit), and a memory circuit unit 25. In the present embodiment and the like, the CPU 23, the GPU 24, the memory circuit unit 25, etc. may be collectively referred to as a "functional circuit."

[0363] For example, the CPU 23 has a function of controlling the operation of the GPU 24 and circuits provided in the layer 40 in accordance with a program stored in the memory circuit unit 25. The GPU 24 has a function of performing arithmetic processing to form image data. Furthermore, the GPU 24 can perform many matrix operations (product-sum operations) in parallel, allowing it to perform arithmetic processing using, for example, a neural network at high speed. The GPU 24 has a function of adjusting image data using adjustment data stored in the memory circuit unit 25. For example, the GPU 24 has a function of generating image data with brightness, color, and / or contrast adjusted.

[0364] The GPU 24 may be used to upconvert or downconvert image data. A super-resolution circuit may also be provided in the layer 40. The super-resolution circuit has a function of determining the potential of any pixel in the display area 235 by multiplying and adding the potentials and weights of the pixels surrounding the pixel. The super-resolution circuit has a function of upconverting image data having a resolution lower than that of the display area 235. The super-resolution circuit also has a function of downconverting image data having a resolution higher than that of the display area 235.

[0365] By providing a super-resolution circuit, it is possible to reduce the load on the GPU 24. For example, the GPU 24 can process up to 2K resolution (or 4K resolution), and the super-resolution circuit can upconvert to 4K resolution (or 8K resolution), thereby reducing the load on the GPU 24. Downconversion can be performed in the same way.

[0366] The functional circuits included in the layer 40 do not necessarily have to include all of these components, and may include other components. For example, the functional circuits may include a potential generating circuit that generates a plurality of different potentials, and / or a power management circuit that controls the supply and stop of power to each circuit included in the display device 10.

[0367] The supply and stopping of power may be performed for each circuit constituting the CPU 23. For example, power supply to a circuit constituting the CPU 23 that is determined not to be used for a while may be stopped, and power supply may be resumed when necessary, thereby reducing power consumption. Data required when power supply is resumed may be stored in a memory circuit within the CPU 23 or in the memory circuit unit 25 before the circuit is stopped. Storing data required when the circuit is restored enables the circuit to be restored quickly. Note that circuit operation may be stopped by stopping the supply of a clock signal.

[0368] Furthermore, the functional circuits may include a DSP circuit, a sensor circuit, a communication circuit, and / or an FPGA (Field Programmable Gate Array).

[0369] When the peripheral driver circuit and the display region 235 are provided so as to overlap, a conductive layer 701 may be provided between the peripheral driver circuit and the display region 235. When the peripheral driver circuit and the functional circuit are provided so as to overlap with the display region 235, a conductive layer 701 may be provided between the peripheral driver circuit and the functional circuit and the display region 235.

[0370] Fig. 64A shows a perspective view of a display device 10 having a conductive layer 701 between a peripheral driving circuit and a functional circuit and a display area 235. Fig. 64B is a plan view of the display device 10 shown in Fig. 64A as seen from the display area 235 side. Note that in Fig. 64B, a portion of the display area 235 is omitted to make it easier to understand the relationship between the display area 235 and the conductive layer 701.

[0371] Each of the peripheral drive circuits and functional circuits may generate electromagnetic noise during operation. If this electromagnetic noise reaches the display area 235, the display quality of the display device 10 may be degraded. Specifically, this electromagnetic noise may affect the floating nodes (nodes ND1 to ND4) of the pixel circuits 51 in the display area 235, preventing accurate potential retention. As a result, stable operation of the pixel circuits 51 may be impaired, and the display quality of the display device 10 may be degraded.

[0372] By providing the conductive layer 701 between the peripheral driving circuits and functional circuits and the display region 235, it is possible to block electromagnetic noise that occurs when the peripheral driving circuits and functional circuits are operating, thereby preventing a decrease in display quality. Furthermore, blocking electromagnetic noise stabilizes the operation of the pixel circuits 51, enabling more precise potential control. This improves the display quality of the display device 10.

[0373] Furthermore, when viewed from the conductive layer 701 side, it is preferable that the conductive layer 701 covers the entire display region 235. Therefore, it is preferable that the conductive layer 701 and the display region 235 have an overlapping region. Furthermore, the display region 235 has a plurality of pixel circuits 51. Therefore, it is preferable that the conductive layer 701 and the plurality of pixel circuits 51 have an overlapping region.

[0374] The conductive layer 701 is not limited to a planar shape, and may be in a mesh or stripe shape, etc. If the internal stress of the conductive layer 701 is large, providing the conductive layer 701 in a wide area may cause distortion in the layers that make up the display device 10, which may reduce the reliability of the display device 10. By forming the conductive layer 701 in a mesh or stripe shape, it is possible to block electromagnetic noise and alleviate the stress of the conductive layer 701.

[0375] FIG. 65 is a perspective view of a display device 10 having conductive layers 702 (conductive layers 702a, 702b, 702c, 702d, and 702e) between the peripheral drive circuits and functional circuits and the display region 235. FIG. 65 shows an example in which conductive layer 702a is provided overlapping the first drive circuit unit 231, conductive layer 702b is provided overlapping the second drive circuit unit 232, conductive layer 702c is provided overlapping the CPU 23, conductive layer 702d is provided overlapping the GPU 24, and conductive layer 702e is provided overlapping the memory circuit unit 25. It is preferable that each of the conductive layers 702 completely covers the peripheral drive circuits and functional circuits, respectively. However, a configuration in which each of the peripheral drive circuits and functional circuits is partially covered may also be used.

[0376] 66A is a perspective view of display device 10 having conductive layers 701 and 702 between peripheral drive circuits and functional circuits and display region 235. By providing conductive layer 701 in addition to conductive layer 702, the electromagnetic noise blocking effect can be further improved.

[0377] In this way, the conductive layers 701 and 702 function as an electromagnetic shield (sometimes referred to as a "shield layer" or "shielding layer"). The conductive layers 701 and 702 may be in a floating state, but are preferably supplied with a fixed potential such as a high power supply potential VDD, a low power supply potential VSS, a common potential COM, or a ground potential GND. For example, the ground potential GND may be supplied to the conductive layers 701 and 702. When the display device 10 has both the conductive layers 701 and 702, the conductive layers 701 and 702 may be at the same potential or may be at different potentials. Alternatively, one of the conductive layers 701 and 702 may be in a floating state.

[0378] 66A shows an example in which the display device 10 has two layers of conductors that function as electromagnetic shields, but it may have three or more layers of conductors that function as electromagnetic shields. By using a multi-layer electromagnetic shield, it is possible to improve the effectiveness of blocking electromagnetic noise. When providing a multi-layer electromagnetic shield, each layer of the electromagnetic shield can be stacked with an insulator between them.

[0379] Similarly to conductive layer 701, conductive layer 702 is not limited to a planar shape, and may be a mesh shape (see FIG. 66B) or a stripe shape (see FIG. 66C).

[0380] Furthermore, instead of the conductive layers 701 and 702, a conductive layer functioning as wiring may be used as the electromagnetic shield. For example, wiring that supplies a fixed potential such as an anode potential or a cathode potential may be formed below the plurality of pixel circuits 51, and the wiring may be used as the electromagnetic shield. By using the conductive layer functioning as wiring as the electromagnetic shield, the number of layers constituting the display device 10 can be reduced. Therefore, the productivity of the display device 10 can be improved.

[0381] Furthermore, some of the transistors constituting the functional circuits included in the layer 40 may be provided in the layer 50. Furthermore, some of the transistors constituting the pixel circuits 51 included in the layer 50 may be provided in the layer 40. Therefore, the functional circuits may be configured to include Si transistors and OS transistors. Furthermore, the pixel circuits 51 may be configured to include Si transistors and OS transistors.

[0382] The transistors included in the display device 10 may be n-channel transistors or p-channel transistors. Both n-channel transistors and p-channel transistors may be used. For example, the circuit included in the display device 10 may have a CMOS structure that combines n-channel transistors and p-channel transistors.

[0383] Furthermore, for example, when the pixel circuit 51 is configured with multiple types of transistors using different semiconductor materials, the transistors may be provided in different layers depending on the type of transistor. For example, when the pixel circuit 51 is configured with a region 51a including Si transistors and a region 51b including OS transistors, the region 51a may be formed in the layer 40, and the region 51b may be formed in the layer 50 (see FIG. 67). Furthermore, by providing the regions 51a and 51b so that they overlap, the area occupied by the pixel circuit 51 can be reduced. This allows for an improvement in the resolution of the display device 10.

[0384] Note that the transistors included in the region 51a may be transistors having low temperature polysilicon (LTPS) in their semiconductor layers (hereinafter also referred to as LTPS transistors). LTPS transistors have high field-effect mobility and favorable frequency characteristics. A configuration in which an LTPS transistor and an OS transistor are combined may be referred to as LTPO.

[0385] The conductivity types of the transistors included in the regions 51a and 51b may be different or the same. For example, the region 51a may include p-channel transistors and the region 51b may include n-channel transistors. Alternatively, the regions 51a and 51b may each include n-channel transistors. Alternatively, the regions 51a and 51b may each include n-channel transistors and p-channel transistors.

[0386] Furthermore, for example, if the peripheral drive circuit is composed of multiple types of transistors using different semiconductor materials, the transistors may be provided in different layers for each type of transistor. For example, if the first drive circuit unit 231 is composed of a region 231a including Si transistors and a region 231b including OS transistors, the region 231a may be formed on the layer 40, and the region 231b may be formed on the layer 50. For example, if the second drive circuit unit 232 is composed of a region 232a including Si transistors and a region 232b including OS transistors, the region 232a may be formed on the layer 40, and the region 232b may be formed on the layer 50. For example, the peripheral drive circuit may be composed of LTPO.

[0387] The conductivity types of the transistors included in the region 231a and the region 231b may be different or the same. For example, the region 231a may include a p-channel transistor, and the region 231b may include an n-channel transistor. Alternatively, the region 231a and the region 231b may each include an n-channel transistor. Alternatively, the region 231a and the region 231b may each include an n-channel transistor and a p-channel transistor.

[0388] The conductivity types of the transistors included in the region 232a and the region 232b may be different or the same. For example, the region 232a may include p-channel transistors and the region 232b may include n-channel transistors. Alternatively, the region 232a and the region 232b may include n-channel transistors and p-channel transistors, respectively.

[0389] Modifications of the display device 10 shown in Figures 63A and 63B are shown in Figures 68A and 68B. The display device 10 shown in Figure 68A has a configuration in which one pixel circuit 51 and two light-emitting elements 61 (light-emitting element 61a and light-emitting element 61b) are electrically connected. One pixel circuit 51 can alternately control the light emission of the two light-emitting elements 61. In other words, one pixel circuit 51 can control the operation of two pixels 230 (pixel 230a and pixel 230b). It is also possible to cause the light-emitting element 61a and the light-emitting element 61b to emit light simultaneously, so that they function as one pixel 230.

[0390] 68A and 68B may include, for example, the semiconductor device 100F, the semiconductor device 100G, or the semiconductor device 100H described in the above embodiment. As described above, the semiconductor device 100F, the semiconductor device 100G, and the semiconductor device 100H are suitable for display devices with high pixel density.

[0391] Furthermore, similar to the display device 10 shown in FIG. 63B, the layer 40 may be provided in the display device 10 shown in FIG. 68A (see FIG. 68B).

[0392] In this embodiment, a configuration in which one pixel circuit 51 controls two light-emitting elements 61 has been shown, but it is also possible for one pixel circuit 51 to control three or more light-emitting elements 61.

[0393] <Example of display module configuration> Next, a structural example of a display module including the display device according to one embodiment of the present invention will be described.

[0394] 69A to 69C are perspective schematic diagrams of a display module 400. The display module 400 has a structure in which an FPC 404 (Flexible Printed Circuits) is provided in the input / output terminal section 29 of the display device 10. The FPC 404 has a structure in which wiring is provided on a film made of an insulating material. The FPC 404 is also flexible. The FPC 404 functions as wiring for supplying video signals, control signals, power supply potential, and the like from the outside to the display device 10. An IC may also be mounted on the FPC 404.

[0395] Display module 400 shown in Fig. 69B has a configuration in which display device 10 is provided on printed wiring board 401. Printed wiring board 401 has a structure in which wiring is provided inside or on the surface, or inside and on the surface, of a substrate made of an insulating material.

[0396] In display module 400 shown in Fig. 69B, input / output terminal section 29 of display device 10 and terminal section 402 of printed wiring board 401 are electrically connected via wire 403. Wire 403 can be formed by wire bonding. Furthermore, ball bonding or wedge bonding can be used for wire bonding.

[0397] After forming the wires 403, the wires 403 may be covered with a resin material or the like. Note that the electrical connection between the display device 10 and the printed wiring board 401 may be achieved by a method other than wire bonding. For example, the electrical connection between the display device 10 and the printed wiring board 401 may be achieved by an anisotropic conductive adhesive, a bump, or the like.

[0398] 69B, terminal section 402 of printed wiring board 401 is electrically connected to FPC 404. For example, if the pitch of electrodes in input / output terminal section 29 of display device 10 differs from the pitch of electrodes in FPC 404, input / output terminal section 29 and FPC 404 may be electrically connected via printed wiring board 401. Specifically, the spacing (pitch) between the multiple electrodes in input / output terminal section 29 can be converted to the spacing between the multiple electrodes in terminal section 402 using wiring formed on printed wiring board 401. In other words, even if the pitch of electrodes in input / output terminal section 29 differs from the pitch of electrodes in FPC 404, electrical connection between the electrodes can be achieved.

[0399] Furthermore, printed wiring board 401 can be provided with various elements such as resistor elements, capacitor elements, and semiconductor elements.

[0400] 69C, terminal section 402 may be electrically connected to connection section 405 provided on the lower surface (the surface on which display device 10 is not provided) of printed wiring board 401. For example, by using a socket-type connection section as connection section 405, display module 400 can be easily attached to and detached from other devices.

[0401] Fig. 70 shows an example of a cross-sectional configuration of a portion of the display device 10 shown in Fig. 63A. The display device 10 shown in Fig. 70 includes a layer 50 including a substrate 301, a capacitor 246, and a transistor 310, and a layer 60 including light-emitting elements 61R, 61G, and 61B. The layer 60 is provided on an insulating layer 363 included in the layer 50.

[0402] The transistor 310 is a transistor including a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as either a source or a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311 and functions as an insulating layer.

[0403] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0404] In addition, an insulating layer 261 is provided to cover the transistor 310 , and a capacitor 246 is provided on the insulating layer 261 .

[0405] Capacitor 246 includes conductive layer 241, conductive layer 245, and insulating layer 243 located therebetween. Conductive layer 241 functions as one electrode of capacitor 246, conductive layer 245 functions as the other electrode of capacitor 246, and insulating layer 243 functions as a dielectric of capacitor 246.

[0406] The conductive layer 241 is provided over the insulating layer 261 and is buried in the insulating layer 254. The conductive layer 241 is electrically connected to one of the source and drain of the transistor 310 by a plug 266 buried in the insulating layer 261. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0407] An insulating layer 255 is provided to cover the capacitor 246, an insulating layer 363 is provided on the insulating layer 255, and light emitting elements 61R, 61G, and 61B are provided on the insulating layer 363. A protective layer 415 is provided on the light emitting elements 61R, 61G, and 61B, and a substrate 420 is provided on the upper surface of the protective layer 415 with a resin layer 419 interposed therebetween.

[0408] The pixel electrode of the light-emitting element is electrically connected to one of the source or drain of the transistor 310 by a plug 256 embedded in the insulating layer 255 and the insulating layer 363, a conductive layer 241 embedded in the insulating layer 254, and a plug 266 embedded in the insulating layer 261.

[0409] Figure 71 shows a modification of the cross-sectional configuration example shown in Figure 70. The cross-sectional configuration example of display device 10 shown in Figure 71 differs from the cross-sectional configuration example shown in Figure 70 mainly in that transistor 320 is provided instead of transistor 310. Note that descriptions of parts similar to those in Figure 70 may be omitted.

[0410] The transistor 320 is a transistor in which a metal oxide (also referred to as an oxide semiconductor) is used for a semiconductor layer in which a channel is formed.

[0411] The transistor 320 includes a semiconductor layer 321 , an insulating layer 323 , a conductive layer 324 , a pair of conductive layers 325 , an insulating layer 326 , and a conductive layer 327 .

[0412] The substrate 331 may be an insulating substrate or a semiconductor substrate.

[0413] An insulating layer 332 is provided over a substrate 331. The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0414] A conductive layer 327 is provided over the insulating layer 332, and an insulating layer 326 is provided to cover the conductive layer 327. The conductive layer 327 functions as a first gate electrode of the transistor 320, and part of the insulating layer 326 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 326 that is in contact with the semiconductor layer 321. The top surface of the insulating layer 326 is preferably planarized.

[0415] The semiconductor layer 321 is provided over the insulating layer 326. The semiconductor layer 321 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor characteristics. Materials that can be suitably used for the semiconductor layer 321 will be described in detail later.

[0416] The pair of conductive layers 325 are provided on and in contact with the semiconductor layer 321 and function as a source electrode and a drain electrode.

[0417] An insulating layer 328 is provided to cover top surfaces and side surfaces of the pair of conductive layers 325 and side surfaces of the semiconductor layer 321, and an insulating layer 264 is provided over the insulating layer 328. The insulating layer 328 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 264 or the like to the semiconductor layer 321 and prevents oxygen from being released from the semiconductor layer 321. The insulating layer 328 can be an insulating film similar to the insulating layer 332.

[0418] An opening reaching the semiconductor layer 321 is provided in the insulating layer 328 and the insulating layer 264. An insulating layer 323 and a conductive layer 324 are buried inside the opening and are in contact with the side surfaces of the insulating layer 264, the insulating layer 328, and the conductive layer 325, as well as the top surface of the semiconductor layer 321. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0419] The upper surfaces of conductive layer 324, insulating layer 323, and insulating layer 264 are flattened to be approximately the same height, and insulating layer 329 and insulating layer 265 are provided to cover them.

[0420] The insulating layer 264 and the insulating layer 265 function as interlayer insulating layers. The insulating layer 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like to the transistor 320. The insulating layer 329 can be formed using an insulating film similar to the insulating layer 328 and the insulating layer 332.

[0421] A plug 274 electrically connected to one of the pair of conductive layers 325 is provided so as to be embedded in the insulating layer 265, the insulating layer 329, and the insulating layer 264. Here, the plug 274 preferably includes a conductive layer 274a covering the side surfaces of the openings in the insulating layer 265, the insulating layer 329, the insulating layer 264, and the insulating layer 328 and a portion of the upper surface of the conductive layer 325, and a conductive layer 274b in contact with the upper surface of the conductive layer 274a. In this case, the conductive layer 274a is preferably made of a conductive material that is difficult for hydrogen and oxygen to diffuse into.

[0422] Fig. 72 shows an example of a cross-sectional configuration of a portion of the display device 10 shown in Fig. 63B. The display device 10 shown in Fig. 72 has a configuration in which a transistor 310A having a channel formed in a substrate 301A included in the layer 40 and a transistor 310B having a channel formed in the substrate 301A included in the layer 40 are stacked. The same material as that of the substrate 301 can be used for the substrate 301A.

[0423] The display device 10 shown in Figure 72 has a configuration in which a layer 60 in which a light-emitting element 61 is provided, a layer 50 in which a substrate 301B, a transistor 310B, and a capacitor 246 are provided, and a layer 40 in which a substrate 301A and a transistor 310A are provided are bonded together.

[0424] The substrate 301B is provided with a plug 343 penetrating the substrate 301B. The plug 343 functions as a through silicon electrode (TSV: Through Silicon Via). The plug 343 is also electrically connected to a conductive layer 342 provided on the back surface of the substrate 301B (the surface opposite to the substrate 420 side). On the other hand, the substrate 301A has a conductive layer 341 provided on an insulating layer 261.

[0425] The conductive layer 341 and the conductive layer 342 are joined together, thereby electrically connecting the layer 40 and the layer 50 .

[0426] The conductive layers 341 and 342 are preferably made of the same conductive material. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Sn, Zn, Au, Ag, Pt, Ti, Mo, and W, or a metal nitride film containing the above elements (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc., can be used. In particular, copper is preferably used for the conductive layers 341 and 342. This allows for the application of Cu-Cu (copper-copper) direct bonding technology (a technology that achieves electrical conductivity by connecting Cu (copper) pads together). The conductive layers 341 and 342 may also be bonded via bumps.

[0427] Fig. 73 shows a modification of the cross-sectional configuration example shown in Fig. 72. The cross-sectional configuration example of the display device 10 shown in Fig. 73 has a stacked configuration of a transistor 310A in which a channel is formed in a substrate 301A and a transistor 320 in which a channel is formed and which contains metal oxide in a semiconductor layer. Note that descriptions of parts similar to those in Figs. 70 to 72 may be omitted.

[0428] The layer 50 shown in FIG. 73 has a configuration in which the substrate 331 is removed from the layer 50 shown in FIG. 71 . In the layer 40 shown in FIG. 73 , an insulating layer 261 is provided covering the transistor 310A, and a conductive layer 251 is provided on the insulating layer 261. An insulating layer 262 is provided covering the conductive layer 251, and the conductive layer 252 is provided on the insulating layer 262. The conductive layers 251 and 252 each function as wiring. An insulating layer 263 and an insulating layer 332 are provided covering the conductive layer 252, and the transistor 320 is provided on the insulating layer 332. An insulating layer 265 is provided covering the transistor 320, and a capacitor 246 is provided on the insulating layer 265. The capacitor 246 and the transistor 320 are electrically connected by a plug 274. The layer 50 is provided over the insulating layer 263 included in the layer 40.

[0429] The transistor 320 can be used as a transistor included in the pixel circuit 51. The transistor 310 can be used as a transistor included in the pixel circuit 51 or a transistor included in a peripheral driver circuit. The transistors 310 and 320 can be used as transistors included in a functional circuit such as an arithmetic circuit or a memory circuit.

[0430] With this configuration, not only the pixel circuits 51 but also peripheral driving circuits and the like can be formed directly below the layer 60 including the light-emitting elements 61. This makes it possible to reduce the size of the display device compared to when driving circuits are provided around the display area.

[0431] Fig. 74 shows an example cross-sectional configuration of a portion of display device 10 shown in Fig. 64A and Fig. 64B. Fig. 74 is a modification of the example cross-sectional configuration shown in Fig. 70. In Fig. 74, conductive layer 701 is provided on insulating layer 263, and insulating layer 333 is provided on conductive layer 701. Furthermore, insulating layer 332 is provided on insulating layer 333.

[0432] Conductive layer 701 is not electrically connected to conductors (such as plugs) for supplying signals from circuits included in layer 40 to circuits included in layer 50. Similarly, conductive layer 701 is not electrically connected to conductors (such as plugs) for supplying signals from circuits included in layer 50 to circuits included in layer 40.

[0433] FIG. 74 shows an example of a cross-sectional configuration in which the conductive layer 701 is provided between the layer 40 and the layer 50, but the conductive layer 701 may be provided on the layer 40 or on the layer 50.

[0434] Fig. 75 shows an example of a cross-sectional configuration of a portion of the display device 10 shown in Fig. 66. Fig. 75 is also a modified example of the cross-sectional configuration example shown in Fig. 74. In Fig. 75, a conductive layer 702 is provided on an insulating layer 263, and an insulating layer 334 is provided on the conductive layer 702. Furthermore, a conductive layer 701 is provided on the insulating layer 334, and an insulating layer 333 is provided on the conductive layer 701. Furthermore, an insulating layer 332 is provided on the insulating layer 333.

[0435] Like the conductive layer 701, the conductive layer 702 is not electrically connected to a conductor (such as a plug) for supplying a signal from a circuit included in the layer 40 to a circuit included in the layer 50. Moreover, the conductive layer 702 is not electrically connected to a conductor (such as a plug) for supplying a signal from a circuit included in the layer 50 to a circuit included in the layer 40. Note that the conductive layer 701 and the conductive layer 702 may be electrically connected.

[0436] 75 shows an example of a cross-sectional structure in which the conductive layer 701 and the conductive layer 702 are provided between the layer 40 and the layer 50, the conductive layer 701 and the conductive layer 702 may be provided on the layer 40 or on the layer 50. Alternatively, the conductive layer 702 may be provided on the layer 40, and the conductive layer 701 may be provided on the layer 50.

[0437] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0438] (Embodiment 10) A display device 10 according to an aspect of the present invention can display images using interlaced driving. In this embodiment, the interlaced driving of the display device 10 will be described.

[0439] [Drive method 1] FIG. 76A shows a block diagram of the display device 10. Of the pixels 230 arranged in a matrix of m rows and n columns, FIG. 76A shows 4 rows and 3 columns of pixels 230. The pixels 230 in the first row are electrically connected to the first drive circuit unit 231 via a wiring GLa[1]. The pixels 230 in the second row are electrically connected to the first drive circuit unit 231 via a wiring GLa[2]. The pixels 230 in the third row are electrically connected to the first drive circuit unit 231 via a wiring GLa[3]. The pixels 230 in the fourth row are electrically connected to the first drive circuit unit 231 via a wiring GLa[4]. The wiring GLa functions as a scanning line.

[0440] The pixels 230 in the first column are electrically connected to the second drive circuit unit 232 via wiring DL[1]. The pixels 230 in the second column are electrically connected to the second drive circuit unit 232 via wiring DL[2]. The pixels 230 in the third column are electrically connected to the second drive circuit unit 232 via wiring DL[3]. The wiring DL functions as a video signal line.

[0441] In Fig. 76A, the pixel 230 in the fourth row and third column is shown as pixel 230[4,3]. Also, the pixel 230 in the mth row and third column is shown as pixel 230[m,3]. Note that in Fig. 76A, the illustration of wirings other than wiring GLa and wiring DL is omitted.

[0442] The first drive circuit section 231 is supplied with a start pulse VSP and a clock signal VCLK.

[0443] FIG. 76B is a timing chart illustrating the operation of the display device 10 shown in FIG. 76A. When a start pulse VSP is supplied to the first drive circuit unit 231, the wiring GLa is selected in sequence in synchronization with the clock signal VCLK. During the period in which the wiring GLa is selected, a video signal is supplied from the second drive circuit unit 232 to the pixel 230. The period in which the wirings GLa[1] to GLa[m] are selected in sequence is called a "frame" or "frame period." Generally, during the image display period, selection of the wirings GLa[1] to GLa[m] is repeated. Therefore, the start pulse VSP is supplied every frame period.

[0444] For example, depending on the video source to be displayed, the display quality may be comparable even if the pixel density is lower than that of the display device 10. In this case, by switching the selection between the odd-numbered and even-numbered line GLa every frame, the load on the light-emitting element 61 can be reduced while maintaining the display quality. This can improve the reliability of the display device 10.

[0445] The timing chart shown in FIG. 76B illustrates an example of operation in which odd-numbered line wirings GLa are sequentially selected in the first frame (odd frame), and even-numbered line wirings GLa are not selected. Also, in the second frame (even frame), even-numbered line wirings GLa are sequentially selected, and odd-numbered line wirings GLa are not selected. It is also possible to sequentially select even-numbered line wirings GLa in odd-numbered frames, and odd-numbered line wirings GLa in even-numbered frames. A driving method in which the row to which a video signal is written is switched for each frame is called "interlace" or "interlace driving." A driving method in which a video signal is written to all pixels in one frame is called "progressive" or "progressive driving."

[0446] If it is desired to increase the luminance of light emitted, the light-emitting elements 61a and 61b can be simultaneously illuminated and the display operation can be performed using progressive driving without interlaced driving. Alternatively, the frame frequency during interlaced driving can be increased. The frame frequency is preferably 60 Hz or higher, more preferably 120 Hz or higher, and even more preferably 240 Hz or higher. Interlaced driving and progressive driving can be switched between as needed.

[0447] [Drive method 2] Next, interlaced driving when the semiconductor device 100F or the semiconductor device 100G is used as the pixel 230 will be described with reference to Fig. 77. To reduce repetition of the description, differences from Fig. 76 will be mainly described.

[0448] As shown in the above embodiments, each of the semiconductor devices 100F and 100G includes the light emitting element 61a whose cathode is electrically connected to the wiring 104a and the light emitting element 61b whose cathode is electrically connected to the wiring 104b.

[0449] Fig. 77A is a block diagram of a display device 10 that uses a semiconductor device 100F or a semiconductor device 100G as pixels 230. In Fig. 77A, the pixels 230 in odd-numbered rows are electrically connected to wiring 104a, and the pixels 230 in even-numbered rows are electrically connected to wiring 104b. Alternatively, the pixels 230 in even-numbered rows may be electrically connected to wiring 104a, and the pixels 230 in odd-numbered rows may be electrically connected to wiring 104b.

[0450] In FIG. 77A, wiring other than the wiring GLa and the wiring DL is omitted.

[0451] Furthermore, the semiconductor device 100F and the semiconductor device 100G can halve the number of wirings GLa because the light-emitting element 61a and the light-emitting element 61b can be driven by one pixel circuit 51. In Fig. 77A, the pixels 230 in the first row and the pixels 230 in the second row are electrically connected to the wiring GLa[1], which is the first wiring GLa, and the pixels 230 in the third row and the pixels 230 in the fourth row are electrically connected to the wiring GLa[2], which is the second wiring GLa.

[0452] 77A, the wiring GLa electrically connected to the pixel 230 in the mth row is shown as wiring GLa[p]. When m is an even number, p is half of m, and when m is an odd number, p is half of m+1.

[0453] Moreover, the light emitting element 61a is used for the odd-numbered pixels 230, and the light emitting element 61b is used for the even-numbered pixels 230. Alternatively, the light emitting element 61a may be used for the even-numbered pixels 230, and the light emitting element 61b may be used for the odd-numbered pixels 230.

[0454] FIG. 77B is a timing chart illustrating the operation of the display device 10 shown in FIG. 77A. The first through p-th wirings GLa are sequentially selected for each frame in synchronization with the clock signal VCLK. In addition, in the first frame (odd-numbered frame), a potential Vc is supplied to the wiring 104a, and a potential Va is supplied to the wiring 104b. In addition, in the second frame (even-numbered frame), a potential Va is supplied to the wiring 104a, and a potential Vc is supplied to the wiring 104b. In this way, interlaced driving can be achieved.

[0455] As described in the above embodiment, the semiconductor device 100F and the semiconductor device 100G are suitable for improving the resolution of the display device because the pixel circuits 51F and 51G that control the light emission of the light-emitting element 61 occupy a small area. A display device with high pixel density can be realized by operating the display device 10 that uses the semiconductor device 100F or the semiconductor device 100G for the pixel 230 in interlaced driving.

[0456] [Drive method 3] Next, interlaced driving when the semiconductor device 100H is used as the pixel 230 will be described with reference to Fig. 78. Note that Fig. 78 is a modified example of Fig. 77. Therefore, to reduce repetition of explanation, differences from Fig. 77 will be mainly described.

[0457] As described in the above embodiment, the semiconductor device 100H includes the circuit 52a, the circuit 52b, the light-emitting element 61a, and the light-emitting element 61b. The circuit 52a functions as a switch that selects whether or not the light-emitting element 61a emits light, and the circuit 52b functions as a switch that selects whether or not the light-emitting element 61b emits light. The circuit 52a is electrically connected to the wiring GLc, and the circuit 52b is electrically connected to the wiring GLd.

[0458] When the light-emitting element 61a is used for the pixels 230 in the odd-numbered rows, the wiring GLc is electrically connected to the pixels 230 in the odd-numbered rows. When the light-emitting element 61b is used for the pixels 230 in the even-numbered rows, the wiring GLd is electrically connected to the pixels 230 in the even-numbered rows.

[0459] FIG. 78B is a timing chart illustrating the operation of the display device 10 shown in FIG. 78A. The first to pth wirings GLa are sequentially selected in synchronization with the clock signal VCLK for each frame. Furthermore, in the first frame (odd frame), wirings GLc are sequentially selected in synchronization with wirings GLa. For example, when wiring GLa[1] is selected, wiring GLc[1] is also selected. In the first frame (odd frame), none of the wirings GLd are selected. Therefore, the light-emitting element 61a emits light, and the light-emitting element 61b does not emit light.

[0460] In the second frame (even frame), the wiring GLd is selected sequentially in synchronization with the wiring GLa. For example, when the wiring GLa[1] is selected, the wiring GLd[1] is also selected. In the second frame (even frame), none of the wirings GLc are selected. Therefore, the light-emitting element 61b emits light, and the light-emitting element 61a does not emit light. In this way, interlaced driving can be achieved.

[0461] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0462] (Embodiment 11) In this embodiment, a transistor that can be used in a semiconductor device according to one embodiment of the present invention will be described.

[0463] <Transistor configuration example> 79A, 79B, and 79C are a top view and a cross-sectional view of a transistor 500 that can be used in a semiconductor device according to one embodiment of the present invention. The transistor 500 can be used in a semiconductor device according to one embodiment of the present invention.

[0464] FIG. 79A is a top view of the transistor 500. Also, FIGS. 79B and 79C are cross-sectional views of the transistor 500. Here, FIG. 79B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 79A, and is also a cross-sectional view of the transistor 500 in the channel length direction. Also, FIG. 79C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 79A, and is also a cross-sectional view of the transistor 500 in the channel width direction. Note that in the top view of FIG. 79A, some elements are omitted for clarity.

[0465] As shown in FIG. 79, the transistor 500 has a metal oxide 531a arranged on a substrate (not shown), a metal oxide 531b arranged on the metal oxide 531a, conductors 542a and 542b arranged spaced apart from each other on the metal oxide 531b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed between the conductors 542a and 542b, a conductor 560 arranged in the opening, an insulator 550 arranged among the metal oxide 531b, the conductors 542a, 542b, and the insulator 580, and the conductor 560, and a metal oxide 531c arranged among the metal oxide 531b, the conductors 542a, 542b, the insulator 580, and the insulator 550. 79B and 79C, it is preferable that the top surface of conductor 560 substantially coincides with the top surfaces of insulator 550, insulator 554, metal oxide 531c, and insulator 580. Note that, hereinafter, metal oxide 531a, metal oxide 531b, and metal oxide 531c may be collectively referred to as metal oxide 531. Furthermore, conductor 542a and conductor 542b may be collectively referred to as conductor 542.

[0466] In the transistor 500 shown in Figure 79, the side surfaces of the conductors 542a and 542b facing the conductor 560 have a substantially vertical shape. Note that the transistor 500 shown in Figure 79 is not limited to this, and the angle formed between the side surface and the bottom surface of the conductors 542a and 542b may be 10° or more and 80° or less, preferably 30° or more and 60° or less. Furthermore, the opposing side surfaces of the conductors 542a and 542b may have multiple surfaces.

[0467] 79, it is preferable that insulator 554 be disposed between insulator 524, metal oxide 531a, metal oxide 531b, conductor 542a, conductor 542b, and metal oxide 531c and insulator 580. Here, it is preferable that insulator 554 be in contact with the side surface of metal oxide 531c, the top and side surfaces of conductor 542a, the top and side surfaces of conductor 542b, the side surfaces of metal oxide 531a and metal oxide 531b, and the top surface of insulator 524, as shown in FIGS.

[0468] Although the transistor 500 has a three-layer structure of the metal oxide 531a, the metal oxide 531b, and the metal oxide 531c in and around a region where a channel is formed (hereinafter also referred to as a channel formation region), the present invention is not limited to this. For example, a two-layer structure of the metal oxide 531b and the metal oxide 531c or a stacked structure of four or more layers may be provided. Furthermore, the transistor 500 has a two-layer structure of the conductor 560, but the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide 531a, the metal oxide 531b, and the metal oxide 531c may have a stacked structure of two or more layers.

[0469] For example, when the metal oxide 531c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of the metal oxide 531b, and the second metal oxide has a composition similar to that of the metal oxide 531a.

[0470] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. Here, the arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for a high-resolution display device. Furthermore, the display device can have a narrow frame.

[0471] As shown in FIG. 79, the conductor 560 preferably has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a.

[0472] The transistor 500 preferably includes an insulator 514 disposed on a substrate (not shown), an insulator 516 disposed on the insulator 514, a conductor 505 disposed so as to be embedded in the insulator 516, an insulator 522 disposed on the insulator 516 and the conductor 505, and an insulator 524 disposed on the insulator 522. A metal oxide 531a is preferably disposed on the insulator 524.

[0473] An insulator 574 and an insulator 581, which function as interlayer films, are preferably disposed over the transistor 500. Here, the insulator 574 is preferably disposed in contact with top surfaces of the conductor 560, the insulator 550, the insulator 554, the metal oxide 531c, and the insulator 580.

[0474] The insulators 522, 554, and 574 preferably have a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). For example, the insulators 522, 554, and 574 preferably have lower hydrogen permeability than the insulators 524, 550, and 580. The insulators 522 and 554 preferably have a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulators 522 and 554 preferably have lower oxygen permeability than the insulators 524, 550, and 580.

[0475] Here, the insulator 524, the metal oxide 531, and the insulator 550 are separated from each other by the insulators 580 and 581, and the insulators 554 and 574. This prevents impurities such as hydrogen and excess oxygen contained in the insulators 580 and 581 from being mixed into the insulators 524, the metal oxide 531, and the insulator 550.

[0476] A conductor 545 (conductor 545a and conductor 545b) that is electrically connected to the transistor 500 and functions as a plug is preferably provided. Note that the insulator 541 (insulator 541a and insulator 541b) is provided in contact with the side surface of the conductor 545 that functions as a plug. That is, the insulator 541 is provided in contact with the inner walls of the openings of the insulators 554, 580, 574, and 581. Alternatively, a first conductor of the conductor 545 may be provided in contact with the side surface of the insulator 541, and a second conductor of the conductor 545 may be provided further inward. Here, the height of the top surface of the conductor 545 and the height of the insulator 581 can be made approximately the same. Note that the transistor 500 illustrates a structure in which the first conductor of the conductor 545 and the second conductor of the conductor 545 are stacked, but the present invention is not limited to this. For example, the conductor 545 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, it may be distinguished by adding an ordinal number to the order of formation.

[0477] The transistor 500 preferably uses a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) for the metal oxide 531 (metal oxide 531a, metal oxide 531b, and metal oxide 531c) including the channel formation region. For example, the metal oxide that forms the channel formation region of the metal oxide 531 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more.

[0478] The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). Furthermore, it is preferable that it contains an element M in addition to these. The element M can be one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, it is preferable that the element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is more preferable that the element M contains either or both of Ga and Sn.

[0479] Furthermore, as shown in FIG. 79B , the thickness of the metal oxide 531b in a region that does not overlap with the conductor 542 may be thinner than the thickness of the region that overlaps with the conductor 542. This is formed by removing a portion of the upper surface of the metal oxide 531b when forming the conductors 542a and 542b. When a conductive film that will become the conductor 542 is formed on the upper surface of the metal oxide 531b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region located between the conductors 542a and 542b on the upper surface of the metal oxide 531b, it is possible to prevent a channel from being formed in that region.

[0480] According to one embodiment of the present invention, a display device having high definition and a small transistor can be provided. Alternatively, a display device having high luminance and a transistor with high on-state current can be provided. Alternatively, a display device having high-speed operation and a transistor with stable electrical characteristics can be provided. Alternatively, a display device having low power consumption and a transistor with low off-state current can be provided.

[0481] A detailed structure of a transistor 500 that can be used in a display device according to one embodiment of the present invention will be described.

[0482] The conductor 505 is arranged to have a region overlapping with the metal oxide 531 and the conductor 560. The conductor 505 is preferably embedded in the insulator 516.

[0483] The conductor 505 includes conductors 505a, 505b, and 505c. The conductor 505a is provided in contact with the bottom surface and sidewall of an opening provided in the insulator 516. The conductor 505b is provided so as to be embedded in a recess formed in the conductor 505a. Here, the upper surface of the conductor 505b is lower than the upper surface of the conductor 505a and the upper surface of the insulator 516. The conductor 505c is provided in contact with the upper surface of the conductor 505b and the side surface of the conductor 505a. Here, the height of the upper surface of the conductor 505c is approximately the same as the height of the upper surface of the conductor 505a and the height of the upper surface of the insulator 516. In other words, the conductor 505b is configured to be surrounded by the conductors 505a and 505c.

[0484] Conductor 505a and conductor 505c are preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0485] By using a conductive material capable of reducing hydrogen diffusion for the conductors 505a and 505c, it is possible to prevent impurities such as hydrogen contained in the conductor 505b from diffusing into the metal oxide 531 via the insulator 524 or the like. Furthermore, by using a conductive material capable of suppressing oxygen diffusion for the conductors 505a and 505c, it is possible to prevent the conductor 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials capable of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 505a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 505a may be made of titanium nitride.

[0486] The conductor 505b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0487] Here, the conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 505 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the conductor 505 may be changed independently of the potential applied to the conductor 560, thereby controlling the V th In particular, applying a negative potential to the conductor 505 can control the V th The off-state current can be reduced by making the potential greater than 0 V. Therefore, applying a negative potential to the conductor 505 can reduce the drain current when the potential applied to the conductor 560 is 0 V, compared to when no potential is applied.

[0488] The conductor 505 is preferably provided to be larger than the channel formation region of the metal oxide 531. In particular, as shown in Fig. 79C, the conductor 505 preferably extends also in a region outside the end portion intersecting with the channel width direction of the metal oxide 531. In other words, outside the side surface of the metal oxide 531 in the channel width direction, the conductor 505 and the conductor 560 preferably overlap with each other with an insulator interposed therebetween.

[0489] With the above structure, the channel formation region of the metal oxide 531 can be electrically surrounded by the electric field of the conductor 560 functioning as a first gate electrode and the electric field of the conductor 505 functioning as a second gate electrode.

[0490] 79C, the conductor 505 is extended to function as wiring. However, the present invention is not limited to this, and a conductor that functions as wiring may be provided below the conductor 505.

[0491] The insulator 514 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 500 from the substrate side. Therefore, the insulator 514 is preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., the impurities are less likely to permeate through the insulator). Alternatively, the insulator 514 is preferably made of an insulating material that has a function of preventing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate through the insulator).

[0492] For example, aluminum oxide, silicon nitride, or the like is preferably used for the insulator 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulator 514 to the transistor 500 side. Alternatively, oxygen contained in the insulator 524 or the like can be prevented from diffusing from the insulator 514 to the substrate side.

[0493] The insulators 516, 580, and 581, which function as interlayer films, preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 516, 580, and 581.

[0494] The insulators 522 and 524 function as gate insulators.

[0495] Here, the insulator 524 in contact with the metal oxide 531 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 524 can be formed using silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the metal oxide 531, oxygen vacancies in the metal oxide 531 can be reduced, and the reliability of the transistor 500 can be improved.

[0496] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as the insulator 524. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0497] 79C, the thickness of insulator 524 in a region that does not overlap with insulator 554 and metal oxide 531b may be thinner than the thickness of the other region. In insulator 524, the thickness of the region that does not overlap with insulator 554 and metal oxide 531b is preferably a thickness that allows sufficient diffusion of the oxygen.

[0498] Like the insulator 514 and the like, the insulator 522 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 500 from the substrate side. For example, the insulator 522 preferably has lower hydrogen permeability than the insulator 524. By surrounding the insulator 524, the metal oxide 531, the insulator 550, and the like with the insulators 522, 554, and 574, impurities such as water or hydrogen can be prevented from entering the transistor 500 from the outside.

[0499] Furthermore, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, the insulator 522 preferably has lower oxygen permeability than the insulator 524. The insulator 522 preferably has a function of suppressing the diffusion of oxygen and impurities, which can reduce the diffusion of oxygen contained in the metal oxide 531 toward the substrate side. Furthermore, the conductor 505 can be prevented from reacting with oxygen contained in the insulator 524 and the metal oxide 531.

[0500] The insulator 522 may be an insulator containing an oxide of one or both of insulating materials, such as aluminum and hafnium. Examples of the insulator containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that prevents oxygen from being released from the metal oxide 531 and prevents impurities, such as hydrogen, from entering the metal oxide 531 from the periphery of the transistor 500.

[0501] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0502] The insulator 522 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0503] The insulator 522 and the insulator 524 may have a layered structure of two or more layers. In this case, the layers are not limited to being made of the same material, and may be made of different materials. For example, an insulator similar to the insulator 524 may be provided below the insulator 522.

[0504] Metal oxide 531 includes metal oxide 531a, metal oxide 531b on metal oxide 531a, and metal oxide 531c on metal oxide 531b. Having metal oxide 531a below metal oxide 531b makes it possible to suppress the diffusion of impurities from structures formed below metal oxide 531a to metal oxide 531b. Also, having metal oxide 531c on metal oxide 531b makes it possible to suppress the diffusion of impurities from structures formed above metal oxide 531c to metal oxide 531b.

[0505] Metal oxide 531 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, when metal oxide 531 contains at least indium (In) and element M, the ratio of the number of atoms of element M contained in metal oxide 531a to the number of atoms of all elements constituting metal oxide 531a is preferably higher than the ratio of the number of atoms of element M contained in metal oxide 531b to the number of atoms of all elements constituting metal oxide 531b. Furthermore, the ratio of the number of atoms of element M contained in metal oxide 531a to In is preferably higher than the ratio of the number of atoms of element M contained in metal oxide 531b to In. Here, metal oxide 531c can be the same as that used for metal oxide 531a or metal oxide 531b.

[0506] The energy of the conduction band minimum of metal oxide 531a and metal oxide 531c is preferably higher than the energy of the conduction band minimum of metal oxide 531b. In other words, the electron affinity of metal oxide 531a and metal oxide 531c is preferably lower than the electron affinity of metal oxide 531b. In this case, metal oxide 531c is preferably a metal oxide that can be used for metal oxide 531a. Specifically, the ratio of the number of atoms of element M contained in metal oxide 531c to the number of atoms of all elements constituting metal oxide 531c is preferably higher than the ratio of the number of atoms of element M contained in metal oxide 531b to the number of atoms of all elements constituting metal oxide 531b. Furthermore, the atomic ratio of element M contained in metal oxide 531c to In is preferably higher than the atomic ratio of element M contained in metal oxide 531b to In.

[0507] Here, the energy level of the conduction band minimum changes smoothly at the junction between the metal oxides 531a, 531b, and 531c. In other words, the energy level of the conduction band minimum at the junction between the metal oxides 531a, 531b, and 531c changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layers formed at the interface between the metal oxides 531a and 531b and at the interface between the metal oxides 531b and 531c.

[0508] Specifically, when the metal oxide 531a and the metal oxide 531b, and the metal oxide 531b and the metal oxide 531c have a common element other than oxygen (as a main component), a mixed layer with a low density of defect states can be formed. For example, when the metal oxide 531b is an In-Ga-Zn oxide, the metal oxide 531a and the metal oxide 531c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like. The metal oxide 531c may also have a layered structure. For example, a layered structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide, or a layered structure of an In-Ga-Zn oxide and a gallium oxide on the In-Ga-Zn oxide, may be used. In other words, a layered structure of an In-Ga-Zn oxide and an oxide not containing In may be used as the metal oxide 531c.

[0509] Specifically, metal oxide 531a may have an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. Metal oxide 531b may have an atomic ratio of In:Ga:Zn=4:2:3 or 3:1:2. Metal oxide 531c may have an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the metal oxide 531c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0510] In this case, the main carrier path is the metal oxide 531b. The above-described configuration of the metal oxide 531a and the metal oxide 531c can reduce the defect state density at the interface between the metal oxide 531a and the metal oxide 531b and at the interface between the metal oxide 531b and the metal oxide 531c. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 500 to achieve a high on-state current and high frequency characteristics. Note that, when the metal oxide 531c has a layered structure, in addition to the effect of reducing the defect state density at the interface between the metal oxide 531b and the metal oxide 531c, it is expected to suppress the diffusion of constituent elements of the metal oxide 531c toward the insulator 550. More specifically, the metal oxide 531c has a layered structure, and an oxide not containing In is positioned above the layered structure, thereby suppressing In diffusion toward the insulator 550. The insulator 550 functions as a gate insulator, and diffusion of In leads to poor transistor characteristics. Therefore, by forming the metal oxide 531c into a stacked structure, a highly reliable display device can be provided.

[0511] Conductor 542 (conductor 542a and conductor 542b) functioning as a source electrode and a drain electrode are provided on metal oxide 531b. Conductor 542 is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when they absorb oxygen.

[0512] By providing the conductor 542 so as to be in contact with the metal oxide 531, the oxygen concentration may be reduced in the vicinity of the conductor 542 of the metal oxide 531. Furthermore, a metal compound layer containing the metal contained in the conductor 542 and components of the metal oxide 531 may be formed in the vicinity of the conductor 542 of the metal oxide 531. In such a case, the carrier concentration increases in the region of the metal oxide 531 in the vicinity of the conductor 542, and the region becomes a low-resistance region.

[0513] Here, the region between the conductor 542a and the conductor 542b is formed to overlap the opening of the insulator 580. This allows the conductor 560 to be arranged in a self-aligned manner between the conductor 542a and the conductor 542b.

[0514] The insulator 550 functions as a gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the metal oxide 531c. The insulator 550 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0515] The insulator 550 preferably has a reduced concentration of impurities such as water or hydrogen, similar to the insulator 524. The thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0516] A metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. This can suppress oxidation of the conductor 560 by oxygen in the insulator 550.

[0517] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 550, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator as a stacked structure of the insulator 550 and the metal oxide, a stacked structure that is thermally stable and has a high dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0518] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0519] Although the conductor 560 is shown as having a two-layer structure in FIG. 79, it may have a single-layer structure or a laminated structure of three or more layers.

[0520] The conductor 560a is preferably made of a conductor having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0521] Conductor 560a has the function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of conductor 560b caused by oxygen contained in insulator 550. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0522] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0523] 79A and 79C, in a region of the metal oxide 531b that does not overlap with the conductor 542, in other words, in the channel formation region of the metal oxide 531, the conductor 560 is arranged to cover the side surface of the metal oxide 531. This makes it easier for the electric field of the conductor 560, which functions as the first gate electrode, to act on the side surface of the metal oxide 531. This increases the on-state current of the transistor 500 and improves its frequency characteristics.

[0524] Like the insulator 514, the insulator 554 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 500 from the insulator 580 side. For example, the insulator 554 preferably has lower hydrogen permeability than the insulator 524. Furthermore, as shown in FIGS. 79B and 79C , the insulator 554 preferably contacts the side surface of the metal oxide 531c, the top and side surfaces of the conductor 542a, the top and side surfaces of the conductor 542b, the side surfaces of the metal oxide 531a and the metal oxide 531b, and the top surface of the insulator 524. This structure prevents hydrogen contained in the insulator 580 from entering the metal oxide 531 from the top or side surfaces of the conductor 542a, the conductor 542b, the metal oxide 531a, the metal oxide 531b, and the insulator 524.

[0525] Furthermore, the insulator 554 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., is less permeable to oxygen). For example, the insulator 554 preferably has lower oxygen permeability than the insulator 580 or the insulator 524.

[0526] The insulator 554 is preferably formed by a sputtering method. By forming the insulator 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulator 524 near a region in contact with the insulator 554. This allows oxygen to be supplied from the region to the metal oxide 531 through the insulator 524. The insulator 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 531 to the insulator 580. The insulator 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 531 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the metal oxide 531. This reduces oxygen vacancies in the metal oxide 531 and suppresses the transistor from becoming normally on.

[0527] For example, an insulator containing one or both of an oxide of aluminum and hafnium may be formed as the insulator 554. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.

[0528] The insulator 524, the insulator 550, and the metal oxide 531 are covered with the insulator 554, which has a barrier property against hydrogen, and thus the insulator 580 is separated from the insulator 524, the metal oxide 531, and the insulator 550 by the insulator 554. This can prevent impurities such as hydrogen from penetrating from the outside of the transistor 500, thereby providing the transistor 500 with good electrical characteristics and reliability.

[0529] The insulator 580 is provided over the insulator 524, the metal oxide 531, and the conductor 542 with the insulator 554 interposed therebetween. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly preferred because they can easily form a region containing oxygen that is released by heating.

[0530] It is preferable that the concentration of impurities such as water or hydrogen is reduced in the insulator 580. The top surface of the insulator 580 may be planarized.

[0531] Like the insulator 514, the insulator 574 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 580 from above. The insulator 574 can be, for example, an insulator that can be used for the insulator 514, the insulator 554, and the like.

[0532] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524 and the like, the insulator 581 preferably has a low concentration of impurities such as water or hydrogen.

[0533] Conductor 545a and conductor 545b are arranged in openings formed in insulator 581, insulator 574, insulator 580, and insulator 554. Conductor 545a and conductor 545b are provided facing each other with conductor 560 interposed therebetween. Note that the height of the upper surfaces of conductor 545a and conductor 545b may be flush with the upper surface of insulator 581.

[0534] Note that insulator 541a is provided in contact with the inner walls of the openings of insulators 581, 574, 580, and 554, and a first conductor of conductor 545a is formed in contact with the side surface of insulator 541a. Conductor 542a is located on at least a portion of the bottom of the openings, and conductor 545a is in contact with conductor 542a. Similarly, insulator 541b is provided in contact with the inner walls of the openings of insulators 581, 574, 580, and 554, and a first conductor of conductor 545b is formed in contact with the side surface of insulator 541b. Conductor 542b is located on at least a portion of the bottom of the openings, and conductor 545b is in contact with conductor 542b.

[0535] The conductors 545a and 545b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 545a and 545b may have a layered structure.

[0536] When the conductor 545 has a layered structure, the conductors in contact with the metal oxide 531a, the metal oxide 531b, the conductor 542, the insulator 554, the insulator 580, the insulator 574, and the insulator 581 preferably have the above-described function of suppressing the diffusion of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Furthermore, the conductive material capable of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a layered structure. The use of such a conductive material can suppress the absorption of oxygen added to the insulator 580 by the conductors 545a and 545b. Furthermore, it can suppress the intrusion of impurities such as water or hydrogen from layers above the insulator 581 into the metal oxide 531 through the conductors 545a and 545b.

[0537] The insulators 541a and 541b can be, for example, an insulator that can be used for the insulator 554. The insulators 541a and 541b are provided in contact with the insulator 554, and thus can prevent impurities such as water or hydrogen from the insulator 580 or the like from being mixed into the metal oxide 531 through the conductors 545a and 545b. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 545a and 545b.

[0538] Although not shown, a conductor functioning as wiring may be disposed in contact with the upper surface of the conductor 545a and the upper surface of the conductor 545b. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0539] <Transistor constituent materials> The constituent materials that can be used for the transistor will be described.

[0540] [substrate] The substrate on which the transistor 500 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate, are also available. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having metal nitrides and substrates having metal oxides. Examples of other substrates include an insulating substrate with a conductor or semiconductor provided thereon, a semiconductor substrate with a conductor or insulator provided thereon, and a conductive substrate with a semiconductor or insulator provided thereon. Alternatively, these substrates may be used with elements provided thereon. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0541] [Insulator] Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0542] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials based on the insulator's function.

[0543] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0544] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0545] The electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding it with an insulator (such as insulator 514, insulator 522, insulator 554, or insulator 574) that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, a single-layer or stacked insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide; and metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0546] The insulator serving as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the metal oxide 531, oxygen vacancies in the metal oxide 531 can be compensated for.

[0547] [conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0548] A plurality of conductors formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0549] When a metal oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure of a combination of a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0550] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0551] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0552] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0553] (Embodiment 12) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0554] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 80A, which is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0555] As shown in Figure 80A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0556] The structure within the bold frame in Figure 80A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as a structure that is completely different from "Crystal" or the energetically unstable "Amorphous."

[0557] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 80B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 80B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 80B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 80B is 500 nm.

[0558] As shown in Figure 80B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 80B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0559] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). Figure 80C shows the diffraction pattern of a CAAC-IGZO film. Figure 80C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 80C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0560] As shown in FIG. 80C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0561] [Structure of oxide semiconductor] Note that oxide semiconductors may be classified differently from those shown in FIG. 80A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0562] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0563] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0564] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0565] In an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0566] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0567] For example, in the electron diffraction pattern of a CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0568] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries can be identified even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0569] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the transistor's on-state current and field-effect mobility. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in transistor semiconductor layers. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0570] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, because the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities and / or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0571] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of these microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when electron diffraction (also known as selected-area electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0572] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0573] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0574] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0575] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0576] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0577] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0578] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0579] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0580] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0581] Oxide semiconductors have a variety of structures and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0582] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0583] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0584] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO") as the semiconductor layer in which the channel is formed. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used as the semiconductor layer.

[0585] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 That is all. Note that in order to reduce the carrier concentration of an oxide semiconductor, the impurity concentration in the oxide semiconductor may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0586] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states, and therefore may also have a low density of trap states.

[0587] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0588] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0589] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0590] When an oxide semiconductor contains silicon and / or carbon, which are elements of Group 14, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by SIMS) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0591] When an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0592] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0593] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0594] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0595] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0596] (Embodiment 13) In this embodiment, electronic devices to which a semiconductor device according to one embodiment of the present invention can be applied will be described.

[0597] The semiconductor device according to one embodiment of the present invention can be applied to a display portion of an electronic device. Therefore, an electronic device with high display quality, extremely high resolution, or high reliability can be realized.

[0598] Examples of electronic devices using a semiconductor device or the like according to one embodiment of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and DVD (Digital Versatile Disc) players. Examples of such equipment include image playback devices that play back still images or videos stored on recording media such as CDs, portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, car phones, mobile phones, personal digital assistants, tablet terminals, portable game consoles, fixed game consoles such as pachinko machines, calculators, electronic organizers, e-book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, air conditioning equipment such as electric rice cookers, electric washing machines, electric vacuum cleaners, hot water heaters, electric fans, hair dryers, air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Other examples include industrial equipment such as emergency lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids. Mobile vehicles propelled by fuel-powered engines or electric motors powered by power storage devices may also be included in the category of electronic devices. Examples of such mobile vehicles include electric vehicles (EVs), hybrid vehicles (HVs) that combine internal combustion engines and electric motors, plug-in hybrid vehicles (PHVs), tracked vehicles in which the tires and wheels of these vehicles have been replaced with tracks, mopeds including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, satellites, space probes, planetary probes, and spacecraft.

[0599] An electronic device according to one embodiment of the present invention may include a secondary battery (battery), and it is preferable that the secondary battery can be charged using contactless power transmission.

[0600] Examples of secondary batteries include lithium ion secondary batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0601] An electronic device according to one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0602] An electronic device according to one embodiment of the present invention may have a sensor (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0603] An electronic device according to one embodiment of the present invention can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[0604] Furthermore, electronic devices having multiple display units can have a function of mainly displaying image information on one part of the display units and mainly displaying text information on another part, or a function of displaying a stereoscopic image by displaying an image taking into account parallax on the multiple display units. Furthermore, electronic devices having an image receiving unit can have a function of capturing a still image or a moving image, a function of automatically or manually correcting the captured image, a function of storing the captured image in a recording medium (external or built in the electronic device), a function of displaying the captured image on the display unit, etc. Note that the functions of the electronic device of one embodiment of the present invention are not limited to these, and can have various functions.

[0605] The semiconductor device according to one embodiment of the present invention can display high-resolution images. Therefore, the semiconductor device can be suitably used in portable electronic devices, wearable electronic devices, e-book readers, and the like. For example, the semiconductor device can be suitably used in xR devices such as VR devices and AR devices.

[0606] FIG. 81A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0607] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. A detachable lens 8006 is attached to the camera 8000. Note that the lens 8006 and the housing of the camera 8000 may be integrated together.

[0608] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0609] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as a strobe device and the like.

[0610] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0611] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0612] The button 8103 has a function such as a power button.

[0613] The semiconductor device according to one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the finder 8100 may be built in the camera 8000.

[0614] FIG. 81B is a diagram showing the appearance of the head mounted display 8200.

[0615] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0616] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like, and can display received video information on a display portion 8204. The main body 8203 also includes a camera, and can use information on the movement of the user's eyeballs or eyelids as an input means.

[0617] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that come into contact with the user, capable of detecting a current that flows in accordance with the movement of the user's ...

Claims

1. a display element; and a display device including first to eighth transistors, first to third capacitors, and a display element. a gate of the first transistor and a gate of the sixth transistor are electrically connected to a first wiring; a gate of the third transistor and a gate of the fourth transistor are electrically connected to a second wiring; a gate of the seventh transistor is electrically connected to a third wiring; a gate of the eighth transistor is electrically connected to a fourth wiring; one of the source and the drain of the first transistor is electrically connected to a fifth wiring; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor, one of the source and the drain of the third transistor, and one terminal of the first capacitor; one of the source and the drain of the second transistor is electrically connected to a sixth wiring; one of the source and the drain of the fourth transistor is electrically connected to the sixth wiring; the other of the source and the drain of the fourth transistor is electrically connected to one terminal of the second capacitor; the other of the source or the drain of the second transistor is electrically connected to the other of the source or the drain of the third transistor, the other terminal of the first capacitor, the other terminal of the second capacitor, one of the source or the drain of the fifth transistor, and one of the source or the drain of the sixth transistor; one of the source and the drain of the seventh transistor is electrically connected to the sixth wiring; a gate of the fifth transistor is electrically connected to the other of the source and the drain of the seventh transistor, one of the source and the drain of the eighth transistor, and one terminal of the third capacitor; the other of the source or the drain of the sixth transistor and the other of the source or the drain of the eighth transistor are electrically connected to a seventh wiring; the other of the source and the drain of the fifth transistor is electrically connected to the other terminal of the third capacitor and one terminal of the display element; The other terminal of the display element is electrically connected to an eighth wiring, the second transistor has a back gate; The back gate is electrically connected to the other of the source and the drain of the fourth transistor and one terminal of the second capacitor.

2. In claim 1, At least one of a semiconductor in which a channel of the second transistor is formed and a semiconductor in which a channel of the fifth transistor is formed includes an oxide semiconductor.

3. In claim 2, The oxide semiconductor includes at least one of indium and zinc.

4. In claim 1, The display element is a semiconductor device that is an organic EL element having a tandem structure.

Images