Nor type flash memory and operation method thereof

Abstract

To provide a NOR type flash memory suitable for data protection, which requires high reliability and an operation method thereof.SOLUTION: A NOR type flash memory 100 of the present invention includes: a memory cell array 110 including a plurality of memory cells; an ECC circuit 130 that performs error detection and correction in data read from a boot storage area 112 of the memory cell array 110; means for storing identification information for identifying an error mode of a failed cell that is subjected to the error detection and correction by the ECC circuit 130 in a boot management area 210; and recovery means for recovering the failed cell so that the error of the failed cell is solved based on the identified error mode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a NOR flash memory and an operating method thereof, and more particularly to a NOR flash memory equipped with an ECC function. [Background technology]

[0002] In NAND flash memories, repeated read / program / erase cycles can cause threshold fluctuations due to degradation of the tunnel insulating film, degradation of Gm (transconductance), etc., which can lead to bit errors. To prevent such bit errors, an error detection and correction function (hereinafter referred to as an ECC function) is used (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7253594 Summary of the Invention [Problem to be solved by the invention]

[0004] NOR flash memory has memory cells connected in parallel, allowing access to memory cells on a bit-by-bit basis, making it less susceptible to disturbances and less likely to experience bit errors than NAND flash memory. This makes it suitable for storing data that requires high reliability, such as boot data and program code for running a system.

[0005] In recent years, the data volume of boot data and program code has increased, while the memory size of NOR flash memory has also been miniaturized, leading to an increase in storage capacity. As memory cells become smaller, the occurrence of bit errors can no longer be ignored, even in NOR flash memory, and the use of ECC functionality is being considered.

[0006] However, simply correcting errors using the ECC function is not sufficient to protect data that requires high reliability. For example, boot data is read from NOR flash memory when the system or software is started, but the boot data is read more frequently than other data, so the probability of an error occurring in the boot data is higher than in other data. If an error occurs in the boot data that exceeds the number of bits that the ECC function can correct, the error cannot be corrected, which is fatal to the system that is started by the boot data.

[0007] SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a NOR flash memory suitable for protecting data that requires high reliability, and an operating method thereof. [Means for solving the problem]

[0008] The NOR flash memory according to the present invention includes a memory cell array including a plurality of memory cells, an ECC means for detecting and correcting errors in data read from the memory cell array, an error identification means for identifying an error type of a fail cell whose error has been detected and corrected by the ECC means, and a recovery means for recovering the fail cell so as to eliminate the error in the fail cell based on the identified error type.

[0009] In one embodiment, when the error type indicates a decrease in the threshold value of the memory cell, the recovery means programs the failed cell to increase the threshold value. In another embodiment, the error identification means holds the address of the failed cell, and the recovery means programs the failed cell based on the address. In another embodiment, when the error type indicates an increase in the threshold value of the memory cell, the recovery means increases a read verify voltage of the failed cell. In another embodiment, the error identification means holds the address of the failed cell, and the recovery means increases a read verify voltage when reading the failed cell based on the address. In another embodiment, the NOR flash memory further includes management means for managing the occurrence of failed cells in sectors of the memory cell array, and transfer means for transferring data of the sector including the failed cell to a redundant area of ​​the memory cell array based on the management result of the management means. In another embodiment, the memory cell array includes a boot data storage area for storing boot data, and the recovery means recovers the failed cell storing the boot data.

[0010] An operating method performed by a NOR flash memory according to the present invention includes the steps of: correcting an error in data read from a memory cell array by an ECC means; identifying an error type of a failed cell whose error has been detected and corrected by the ECC means; and recovering the failed cell based on the identified error type so as to eliminate the error in the failed cell.

[0011] In one embodiment, when the error mode indicates a decrease in the threshold voltage of the memory cell, the recovering step programs the failed cell to increase the threshold voltage, and when the error mode indicates an increase in the threshold voltage of the memory cell, the recovering step increases the read verify voltage of the failed cell. [Effects of the Invention]

[0012] According to the present invention, the fail cells are recovered so that the errors in the error-detected and corrected fail cells are eliminated, so that the error detection and correction function of the ECC means can have a margin, and as a result, high reliability of the data can be maintained. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram showing a schematic configuration of a NOR flash memory according to an embodiment of the present invention; [Figure 2] 1 is a diagram showing an example of the configuration of a boot storage area and a boot management area according to an embodiment of the present invention; [Figure 3] FIG. 3A shows an error that causes the threshold voltage of a memory cell to transition in a decreasing direction, and FIG. 3B is a diagram illustrating recovery from that error. [Figure 4] FIG. 4A shows an error in which the threshold voltage of a memory cell transitions in an increasing direction, and FIG. 4B is a diagram illustrating recovery from that error. [Figure 5] 10 is a flowchart showing an operation flow when programming boot data according to the present embodiment. [Figure 6] 10 is a flow chart showing an operation flow when reading boot data according to the present embodiment. [Figure 7] FIG. 10 is a diagram showing an example of a boot management area updated when boot data is read; [Figure 8] 10 is an operational flow when replacing boot data according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] The NOR flash memory of the present invention has a memory management scheme suitable for protecting data that requires high reliability, such as boot data and program code that are read when the system or software is started, and minimizes errors in the stored data, providing highly reliable data. [Example]

[0015] Next, an embodiment of the present invention will be described in detail with reference to the drawings. Fig. 1 is a block diagram showing the configuration of a NOR flash memory according to an embodiment of the present invention. As shown in the figure, a NOR flash memory 100 of this embodiment includes a memory cell array 110 having a plurality of memory cells formed therein, an input / output circuit 120 that outputs read data to the outside in synchronization with a clock signal ExCLK and takes in data input from the outside, an ECC circuit 130 that generates codes for data to be programmed and performs error detection and correction for read data, an address register 140 that receives address data via the input / output circuit 120, a controller 150 that controls operation based on command data received via the input / output circuit 120 and control signals applied to external terminals, and a controller 150 that receives row address information Ax from the address register 140 and converts the row address information Ax into an ECC circuit 130. The memory cell array includes a row selection circuit 160 that decodes data and selects a word line or a sector based on the decoded result, a sense / write circuit 170 that senses data read from a memory cell selected by the row selection circuit 160 and writes data to be programmed into the selected memory cell, a column selection circuit 180 that receives column address information Ay from the address register 140, decodes the column address information Ay, and selects a bit line / source line based on the decoded result, and an internal voltage generation circuit 190 that generates various voltages (program voltage Vpgm, read voltage Vread, erase voltage Vers, etc.) required for reading, programming, erasing, etc. of data.

[0016] The memory cell array 110 includes a plurality of memory cells arranged in a matrix, each connected in parallel between a bit line and a source line. In other words, it has a NOR structure. The memory cells may have a two-dimensional structure formed on the surface of a substrate such as silicon, or a three-dimensional structure formed vertically from the substrate surface. The memory cells may be SLC, which stores binary data, or MLC, which stores multi-level data.

[0017] The input / output circuit 120 receives commands, addresses, data, etc. from the host system in synchronization with the clock signal ExCLK, and provides the received commands, addresses, and data to the controller 150, the address register 140, the column selection circuit 180, and the sense / write circuit 170. The input / output circuit 120 also receives data read from the memory cell array 110 from the sense / write circuit 170, and provides this to the host system.

[0018] The ECC circuit 130 includes an encoder that encodes data to generate an ECC code, and a decoder that decodes the data based on the ECC code. During a program operation, the ECC circuit 130 generates an ECC code required for error detection and correction of the input data by calculating the bit string of data input via the input / output circuit 120, and during a read operation, performs error detection and correction of data read from the memory cell array 110 based on the ECC code.

[0019] There is no particular limitation on the number of bits that can be detected and corrected by the ECC circuit 130. The ECC circuit 130 performs error detection and correction using, for example, a Hamming code, a Reed-Solomon code, or a BCH code. In the case of a BCH code, it is possible to detect and correct errors of multiple bits (e.g., 2 bits, 4 bits, 8 bits, etc.). The ECC circuit 130 may correct (bit invert) error bits in the read data held in the sense / write circuit 170, or the ECC circuit 130 may receive the read data, perform error correction therein, and output the error-corrected data to the sense / write circuit 170.

[0020] The controller 150 is configured by hardware and / or software resources, such as a microcontroller or a state machine including ROM / RAM. The controller 150 receives commands from a host system and controls overall operations such as reading, programming, and erasing based on the commands.

[0021] When a memory cell is read, the row selection circuit 160 applies a positive voltage to the selected word line, and the sense / write circuit 170 senses the current or voltage flowing between the selected bit line and the selected source line. When a memory cell is programmed (written), the row selection circuit 160 applies a program voltage to the selected word line, and the sense / write circuit 170 applies a voltage corresponding to the data to be programmed to the selected bit line. Hot electrons flowing from the selected bit line to the selected source line are stored in the charge storage layer. However, other write methods are also possible, such as trapping charges in the charge storage layer by FN tunneling. When a memory cell is erased, a voltage is applied to the selected word line, and hot holes are injected into the charge storage layer, or an erase voltage is applied to the substrate to discharge the charges stored in the charge storage layer by FN tunneling. Memory cells are erased in units of sectors containing multiple memory cells, but it can also be erased in units of memory cells.

[0022] In the memory management scheme of this embodiment, when a failed cell (error bit) is detected by the ECC circuit 130, the type of error is identified and the failed cell is recovered to eliminate the error in accordance with the identified type of error. By recovering the failed cell, it is ensured that the error can be corrected within the range that the ECC circuit 130 can detect and correct, thereby improving the reliability of the data.

[0023] In another aspect, the recovery of a fail cell is performed during the period in which the data in the fail cell is replaced. That is, in parallel with the recovery of the fail cell, the data stored in the fail cell or the sector containing the fail cell is transferred to a fresh redundant area, and the recovery of the fail cell is completed. The occurrence of a fail cell is a sign of a failure, and by avoiding the storage area in which the fail cell occurred, the occurrence of further fail cells can be suppressed.

[0024] The memory management scheme of this embodiment is implemented for data that requires high reliability, and here, boot data is used as an example of such data. Boot data (boot code) is data necessary for system operation and is protected separately from normal data used by users. Boot data is read from the memory cell array when the system is running or when the flash memory is powered on, and is provided to an external host system. If part of the boot data is lost or rewritten, it will cause a malfunction in system operation. Therefore, high reliability is required for boot data.

[0025] 2 shows a schematic example of data stored in the memory cell array and RAM. The memory cell array 110 includes a boot storage area 112 for storing boot data and a redundant area 114, in addition to an area used by the user to store normal data. The RAM 200 is a volatile memory such as an SRAM, and is provided in, for example, the controller 150. The RAM 200 also includes a boot management area 210 for storing management information for the boot data. The boot storage area 112 and the redundant area 114 can be set in any address space in the memory cell array 110, and information about the set address space is stored in, for example, a fuse ROM in the memory cell array 110. The fuse ROM stores various information related to the operation of the NOR flash memory 100. When the NOR flash memory 100 is started, the data stored in the fuse ROM is loaded into a configuration register or the like and referenced by the controller 150.

[0026] Boot data is input via the input / output circuit 120, and the controller 150 writes the input boot data to the main area of ​​the boot storage area 112. In addition, the ECC circuit 130 processes the input boot data and generates an ECC code required for error detection and correction. The generated ECC code is written to the spare area of ​​the boot storage area 112.

[0027] The boot storage area 112 has a plurality of sectors #1 to #n (or a plurality of blocks) as shown in FIG. 2. Memory cells connected to one word line can be called one page, and one sector is made up of a plurality of pages. A sector includes a main area that can be accessed by the user and a spare area that cannot be accessed by the user. The main area stores boot data, and the spare area stores, for example, an ECC code of the boot data generated by the ECC circuit 130 as attribute information of the data written in the main area. The ECC code of the boot data may be managed on a sector-by-sector basis or on a page-by-page basis.

[0028] Meanwhile, the boot management area 210 of the RAM 200 stores an ECC flag indicating that a fail cell (error bit) has been detected by the ECC circuit 130 during a boot data read operation or that the fail cell has been corrected, the address of the fail cell, identification information identifying the type of error in the fail cell, and information regarding recovery of the fail cell according to the type of error. Furthermore, although not shown, the boot management area 210 may include a lookup table (LUT) that defines the correspondence between addresses between the boot storage area 112 and the redundant area 114.

[0029] The boot management area 210 is not particularly limited, but for example, manages the boot data of the boot storage area 112 in sector units. Fig. 2 shows an example of a management area_sector #1 for storing management information for sector #1 of the boot storage area 112. The management area_sector #1 includes information on failed cells, ECC flags, addresses of failed cells, identification of the error type of the failed cell, and recovery information according to the error type.

[0030] For example, if a fail cell FC1 is detected when reading the boot data of sector #1, the fail cell FC1 is registered in the management area_sector #1, an ECC flag is set indicating that the fail cell FC1 is an error bit or has been error corrected, and the address of the fail cell FC1 is stored. Furthermore, the identification of the error type of the fail cell FC1 is stored. In this example, the data "0" indicating that the fail cell FC1 has transitioned from data "1" to data "0" is used as the identification information. In other words, this means that the fail cell FC1 has been corrected from data "0" to data "1" by the ECC circuit 130.

[0031] Furthermore, if another fail cell FC2 is detected when reading sector #1, the fail cell FC2 is registered, the ECC flag of the fail cell FC2 is set, and the address of the fail cell FC2 is stored. To identify the error type of the fail cell FC2, the data "1" indicating that the fail cell FC2 has transitioned from data "0" to "1" is used as an example of the identification information. In other words, the fail cell FC2 means that the data "1" has been corrected to data "0" by the ECC circuit 130.

[0032] Next, the relationship between error modes and recovery will be explained. Figure 3(A) shows an error when the data in a memory cell transitions from "0" to "1" (i.e., the threshold value of the fail cell drops from square to square). The threshold value of a memory cell programmed with data "0" is the read verify voltage V WL must be greater than the threshold voltage V WL In a failed cell where the transition is smaller than 0, data "1" is read out even though data "0" was programmed. This error occurs due to the deterioration of retention characteristics, where the charge accumulated in the memory cell is lost and the threshold voltage gradually decreases.

[0033] In this embodiment, to recover from an error due to such a retention characteristic, the address of the fail cell is stored in the memory management area 210, and then the threshold voltage of the fail cell is read at any timing and the verify voltage V WL The failed cell is over-programmed so that the threshold voltage exceeds , and the failed cell is refreshed. This is shown in Figure 3(B) (the threshold voltage of the failed cell increases from square to square). For example, if the program voltage used in the previous programming is known, a program voltage higher than the previous program voltage can be applied to the failed cell to increase the threshold voltage of the memory cell in a positive direction. If the program voltage is not known, the over-programming can be performed using the ISPP (Incremental Step Pulse Program) method, as with normal memory cells. Finally, the over-programming is completed when the program verify is passed. A flag indicating whether the over-programming has been completed is set in the recovery for the failed cell FC1 in the boot management area.

[0034] Unlike NAND flash memory, NOR flash memory has memory cells connected in parallel, making it easy to program only failed cells, and also suppressing program disturbance to unselected memory cells, as occurs with NAND memory cells. By over-programming failed cells to recover them, bit errors in the recovered failed cells are no longer detected the next time the boot data is read. This allows a margin for the number of bits that the ECC circuit 130 can detect and correct errors in, so that the number of error bits in the boot data does not exceed the number of bits that the ECC circuit 130 can detect and correct, thereby improving the reliability of the boot data.

[0035] Figure 4(A) shows an error when the data in a memory cell transitions from "1" to "0" (the threshold value of the failed cell increases from square to square). The threshold value of the data "1", i.e., the erased memory cell, increases by the read verify voltage V WLHowever, the threshold voltage must be less than the read verify voltage V WL In the case of a failed cell where the transition is greater than 0, data "0" is read out even though it was erased to data "1." This error occurs because the boot data is read more frequently than other data, and when a memory cell with data "1" is read out many times, the Gm (transconductance) deteriorates due to the current flowing through the memory cell, and the threshold value gradually rises.

[0036] The read verify voltage V when reading a failed cell as a recovery against an error that causes the threshold voltage to rise WL The new read verify voltage V WL ΔV can be a predetermined value (e.g., 0.2 V), which is determined empirically. FIG. 4B shows the recovery process. The threshold voltage of the recovered failed cell is set to a new read verify voltage V WL The voltage V_R is smaller than the voltage V_R, and the read data of the recovered failed cell becomes "1" during a read operation. WL In this way, the recovered fail cells are not detected as error bits the next time the boot data is read, and the number of bits that can be corrected by the ECC circuit 130 is increased, thereby improving the reliability of the boot data.

[0037] If the recovered fail cell is detected as an error bit by the ECC circuit 130 again, the read verify voltage V set in the boot management area 210 is WL It is also possible to further increase R by ΔV.

[0038] Next, the operation of the NOR flash memory of this embodiment will be described. Figure 5 shows the operation flow when programming boot data into the boot storage area. In the NOR flash memory 100, when a command, address, and boot data for programming the boot data are received from the host system via the input / output circuit 120 (S100), the ECC circuit 130 performs arithmetic processing on the received boot data and generates an ECC code (S110).

[0039] The controller 150 controls the programming of the boot data based on the received command, and programs the boot data and ECC code into a selected sector of the boot storage area 112 by the row selection circuit 160 and the column selection circuit 180 based on the address held in the address register 140 (S120). The boot data is written to the main area, and the ECC code is written to the spare area. Note that if the location where the boot data is stored is predetermined, it is not necessary to receive an address from the host system. For example, the address where the boot data is stored may be stored in a fuse ROM, and the controller 150 may program the boot data into the boot storage area 112 by referring to the address stored in the fuse ROM.

[0040] Next, the operation of reading boot data will be described. When reading boot data, the controller 150 refers to the information stored in the boot management area 210, controls the reading of the boot data, and updates the management information of the boot data.

[0041] 6 is a flow diagram showing the operation of reading boot data. When a command for reading boot data or the like is received from the host system (S200), the controller 150 reads management information corresponding to a selected sector of the boot storage area 112 from the boot management area 210 and detects fail cells in the sector whose ECC flags are set (S210). For example, when the boot data of sector #1 shown in FIG. 2 is read, the controller 150 detects fail cells FC1 and FC2 whose ECC flags are set.

[0042] When a fail cell with the ECC flag set is detected, the controller 150 performs read control according to the error type (S220). Specifically, for a fail cell whose error type corresponds to the identification of "1", the controller 150 sets the read verify voltage when reading the fail cell based on the address of the fail cell stored in the boot management area 210 to the verify read V set in recovery. WL On the other hand, for a fail cell whose error mode corresponds to the identification of "0", the over-programming of the fail cell is already completed at an appropriate timing after the error is detected, and a recovery flag is set.

[0043] The controller 150 then applies a verify read V to the word line when reading the selected memory cell. WL When reading a failed cell, a verify read V is applied to the word line. WL _R is applied, and the boot data is read from the boot storage area (S230). In reading this boot data, the ECC circuit 130 detects whether or not a fail cell (error bit) has occurred in the boot data based on the ECC code (S240). As described above, a recovered fail cell is not detected as an error bit, but if a new error has occurred in a memory cell other than the recovered fail cell, that fail cell will be detected.

[0044] If an error is detected, the ECC circuit 130 corrects the error in the new fail cell (S250), and the controller 150 updates the data related to the newly detected fail cell in the boot management area (S260). For example, if a new fail cell FC3 is detected when reading sector #1, the fail cell FC3 is registered in the management area_sector #1, its ECC flag is set, its address is stored, and an identification of the error type is stored, as shown in FIG. 7. In addition, the ECC flags of the fail cells FC1 and FC2 are reset. The read boot data is then output to the host system via the input / output circuit 120 (S270).

[0045] As described above, according to this embodiment, the error type of the fail cell that has been detected and corrected by the ECC circuit 130 is identified, and the fail cell is recovered based on the error type. This ensures the error detection and correction function of the ECC circuit 130, thereby maintaining the reliability of the boot data.

[0046] In the above embodiment, the boot management area 210 is set in the RAM 200 of the controller 150, but when the NOR flash memory 100 is powered down, the data held in the RAM 200 becomes volatile. For this reason, it is desirable to back up the data in the boot management area 210 to a non-volatile memory, for example, the memory cell array 110, during the power-down sequence of the NOR flash memory 100, and then load the backed-up data into the boot management area 210 when the NOR flash memory 100 is restarted, thereby preventing the loss of data in the boot management area.

[0047] Next, another embodiment of this embodiment will be described. In the above embodiment, the error correction function of the ECC circuit 130 is maximized by recovering failed cells, thereby maintaining the reliability of the boot data. In this embodiment, however, the reliability of the boot data is further improved by limiting the recovery period.

[0048] The occurrence of fail cells is a sign of sector failure due to repeated reads, and performing recovery (increasing the read verify voltage) as shown in Figure 4(B) increases the likelihood of errors (where the memory threshold voltage transitions to a value lower than the read verify voltage) as shown in Figure 3(A). Therefore, continuing to recover fail cells will ultimately increase the probability of fail cells occurring, potentially reducing the reliability of the boot data.

[0049] Therefore, in this embodiment, a sector in which a certain number of failed cells have occurred (for convenience, referred to as a failed sector) is determined to be unsuitable for protecting highly reliable data, and the data stored in the failed sector is replaced with a fresh sector in the redundant area 114. After replacement, the data in the failed sector is erased, and the failed sector is reused as an area for storing normal data. Such replacement of failed sectors also contributes to wear leveling, which aims to equalize the frequency of use of the memory cell array.

[0050] 8 shows the operation flow when replacing boot data. The controller 150 refers to the boot management area 210 and determines whether a certain number of fail cells have occurred in a sector (S300). The boot management area 210 manages fail cells on a sector-by-sector basis, and stores the history of fail cells that have occurred in the sector. The certain number can be determined arbitrarily, and may be, for example, one fail cell or multiple fail cells.

[0051] When the controller 150 determines that a certain number of failed cells have occurred in a sector, it transfers the data of that sector to a fresh sector in the redundant area 114 (S310). When replacing data between sectors, the controller 150 registers the relationship between the address of the source sector and the address of the destination sector in a lookup table or the like in the boot management area 210, and links the two together (S320). When the transfer is complete, the controller 150 erases the data in the source failed sector (S330).

[0052] In this way, if a certain number of failed cells occur in a sector, the boot data is replaced with fresh sectors, thereby protecting the boot data so that errors in the boot data are minimized and improving its reliability. Furthermore, by replacing the boot data, the frequency of use of sectors in the memory cell array can be equalized.

[0053] Next, a modified example will be described. In the above embodiment, boot data is replaced when a certain number of fail cells occur in a sector. However, in this modified example, the controller 150 may refer to the ECC flags in the boot management area, and if at least one ECC flag is detected to be set in the sector, the boot data of that sector may be transferred to a sector in the redundant area. After the data transfer is completed, the controller 150 erases the data in the sector from which the data was transferred.

[0054] In the above-described embodiment, boot data (boot code) is shown as data that requires high reliability, but such data is not limited to boot data and may be other specific data that should be protected in the same way as boot data, and this can be defined arbitrarily by the user. Also, in the above-described embodiment, an example is shown in which an ECC flag is stored in the boot management area, but this is just one example, and the ECC flag may also be stored in a spare area within a sector.

[0055] Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications and variations are possible within the scope of the gist of the invention described in the claims. [Explanation of symbols]

[0056] 100: NOR flash memory 110: Memory cell array 120: Input / output circuit 130:ECC circuit 140: Address register 150: Controller 160: Row selection circuit 170: Sense / write circuit 180: Column selection circuit 190: Internal voltage generation circuit

Claims

1. a memory cell array including a plurality of memory cells; an ECC means for detecting and correcting errors in data read from the memory cell array; an error identifying means for identifying an error type of a fail cell whose error has been detected and corrected by said ECC means; recovery means for recovering the failed cell so that the error in the failed cell is eliminated based on the identified error mode; A NOR type flash memory including:

2. 2. The NOR type flash memory according to claim 1, wherein when the error mode indicates a decrease in a threshold value of a memory cell, the recovery means programs the failed cell so that the threshold value increases.

3. the error identifying means holds the address of the fail cell; 3. The NOR type flash memory according to claim 2, wherein said recovery means programs said fail cell based on said address.

4. 2. The NOR type flash memory according to claim 1, wherein said recovery means increases a read verify voltage of said fail cell when said error mode indicates an increase in a threshold voltage of said memory cell.

5. the error identifying means holds the address of the fail cell; 5. The NOR type flash memory according to claim 4, wherein said recovery means increases a read verify voltage when reading said fail cell based on said address.

6. NOR type flash memory further includes: a management means for managing occurrence of failed cells in the sectors of the memory cell array; 2. The NOR type flash memory according to claim 1, further comprising transfer means for transferring data of the sector including said fail cell to a redundant area of ​​said memory cell array based on the management result of said management means.

7. the memory cell array includes a boot data storage area for storing boot data; 2. The NOR type flash memory according to claim 1, wherein said recovery means recovers a fail cell storing boot data.

8. An operating method performed by a NOR type flash memory, comprising: a step of correcting errors in data read from the memory cell array by an ECC means; a step of identifying an error type of a fail cell whose error has been detected and corrected by the ECC means; recovering the failed cell so that the error in the failed cell is eliminated based on the identified error mode; A method of operation including:

9. 9. The method of claim 8, wherein when the error mode indicates a decrease in a threshold value of a memory cell, the recovering step includes programming the failed cell to increase its threshold value.

10. 9. The method of claim 8, wherein when the error mode indicates an increase in a threshold voltage of a memory cell, the recovering step increases a read verify voltage of the failed cell.

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