Start-up circuit

Abstract

To reduce the circuit area and current consumption of a startup circuit.SOLUTION: A detection voltage generation circuit 105 generates a detection voltage VdetL that varies depending on a detection current Idst1 obtained by amplifying a reference current Iref generated inside a reference voltage generation circuit 10A using a current detection transistor MPdet1. A determination circuit 102 is configured to generate a startup current Ist2 that acts on the reference voltage generation circuit 10A to increase the reference current Iref by turning on a startup transistor MNdetL when it determines, based on a comparison between a detection voltage VetL and a predetermined threshold, that the reference current Iref is smaller than a predetermined reference value. The upper limit of the variation range of the detection voltage VdetL is limited by a voltage limiting circuit 101 to a low power supply voltage VDDL that is lower than the power supply voltage VDD of the reference voltage generation circuit 10A.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a startup circuit, and more particularly to a startup circuit for starting up a reference voltage generating circuit. [Background technology]

[0002] In recent years, the demand for low-power, small-area analog circuit element technologies has increased with the development of mobile devices, battery-less systems, sensor devices, etc. Reference voltage generation circuits generate a constant reference voltage and / or reference current despite fluctuations in power supply voltage, temperature, and process variations, and are widely used in high-precision analog circuits.

[0003] However, it is known that a typical feedback reference voltage generating circuit has multiple stable operating points, some of which are operating points at which no current is generated. If the operation of the reference voltage generating circuit becomes stable at such an operating point, it will not be able to output a normal reference voltage or reference current, and the entire system will not operate as designed.

[0004] The startup circuit is provided to avoid the above-mentioned phenomenon when the reference voltage generating circuit is started up, and is configured to detect the current or node voltage flowing in the reference voltage generating circuit, and to force the reference voltage generating circuit to operate by generating a current when the designed current level or voltage level cannot be detected.

[0005] For example, Japanese Patent Laid-Open Publication No. 2001-147725 (Patent Document 1) describes a bandgap reference circuit including a bandgap circuit and a startup circuit that forcibly injects current when the current at a node in the bandgap circuit is lower than a reference value, and further includes a signal level conversion circuit. In the configuration of Patent Document 1, the current in the bandgap circuit is amplified by the signal level conversion circuit and transmitted to the startup circuit, thereby enabling the transistors that make up the startup circuit to be miniaturized. This allows for reductions in the power consumption and circuit area of ​​the startup circuit. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-147725 [Non-patent literature]

[0007] [Non-Patent Document 1] K. Ishida et al., “An outside-rail opamp design relaxing low-voltage constraint on future scaled transistors 5.5-V IO in a 2.5-V 0.25-um CMOS Technology”, IEICE TRANS, ELELTRON.VOL.E90-C,N.4 APRIL 2007, PP786-792 Summary of the Invention [Problem to be solved by the invention]

[0008] However, while the configuration of Patent Document 1 can reduce the steady-state current consumed in the startup circuit, a current that is an amplified version of the current consumed in the startup circuit is generated in the additional signal level conversion circuit. Therefore, while it is possible to reduce the size of the startup circuit, it is understood that there is room for improvement in reducing current consumption in light of recent demands for lower power consumption.

[0009] The present disclosure has been made to solve such problems, and an object of the present disclosure is to reduce the circuit area and current consumption of a startup circuit for reliably starting up a reference voltage generation circuit. [Means for solving the problem]

[0010] In one aspect of the present disclosure, a startup circuit for a reference voltage generation circuit is provided. The reference voltage generation circuit is configured to generate a reference current therein and output a constant reference voltage using the reference current. The startup circuit includes a detection voltage generation circuit, a determination circuit, a detection resistor, and a detection voltage limiting circuit. The detection voltage generation circuit generates a detection voltage that varies depending on the reference current. The determination circuit is configured to generate a startup current that acts on the reference voltage generation circuit to increase the reference current when it determines, based on a comparison between the detection voltage and a predetermined threshold, that the reference current is smaller than the predetermined reference value. The detection voltage generation circuit includes a current detection transistor and a detection resistor. The current detection transistor forms a current mirror with a transistor in the reference voltage generation circuit through which the reference current passes, and generates a detection current that is amplified by a predetermined amplification factor. The detection resistor is arranged to generate a voltage drop in response to the passage of the detection current, thereby generating the detection voltage at a first node. The detection voltage limiting circuit uses a second power supply voltage lower than the first power supply voltage of the reference voltage generating circuit to limit the upper limit of the variation range of the detection voltage to equal to or less than the second power supply voltage. The determination circuit includes a start-up transistor. The start-up transistor is connected to a second node in the reference voltage generating circuit so as to generate a start-up current by turning on when a comparison result between the detection voltage and a threshold value indicates that the reference current is smaller than the reference value. [Effects of the Invention]

[0011] According to the present disclosure, a startup current can be generated to reliably start up a reference voltage generation circuit even when the voltage value of the detection voltage is reduced. Therefore, by reducing the required detection current, the current amplification factor of the current detection transistor and the resistance value of the detection resistor can be reduced, thereby reducing the circuit area and current consumption of the startup circuit. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 3 is a circuit diagram illustrating the configuration of a startup circuit according to a first comparative example. [Figure 2]FIG. 2 is a circuit diagram illustrating a basic configuration of the circuit shown in FIG. 1 excluding a signal level conversion circuit. [Figure 3] FIG. 10 is a circuit diagram illustrating the configuration of a startup circuit according to a second comparative example. [Figure 4] 1 is a circuit diagram illustrating a configuration of a startup circuit according to a first embodiment. [Figure 5] FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a local power supply that generates a low power supply voltage. [Figure 6] 4 is a circuit diagram illustrating another example of a reference voltage generating circuit to which the startup circuit according to the first embodiment is applied. FIG. [Figure 7] FIG. 10 is a circuit diagram illustrating the configuration of a startup circuit according to a first modification of the first embodiment. [Figure 8] FIG. 10 is a circuit diagram illustrating the configuration of a startup circuit according to a second modification of the first embodiment. [Figure 9] FIG. 10 is a circuit diagram illustrating the configuration of a startup circuit according to a third modification of the first embodiment. [Figure 10] FIG. 10 is a circuit diagram illustrating the configuration of a startup circuit according to a fourth modification of the first embodiment. [Figure 11] FIG. 10 is a circuit diagram illustrating a configuration of a startup circuit according to a fifth modification of the first embodiment. [Figure 12] FIG. 13 is a circuit diagram illustrating the configuration of a startup circuit according to a sixth modification of the first embodiment. [Figure 13] FIG. 10 is a circuit diagram illustrating the configuration of a startup circuit according to a second embodiment. [Figure 14] FIG. 10 is a circuit diagram illustrating the configuration of a startup circuit according to a modification of the second embodiment. [Figure 15] 3 is a block diagram illustrating a first example of mounting a startup circuit according to the present embodiment. [Figure 16] 10 is a block diagram illustrating a second example of mounting the startup circuit according to the present embodiment. [Figure 17] FIG. 10 is a circuit diagram illustrating another example of the circuit configuration of the local power supply that generates a low power supply voltage. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0014] Embodiment 1 (Explanation of Comparative Example) First, a comparative example will be described to explain the problems in Patent Document 1 in detail.

[0015] 1 is a circuit diagram illustrating the configuration of a startup circuit according to a first comparative example. The first comparative example has the same circuit configuration as the bad gap reference circuit described in Patent Document 1 (FIG. 1).

[0016] 1, a startup circuit 100X according to the first comparative example includes a basic startup circuit 100Z and a signal level conversion circuit 30. The startup circuit 100X is arranged to reliably start up a reference voltage generation circuit 10A similar to the bad gap circuit of Patent Document 1.

[0017] The reference voltage generating circuit 10A includes P-type transistors MPb01-MPb2, N-type transistors MNb0 and MNb1, resistor elements R1 and Rb, and a diode element D0. Hereinafter, the resistance values ​​of the resistor elements R1 and Rb will also be represented as R1 and Rb, respectively.

[0018] The P-type transistors MPb0 to MPb2 are connected between a power supply node Np that transmits a power supply voltage VDD and nodes NA0 to NA2, respectively. Each source of the P-type transistors MPb1 to MPb2 is connected to the power supply node Np, and each gate is connected to the node NA0, thereby forming a current mirror.

[0019] In the disclosure of this specification, the P-type transistor and the N-type transistor can be typically configured by P-type and N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), respectively.

[0020] N-type transistor MNb0 is connected in series with resistor element Rb, which acts as a bias resistor, between node NA0 and ground node Ng. N-type transistor MNb1 is connected between node NA0 and ground node Ng. The gates of N-type transistors MNb0 and MNb1 are commonly connected to node NA1.

[0021] Resistance element R1 and diode element D0 are connected between node NA2 and ground node Ng. Diode element D0 is connected in series with resistance element R1, with the forward direction being the direction from node NA2 to ground node Ng.

[0022] The startup circuit 100Z includes a determination circuit 22 and a detection voltage generation circuit 25. The determination circuit 22 has a startup transistor MPdet configured as a P-type transistor connected between a power supply node Np and a node Nb. The node Nb of the detection voltage generation circuit 25 is connected to a node NA1 of the reference voltage generation circuit 10A.

[0023] The detection voltage generating circuit 25 has a current detection transistor MPst0 and a detection resistor Rst0, which are configured using P-type transistors and connected in series between a power supply node Np and a ground node Ng. Hereinafter, the resistance value of the detection resistor Rst0 will also be referred to as Rst0. The current detection transistor MPst0 is connected between the power supply node Np and a node Na, where the detection voltage Vdet is generated, and the detection resistor Rst0 is connected between the node Na and the ground node Ng.

[0024] The signal level conversion circuit 30 has P-type transistors MPc1 and MPc2 and N-type transistors MNc1 and MNc2.

[0025] First, the basic operation of the startup circuit 100Z will be described by showing the basic configuration of the startup circuit 100Z in which the signal level conversion circuit 30 is removed from the configuration of the startup circuit 100Z in FIG. 2. First, the circuit operation of the reference voltage generation circuit 10A will be described with reference to FIG. 2.

[0026] The reference current Iref of node NA0 is copied to nodes NA1 and NA2 by a current mirror formed by P-type transistors MPb1 and MPb2. The gates of N-type transistors MNb1 and MNb0 are commonly connected to node NA1, and N-type transistor MNb1 is diode-connected. A resistor Rb is connected as a bias resistor between the source of N-type transistor MNb0 and the ground node.

[0027] As a result, the following equation (1) holds between the gate-source voltage VGSnb1 of N-type transistor MNb1 and the gate-source voltage VGSnb0 of N-type transistor MNb0, using reference current Iref and resistance value Rb (bias resistance). VGSnb1 ≒ VGSnb0 - Iref × Rb … (1)

[0028] By modifying equation (1), the reference current Iref is expressed by the following equation (2). Iref=(VGSnb0-VGSnb1) / Rb …(2)

[0029] The reference current Iref is copied to the node NA2 via the P-type transistor MPb2, and therefore the reference voltage Vref shown in equation (3) is generated at the node NA2. Vref=Iref×R1+Vf0 =(VGSnb0-VGSnb1)×(R1 / Rb)+Vf0 …(3)

[0030] Vf0 in equation (3) is the voltage across the terminals of the diode element D0. The diode element D0 is generally configured using a diode-connected bipolar transistor, but it can also be configured using a field-effect transistor that operates in the weak inversion region. The reference voltage Vref shown in equation (3) is known to be a constant voltage that is less dependent on the process, temperature, and power supply voltage.

[0031] 2, the gate of current detection transistor MPst0 of detection voltage generating circuit 25 is connected to node NA0 of reference voltage generating circuit 10A. As a result, current detection transistor MPst0 forms a current mirror with P-type transistors MPb0 to MPb2 of reference voltage generating circuit 10A. Since current detection transistor MPst0 has an aspect ratio (ratio of gate length Lg to gate width Wg: Lg / Wg) that is L times (L: natural number greater than or equal to 1) that of P-type transistor MPb1, a detection current Ist0, which is L times the reference current Iref (node ​​NA0), can be passed through node Na.

[0032] A detection voltage Vdet is generated at the node Na and input to the determination circuit 22. The detection voltage Vdet is generated when the detection current Ist0 from the current detection transistor MPst0 passes through the resistance element Rst0, and therefore has a voltage proportional to the detection current Ist0 (Vdet=Idet×Rst0).

[0033] The detection voltage Vdet is input to the gate of the startup transistor MPdet that constitutes the determination circuit 22. The determination circuit 22 can determine whether the detection voltage Vdet is larger than a threshold VTH that corresponds to the threshold voltage Vthp of the startup transistor MPdet. In Figure 2, a node Nb (corresponding to the drain of the startup transistor MPdet) of the determination circuit 22 is also connected to a node NA1 of the reference voltage generation circuit 10A, i.e., to the gates of the N-type transistors MNb0 and MNb1 that constitute an N-type current mirror.

[0034] In the determination circuit 22, regarding the gate-source voltage VSGdet = VDD - Vdet of the startup transistor MPdet, when VSGdet = VDD - Vdet > Vthp, the startup transistor MPdet is turned on, while when VSGdet = VDD - Vdet < Vthp, the startup transistor MPdet is turned off. Thus, when the detection voltage Vdet is lower than (VDD - Vthp) corresponding to the threshold value VTH of the determination circuit 22, the startup transistor MPdet is turned on, and current can be injected from the power supply node Np to the node NA1 of the reference voltage generation circuit 10A. On the other hand, when the detection voltage Vdet is higher than the threshold value (VDD - Vthp), the startup transistor MPdet is turned off, and the above-mentioned current injection is not performed.

[0035] Therefore, when the reference current Iref flowing in the reference voltage generation circuit 10A is lower than the reference value, the determination circuit 22 can forcibly inject current into the reference voltage generation circuit 10A by turning on the startup transistor MPdet.

[0036] As described above, there are a plurality of stable operating points in the reference voltage generation circuit 10A, and the plurality of stable operating points include an undesirable operating point where the reference current Iref is zero and in a stable state. Therefore, the "reference value of the reference current" in the present embodiment can be determined to be larger than, for example, the value of the reference current at the stable operating point with the minimum reference current among the plurality of stable operating points in order to distinguish the above-mentioned undesirable operating points.

[0037] Furthermore, by appropriately designing the current amplification factor L and the resistance value Rst0 corresponding to the reference value of the reference current Iref, the comparison of the magnitude between the detection voltage Vdet and the threshold value (VDD - Vdet) can be made equivalent to the comparison of the magnitude between the reference current Iref and the above-mentioned reference value.

[0038] As a result, when the reference voltage generating circuit 10A is at an undesired stable operating point, it is determined that the reference current Iref is smaller than the reference value and therefore is not operating normally, and a current is injected into node NA1. This current injection can raise the voltage at node NA1, i.e., the gate voltages of N-type transistors MNb0 and MNb1, from the stable voltage at the undesired stable operating point. As a result, by increasing the current flowing through nodes NA1 to NA3 via the current mirror formed by P-type transistors MPb0 to MPb2, the reference voltage generating circuit 10A can escape from the undesired stable operating point and move to a stable operating point where a normal reference voltage Vref is generated. This ensures the start-up of the reference voltage generating circuit 10A.

[0039] As described above, by amplifying the detection current Ist0 to L×Iref, the judgment circuit 22 can easily determine that the reference current Iref is small, but it is necessary to prevent erroneous judgment (start-up transistor MPdet being on) at a normal stable operating point where the reference voltage Vref is normally output.

[0040] Specifically, when the reference voltage generating circuit 10A is operating normally, the start-up transistor MPdet must not be turned on for the steady-state value Ist0* of the detection current Ist0 flowing through the detection voltage generating circuit 25, that is, the following equation (4) must be satisfied. Vthp>VDD-Ist0*×Rst0 …(4)

[0041] Furthermore, if the start-up transistor MPdet is not turned on for the detection current Ist0 equivalent to the leakage current Ileak that occurs when the current detection transistor MPst0 is turned off after the rush current Irush has subsided during startup of the reference voltage generation circuit 10A, the reference current Iref may be too small, and the reference voltage generation circuit 10A may malfunction and stop current injection midway even though it has not yet reached stable operation. For this reason, the following equation (5) must be satisfied for the leakage current Ileak: Vthp <VDD-Ileak×Rst0 …(5)

[0042] From these equations (4) and (5), in order to avoid malfunction with respect to the steady-state values (Ist0*) of the leakage current Ileak and the detection current Ist0, the circuit constants Vthp and Rst0 of the startup circuit 100Z need to be designed to satisfy the following equation (6). Ileak < (VDD - Vthp) / Rst0 < Ist0* …(6)

[0043] Therefore, in the circuit configuration of FIG. 2, in order to satisfy the above equation (6), it is necessary to increase the current amplification factor (L) of Ist0 = L×Iref or set the resistance value Rst0 to an appropriate value. In order to increase the current amplification factor, it is necessary to increase the circuit area of the current detection transistor MPst0 in order to ensure the aspect ratio.

[0044] Furthermore, the steady-state value of the detection current Ist0 is Ileak = (VDD - VDS) / Rst0 when the current detection transistor MPst0 enters the linear region, that is, when VDS < VGS - Vthp holds among the drain-source voltage VDS, gate-source voltage VGS, and threshold voltage Vth of the current detection transistor MPst0. For this reason, in order to reduce the steady-state value of the detection current Ist0 to reduce power consumption, it is necessary to increase the resistance value of the detection resistor Rst0 to some extent. For these reasons, in the circuit configuration of FIG. 2, in the case of a process in which a special high-unit resistance device cannot be used, the power consumption and circuit area of the startup circuit 100X may increase.

[0045] Therefore, the startup circuit 100X according to the first comparative example (FIG. 1) described in Patent Document 1 adds the signal level conversion circuit 30 to the startup circuit 100Z and performs current amplification in multiple stages to reduce the power consumption and circuit area.

[0046] 1, in signal level conversion circuit 30, N-type transistor MNc1 is connected between node Nc and ground node Ng, and N-type transistor MNc2 is connected between node Nd and ground node Ng. N-type transistors MNc1 and MNc2 have their gates commonly connected to node Nc and their sources connected to ground node Ng, thereby forming a current mirror. N-type transistor MNc2 has an aspect ratio M times that of N-type transistor MNc1 (M: natural number equal to or greater than 1), so that a current M times that of node Nc flows through node Nd.

[0047] Furthermore, P-type transistor MPc1 is connected between power supply node Np and node Nc, and P-type transistor MPc2 is connected between power supply node Np and node Nd. The gate of P-type transistor MPc1 is connected to node NA0, so P-type transistor MPc1 forms a current mirror with P-type transistors MPb0 to MPb2 of reference voltage generating circuit 10A. Since P-type transistor MPc1 has an aspect ratio N times that of P-type transistors MPb0 and MPb1 (N: a natural number equal to or greater than 1), a current N times the reference current Iref of node NA0 flows through node Nc. P-type transistor MPc2 has its gate connected to node Nd, so that it is diode-connected. The aspect ratio of P-type transistor MPc2 is equal to the aspect ratio (×1) of P-type transistors MPb0 and MPb1.

[0048] 1, the gate of the current detection transistor MPst0 of the detection voltage generation circuit 25 is connected to the gate of the P-type transistor MPc2 of the signal level conversion circuit 30. As a result, the current detection transistors MPst0 and MPc2, each having a source connected to the power supply node Np, form a current mirror, and the current flowing through the current detection transistor MPst0 (detection current Ist0) is amplified by L times the current flowing through the P-type transistor MPc2 (current at node Nd).

[0049] Therefore, in the startup circuit 100X according to the first comparative example, the reference current Iref is amplified by (M×N) times by the signal level conversion circuit 30 and transmitted to the detection voltage generation circuit 25. As a result, the detection current Ist0 generated by the current detection transistor MPst0 is amplified by (L×M×N) times the reference current Iref (Ist0=(L×M×N)×Iref). As a result, the detection voltage Vdet becomes Vdet=(L×M×N)×Iref×Rst0.

[0050] 2, in order to obtain an equivalent detection voltage Vdet for the same reference current Iref, it is sufficient to increase the sizes of the P-type transistor MPc1, N-type transistor MNc2, and current detection transistor MPst0 by N, M, and L, respectively, rather than increasing the size of the current detection transistor MPst0 or detection resistor Rst0 by (L×M×N).As a result, the current amplification factor can be effectively ensured despite an increase in the aspect ratio of each transistor (i.e., transistor area).

[0051] For example, compared to the configuration in Figure 2 where Ist0 = (L x M x N) x Iref is ensured using only the current detection transistor MPst0, the configuration in Figure 1 can ensure the same current gain while reducing the transistor area by ((L x M x N) - (L + M + N)) times the transistor area of ​​the P-type transistors MPb0 and MPb1 (x1). Note that the aspect ratios of the P-type transistor MPc2 and N-type transistor MNc1 are small (x1), so this does not impair the area reduction effect described above.

[0052] For example, if it is desired to make the detection current Ist0 100 times the reference current Iref, then N×M×L=100 can be set to N=4 and M=L=5. In this case, L+M+N=14, so it can be seen that the transistor area can be reduced by 86% in the startup circuit 100X of FIG. 1 compared to the case where a current amplification factor of 100 times is ensured in the configuration of FIG. 2 (startup circuit 100Z).

[0053] On the other hand, in the additionally arranged signal level conversion circuit 30, a current that is (N+M) times the steady-state reference current Iref is continuously generated when the reference voltage generation circuit 10A is in operation. Therefore, it can be seen that the startup circuit 100X according to the first comparative example is highly effective in reducing the circuit area, but there is room for improvement in suppressing current consumption.

[0054] 3 is a circuit diagram illustrating the configuration of a startup circuit 100Y according to a second comparative example. The startup circuit 100Y is a modified example of the startup circuit 100X according to the first comparative example, and differs in that it includes a determination circuit 23 instead of the determination circuit 22 using the startup transistor MPdet.

[0055] The determination circuit 23 includes an inverter INV1 to which the detection voltage Vdet from the detection voltage generation circuit 25, similar to that shown in FIG. 1, is input, and an activation transistor MNdet configured with an N-type transistor. The activation transistor MNdet is connected between a node Nb and a ground node Ng. The node Nb of the determination circuit 23 is connected to a node NA0 of the reference voltage generation circuit 10A. As a result, the drain of the N-type transistor MPdet of the determination circuit 23 is connected to the gates of the P-type transistors MPb0 to MPb2 that configure a P-type current mirror.

[0056] The output signal of the inverter INV1 is input to the gate of the startup transistor MNdet, so the startup transistor MNdet is turned on and off according to the binary output signal of the inverter INV1. The output signal of the inverter INV1 is set to either H level (power supply voltage VDD) or L level (GND) depending on the magnitude relationship between the detection voltage Vdet (Vdet = Ist0 × Rst0) and the threshold value Vinv (VHT = Vinv). The threshold value Vinv is a function of the power supply voltage VDD and is known to have hysteresis.

[0057] When Ist0×Rst0 > Vinv(VTH), the output signal of the inverter INV1 becomes the L level, so the startup transistor MNdet is turned off. On the other hand, when Ist0×Rst0 < Vinv, the output signal of the inverter INV1 becomes the H level (VDD), so the startup transistor MNdet is turned on.

[0058] Thus, when the reference current Iref is smaller than the reference value, that is, when the reference voltage generation circuit 10A is at an undesirable stable operating point, the startup current Ist2 can be generated by turning on the startup transistor MNdet. Due to the startup current Ist2, the voltage of node NA0, that is, the gate voltages of the P-type transistors MPb0 to MPb2, can be changed from the voltage that is stable at the above-mentioned undesirable stable operating point to approach GND corresponding to the on-voltage of the P-type transistor, that is, in the direction of increasing the supply current of the P-type transistor. As a result, by increasing the current flowing through nodes NA1 to NA3 via the P-type current mirror (P-type transistors MPb0 to MPb2), the reference voltage generation circuit 10A can get out of the undesirable stable operating point and operate at a normal stable operating point where the reference current Ir0 is normally generated. Thereby, the startup circuit 100Y can also surely start up the reference voltage generation circuit 10A. Thus, the startup circuit 100Y corresponds to the one with the polarity of the startup circuit 100X inverted.

[0059] In the startup circuit 100Y including the determination circuit 23, the formula (6) in the startup circuit 100X(100Z) is transformed into the following formula (7). That is, in the startup circuit 100Y, the circuit constants Vinv and Rst0 need to be designed to satisfy the following formula (7). Ileak < Vinv / Rst0 < Ist0 …(7)

[0060] Furthermore, the startup circuit 100Y includes a signal level conversion circuit 30 similar to that shown in FIG. 1, and thus, like the startup circuit 100X, the circuit area can be reduced. However, there is a concern that the signal level conversion circuit 30 will consume power in steady state.

[0061] In the startup circuit 100Y having the inverter INV1, in order to lower the steady-state value of the detection current Ist0 and reduce the steady-state power consumption of the detection voltage generation circuit 25, it is necessary to lower the threshold Vinv of the inverter INV1. As described above, the threshold Vinv is a function of the power supply voltage VDD, so by lowering the power supply voltage VDD, it is possible to lower the threshold Vinv and reduce power consumption. However, because a decrease in the power supply voltage VDD puts pressure on the voltage swing of the reference voltage generation circuit 10A, it is generally not possible to freely determine the power supply voltage VDD just for the startup circuit.

[0062] (Start-up circuit according to the first embodiment) Below, we will explain the startup circuit of this embodiment, which addresses the problems with the startup circuits of the first and second comparative examples described above and aims to achieve both a reduction in steady-state power consumption and a reduction in circuit area.

[0063] Fig. 4 is a circuit diagram illustrating the configuration of a startup circuit 100A according to the first embodiment. In the example of Fig. 4, the startup circuit 100A is connected to a reference voltage generating circuit 10A similar to that shown in Figs. 1 to 3 via output nodes No. 1 and No. 2. Both output nodes No. 1 and No. 2 of the reference voltage generating circuit 10A are connected to a node NA0.

[0064] The startup circuit 100A includes a voltage limiting circuit 101, a determination circuit 102, and a detection voltage generating circuit 105.

[0065] The detection voltage generating circuit 105 includes a current detection transistor MPst1 configured with a P-type transistor that forms a current mirror with the P-type transistors MPb0 to Mb2 of the reference voltage generating circuit 10A, and a detection resistor Rst1 for generating the detection voltage VdetL. Hereinafter, the resistance value of the detection resistor Rst1 will also be referred to as Rst1. The detection resistor Rst1 is connected between a node N1 and a ground node Ng.

[0066] The current detection transistor MPst1 has an aspect ratio L1 times (L1: a natural number equal to or greater than 1) that of the P-type transistors MPb0 to Mb2. This allows the current detection transistor MPst1 to pass a detection current Ist1, which is L1 times the reference current Iref in the reference voltage generating circuit 10A, through the detection resistor Rst1. This allows the detection voltage generating circuit 105 to generate, at the node N1, a detection voltage VdetL that corresponds to the product of the detection current Ist1 passing through the node N1 and the resistance value Rst1. The detection voltage VdetL can be expressed as VdetL=Iref×L1×Rst1 using the reference current Iref. That is, the detection voltage VdetL can also have a voltage value proportional to the reference current Iref.

[0067] The determination circuit 102 includes an inverter INV1L to which the detection voltage VdetL from the detection voltage generation circuit 105 is input, and an activation transistor MNdetL configured with an N-type transistor. The inverter INV1L operates by receiving the low power supply voltage VDDL from the low power supply node Npl, and outputs an H level (low power supply voltage VDDL) or an L level (GND) according to the magnitude relationship between the detection voltage VdetL and a threshold VTH. The low power supply voltage VDDL is set lower than the power supply voltage VDD of the power supply node Np. The threshold of the inverter INV1L, i.e., the threshold VTH of the determination circuit 102, is a function of the low power supply voltage VDDL. The relationship between the threshold of the inverter INV1 and the power supply voltage (H-level voltage) when the inverter INV1 operates will be explained in detail at the end of the first embodiment.

[0068] The startup transistor MNdetL is connected between the node N3 where the output of the determination circuit 102 is generated and the ground node Ng. The output signal of the inverter INV1L is input to the gate of the startup transistor MNdetL. Therefore, when the detection voltage VdetL > VTH, the output signal of the inverter INV1L becomes the L level, so the startup transistor MNdetL is turned off. On the other hand, when VdetL < VTH, the output signal of the inverter INV1L becomes the H level (VDDL), so it is turned on. As described above, since the detection voltage VdetL is proportional to the reference current Iref, by designing the current amplification factor L1 and the resistance value Rst1, the startup transistor MNdetL can also be turned on when the reference current Iref is lower than the same reference value as described in the determination circuit 22.

[0069] When the startup current Ist2 is generated in response to the turning on of the startup transistor MNdetL, by the same mechanism as the comparative example in FIG. 3, the voltage of the node NA0, that is, the gate voltages of the P-type transistors MPb0 to MPb2, can be changed from the stable voltage at the above-mentioned undesirable stable operating point to approach GND corresponding to the on-voltage of the P-type transistor, that is, in the direction of increasing the supply current of the P-type transistor. Thus, by configuring the generation of the startup current Ist2 to act so as to increase the current of the transistor that generates the reference current Iref with respect to the reference voltage generation circuit 10A, the reference voltage generation circuit 10A can surely start up by getting out of the undesirable stable operating point and moving to the normal stable operating point where the reference current Ir0 is generated.

[0070] When the reference voltage generation circuit 10A is normally started up and a normal level of the reference current Iref is generated, the startup transistor MNdetL is turned off in response to the increase in the detection voltage VdetL, so the startup current Ist2 = 0. Therefore, the startup circuit 100A does not affect the operation of the reference voltage generation circuit 10A after startup. However, in the startup circuit 100A, the detection current Ist1 (constant value) is continuously generated.

[0071] The number of inverter stages arranged as "drive elements" in the determination circuit 102 can be any odd number. Although Fig. 4 illustrates a configuration in which one inverter INV1 is arranged, any odd number of inverters connected in series can be arranged between the node N1 where the detection voltage Vdet is generated and the gate of the N-type transistor MNdetL.

[0072] The transistors included in the determination circuit 102, i.e., the transistor group constituting the inverter INV1L and the start-up transistor MNdetL, are configured using transistors with a lower threshold voltage than the transistors MPb0-MPb2, MNb0, and MNb1 constituting the reference voltage generation circuit 10A and the current detection transistor MPst1 of the detection voltage generation circuit 105. For example, the transistors included in the determination circuit 102 are configured using low-voltage (hereinafter also referred to as LV (Low Voltage)) transistors. LV transistors can be defined as transistors with a lower withstand voltage than the standard-voltage (hereinafter also referred to as SV (Standard Voltage)) transistors used as the transistors constituting the reference voltage generation circuit 10A and the current detection transistor MPst1 of the detection voltage generation circuit 105. Typically, MOSFETs with a withstand voltage of 5V are used as SV transistors, while MOSFETs with a withstand voltage of 1.8V are used as LV transistors. However, the withstand voltage values ​​of the SV and LV transistors can be combined arbitrarily.

[0073] The voltage limiting circuit 101 has N-type transistors MNL1 and MNL2. The gates of the N-type transistors MNL1 and MNL2 are interconnected with a node N2 connected to a low power supply node Npl. The N-type transistor MNL1 is connected between the current detection transistor MPst1 and the node N1, and the N-type transistor MNL2 is connected between a node N3 of the determination circuit 102 and an output node No2 connected to the reference voltage generating circuit 10A.

[0074] As a result, the drain of the startup transistor MNdetL of the determination circuit 102 is connected to the node NA0 of the reference voltage generation circuit 10A via the N-type transistor MNL2 of the voltage limiting circuit 101. The node NA0 of the reference voltage generation circuit 10A corresponds to an example of a "second node" to which the startup current Ist2 is supplied. Furthermore, the node N1 at which the detection voltage VdetL is generated corresponds to an example of a "first node."

[0075] In this embodiment, the power supply voltage VDD corresponds to an example of a "first power supply voltage," and the power supply node Np corresponds to an example of a "first power supply node." The low power supply voltage VDDL corresponds to an example of a "second power supply voltage," and the low power supply node Npl corresponds to an example of a "second power supply node." Furthermore, in the voltage limiting circuit 101, the N-type transistor MNL1 corresponds to an example of a "first voltage limiting transistor," and the N-type transistor MNL2 corresponds to an example of a "second voltage limiting transistor."

[0076] The voltage limiting circuit 101 operates as a circuit that level-shifts (lowers) the low power supply voltage VDDL by the gate-source voltages VGSL1 and VGSL2 of the N-type transistors MNL1 and MNL2, and transmits the voltage to the nodes N1 and N3.

[0077] This allows the upper limit of the detection voltage VdetL output from the detection voltage generation circuit 105 to the node N1 to be limited to a value equal to or lower than the low power supply voltage VDDL, more specifically, equal to or lower than (VDDL-VGSL1) (VdetL≦VDDL-VGSL1). Similarly, the output voltage from the determination circuit 102 to the node N3 can also be limited to a value equal to or lower than (VDDL-VGSL1).

[0078] Here, in the N-type transistor MNL1, the gate-source voltage VGSL1 between the source connected to the node N1 and the gate to which the low power supply voltage VDDL is input can be expressed by the following equation (8) using the current (detection current Ist1) and threshold voltage Vthn of the N-type transistor MNL1. VGSL1=Vthn+√(2×Ist1 / β) …(8)

[0079] Similarly, in the N-type transistor MNL2, the gate-source voltage VGSL2 between the source connected to node N3 and the gate to which the low power supply voltage VDDL is input can be expressed by the following equation (9) using the current (start-up current Ist2) and threshold voltage Vthn of the N-type transistor MNL2. VGSL2=Vthn+√(2×Ist2 / β) …(9)

[0080] The gain coefficient β in equations (8) and (9) is a circuit constant expressed as β = (Wg / Lg) × μ × Cox, where μ is the electron mobility of each transistor, Cox is the gate oxide capacitance per unit area, Wg is the gate width, and Lg is the gate length.

[0081] Therefore, by appropriately setting the gate-source voltages VGSL1 and VGSL2, which depend on the circuit constants, for the low power supply voltage VDDL, it is possible to protect the gate-source voltage and drain-source voltage of the startup transistor MNdetL of the determination circuit 102 to be below the withstand voltage of the LV transistor that constitutes the startup transistor MNdetL.

[0082] It is known that in an NMOS transistor, the on-resistance is proportional to the inverse of the gate width (1 / Wg), and the leakage current is proportional to the inverse of the gate length Lg (1 / Lg). Therefore, increasing the gate length Lg and gate width Wg of the startup transistor MNdetL in the decision circuit 102 can improve the startup performance and reduce power consumption of the startup circuit 100A. However, as the size of the transistor's gate width Wg × gate length Lg increases, the gate-source capacitance Cgs also increases proportionally, slowing the turn-on and turn-off speed of the startup transistor MNdetL. Therefore, to drive the startup transistor MNdetL at high speed, it is effective to connect inverters in multiple stages as described above and gradually increase the aspect ratio (Wg / Lg) of the transistors constituting each inverter by a fixed factor from the first stage to the last. In this case, the fixed factor is known to be 2 to 3 times.

[0083] The low power supply voltage VDDL is set to a value lower than the power supply voltage VDD of the reference voltage generating circuit 10A and not exceeding the breakdown voltage of the LV transistors constituting the determination circuit 102. The low power supply voltage VDDL can be generated by, for example, the local power supply circuit 110 shown in FIG.

[0084] 5, a local power supply circuit 110 that generates a low power supply voltage VDDL includes a resistance element Rb110 and a constant voltage generating circuit 120. The resistance element Rb110 and the constant voltage generating circuit 120 generate a low power supply voltage VDDL.

[0085] The resistor element Rb110 is connected between a power supply node Np that supplies a power supply voltage VDD and a low power supply node Npl that supplies a low power supply voltage VDDL. The constant voltage generating circuit 120 includes a plurality of diode elements Db1 to Db3 that are connected in series between the low power supply node Npl and the ground node Ng, with the direction from the low power supply node Npl to the ground node Ng being the forward direction.

[0086] The low power supply voltage VDDL generated at the low power supply node Npl is expressed as VDDL=3×Vf, where Vf is the forward drop voltage of each of the diode elements Db1 to Db3.

[0087] Here, the forward drop voltage Vf mentioned above is the voltage difference that occurs across the diode when a specified forward current If flows through the diode, and in the example of Figure 5, it is the voltage value when If = (VDD - 3 × Vf) / Rb110 flows through each of the diode elements Db1 to DB3.

[0088] In general, the current-voltage characteristics of a pn junction diode are expressed by the following equation (10): If=Is×exp [q×Vf / (k×T)-1] …(10)

[0089] In equation (10), Is is the saturation current, k is the Boltzmann constant, q is the amount of charge per unit charge (elementary charge), and T is the absolute temperature (K). A diode is characterized by a small voltage fluctuation range relative to current changes because the forward current If increases exponentially with changes in forward drop voltage Vf. Therefore, as described above, the constant voltage generating circuit 120 can set the low power supply voltage VDDL to a voltage value that depends only on the forward drop voltage Vf of each of the diode elements Db1 to DB3. For example, in FIG. 5, a VDDL of 1.8 (V) can be obtained by connecting three diode elements with Vf = 0.6 V in three stages.

[0090] In the constant voltage generating circuit 120, the low power supply voltage VDDL can be set within a range that does not exceed the breakdown voltage of the above-mentioned LV transistor by adjusting the number of diode element stages (number of diodes connected in series). Note that each diode element can also be configured using a diode-connected NMOS transistor. In this case, the forward drop voltage Vf across the diode element corresponds to the sum of the overdrive voltage Vov and threshold voltage Vthn of the NMOS transistor. For example, when the constant voltage generating circuit 120 is configured using n diode-connected NMOS transistors (n: natural number) connected in series, VDDL is expressed as VDDL=n×(Vov+Vthn).

[0091] 5, the low power supply voltage VDDL applied to the startup circuit 100A is generated from the power supply voltage VDD of the reference voltage generation circuit 10A, but it is not necessary to generate the low power supply voltage VDDL from the power supply voltage VDD. For example, in an application where there are multiple power supply voltages, the low power supply voltage VDDL can be generated from any power supply voltage as long as the relationship VDD>VDDL is established.

[0092] 4 again, in the startup circuit 100A according to the first embodiment, a low power supply voltage VDDL lower than the power supply voltage VDD of the reference voltage generating circuit 10A is transmitted to the determination circuit 102 and the detection voltage generating circuit 105 via the voltage limiting circuit 101. This locally reduces the voltage handled by the determination circuit 102, so that even if a detection voltage VdetL lower than the detection voltage Vdet in the comparative example is input, the determination circuit 102 according to the first embodiment can detect that the reference current Iref is smaller than the reference value, similar to the determination circuits 22 and 23 (FIGS. 1 and 3) of the comparative example.

[0093] Therefore, the current amplification factor (Ist1 / Iref) for detecting that the reference current Iref is smaller than the reference value can be reduced, eliminating the need for the signal level conversion circuit 30 (FIGS. 1 and 3) described in the comparative example. Furthermore, the aspect ratio of the current detection transistor MPst1 (detection voltage generation circuit 105) that generates the detection current Ist1 and the resistance value of the detection resistor Rst1 can be reduced, thereby reducing the circuit area of ​​the startup circuit 100A.

[0094] Furthermore, since the power consumption by the signal level conversion circuit 30 in the comparative example is not generated and the detection current Ist1 (steady-state value) in the detection voltage generation circuit 105 is also suppressed, the power consumption of the startup circuit 100A can also be reduced at the same time.

[0095] As a result of the above-described voltage reduction, the gate voltage when turning on the startup transistor MNdetL of the determination circuit 102 decreases, which increases the on-resistance of the startup transistor MNdetL. The increase in on-resistance makes it difficult to ensure the startup current Ist2 required to increase the reference current Iref, which may reduce the original function of ensuring startup performance.

[0096] In response to this, in the startup circuit 100A according to the first embodiment, at least the startup transistor MNdetL of the determination circuit 102 is configured with an LV transistor having a low threshold voltage. As a result, in response to a decrease in the detection voltage VdetL, the threshold voltage Vthn of the startup transistor MNdetL is lowered, thereby making it possible to avoid an increase in on-resistance.

[0097] For example, in a situation where devices with different breakdown voltages and / or different doping densities can be used on the same chip, the level of the low power supply voltage VDDL can be determined so that the voltage relationship is power supply voltage VDD=5V and low power supply voltage VDDL=1.8V for SV transistors with a breakdown voltage of about 6V and LV transistors with a breakdown voltage of about 2V.

[0098] Furthermore, in the startup circuit 100A according to the first embodiment, by introducing a voltage limiting circuit 101 between the SV transistors of the detection voltage generating circuit 105 and the reference voltage generating circuit 10A and the LV transistors of the determination circuit 102, it is possible to limit the voltage applied to the LV transistors to a value equal to or lower than the low power supply voltage VDDL. This ensures the withstand voltage reliability of the newly introduced LV transistors.

[0099] Here, the threshold value Vinv1 at which the output of a CMOS (Complementary Metal Oxide Semiconductor) inverter, which is generally used as the inverter INV1L constituting the decision circuit 102, is inverted will be considered.

[0100] Considering the inverter INV1 operating at the power supply voltage VDD shown in the comparative example of FIG. 3, the threshold Vinv1 is expressed by the following equations (11) and (12) using the threshold voltage Vthn of the NMOS transistor, the electron mobility μn, and the aspect ratio (Wn / Ln), and the Vthp, electron mobility μp, and aspect ratio (Wp / Lp) of the PMOS transistor.

Number

Number

[0101] In equation (11), when βn = βp and Vthn = Vthp, Vinv1 = VDD / 2. Generally, this value is used as the threshold of the inverter. Therefore, to lower the threshold Vinv1, it is only necessary to lower the power supply voltage VDD. Since the inverter INV1L in FIG. 4 operates at the low power supply voltage VDDL, its threshold Vinv1 = VDDL / 2 (< Vinv1). The threshold VTH of the determination circuit 102 is VTH = Vinv1 = VDDL / 2.

[0102] In the determination circuit 102 of FIG. 4, when VdetL < VDDL / 2, the output voltage of the inverter INV1 = VDDL (H level). At this time, the startup transistor MNdetL is in the on state. On the other hand, when VdetL > VDDL / 2, the output voltage of the inverter INV1 = GND (L level) VDDL. At this time, the startup transistor MNdetL is in the off state.

[0103] However, in order to sufficiently lower the resistance value (on-resistance) when the startup transistor MNdetL is in the on state, it is necessary to consider setting VDDL >> Vthn. As described above, in FIG. 4, by configuring the startup transistor MNdetL with an LV system transistor, the threshold voltage Vthn is lowered, and thus, even when using the low power supply voltage VDDL, an increase in the on-resistance can be avoided.

[0104] It is known that the threshold voltage Vthn of an NMOS transistor is determined depending on the transistor structure or manufacturing process, and is expressed by the following equation (13).

number

[0105] In equation (13), Vt0 is the threshold voltage when the source-bulk voltage Vsb=0, φf is the Fermi voltage, q is the elementary charge, and N A is the doping density of the p-type substrate on which the NMOS transistor is fabricated, ε is the dielectric constant of silicon, and Cox is the gate oxide capacitance per unit area. It is known that there is a relationship between the gate oxide capacitance Cox and the gate oxide thickness tox, Cox ∝ (1 / tox).

[0106] Therefore, it can be understood from equation (13) that by using a device with a thin gate oxide film that has been scaled, the gate oxide film capacitance Cox can be increased and the threshold voltage Vthn can be lowered. As described above, by using LV transistors, which are devices with a thin gate oxide film, as the transistors that make up the determination circuit 102, the threshold voltage of each transistor can be lowered to avoid an increase in on-resistance due to the introduction of a low power supply voltage VDDL.

[0107] On the other hand, a transistor with a low threshold voltage can be realized by applying devices other than the above-mentioned LV transistor. For example, A In equation (13), instead of increasing the gate oxide film capacitance Cox, the doping density N A It can be seen that the threshold voltage Vthn can be lowered even if the threshold voltage Vthn is lowered.

[0108] Thus, the transistors used in the determination circuit 102 that constitute the reference voltage generating circuit 10A and the transistors that have a lower threshold voltage than the current detection transistor MPst1 in the detection voltage generating circuit 105 are not limited to the LV transistors illustrated in FIG. 4, but may be realized by applying other devices such as the above-mentioned Low-VT transistors. However, because Low-VT transistors generally have a large leakage current, FIG. 4 illustrates LV transistors. Therefore, if the application allows for a standby current, the determination circuit 102 can also be configured using Low-VT transistors.

[0109] In addition, in the startup circuit 100A, the circuit constants Vinv(VTH) and Rst1 must be designed to satisfy equation (14), which is a variation of equation (7) in the startup circuit 100Y, using the leakage current Ileak of the current detection transistor MPst1 and the steady-state value Ist* of the detection current Ist1 (when the reference current generating circuit 10A is operating normally). Ileak <Vinv / Rst1<Ist1* …(14)

[0110] The startup circuit 100A according to the first embodiment is not limited to application to the reference voltage generating circuit 10A in the configuration example of FIG. 4, but can be used to ensure the startup of any reference voltage generating circuit with any configuration.

[0111] Fig. 6 is a circuit diagram illustrating another example of a reference voltage generating circuit to which the startup circuit 100A according to embodiment 1 is applied. In the example of Fig. 6, the startup circuit 100A is connected via output nodes No. 1 and No. 2 to a reference voltage generating circuit 10B configured as a known BGR (Bang Gap Reference) circuit.

[0112] 6, the reference voltage generating circuit 10B includes P-type transistors MPb0 and MPb1, a differential amplifier AMP, resistor elements Rb1 to Rb3, and diode elements Db0 and Db1. The diode elements Db0 and Db1 can also be configured using diode-connected transistors (typically, bipolar transistors). The diode element Db0 is designed to pass K times the current of the diode element Db1 (similar to the "×K" between the N-type transistors MNb1 and MNb2 in the reference voltage generating circuit 10A).

[0113] The sources of P-type transistors MPb0 and MPb1 are connected to a power supply node Np, and their gates are interconnected via a node NB0, forming a current mirror. The P-type transistor MPb1 is connected between the power supply node Np and a resistor element Rb2, and the resistor element Rb2 is connected between the P-type transistor MPb1 (drain) and a node NB1. The resistor element Rb1 and a diode element Db0 are connected in series between the node NB1 and a ground node Ng.

[0114] P-type transistor MPb0 is connected between power supply node Np and node NB3, where reference voltage Vref is generated, and between P-type transistor MPb0 and resistor element Rb2, which is connected between node NB3 and node NB2. Diode element Db1 is connected between node NB2 and ground node Ng. Diode elements Db0 and Db1 are connected such that their cathodes face the ground node Ng. Differential amplifier AMP amplifies the voltage difference between nodes NB1 and NB2 and outputs the amplified output voltage to node NB0. That is, the output voltage of differential amplifier AMP is input to the gates of P-type transistors MPb0 and MPb1, which form a P-type current mirror.

[0115] Even in the reference voltage generation circuit 10B, a feedback path is formed to make the voltages of nodes NB1 and NB2 equal while the currents of nodes NB1 and NB2 are made equal by a P-type current mirror. As a result, a reference current Iref and a reference voltage Vref shown in FIG. 6 can be generated as a constant current and a constant voltage with low dependency on the process, temperature, and power supply voltage.

[0116] For the reference voltage generation circuit 10B, the output node No1 is connected to the gates of P-type transistors MPb0 and MPb1 that form a P-type current mirror. Thereby, the current detection transistor MPst1 of the detection voltage generation circuit 105 can form a current mirror with the P-type transistors MPb and MPb1 of the reference voltage generation circuit 10B to generate a detection current Ist1 that replicates the reference current Iref.

[0117] Furthermore, the output node No2 is connected to the node NB0 in the reference voltage generation circuit 10B, that is, the gates of the P-type transistors MPb0 and MPb1 that form a P-type current mirror. That is, when the startup circuit 100A is connected to the reference voltage generation circuit 10B, the node NB0 (the gates of the P-type transistors MPb0 and MPb1) of the reference voltage generation circuit 10B corresponds to an embodiment of the "second node". As a result, since the reference current Iref is smaller than the reference value, the startup current Ist2 generated with the detection voltage VdetL < VTH (determination circuit 102) also acts on the reference voltage generation circuit 10B to change the gate voltages of the P-type transistors MPb0 and MPb1 closer to GND corresponding to the on-voltage of the P-type transistors, thereby increasing the supply current of the transistor that generates the reference current Iref. As a result, the startup current Ist2 can act on the reference voltage generation circuit 10B to increase the reference current Iref.

[0118] In this way, the startup circuit 100A according to the first embodiment can be applied to any reference voltage generating circuit having a current mirror and a feedback path, including the reference voltage generating circuits 10A and 10B. Specifically, the output nodes No1 and No2 of the startup circuit 100A can be connected to a node in the reference voltage generating circuit for replicating the reference current (constant current) Iref, and to a node where the generation of the startup current Ist2 acts to increase the reference current Iref (for example, the gate (control electrode) of the transistor that generates the reference current Iref), respectively.

[0119] A variation of the first embodiment. Next, variations of the determination circuit 102 or the voltage limiting circuit 101 in the first embodiment will be described in order as modified examples of the first embodiment.

[0120] (First Modification) In the first modification, another example of the configuration of the determination circuit 102 will be described. 7 is a circuit diagram illustrating the configuration of a startup circuit 100B according to a first modification of embodiment 1. In the following description, it is assumed that each startup circuit according to this embodiment is connected to a reference voltage generating circuit 10 including at least reference voltage generating circuits 10A (FIG. 4) and 10B (FIG. 6).

[0121] 7, the startup circuit 100B differs from the startup circuit 100A according to the first embodiment (FIGS. 4 and 6) in that it includes a determination circuit 102a instead of the determination circuit 102. In the example shown in FIG.

[0122] The determination circuit 102a differs from the determination circuit 102 in that it includes a Schmitt trigger circuit ST1L instead of the inverter INV1L. Like the inverter INV1L, the Schmitt trigger circuit ST1L is configured by a transistor (not shown) having a lower threshold voltage than the transistors constituting the reference voltage generating circuit 10 and the current detection transistor MPst1 (detection voltage generating circuit 105). Typically, the Schmitt trigger circuit ST1L can be configured using an LV transistor, as in the description of the first embodiment.

[0123] As is well known, the Schmitt trigger circuit ST1L is also called a Schmitt trigger inverter, and is configured so that a first threshold VTHSL1 when the output signal changes from an L level to an H level is different from a second threshold VTHSL2 when the output signal changes from an H level to an L level.

[0124] More specifically, the hysteresis width dVTHSL is designed to be (VTHSL1-VTHSL2)>0, and the hysteresis width dVTHSL can be designed arbitrarily by changing the circuit constant of the Schmitt trigger circuit ST1L.

[0125] The configuration of other parts of startup circuit 100B is the same as that of startup circuit 100A, and therefore detailed description will not be repeated. That is, output nodes No1 and No2 of startup circuit 100B can also be connected to reference voltage generating circuits 10A and 10B, as in FIGS. 4 and 6.

[0126] In the startup circuit 100B according to the first modification of the first embodiment, by using the Schmitt trigger circuit ST1L, chattering and malfunctions due to noise can be suppressed when the startup transistor MNdetL is turned on and off. This makes it possible to improve robustness in addition to the effects of the startup circuit 100A according to the first embodiment.

[0127] In the startup circuit 100B, when the rush current Irush (Ist1 = Irush) generated at the startup of the power supply voltage VDD causes VdetL = Irush × Rst1 to be higher than the first threshold value VTHSL1 of the Schmitt trigger circuit ST1L, a phenomenon occurs where the startup transistor MNdetL is turned off even if the reference current Iref is smaller than the reference value, impairing the function of the determination circuit 102a. However, when the startup of the power supply voltage VDD is completed and the rush current subsides, the determination function of the determination circuit 102a recovers as the detection current Ist1 reaches its original level proportional to the reference current Iref.

[0128] However, if the hysteresis width dVTHSL of the Schmitt trigger circuit ST1L and the resistance value of the detection resistor Rst1 are inappropriate, after the rush current subsides, if VdetL = Ileak × Rst1 > VTHSL2 holds for the leakage current Ileak (Ist1 = Ileak) of the current detection transistor MPst1, the operating state of the reference voltage generation circuit 10 is misjudged, and the startup transistor MNdetL remains off, fixing the operating state of the startup circuit 100B. As a result, there is concern that the reference voltage generation circuit 10 cannot escape from an undesirable stable operating point and cannot be started up.

[0129] Therefore, in the startup circuit 100B of FIG. 7, it is necessary to design the circuit constants such that VdetL = Ileak × Rst1 < VTHSL2 for the setting of the hysteresis width of the Schmitt trigger circuit ST1L.

[0130] For example, when setting VTHSL1 and VTHSL2 of the Schmitt trigger circuit ST1L with the threshold Vinv1L of the inverter INV1L without a hysteresis width as the median value, VTHSL2 = Vinv1L - dVTHSL / 2 is shown. Therefore, for the resistance value Rst1, it is necessary to determine it so that Rst1 < (Vinv1L - dVTHSL / 2) / Ileak. That is, in the startup circuit 100B of FIG. 7, when compared with the startup circuit 100A (Rst1 < Vinv1L / Ileak) using the inverter INV1L of FIGS. 4 and 6, it is necessary to lower the resistance value of the detection resistor Rst, specifically, at least by (dVTHSL / (2×Ileak)).

[0131] (Second modification example) In the second modification example, another configuration example of the determination circuit 102 will be described.

[0132] FIG. 8 is a circuit diagram for explaining the configuration of the startup circuit 100C according to the second modification example of the first embodiment. Similar to the startup circuits 100A and 100B, the startup circuit 100C can be connected to the reference voltage generation circuit 10 including the reference voltage generation circuits 10A and 10B to ensure the startup of the reference voltage generation circuit 10.

[0133] Referring to FIG. 8, the startup circuit 100C is different from the startup circuit 100A (FIGS. 4 and 6) according to the first embodiment in that it includes a determination circuit 102b instead of the determination circuit 102.

[0134] The determination circuit 102c differs from the determination circuit 102 in that even-stage inverters, rather than odd-stage inverters, are connected in series as "drive elements," and that a startup transistor MPdetL formed of a P-type transistor is connected between node N3 and ground node Ng instead of startup transistor MNdetL. Each of the even-stage inverters is also configured using a transistor with a low threshold voltage (e.g., an LV transistor) because it operates while connected to a low power supply voltage VDDL. Similarly to startup transistor MNdetL, startup transistor MPdetL is also configured using a transistor with a low threshold voltage (e.g., an LV transistor).

[0135] In the example of Fig. 8, two inverters, INV1L and INV2L, are connected in series, but the number of inverters connected in series can be any even number. In Fig. 8, the detection voltage VdetL is input to the inverter INV1L as in Figs. 4 and 6, and the output signal of the inverter INV1L is input to the inverter INV2L. The output signal of the inverter INV2L is input to the gate of the start-up transistor MPdetL.

[0136] Since the output signal of the inverter INV2L has an inverted logic level relative to the output signal of the inverter INV1L, the start-up transistor MPdetL is controlled on and off in the same way as the start-up transistor MNdetL in the startup circuit 100A, depending on the detection voltage VdetL, which is proportional to the reference current Iref.

[0137] In addition, the drain of the startup transistor MPdetL is connected to a transistor in the reference voltage generating circuit 10 via the N-type transistor MNL2 of the voltage limiting circuit 101. This makes it possible to protect the gate-source voltage and drain-source voltage of the startup transistor MPdetL of the determination circuit 102c to be equal to or lower than the withstand voltage of the LV transistor.

[0138] The configuration of other parts of startup circuit 100C is the same as that of startup circuit 100A, and therefore detailed description will not be repeated. That is, output nodes No1 and No2 of startup circuit 100C can also be connected to reference voltage generating circuits 10A and 10B, as in FIGS. 4 and 6.

[0139] According to the startup circuit 100C of the second modification of the first embodiment, even if the number of inverter stages in the determination circuit is an even number, it is possible to obtain the same effect as the startup circuit 100A of the first embodiment. In this way, by selecting the startup circuit 100A, 100C according to the minimum number of inverter stages required to drive the startup transistor (MNdetL or MPdetL) for flowing the startup current Ist2 to the output node No2 at a desired speed, it is possible to optimize the number of inverters and enhance the effect of reducing the area.

[0140] (Third Modification) In the third modification, still another example of the configuration of the determination circuit 102 will be described.

[0141] 9 is a circuit diagram illustrating the configuration of a startup circuit 100D according to a third modification of embodiment 1. Like the startup circuits 100A to 100C, the startup circuit 100D can also be connected to the reference voltage generation circuit 10 including the reference voltage generation circuits 10A and 10B to ensure the startup of the reference voltage generation circuit 10.

[0142] 9, a startup circuit 100D differs from the startup circuit 100C (FIG. 8) according to the second modification of the first embodiment in that a determination circuit 102c is provided instead of the determination circuit 102b.

[0143] The determination circuit 102c differs from the determination circuit 102b in that the first-stage inverter INV1L to which the detection voltage VdetL is input is replaced with the Schmitt trigger circuit ST1L used in the determination circuit 102a of the startup circuit 100B. This makes it possible to suppress chattering and malfunctions due to noise when turning on and off the startup transistor MPdetL in the determination circuit 102c.

[0144] The configuration of other parts of startup circuit 100D is the same as that of startup circuit 100C, and therefore detailed description will not be repeated. That is, output nodes No1 and No2 of startup circuit 100D can also be connected to reference voltage generating circuits 10A and 10B, as in FIGS. 4 and 6.

[0145] As described above, the startup circuit 100D according to the third modification of the first embodiment uses the Schmitt trigger circuit ST1L as the first-stage driving element, thereby improving robustness against chattering and noise in addition to the effects achieved by the startup circuit 100B according to the second modification of the first embodiment.

[0146] 7 (Variation 1), it is also possible to configure the circuit such that an even number of inverters are further arranged after the Schmitt trigger circuit ST1L, and the output signal of the final inverter of a total of odd number of drive elements is input to the gate of the start-up transistor MNdetL. That is, by properly using the startup circuits 100A (FIG. 7) and 100D (FIG. 9), it is possible to arbitrarily design the number of inverter stages required to ensure drive speed while suppressing the circuit area in a configuration in which the detection voltage VdetL is input to the Schmitt trigger circuit ST1L, which is the first-stage drive element.

[0147] (Fourth Modification) In the fourth modification, another configuration example of the voltage limiting circuit 101 will be described.

[0148] 10 is a circuit diagram illustrating the configuration of a startup circuit 100E according to a fourth modification of embodiment 1. Like the startup circuits 100A to 100D, the startup circuit 100E can be connected to the reference voltage generation circuit 10 including the reference voltage generation circuits 10A and 10B to ensure the startup of the reference voltage generation circuit 10.

[0149] 10, startup circuit 100E differs from startup circuit 100A according to the first embodiment (FIGS. 4 and 6) in that voltage limiting circuit 101 is replaced with a voltage limiting circuit 101a.

[0150] The voltage limiting circuit 101a is configured such that the N-type transistors MNL1 and MNL2 constituting the voltage limiting circuit 101 are replaced with N-type transistors MNL1a and MNL2a, which have a lower threshold voltage than enhancement type transistors. Normally, each transistor constituting the reference voltage generating circuit 10 and the current detection transistor MPst1 (detection voltage generating circuit 105) are configured with enhancement type transistors, so the N-type transistors MNL1a and MNL2a can also be defined as transistors with a lower threshold voltage than these transistors.

[0151] In the voltage limiting circuit 101a, the N-type transistor MNL1a corresponds to an embodiment of a "first voltage limiting transistor," and the N-type transistor MNL2a corresponds to an embodiment of a "second voltage limiting transistor."

[0152] As explained in the voltage limiting circuit 101, the gate-source voltages VGSL1 and VGSL2 of the N-type transistors MNL1a and MNL2a are also expressed by the above-mentioned equations (8) and (9). The voltage limiting circuit 101 limits the voltages of the nodes N1 and N3 to below (VDDL-VGSL1) and below (VDDL-VGSL2), thereby protecting the withstand voltage of the LV transistors that make up the determination circuit 102.

[0153] On the other hand, if the gate-source voltages VGSL1 and VGSL2 become excessively large due to fluctuations in the threshold voltage Vthn in equations (8) and (9), there is a concern that the level of the detection voltage VdetL will drop, making it impossible for the determination circuit 102 to generate the startup current Ist2 even when the reference current Iref is smaller than the reference value.

[0154] Generally, the higher the threshold voltage of a transistor, the greater the absolute amount of variation in threshold voltage. Therefore, in the voltage limiting circuit 101 using enhancement-type N-type transistors MNL1 and MNL2, the variation in threshold voltage Vthn may cause the voltage upper limits (VDDL-VGSL1) and (VDDL-VGSL2) of the nodes N1 and N3 to drop more than expected.

[0155] As an example, consider a case where the threshold voltage Vthn varies in the range of 0.7V to 1.0V due to manufacturing, and the breakdown voltage of the LV transistor is 1.9V. In this case, the low power supply voltage VDDL supplied to the inverter INV1L formed by the LV transistor must not exceed the breakdown voltage of 1.9V. Therefore, the threshold value Vinv1 of the inverter INV1L is set to VDDL / 2=0.85V.

[0156] On the other hand, the detection voltage VdetL is limited to VdetL≦VDDL-VGSL1. Even if the second term in equations (8) and (9) is nearly zero and can be ignored, when the threshold voltage Vthn is 1.0V, the upper limit within the manufacturing variation range, the upper limit of the detection voltage VdetL becomes 1·9-1.0=0.9V, raising concerns that a margin cannot be secured for the threshold Vinv1=0.85V. If this margin cannot be secured, the output signal of inverter INV1 will be fixed at the H level (VDDL), turning on the startup transistor MNdetL will continuously generate startup current Ist2, and there is a risk of malfunction that makes it impossible to shut down the startup circuit.

[0157] Furthermore, since the second threshold VTHSL2 of the Schmitt trigger circuit ST1L of the startup circuits 100B and 100D is higher than the threshold Vinv1 of the inverter INV1L, it becomes even more difficult to ensure the above-mentioned margin for variations (on the high voltage side) in the threshold voltage Vthn.

[0158] In the case of a triple-well process that includes a Deep-NWell, it is possible to isolate the backgate terminals of the N-type transistors MNL1 and MNL2 from the ground (p-substrate). Therefore, by connecting the backgate terminal to the source terminal, the threshold voltage Vthn can be lowered, and the gate-source voltages VGSL1 and VSL2 can be lowered, thereby ensuring the above-mentioned margin. However, forming a Deep-NWell generally requires well isolation along with a layout that ensures distance between wells, which has the disadvantage of increasing the area.

[0159] In contrast to this, in the startup circuit 100D, the voltage limiting circuit 101a is configured using N-type transistors MNL1a and MNL2a, which are Low-VT transistors with a low threshold voltage.

[0160] In the N-type transistors MNL1a and MNL2a, both the voltage value and manufacturing variation of the threshold voltage Vthn are reduced, and therefore the voltage value and variation of the gate-source voltages VGSL1 and VSL2 are also reduced. As a result, it is possible to ensure a margin for the upper limit voltage of the detection voltage VdetL relative to the threshold VTH (Vinv1) of the determination circuit 102 without forming a deep N-well.

[0161] In particular, if the N-type transistors MNL1a and MNL2a are configured as native transistors whose threshold voltage Vthn is approximately 0, the amount of voltage drop due to the gate-source voltages VGSL1 and VSL2 can be made approximately 0. This makes it easy to ensure a margin for the upper limit voltage of the detection voltage VdetL relative to the threshold VTH (Vinv1) of the determination circuit 102, even if the low power supply voltage VDDL is set to be equivalent to the withstand voltage of the LV transistors.

[0162] As described above, the startup circuit 100E according to the fourth modification of the first embodiment includes a voltage limiting circuit 101a configured with Low-VT transistors, thereby making it possible to avoid the above-mentioned malfunction (unstoppable state) without increasing the circuit area.

[0163] In the startup circuit 100E, a configuration example has been described in which the voltage limiting circuit 101 in the startup circuit 100A is replaced with the voltage limiting circuit 101a (FIG. 10). However, it is also possible to use a configuration in which the voltage limiting circuit 101 in the startup circuits 100B to 100D (FIGS. 7 to 9) is replaced with the voltage limiting circuit 101a (FIG. 10).

[0164] In particular, it is effective to combine the voltage limiting circuit 101a with the decision circuits 102b and 102c (start-up circuits 100B and 100C) that generate the startup current Ist2 by the startup transistor MPdetL, as will be described below.

[0165] 8 and 9, the maximum value of the gate-source voltage of the startup transistor MPdetL is limited to (VDDL-VGSL2) by the voltage limiting circuit 101. Furthermore, when the startup current Ist2 increases due to the startup transistor MPdetL being turned on, VGSL2 due to the voltage limiting circuit 101 further increases, and the on-resistance of the startup transistor MPdetL increases. Furthermore, PMOS transistors generally have smaller current capabilities than NMOS transistors.

[0166] From these perspectives, it is preferable to make it easier to supply the startup current Ist2 in the startup transistor MPdetL by reducing VGSL2 using the voltage limiting circuit 101 and increasing the gate-source voltage. For this reason, in the startup circuits 100B and 100C, using the voltage limiting circuit 101a configured with Low-VT transistors has the advantage of making it easier to ensure the startup current Ist2 compared to using the voltage limiting circuit 101.

[0167] (Fifth Modification) In the fifth modification, another configuration example of the voltage limiting circuit 101a according to the fourth modification will be described.

[0168] 11 is a circuit diagram illustrating the configuration of a startup circuit 100F according to a fifth modification of embodiment 1. Like the startup circuits 100A to 100E, the startup circuit 100F can be connected to the reference voltage generation circuit 10 including the reference voltage generation circuits 10A and 10B to ensure the startup of the reference voltage generation circuit 10.

[0169] 11, the startup circuit 100F differs from the startup circuit 100A (FIGS. 4 and 6) according to the first embodiment in that it includes a voltage limiting circuit 101b instead of the voltage limiting circuit 101. The voltage limiting circuit 101b is arranged to achieve the same effect as the voltage limiting circuit 101a without using a Low-VT transistor.

[0170] Compared to the voltage limiting circuit 101, the voltage limiting circuit 101b further includes an N-type transistor MNL3 in addition to the N-type transistors NSL1 and NSL2. The N-type transistor MNL3 is connected between the power supply node Np and the inverter INV1L. Furthermore, the gate of the N-type transistor MNL3 is connected to the low power supply node Npl (node ​​N2). The N-type transistor MNL3 corresponds to one embodiment of a "third voltage limiting transistor."

[0171] As a result, a voltage drop equivalent to the gate-source voltages VGSL1 and VGSL2 of the N-type transistors MNL1 and MNL2 occurs between the gate and source of the N-type transistor MNL3. In other words, the gate-source voltage VGSL3 of the N-type transistor MNL3 is equivalent to VGSL1 and VGSL2.

[0172] In the startup circuit 100F, the low power supply voltage VDDL is supplied to the inverter INV1L via the N-type transistor MNL3. As a result, the threshold value Vinv1 of the inverter INV1L (i.e., the threshold value VTH of the determination circuit 102) is lowered to (VDDL-VGSL3). As a result, it can be understood that it is easy to ensure a margin of the upper limit voltage (VDDL-VGSL1) of the detection voltage VdetL with respect to the threshold value Vinv1 of the inverter INV1L.

[0173] As described above, the startup circuit 100F according to the fifth modification of the first embodiment can achieve the same effects as the startup circuit 100E (FIG. 10) even when a Low-VT transistor cannot be used. (VDDL-VGSL3)

[0174] However, in the startup circuit 100F, the number of transistors required to configure the voltage limiting circuit 101a increases, so if low-VT transistors can be used, it is more advantageous to use the startup circuit 100E (FIG. 10).

[0175] In the startup circuit 100F, a configuration example has been described in which the voltage limiting circuit 101 in the startup circuit 100A is replaced with a voltage limiting circuit 101a (FIG. 10). However, in the startup circuits 100B to 100D (FIGS. 7 to 9), the voltage limiting circuit 101 can also be replaced with a voltage limiting circuit 101b (FIG. 11). In this case, in a configuration in which driving elements (such as inverters INV1L and INV2L and Schmitt trigger circuits ST1L) are connected in multiple stages, the source of one N-type transistor MNL3 is connected to each driving element. That is, (VDDL-VGSL3) can be supplied to each of the multiple driving elements using a common N-type transistor MNL3.

[0176] (Sixth Modification) In the sixth modification, still another example of the configuration of the voltage limiting circuit 101 will be described.

[0177] 12 is a circuit diagram illustrating the configuration of a startup circuit 100G according to a sixth modification of embodiment 1. Like the startup circuits 100A to 100F, the startup circuit 100G can be connected to the reference voltage generation circuit 10 including the reference voltage generation circuits 10A and 10B to ensure the startup of the reference voltage generation circuit 10.

[0178] 12, startup circuit 100G differs from startup circuit 100A according to the first embodiment (FIGS. 4 and 6) in that voltage limiting circuit 101 is replaced with a voltage limiting circuit 101c.

[0179] The voltage limiting circuit 101c has an outside rail configuration based on the well-known double cascode configuration described in Non-Patent Document 1, etc. The outside rail configuration is known as a technology that uses scaled transistors to enable operation even under power supply voltages that exceed the breakdown voltage. The voltage limiting circuit 101c is configured including N-type transistors MNL1b-MNL4b and P-type transistors MPL1b-MPL4b, to which LV transistors are applied.

[0180] The N-type transistors MNL3b and MNL1b are connected in series between the current detection transistor MPst1 (drain) and the node N1 of the detection voltage generation circuit 105. That is, in the voltage limiting circuit 101c, the N-type transistors MNL3b and MNL1b cascode-connected in multiple stages constitute one embodiment of a "first voltage limiting transistor."

[0181] Similarly, N-type transistors MNL4b and MNL2b are connected in series between output node No2 connected to reference voltage generating circuit 10 and node N3 of determination circuit 102 in a vertically stacked configuration. That is, in voltage limiting circuit 101c, N-type transistors MNL2b and MNL4b cascode-connected in multiple stages constitute one embodiment of a "second voltage limiting transistor." The gates of N-type transistors MNL1b and MNL2b are connected to node N2, which is connected to low power supply node Npl (low power supply voltage VDDL).

[0182] The P-type transistor MPL3b is connected between the drain and gate of the N-type transistor MNL3b and functions as a switch. Similarly, the P-type transistor MPL1b is connected between the gate of the N-type transistor MNL3b and the gate of the N-type transistor MNL1b and functions as a switch. The gate of the P-type transistor MPL3b is connected to the gate of the N-type transistor MNL1b via the node N2, and the gate of the P-type transistor MPL1b is connected to the drain of the N-type transistor MNL3b.

[0183] Similarly, P-type transistor MPL4b is connected between the drain and gate of N-type transistor MNL4b and functions as a switch. Similarly, P-type transistor MPL2b is connected between the gate of N-type transistor MNL2b and the gate of N-type transistor MNL4b and functions as a switch. The gate of P-type transistor MPL4b is connected to the gate of N-type transistor MNL2b via node N2, and the gate of P-type transistor MPL2b is connected to the drain of N-type transistor MNL4b.

[0184] As described above, the voltage limiting circuit 101c has a symmetrical circuit configuration with respect to the nodes N1 and N3, so the operation of the N-type transistors MNL1b, MNL3b and P-type transistors MPL1b, MPL3b, i.e., the left-side circuit, with respect to the node N1 will be representatively described.

[0185] When the detection voltage VdetL is at the L level, the gate-source voltage VGSL1b of the N-type transistor MNL1b becomes VDDL, and the N-type transistor MNL1b is fully turned on. Therefore, the source potential of the N-type transistor MNL3b becomes approximately 0V (GND). Because the N-type transistor MNL3b is also turned on, its drain potential also becomes close to 0V, and as a result, the P-type transistor MPL3b turns off. Then, the source-gate voltage VSG of the P-type transistor MPL1b rises, and the P-type transistor MPL1b turns on.

[0186] If the gate potential of the N-type transistor MNL3b is equal to or lower than the threshold potential and the drain potential of the N-type transistor MNL3b is higher than the low power supply voltage VDDL, the P-type transistor MPL3b turns on, forcing the N-type transistor MNL3b to turn on. Therefore, when the detection voltage VdetL is at the L level, the N-type transistor MNL3b is always turned on.

[0187] At this time, the gate potentials VGL1b and VGL3b of N-type transistors MNL1b and MNL3b are both VDDL. The gate-source voltage of N-type transistor MNL1b is VGSL1b=VDDL, and the drain-source voltage VDSL1b=0. The gate-source voltage of N-type transistor MNL3b is VGSL3b=VDDL, and the drain-source voltage VDSL3b=0. Therefore, assuming that VDD=3.3V and VDDL=1.8V and the maximum rated withstand voltage of the LV transistors is 2.0V, then VGS1b=1.8V, VDSL1b=0V, VGSL3b=1.8V, and VDSL3b=0V, and none of the withstand voltages are exceeded.

[0188] On the other hand, when the detection voltage VdetL is at the H level, the gate-source voltage VGSL1b of the N-type transistor MNL1b becomes VDDL-VdetL, and when VGSL1b becomes equal to or lower than the threshold voltage of the N-type transistor MNL1b, the N-type transistor MNL1b turns off. The N-type transistor MNL1b in the off state then becomes high impedance, and the N-type transistor MNL3b turns off as its source potential rises, also becoming high impedance. As a result, the drain voltage of the current detection transistor MPst1 becomes equivalent to the low power supply voltage VDDL.

[0189] This causes the P-type transistor MPL3b to turn on, and the switch operates so that the N-type transistor MNL3b is diode-connected. As a result, the source potential of the N-type transistor MNL3b shifts (decreases) by the threshold voltage Vthn of the N-type transistor MNL3b. If VDD=3.3V and Vthn=1V, the source potential of the N-type transistor MNL3b becomes 2.3V. Because the gate-source voltage VGSL1b of the N-type transistor MNL1b is >0, the upper limit voltage of the detection voltage VdetL is limited to the low power supply voltage VDDL.

[0190] At this time, the gate potential of N-type transistor MNL1b is VGL1b=VDDL, and the gate potential of MNL3b is VGL3b=VDD, so the gate-source voltage of N-type transistor MNL1b is VGSL1b=0, and the drain-source voltage VDSL1b=VDD-Vthn (threshold voltage of MNL3b)-VDDL. Also, the gate-source voltage of N-type transistor MNL3b is VGSL3b=VDDL, and the drain-source voltage VDSL3b=0.

[0191] Therefore, if VDD=3.3V, VDDL=1.8V, and Vthn=1.0V, and the maximum rating of the withstand voltage of the LV transistor is 2.0V, then VGS1b=0V, VDSL1b=3.3-1.0-1.8=0.5V, VGSL3b=1.8V, and VDSL3b=0V, and none of the withstand voltages will be exceeded.

[0192] As described above, the voltage limiting circuit 101c has a symmetrical configuration in which the left path relative to node N1 and the right path relative to node N3 are symmetrical. Therefore, the N-type transistors MNL2b and MNL4b and the P-type transistors MPL2b and MPL4b operate in the same manner as the N-type transistors MNL1b and MNL3b and the P-type transistors MPL1b and MPL3b. At this time, the logic level of the detection voltage VdetL is inverted by the inverter INV1 and input to the gate of the startup transistor MNdetL, and the logic level of the output signal of the inverter INV1 is further inverted at the drain of the startup transistor MNdetL. Therefore, the logic levels of nodes N1 and N3 are the same, and it can be understood that the left path and the right path of the voltage limiting circuit 101c operate in the same manner.

[0193] As described above, the startup circuit 100G according to the sixth modification of the first embodiment allows a voltage limiting circuit to be configured using LV transistors, even if the voltage difference between the power supply voltage VDD and the low power supply voltage VDDL is large, due to the double cascode configuration in which transistors are stacked vertically. Note that, although the configuration in which the number of vertical stack stages is two is illustrated in FIG. 12, the number of vertical stack stages can be any number depending on the voltage difference between the power supply voltage VDD and the low power supply voltage VDDL.

[0194] As a result, even in a process in which native-type transistors such as those shown in FIG. 10 (startup circuit 100E) cannot be used, the voltage limiting circuit 101c using SV-type transistors can be used to avoid malfunctions (unstoppable states) of the startup circuit, similar to the startup circuits 100E and 100F, without using SV-type transistors with high threshold voltages.

[0195] In the startup circuit 100G, a configuration example has been described in which the voltage limiting circuit 101 in the startup circuit 100A is replaced with the voltage limiting circuit 101c (FIG. 12). However, it is also possible to replace the voltage limiting circuit 101 in the startup circuits 100B to 100D (FIGS. 7 to 9) with the voltage limiting circuit 101c (FIG. 12).

[0196] Embodiment 2 In the second embodiment, an example of a circuit configuration will be described in which the start-up transistors (MNdet, PNdet) are turned on and off without using a driving element such as an inverter and / or a Schmitt trigger circuit.

[0197] FIG. 13 is a circuit diagram illustrating the configuration of a startup circuit 100H according to the second embodiment.

[0198] 13, the startup circuit 100H differs from the startup circuit 100H according to the second modification of the first embodiment (FIG. 8) in that it includes a determination circuit 103a instead of the determination circuit 102b. The determination circuit 103a has a startup transistor MPdet configured as a P-type transistor. The gate of the startup transistor MPdet is connected to a node N1 of the detection voltage generation circuit 105 without passing through a drive element such as an inverter.

[0199] In other words, the startup circuit 100H has a circuit configuration in which the even-numbered inverters INV1L and INV2L are removed from the determination circuit 102a of the startup circuit 100C in Fig. 8. The configuration of other parts of the startup circuit 100H is the same as that of the startup circuit 100C, and therefore detailed description will not be repeated. As with the startup circuits 100A to 100I, the startup circuit 100H can be connected to the reference voltage generation circuit 10 including the reference voltage generation circuits 10A and 10B to ensure the startup of the reference voltage generation circuit 10.

[0200] In the determination circuit 103a, the detection voltage VdetL is directly input to the gate of the activation transistor MPdet. Therefore, the threshold value VTH of the determination circuit 103a is different from the threshold value Vinv1L of the inverter INV1L in FIG. 6 and can be expressed by the following equation (15) using the threshold voltage Vthp of the activation transistor MPdet and the source potential (VDDL-VGSL2). VTH=VDDL-VSGL2-Vthp …(15)

[0201] When the detection voltage VdetL proportional to the reference current Iref becomes equal to or greater than the threshold VTH of equation (15), that is, when Iref×L1×Rst1>VDDL−VSGL2−Vthp, the start-up transistor MPdet is turned off and the start-up current Ist2 becomes 0. Therefore, it can be seen from equation (15) that, unlike the first embodiment and its modifications, a higher threshold voltage Vthp is advantageous in order to lower the detection voltage VdetL under the control of turning on the start-up transistor MPdet when the reference current Iref is smaller than the reference value.

[0202] Therefore, unlike the determination circuit 102, the determination circuit 103a of the startup circuit 100H preferably has a P-type startup transistor MPdet configured using an SV transistor rather than an LV transistor.

[0203] In the startup circuit 100H, the voltage limiting circuit 101 uses a low power supply voltage VDDL and increases VGSL1 and VGSL2, thereby lowering the detection voltage VdetL used to determine whether the reference current Iref is smaller than the reference value.

[0204] As a result, in the startup circuit 100H according to the second embodiment, as in the first embodiment, the circuit area and power consumption can be reduced by lowering the detection current Ist1 in the detection voltage generating circuit 105 and the resistance value of the detection resistor Rst1.

[0205] Compared to the first embodiment and its modifications, the startup circuit 100H according to the second embodiment does not include drive elements such as an inverter and a Schmitt trigger circuit, which allows the area of ​​the determination circuit 103a to be reduced. However, since no drive elements are used, there is a concern that the drive speed of the startup transistor and robustness against noise or chattering may be reduced. For this reason, the startup circuit 100H is suitable for applications where there are fewer requirements regarding noise and chattering, but where there is a strong need for a smaller area.

[0206] As described above, it is advantageous to increase the threshold voltage of the startup transistor MPdet in the startup circuit 100H. The threshold voltage Vthp of a PMOS transistor is determined depending on the transistor structure or manufacturing process, and is known to be expressed by the following equation (16), which is similar to the above equation (13).

number

[0207] As in equation (13), Vt0 is the threshold voltage when the source-bulk voltage Vsb=0, φf is the Fermi voltage, q is the elementary charge, and N A is the doping density of the p-type substrate on which the NMOS transistor is fabricated, ε is the dielectric constant of silicon, and Cox is the gate oxide capacitance per unit area. It is known that there is a relationship between the gate oxide capacitance Cox and the gate oxide thickness tox, Cox ∝ (1 / tox).

[0208] From equation (16), if the low power supply voltage VDDL is supplied to the back gate terminal of the start-up transistor MPdet, the threshold voltage Vthp can be further increased.

[0209] Since the source potential of the start transistor MPdet is (VDDL-VGSL2), by setting the backgate potential to VDDL, the backgate-source voltage Vbs in equation (16) becomes VDDL-(VDDL-VGSL2)=VGSL2. Therefore, compared to when the backgate is connected to the source (Vbs=0), by increasing the threshold voltage Vthp of the start transistor MPdetL, it is possible to further reduce the detection current Ist1 and the resistance value of the detection resistor Rst1.

[0210] In a manufacturing process where a special element with a high threshold voltage Vthp or a high breakdown voltage element (HV (High Voltage) transistor) is prepared, in place of the SV transistor, the above-mentioned special element or HV transistor can be used to form the startup transistor MPdet in FIG. 13.

[0211] Regarding the startup transistor MPdet, any transistor can be applied as long as it has a breakdown voltage higher than the power supply voltage VDD (for example, an SV transistor) and the threshold voltage Vthp satisfies Vthp < VDDL - VSGL2 - Ileak × Rst1, which is a condition where no malfunction occurs in which the startup transistor MPdet is fixed in the off state under the leakage current Ileak (Ist1 = Ileak).

[0212] Also, in order for the startup transistor MPdet to turn off with respect to the steady value Ist1* of the detection current Ist1, the determination circuit 103a needs to satisfy Vthp > VDDL - VSGL2 - Ist1* × Rst1. As a result, it is understood that for the range of the threshold voltage Vthp, both conditions of the following equations (17) and (18) are required. Ist1* > (VDDL - VGSL2 - Vthp) × Rst1 …(17) (VDDL - VGSL2 - Vthp) × Rst1 > Ileak …(18)

[0213] Therefore, in the startup circuit 100H, by increasing the threshold voltage of the startup transistor MPdet, the effect of reducing the circuit area and power consumption can be enhanced.

[0214] Modification of Embodiment 2. In the modification of Embodiment 2, a configuration example of a determination circuit that uses only an N-type startup transistor without driving elements such as an inverter and / or a Schmitt trigger circuit will be described.

[0215] FIG. 14 is a circuit diagram for explaining the configuration of a startup circuit 100I according to a modification of Embodiment 2.

[0216] Referring to FIG. 14, a startup circuit 100I includes a detection voltage generating circuit 106 and a determination circuit 103b.

[0217] The detection voltage generating circuit 106 includes a detection resistor Rst1 and a current detection transistor MNst1 configured with an N-type transistor. The detection resistor Rst1 is connected between a low power supply node Npl to which a low power supply voltage VDDL is supplied from the local power supply circuit 110 and a node N1 at which a detection voltage VdetL is generated.

[0218] The current detection transistor MNst1 is connected between the node N1 and the ground node Ng. The gate of the current detection transistor MNst1 is connected to the node NA1 of the reference voltage generating circuit 10A, i.e., to the gates of the N-type transistors MNb1 and MNb2 that form an N-type current mirror, via the output node No1 of the startup circuit 100I.

[0219] The source and gate of current detection transistor MNst1 are commonly connected to N-type transistors MNb1 and MNb2, so that an N-type current mirror is formed by current detection transistor MNst1 and N-type transistors MNb1 and MNb2 of reference current generating circuit 10A. Current detection transistor MNst1 has an aspect ratio L1 times that of N-type transistors MNb1 and MNb2, and thus, like detection voltage generating circuit 105, can cause detection current Ist1, which is L1 times the reference current Iref, to flow through node N1.

[0220] This allows the detection voltage generation circuit 106 to generate a detection voltage VdetL that depends on the reference current Iref at the node N1. The detection voltage VdetL of the detection voltage generation circuit 106 can be expressed by the following equation (19). VdetL=VDDL-Ist1×Rst1=VDDL-Iref×L1×Rst1 …(19)

[0221] The determination circuit 103b has an N-type startup transistor MNdet connected between node N3 and a ground node Ng. Node N3 serves as output node No. 2 of the startup circuit 100I and is connected to node NA0 in the reference voltage generating circuit 10A. As described above, node NA0 corresponds to the gates of P-type transistors MPb1 and MPb2 that form a P-type current mirror that outputs the reference current Iref.

[0222] The gate of the startup transistor MNdet is connected to the node N1 of the detection voltage generation circuit 106 without passing through a drive element such as an inverter, so that the detection voltage VdetL is directly input to the gate of the startup transistor MNdet in the determination circuit 103b. Therefore, the threshold value VTH of the determination circuit 103b is different from the threshold value Vinv1L of the inverter INV1L in FIG. 4 and is equivalent to the threshold voltage Vthn of the startup transistor MNdet.

[0223] Specifically, when the detection voltage VdetL of equation (19) is equal to or greater than the threshold voltage Vthn of the startup transistor MNdet, the startup transistor MNdet is turned on to generate a startup current Ist2. On the other hand, when the detection voltage VdetL is lower than the threshold voltage Vthn, the startup transistor MNdet is turned off (Ist2=0).

[0224] Therefore, by determining the resistance value of the detection resistor Rst1 and the current amplification factor L1 of the current detection transistor MNst1 so that the right side of the following equation (20), obtained by transforming VDDL-Iref×L1×Rst1≧Vthn, becomes the reference value of the reference current Iref (for determining undesirable stable operating points), the judgment circuit 103b can be operated in the same way as the judgment circuit 102 of embodiment 1. Iref≦(VDDL-Vthn) / (Rst1×L1) …(20)

[0225] Furthermore, in the determination circuit 103b, in order to avoid malfunction due to the steady-state value Ist1* (leakage current Ileak) of the detection current Ist1 and the leakage current Ileak, the following equation (21) is a condition to be satisfied. Ilaek<(VDDL-Vthn) / Rst1 <Ist1* …(21)

[0226] In this way, in the startup circuit 100I according to the modified example of the second embodiment, as in the startup circuit 100H according to the second embodiment, the circuit area and power consumption can be reduced by using the determination circuit 103b that does not involve the arrangement of driving elements such as an inverter and a Schmitt trigger circuit, and by reducing the detection current Ist1 and the resistance value of the detection resistor Rst1 in the detection voltage generation circuit 106.

[0227] Furthermore, from equation (21), it is clear that in the judgment circuit 103b as well, when the reference current Iref is smaller than the reference value, in order to realize control to turn on the startup transistor MNdet, a higher threshold voltage Vthn is advantageous in order to lower the detection voltage VdetL.

[0228] For this reason, in the detection voltage generation circuit 106, the low power supply voltage VDDL from the local power supply circuit 110 is applied to a series circuit of the current detection transistor MNst1 and the resistance element Rst1, and the current detection transistor MNst1 is configured with an SV transistor instead of an LV transistor to increase the threshold voltage Vthn. As with the startup transistor MPdet in the second embodiment, the startup transistor MNdet can also be configured using a special element or an HV transistor with a high threshold voltage Vthp.

[0229] Furthermore, in the startup circuit 100I, the low power supply voltage VDDL is directly used for the detection voltage generation circuit 106, thereby eliminating the need to arrange transistor groups that constitute the voltage limiting circuits 101, 101a to 101c. This allows for a further reduction in circuit area compared to the startup circuit 100H according to the second embodiment.

[0230] In the first embodiment (FIGS. 4 and 6) and its variations (FIGS. 7 to 12) and the second embodiment (FIG. 13), an example of the "detection voltage limiting circuit" is configured by the low power supply node Npl and the voltage limiting circuits 101, 101a to 101c, whereas in the variation of the second embodiment (FIG. 13), an example of the "detection voltage limiting circuit" is configured by the low power supply node Npl or the local power supply circuit 110 and the low power supply node Npl.

[0231] In the first and second embodiments and their modifications, the transistors constituting the startup circuits 100A-100I and the reference voltage generating circuit 10 are illustrated as field-effect transistors, but each transistor can also be replaced with a bipolar transistor. That is, each P-type transistor, which is an example of a "first conductivity type transistor," can also be configured as a pnp-type bipolar transistor, and each N-type transistor, which is an example of a "second conductivity type transistor," can also be configured as an npn-type bipolar transistor. When bipolar transistors are used, the "source" of each P-type transistor and each N-type transistor can be replaced with the "emitter," the "drain" with the "collector," and the "gate" that is the "control electrode" with the "base."

[0232] (Other embodiments) Hereinafter, other embodiments related to the startup circuits described in the first and second embodiments and their modifications will be described.

[0233] 15 and 16 show examples of mounting a startup circuit 100 according to this embodiment. The startup circuit 100 collectively denotes the startup circuits 100A to 100I according to the first and second embodiments and their modifications.

[0234] FIG. 15 is a block diagram illustrating a first implementation example of the startup circuit 100. As shown in FIG.

[0235] In FIG. 15, a semiconductor chip 500a mounted on a mobile device or the like includes a reference voltage generation circuit 10, a startup circuit 100 connected to the reference voltage generation circuit 10, a local power supply circuit 110, a power supply terminal 150, and a ground terminal 160. In the configuration example of FIG. 15, the power supply terminal 150 corresponds to an embodiment of the “first power supply terminal”.

[0236] A power supply voltage VDD is supplied to the power supply terminal 150 from the outside of the semiconductor chip 500a. The power supply voltage VDD is transmitted to the reference voltage generation circuit 10 and the startup circuit 100 by a power supply node Np connected to the power supply terminal 150. Similarly, a ground voltage GND is supplied to the ground terminal 160 from the outside of the semiconductor chip 500a. The ground voltage GND is transmitted to the reference voltage generation circuit 10 and the startup circuit 100 by a ground node Ng connected to the ground terminal 160.

[0237] The local power supply circuit 110 generates a low power supply voltage VDDL (VDDL < VDD) from the power supply voltage VDD. The low power supply voltage VDDL is transmitted to the startup circuit 100 by a low power supply node Npl. In the configuration example of FIG. 15, the low power supply voltage VDDL used by the startup circuit 100 can be generated inside the semiconductor chip 500a on which the startup circuit 100 is mounted.

[0238] FIG. 16 is a block diagram for explaining a second mounting example of the startup circuit 100.

[0239] In FIG. 16, a semiconductor chip 500b mounted on a mobile device or the like, compared with the semiconductor chip 500a shown in FIG. 15, does not have the local power supply circuit 110 but further includes a power supply terminal 151. A low power supply voltage VDDL is supplied to the power supply terminal 151 from the outside of the semiconductor chip 500b. The low power supply voltage VDDL is transmitted to the startup circuit 100 by a low power supply node Npl connected to the power supply terminal 151. In the configuration example of FIG. 16, the power supply terminal 150 corresponds to an embodiment of the “first power supply terminal”, and the power supply terminal 151 corresponds to an embodiment of the “second power supply terminal”.

[0240] As shown in FIGS. 15 and 16, the low power supply voltage VDDL may be supplied from the outside to a semiconductor chip on which the startup circuit 100 according to this embodiment is mounted, or may be generated inside the semiconductor chip.

[0241] The circuit configuration of the local power supply that generates the low power supply voltage VDDL from the power supply voltage VDD inside the semiconductor chip is not limited to the example shown in FIG. 5, and can be designed arbitrarily.

[0242] 17 is a circuit diagram illustrating another example of the configuration of a local power supply that generates a low power supply voltage VDDL. Fig. 17 shows the configuration of a local power supply circuit 110a that is suitable for combination with a reference voltage generating circuit 10B (BGR circuit).

[0243] 17, local power supply circuit 110a includes, in addition to resistor element Rb110 and constant voltage generating circuit 120 similar to those of the local power supply in Fig. 5, a source follower circuit 130 using N-type transistor MNsf and a bias circuit 140. Bias circuit 140 generates bias current Ib, which is the operating current of differential amplifier AMP, which is an element of reference voltage generating circuit 10B (BGR circuit).

[0244] The bias circuit 140 has a resistor element Rb140 constituting a bias resistor, and N-type transistors MN141 and MN142. The N-type transistor MN142 is connected between a node Namp through which the operating current of the differential amplifier AMP flows and a ground node Ng. The N-type transistor MN141 is connected between the resistor element Rb140 and the ground node Ng, and has a gate interconnected with the gate of the N-type transistor MN141. That is, the N-type transistors MN141 and MN142 constitute a current mirror.

[0245] The bias circuit 140 forms a current source, and when the aspect ratios (Wg / Lg) of the N-type transistors MN141 and MN142 are equal, it can generate a bias current Ib expressed by equation (22) at the node Namp using the power supply voltage VDDL2 at the node Npll. In equation (22), Rb140 represents the resistance value of the resistor element Rb140, and VGS141 represents the gate-source voltage of the N-type transistor MN141. Ib=(VDDL2-VGS141) / Rb140 …(22)

[0246] When the gate-source voltage VGSsf of the N-type transistor MNsf constituting the source follower circuit 130 and VDDL=3×Vf described in FIG. 5 are substituted into equation (22), the bias current Ib is expressed by the following equation (23). Ib=(3×Vf-VGSsf-VGS141) / Rb140…(23)

[0247] It should be noted that, although applications having an external current source are also conceivable for the bias circuit that generates the operating current of the differential amplifier AMP, in the case of an application in which the bias current Ib is generated internally, the bias current Ib can be a current generated from the power supply voltage VDDL2 output to the node Npll and flowing through a resistor element Rb140, as shown in Fig. 17. That is, in Fig. 17, the bias circuit 140 corresponds to an example of a "current source" that generates the bias current Ib, which is an example of the "operating current" of the differential amplifier AMP included in the bandgap circuit.

[0248] The power supply voltage VDLL2 of the node Npll is made independent of the power supply voltage VDD via the constant voltage generating circuit 120 and the source follower circuit 130. Therefore, the bias current Ib can be a constant current that is independent of the power supply voltage VDD. By configuring the local power supply circuit 110a in this manner using the bias circuit 140 that generates the operating current (bias current Ib) of the differential amplifier AMP, the circuit area can be reduced and the bias current Ib can be stabilized. Note that in the local power supply circuit 110a of FIG. 17, the power supply voltage VDDL2 of the node Vpll can also be used as the low power supply voltage VDDL in the startup circuit 100.

[0249] Furthermore, if the transistors (not shown) constituting the differential pair of the differential amplifier AMP are configured using native NMOS transistors with a threshold voltage of approximately 0, the voltage applied to the current source generating the operating current of the differential amplifier AMP is limited to a constant voltage that is independent of the power supply voltage VDD. Therefore, the source potential Vtail of the transistors constituting the differential pair is equivalent to the forward voltage drop Vf generated across the diode element Db1 of the reference voltage generating circuit 10B (Vtail ≒ Vf). Therefore, if Vf = 0.6 V, the current source can be realized using LV transistors.

[0250] As a result, the power supply voltage VDDL2 of the node Npll is applied, and the N-type transistors MN141 and MN142 of the bias circuit 140 that operates as a current source can be realized by LV transistors, which makes it possible to further reduce the circuit area and the variation in the bias current Ib.

[0251] <Additional Notes> The above-described embodiment and modified examples include the following technical ideas. [Configuration 1] A startup circuit (100A-100I) of a reference voltage generating circuit (10) configured to generate a reference current (Iref) therein and output a constant reference voltage (Vref) using the reference current, a detection voltage generating circuit (105, 106) that generates a detection voltage (VdetL) that varies depending on the reference current; a determination circuit (102, 102a to 102c, 103a, 103b) configured to generate an activation current (Ist2) acting on the reference voltage generation circuit so as to increase the reference current when it is determined that the reference current is smaller than a predetermined reference value based on a comparison between the detected voltage and a predetermined threshold value (VTH); The detection voltage generation circuit current detection transistors (MPst1, MNst1) that form a current mirror together with transistors (MPb0, MNb0) through which the reference current passes in the reference voltage generation circuit and generate a detection current obtained by amplifying the reference current by a predetermined amplification factor (L1); a detection resistor (Rst1) arranged to generate a voltage drop in response to the passage of the detection current, thereby generating the detection voltage at a first node (N1); The startup circuit includes: The detection voltage limiting circuit (Npl, 110, 110a to 102c) further includes a second power supply voltage (VDDL) that is lower than the first power supply voltage (VDD) of the reference voltage generating circuit and limits the upper limit of the change range of the detection voltage to less than or equal to the second power supply voltage, The determination circuit a startup circuit including startup transistors (MNdetL, MPdetL) connected to second nodes (NA0, NB0) in the reference voltage generating circuit so as to turn on and generate the startup current when a comparison result between the detection voltage and the threshold indicates that the reference current is smaller than the reference value;

[0252] [Configuration 2] The current detection transistor (MPst1) is a first conductivity type transistor having a source or an emitter connected to a first power supply node (Np) that transmits the first power supply voltage (VDD), the detection resistor (Rst1) is connected between the first node (N1) and a ground node (Ng); The determination circuit Further comprising at least one stage of driving elements (INV1L, INV2L, ST1L) connected between the first node and the control electrodes of the start-up transistors (MNdetL, MPdetL), Each of the driving elements is supplied with the second power supply voltage (VDDL) to operate; The detection voltage limiting circuit (101, 101a) a first voltage limiting transistor (MNL1, MNL1a) configured by a second conductivity type transistor connected between the current detection transistor and the first node; second voltage limiting transistors (MNL2, MNL2a) configured by the second conductivity type transistors connected between the second nodes (NA0, NB0) and the start-up transistors; The startup circuit (100A to 100D) according to configuration 1, wherein control electrodes of the first voltage limiting transistor and the second voltage limiting transistor are commonly connected to a second power supply node (Npl) that transmits the second power supply voltage.

[0253] [Configuration 3] the at least one stage of driving elements includes an odd number of inverter stages (INV1L, ST1L), The detection voltage (VdetL) is input to the first inverter (INV1L, ST1L) of the odd-numbered inverters, The startup circuit (100A, 100B) according to configuration 2, wherein the startup transistor is composed of the second conductivity type transistor (MNdetL) connected between the second voltage limiting transistor (MNL2, MNL2a) and a ground node (Ng) and having an output signal of the final stage inverter of the odd-numbered stage inverters input to a control electrode.

[0254] [Configuration 4] the at least one stage of driving elements includes an even number of stages of inverters (INV1L, INV2L, ST1L), The detection voltage (VdetL) is input to the first inverter (INV1L, ST1L) of the even-numbered inverters, The startup circuit (100C, 100D) according to configuration 2, wherein the startup transistor is composed of the transistor (MPdetL) of the first conductivity type connected between the second voltage limiting transistor (MNL2, MNL2a) and a ground node (Ng) and receiving an output signal of the final-stage inverter of the even-stage inverters at a control electrode.

[0255] [Configuration 5] 5. The startup circuit (100B, 100D) according to configuration 3 or 4, wherein the first-stage inverter is configured with a Schmitt trigger circuit (ST1L).

[0256] [Configuration 6] A startup circuit (100A to 100D) according to any one of configurations 2 to 4, wherein the transistors constituting each of the at least one stage driving elements (INV1L, INV2L, ST1L) and the startup transistors (MNdetL, MPdetL) are configured with transistors having a lower threshold voltage than the current detection transistors (MPst1, MNst1).

[0257] [Configuration 7] The current detection transistor is composed of a first conductivity type transistor (MPst1) having a source or an emitter connected to a first power supply node (Np) that transmits the first power supply voltage (VDD), the detection resistor (Rst1) is connected between the first node (N1) and a ground node (Ng); The detection voltage limiting circuit (101, 101a to 101c) first voltage limiting transistors (MNL1a, MNL1a) configured by a second conductivity type transistor connected between the current detection transistor (MPst1) and the first node; second voltage limiting transistors (MNL1a, MNL1a) configured by the second conductivity type transistors connected between the second nodes (NA0, NB0) and the start-up transistors; control electrodes of the first voltage limiting transistor and the second voltage limiting transistor are commonly connected to a second power supply node (Npl) that transmits the second power supply voltage (VDDL); 2. The startup circuit (100H) of configuration 1, wherein the startup transistor comprises a transistor (MPdet) of the first conductivity type connected between the second voltage limiting transistor and the ground node and having a control electrode connected to the first node without a drive element.

[0258] [Configuration 8] The startup circuit (100E) according to any one of configurations 2 to 7, wherein the first voltage limiting transistor (MNL1a) and the second voltage limiting transistor (MNL1a) are configured with transistors having a lower threshold voltage than the current detection transistors (MPst1, MNst1).

[0259] [Configuration 9] The detection voltage limiting circuit (101b) Further, a third voltage limiting transistor (MNL3) configured by a transistor of the second conductivity type connected between the first power supply node (Np) and each of the driving elements (INV1L, INV2L, ST1L), 8. The startup circuit (100F) according to any one of configurations 2 to 7, wherein a control electrode of the third voltage limiting transistor is connected to the second power supply node (Npl).

[0260] [Configuration 10] The startup circuit (100C) according to any one of configurations 2 to 7, wherein the detection voltage limiting circuit (101c) is configured using transistors (MNL1b to MNL4b, MPL1a to MPL1b) whose threshold voltages are lower than those of the current detection transistors, with each of the first voltage limiting transistor (MNL1) and the second voltage limiting transistor (MNL2) being configured by transistors cascode-connected in multiple stages.

[0261] [Configuration 11] the current detection transistor is configured by a transistor (MNst1) having a source or emitter connected to a ground node (Ng) and a drain or collector connected to the first node (N1); the detection voltage limiting circuit includes a second power supply node (Npl) to which the second power supply voltage (VDDL) is supplied; the detection resistor (Rst) is connected between the second power supply node and the first node (N1); The startup circuit (100I) of configuration 1, wherein the startup transistor is connected between the second node (NA0) and the ground node, and comprises a transistor (MNdet) of the same conductivity type as the current detection transistor, the transistor having a control electrode connected to the first node without passing through a drive element.

[0262] [Configuration 12] 12. The startup circuit (100H, 100I) according to configuration 7 or 11, wherein the startup transistors (MPdetL, MNdetL) are configured with transistors having a threshold voltage equal to or higher than the threshold voltage of the current detection transistors (MPst1, MNst1).

[0263] [Configuration 13] The startup circuit (100A to 100I) according to any one of configurations 1 to 12, wherein the reference value of the reference current (Iref) is greater than the value of the reference current at a stable operating point where the reference current is smallest among a plurality of stable operating points of the reference voltage generating circuit (10), and is smaller than the value of the reference current in stable operation where the reference voltage generating circuit normally generates the reference voltage (Vref).

[0264] [Configuration 14] A startup circuit (100A to 100I) according to any one of configurations 1 to 13, wherein the threshold value (VTH) of the judgment circuit and the resistance value of the detection resistor (Rst1) are determined so that the start-up transistors (MNdet, MNdetL, MPdet, MPdetL) are turned on based on a comparison of the detection voltage (VdetL) and the threshold value when the detection current (Ist1) is a leakage current of the current detection transistors (MPst1, MNst1).

[0265] [Configuration 15] The first power supply voltage (VDD) is supplied from outside the semiconductor chip (500a) to a first power supply terminal (150) of the semiconductor chip (500a) on which the reference voltage generating circuit (10) and the startup circuit (100) are mounted, The startup circuit (100A to 100I) according to any one of configurations 1 to 14, wherein the second power supply voltage (VDDL) is generated by a local power supply circuit (110) mounted on the semiconductor chip using the first power supply voltage.

[0266] [Configuration 16] The reference voltage generating circuit (10) is configured by a bandgap reference circuit (10B) including a differential amplifier (AMP), 16. The startup circuit (100A to 100I) according to configuration 15, wherein the local power supply circuit (110) includes a current source (140) that generates an operating current (Ib) for the differential amplifier using the second power supply voltage (VDDL).

[0267] [Configuration 17] The startup circuit (100A to 100I) according to any one of configurations 1 to 14, wherein the first power supply voltage (VDD) and the second power supply voltage (VDDL) are supplied from outside a semiconductor chip (500b) on which the reference voltage generating circuit (10) and the startup circuit (100) are mounted to a first power supply terminal (150) and a second power supply terminal (151) of the semiconductor chip.

[0268] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0269] 10, 10A, 10B reference voltage generating circuit, 22, 23, 102, 102a to 102c, 103a, 103b judgment circuit, 25, 105, 106 detection voltage generating circuit, 30 signal level conversion circuit, 100, 100A to 100I, 100X to 100Z start-up circuit, 101, 101a to 101c voltage limiting circuit, 110, 110a local power supply circuit, 120 constant voltage generating circuit, 130 source follower circuit, 140 bias circuit, 150, 151 power supply terminal, 160 ground terminal, 500a, 500b semiconductor chip, INV1, INV1L, INV2L inverter, Iref reference current, Ist0, Ist1 detection current, Ist2 startup current, MNdet, MNdetL, MPdet, MPdetL Start transistor, MNst1, MPst0, MPst1 current detection transistor, Ng ground node, No1, No2 output node, Np power node, Npl low power node, Rst, Rst0, Rst1 detection resistor, ST1L Schmitt trigger circuit, VDD, VDLL2 power supply voltage, VDDL low power supply voltage, Vdet, VdetL detection voltage, Vf forward drop voltage, Vref reference voltage.

Claims

1. A startup circuit for a reference voltage generating circuit configured to generate a reference current therein and output a constant reference voltage using the reference current, a detection voltage generating circuit that generates a detection voltage that varies depending on the reference current; a determination circuit configured to generate a startup current that acts on the reference voltage generation circuit so as to increase the reference current when it is determined that the reference current is smaller than a predetermined reference value based on a comparison between the detected voltage and a predetermined threshold value; The detection voltage generation circuit a current detection transistor that forms a current mirror with a transistor in the reference voltage generation circuit through which the reference current passes and that generates a detection current obtained by amplifying the reference current by a predetermined amplification factor; a sense resistor arranged to create a voltage drop in response to the passage of the sense current to generate the sense voltage at a first node; The startup circuit includes: a detection voltage limiting circuit that uses a second power supply voltage that is lower than the first power supply voltage of the reference voltage generating circuit to limit an upper limit value of a variation range of the detection voltage to equal to or lower than the second power supply voltage; The determination circuit a start-up circuit including a start-up transistor connected to a second node in the reference voltage generating circuit to turn on and generate the start-up current when a comparison result between the detection voltage and the threshold value indicates that the reference current is smaller than the reference value.

2. the current detection transistor is a transistor of a first conductivity type having a source or an emitter connected to a first power supply node that transmits the first power supply voltage; the detection resistor is connected between the first node and a ground node; The determination circuit further comprising at least one stage of a driving element connected between the first node and a control electrode of the start-up transistor; each of the driving elements is supplied with the second power supply voltage to operate; The detection voltage limiting circuit a first voltage limiting transistor configured as a transistor of a second conductivity type connected between the current detection transistor and the first node; a second voltage limiting transistor configured of the second conductivity type transistor connected between the second node and the start-up transistor; 2. The startup circuit according to claim 1, wherein control electrodes of said first voltage limiting transistor and said second voltage limiting transistor are commonly connected to a second power supply node transmitting said second power supply voltage.

3. the at least one stage of driving elements includes an odd number of inverter stages; the detection voltage is input to a first inverter of the odd-numbered inverter stages; 3. The startup circuit according to claim 2, wherein the startup transistor is configured by a transistor of the second conductivity type connected between the second voltage limiting transistor and a ground node and receiving an output signal of a final stage inverter of the odd-numbered stage inverters at a control electrode thereof.

4. the at least one stage of driving elements includes an even number of stages of inverters; The detection voltage is input to a first inverter of the even-numbered inverters, 3. The startup circuit according to claim 2, wherein the startup transistor is configured by the transistor of the first conductivity type connected between the second voltage limiting transistor and a ground node and receiving an output signal of a final stage inverter of the even number of stages of inverters at a control electrode thereof.

5. 5. The startup circuit according to claim 3, wherein the first-stage inverter is configured as a Schmitt trigger circuit.

6. 5. The startup circuit according to claim 2, wherein the transistors constituting each of the at least one stage of drive elements and the startup transistor are configured with transistors having a lower threshold voltage than the current detection transistor.

7. the current detection transistor is a transistor of a first conductivity type having a source or an emitter connected to a first power supply node that transmits the first power supply voltage; the detection resistor is connected between the first node and a ground node; The detection voltage limiting circuit a first voltage limiting transistor configured as a transistor of a second conductivity type connected between the current detection transistor and the first node; a second voltage limiting transistor configured of the second conductivity type transistor connected between the second node and the start-up transistor; a control electrode of the first voltage limiting transistor and a control electrode of the second voltage limiting transistor are commonly connected to a second power supply node that transmits the second power supply voltage; 2. The startup circuit of claim 1, wherein the startup transistor is comprised of a transistor of the first conductivity type connected between the second voltage limiting transistor and the ground node and having a control electrode connected to the first node without a drive element.

8. 8. The startup circuit according to claim 2, wherein the first voltage limiting transistor and the second voltage limiting transistor are configured with transistors having a lower threshold voltage than the current detection transistor.

9. The detection voltage limiting circuit a third voltage limiting transistor configured with a transistor of the second conductivity type connected between the first power supply node and each of the driving elements; 8. The startup circuit according to claim 2, wherein a control electrode of said third voltage limiting transistor is connected to said second power supply node.

10. The startup circuit according to any one of claims 2 to 4 and 7, wherein the detection voltage limiting circuit is configured using transistors having a lower withstand voltage than the current detection transistor, with the first voltage limiting transistor and the second voltage limiting transistor each being configured by a multi-stage cascode-connected transistor.

11. the current detection transistor is configured as a transistor having a source or an emitter connected to a ground node and a drain or a collector connected to the first node, the detection voltage limiting circuit includes a second power supply node to which the second power supply voltage is supplied; the detection resistor is connected between the second power supply node and the first node; 2. The startup circuit according to claim 1, wherein the startup transistor is connected between the second node and the ground node, and has a control electrode connected to the first node without a drive element, and is composed of a transistor of the same conductivity type as the current detection transistor.

12. 12. The startup circuit according to claim 7, wherein the start-up transistor is configured with a transistor having a threshold voltage equal to or higher than a threshold voltage of the current detection transistor.

13. A startup circuit as described in any one of claims 1 to 4, 7 and 11, wherein the reference value of the reference current is greater than the value of the reference current at a stable operating point where the reference current is smallest among multiple stable operating points of the reference voltage generation circuit, and is smaller than the value of the reference current at a stable operating point where the reference voltage generation circuit normally generates the reference voltage.

14. The startup circuit of any one of claims 1 to 4, 7, and 11, wherein the threshold value of the determination circuit and the resistance value of the detection resistor are determined so that the startup transistor turns on based on a comparison of the detection voltage and the threshold value when the detection current is a leakage current of the current detection transistor.

15. the first power supply voltage is supplied from outside the semiconductor chip to a first power supply terminal of the semiconductor chip on which the reference voltage generating circuit and the startup circuit are mounted; 12. The startup circuit according to claim 1, wherein the second power supply voltage is generated by a local power supply circuit mounted on the semiconductor chip using the first power supply voltage.

16. the reference voltage generating circuit is configured by a bandgap reference circuit including a differential amplifier; 16. The startup circuit according to claim 15, wherein the local power supply circuit includes a current source that generates an operating current for the differential amplifier using the second power supply voltage.

17. The startup circuit according to any one of claims 1 to 4, 7 and 11, wherein the first power supply voltage and the second power supply voltage are supplied from outside the semiconductor chip to a first power supply terminal and a second power supply terminal of the semiconductor chip on which the reference voltage generating circuit and the startup circuit are mounted.

Images