Display device and display panel

Abstract

To provide a display panel and a display device that have a narrow bezel structure.SOLUTION: A display device and a display panel may include: a substrate; a pixel array layer located on the substrate and including a plurality of subpixels disposed in a display area where an image is displayed; and a base circuit layer located between the substrate and the pixel array layer and including a gate driving circuit disposed in the display area.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] TECHNICAL FIELD The embodiments of the present disclosure relate to a display device and a display panel. [Background technology]

[0002] A display device includes a display panel having a plurality of data lines and a plurality of gate lines, a data driving circuit for driving the plurality of data lines, and a gate driving circuit for driving the plurality of gate lines. The display panel includes a display area where an image is displayed and a non-display area where no image is displayed. In conventional display devices, the gate driving circuit is connected to or disposed in the non-display area (also called a bezel) of the display panel. This makes it difficult to reduce the size of the non-display area (bezel) of the display panel. Summary of the Invention [Problem to be solved by the invention]

[0003] According to the present disclosure, it is possible to solve the above-mentioned problems. [Means for solving the problem]

[0004] The embodiments of the present disclosure can provide a display panel and a display device in which gate drive circuits are arranged across the entire display area.

[0005] Embodiments of the present disclosure can provide a display panel and a display device in which the gate drive circuit is arranged to vertically overlap the pixel array layer.

[0006] The embodiments of the present disclosure can provide a display panel and a display device having a structure for shielding an electric field between a base circuit layer in which a gate driving circuit is arranged and a pixel array layer in which sub-pixels are arranged.

[0007] The embodiments of the present disclosure can provide a display panel and a display device having an extremely narrow bezel structure.

[0008] A display device according to an embodiment of the present disclosure may include a substrate, a pixel array layer located on the substrate and including a plurality of sub-pixels arranged in a display area where an image is displayed, and a base circuit layer located between the substrate and the pixel array layer and including a gate drive circuit arranged across the entire display area.

[0009] The base circuit layer may include two or more power supply lines arranged within the display area, to which two or more common pixel driving voltages are applied and which are supplied to the pixel array layer.

[0010] The display device according to the embodiments of the present disclosure may further include a shielding layer located between the base circuit layer and the pixel array layer.

[0011] The shielding layer can be in electrical contact with metal disposed on the pixel array layer.

[0012] As an example, the shielding layer may be electrically connected to a source electrode or a drain electrode of one of a plurality of pixel driving transistors arranged in the pixel array layer, or may be electrically connected to a first driving voltage line arranged in the pixel array layer.

[0013] As another example, the shielding layer may be electrically connected to the common electrode of the pixel electrode and the common electrode included in the light-emitting element arranged in the pixel array layer, or may be electrically connected to the second driving voltage line arranged in the pixel array layer.

[0014] The shielding layer may be electrically connected to metal located in the base circuit layer.

[0015] The base circuit layer may include two or more power supply lines arranged within the display area, to which two or more common pixel driving voltages are applied and which are supplied to the pixel array layer.

[0016] The shielding layer may be electrically connected to one of two or more power lines.

[0017] For example, the shielding layer may be electrically connected to a first power supply line, among the two or more power supply lines, to which a first driving voltage VDD is applied.

[0018] As another example, the shielding layer may be electrically connected to a second power supply line, to which the second driving voltage VSS is applied, among the two or more power supply lines.

[0019] The shielding layer can electrically connect the metal located in the pixel array layer to the metal located in the base circuit layer.

[0020] The base circuit layer includes a gate driving transistor including a first active layer, and the pixel array layer includes a pixel driving transistor including a second active layer, and the first active layer and the second active layer may include different semiconductor materials.

[0021] The base circuit layer may include an organic film disposed on a plurality of gate drive transistors included in the gate drive circuit.

[0022] A display panel according to an embodiment of the present disclosure may include a substrate, a pixel array layer located on the substrate and including a plurality of sub-pixels arranged in a display area where an image is displayed, a base circuit layer located between the substrate and the pixel array layer and on which a gate driving circuit is arranged, and a shielding layer located between the base circuit layer and the pixel array layer.

[0023] The base circuit layer may include an organic film disposed on a gate drive transistor included in the gate drive circuit.

[0024] The base circuit layer may include two or more power supply lines to which two or more common pixel drive voltages are applied that are supplied to the pixel array layer.

[0025] The shielding layer can electrically connect the metal disposed on the pixel array layer to the metal disposed on the base circuit layer. [Effects of the Invention]

[0026] According to the embodiments of the present disclosure, it is possible to provide a display panel and a display device in which gate drive circuits are arranged across the entire display area, thereby significantly reducing the bezel size of the display panel.

[0027] According to an embodiment of the present disclosure, a display panel and a display device can be provided in which a gate driving circuit is arranged to vertically overlap a pixel array layer, thereby significantly reducing the bezel size of the display panel.

[0028] According to an embodiment of the present disclosure, it is possible to provide a display panel and a display device having a structure for shielding an electric field between a base circuit layer where a gate driving circuit is arranged and a pixel array layer where sub-pixels are arranged, thereby preventing the base circuit layer and the pixel array layer from adversely affecting each other electrically.

[0029] According to an embodiment of the present disclosure, a display panel and a display device can be provided in which a gate driving circuit and various power supply wirings are arranged in the display area, which may enable an extremely narrow bezel structure of the display panel.

[0030] According to an embodiment of the present disclosure, the base circuit layer on which the gate driving circuit and various power supply wiring are arranged is arranged to vertically overlap the pixel array layer, thereby shortening the length of the path through which the gate signal output from the gate driving circuit is supplied to the pixel array layer and shortening the length of the path through which the power supply (pixel driving voltage) output from the various power supply wiring is supplied to the pixel array layer, thereby reducing the amount of metal used in the supply path and enabling the display panel and display device to be lighter. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure. [Figure 2] 1 illustrates a display panel according to an embodiment of the present disclosure. [Figure 3] 1 illustrates a stacked structure of a display panel according to an embodiment of the present disclosure. [Figure 4] 1 illustrates another stacked structure of a display panel according to an embodiment of the present disclosure. [Figure 5] 1 illustrates a plurality of unit areas constituting a base circuit layer within a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 6] 1 illustrates a structure of a first unit area among a plurality of unit areas constituting a base circuit layer in a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 7] 1 illustrates an equivalent circuit of a subpixel in a display panel according to an embodiment of the present disclosure. [Figure 8] 10 illustrates an exemplary structure of a first unit area among a plurality of unit areas in a base circuit layer within a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 9] 10 illustrates an exemplary structure of one driving line region in a base circuit layer in a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 10] 10 exemplarily illustrates a first block in two drive line regions in a base circuit layer in a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 11] 1 is a diagram illustrating a vertical correspondence structure between a base circuit layer and a pixel array layer in a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 12] 10 is another diagram illustrating a vertical correspondence structure between a base circuit layer and a pixel array layer in a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 13] 1 is a simplified diagram of a gate drive circuit according to an embodiment of the present disclosure. [Figure 14] 1 is a cross-sectional view of a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 15]1 is another cross-sectional view of a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 16] FIG. 1 is a plan view of a display panel according to an embodiment of the present disclosure. [Figure 17] 1 illustrates a general area and a first type of optical area included in a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 18] 1 illustrates a general area and a second type of optical area included in a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 19] 1 is a cross-sectional view of an optical region within a display region of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0032] Some embodiments of the present disclosure will be described in detail below with reference to the illustrative drawings. When adding reference numerals to components in each drawing, the same reference numerals may be used to the same components as long as they appear in different drawings. When describing the present disclosure, if a detailed description of related publicly known structures or functions is deemed to obscure the gist of the present disclosure, such a detailed description may be omitted. When terms such as "include," "have," and "perform" are used in this specification, other parts may be added unless "only" is used. When a component is expressed as a singular element, the plural may also be included unless otherwise explicitly stated.

[0033] Furthermore, when describing components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. are used to distinguish the components from other components, and the terms do not limit the essence, order, procedure, number, etc. of the components.

[0034] In describing the positional relationship of components, when two or more components are described as being "coupled," "coupled," or "connected," it should be understood that the two or more components may be directly "coupled," "coupled," or "connected," but that the two or more components may also be "coupled," "coupled," or "connected" through an "intervening" component. Here, the other component may be included in one or more of the two or more components that are "coupled," "coupled," or "connected" to each other.

[0035] In describing the temporal sequence of elements, methods of operation, methods of production, etc., when the temporal or chronological sequence is described using, for example, "after," "following," "after," or "before," non-consecutive sequences may also be included, unless "immediately" or "directly" is used.

[0036] On the other hand, when referring to a numerical value or its corresponding information (e.g., level, etc.) for a component, even if there is no explicit statement otherwise, the numerical value or its corresponding information can be interpreted as including an error range that may arise due to various factors (e.g., process factors, internal or external impact, noise, etc.).

[0037] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0038] FIG. 1 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0039] 1, a display device 100 according to an embodiment of the present disclosure may include components for displaying an image, such as a display panel 110 and a display driver circuit. The display driver circuit is a circuit for driving the display panel 110 and may include a data driver circuit 120, a gate driver circuit 130, a display controller 140, etc.

[0040] The display panel 110 may include a display area DA in which an image is displayed.

[0041] The display panel 110 may not have a non-display area located on the periphery of the display area DA, or may only have a very small non-display area. For example, even if the display panel 110 has a non-display area, the boundary area between the display area and the non-display area may be curved, and the non-display area may be located below the display area. In this case, when a user views the display device 100 from the front, there may be little or no non-display area visible to the user.

[0042] The display panel 110 may include a plurality of sub-pixels SP and various types of signal lines for driving the sub-pixels SP.

[0043] The display device 100 according to the embodiment of the present disclosure may be a liquid crystal display device or a self-emitting display device in which the display panel 110 emits light. When the display device 100 according to the embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0044] For example, the display device 100 according to the embodiment of the present disclosure may be an organic light emitting display device in which the light emitting elements are organic light emitting diodes (OLEDs). As another example, the display device 100 according to the embodiment of the present disclosure may be an inorganic light emitting display device in which the light emitting elements are inorganic-based light emitting diodes. As yet another example, the display device 100 according to the embodiment of the present disclosure may be a quantum dot display device in which the light emitting elements are quantum dots, which are semiconductor crystals that emit light themselves.

[0045] The structure of each of the subpixels SP may vary depending on the type of display device 100. For example, if the display device 100 is a self-emitting display device in which the subpixels SP emit light themselves, each subpixel SP may include a light-emitting element that emits light itself, one or more transistors, and one or more capacitors.

[0046] For example, some types of signal lines may include a plurality of data lines DL that transmit data signals (also referred to as data voltages or video signals) and a plurality of gate lines GL that transmit gate signals (also referred to as scan signals).

[0047] For example, the data lines DL and the gate lines GL may intersect with each other. Each of the data lines DL may extend in a first direction, and each of the gate lines GL may extend in a second direction. Here, the first direction may be the column direction, and the second direction may be the row direction. Alternatively, the first direction may be the row direction, and the second direction may be the column direction. For convenience of explanation, the following description will be given assuming that each of the data lines DL is arranged in the column direction, and each of the gate lines GL is arranged in the row direction.

[0048] The data driving circuit 120 is a circuit for driving a plurality of data lines DL, and can output data signals to the plurality of data lines DL.

[0049] The data driving circuit 120 receives digital image data DATA from the display controller 140, converts the received image data DATA into analog data signals, and outputs the analog data signals to a plurality of data lines DL.

[0050] For example, the data driving circuit 120 may be connected to the display panel 110 using a tape automated bonding (TAB) method, connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or implemented using a chip on film (COF) method to be connected to the display panel 110.

[0051] The data driving circuit 120 may be connected to one side (e.g., the top or bottom) of the display panel 110. Alternatively, the data driving circuit 120 may be connected to both sides (e.g., the top and bottom) of the display panel 110, or to two or more of the four sides of the display panel 110, depending on the driving method, panel design, etc.

[0052] The data driving circuit 120 can be connected to the periphery of the display area DA of the display panel 110, or alternatively, can be disposed within the display area DA of the display panel 110.

[0053] The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL, and can output gate signals to the plurality of gate lines GL.

[0054] The gate driving circuit 130 receives various gate driving control signals GCS as well as a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage, generates gate signals, and supplies the generated gate signals to a plurality of gate lines GL.

[0055] In the display device 100 according to the embodiment of the present disclosure, the gate driving circuit 130 may be arranged to overlap the display area DA of the display panel 110. For example, the gate driving circuit 130 may be arranged across the entire display area DA, or may be arranged only on a portion (e.g., both sides) of the display area DA. When the gate driving circuit 130 is arranged to overlap the display area DA, the gate driving circuit 130 may be arranged not to overlap the subpixels SP, or may be arranged to overlap the subpixels SP partially or entirely.

[0056] In the display device 100 according to the embodiment of the present disclosure, the gate driving circuit 130 may be of a gate-in-panel (GIP) type and built into the display panel 110. When the gate driving circuit 130 is of the gate-in-panel type, the gate driving circuit 130 may be formed on the substrate of the display panel 110 during the manufacturing process of the display panel 110.

[0057] The display controller 140 is a device for controlling the data driving circuit 120 and the gate driving circuit 130, and can control the driving timing for the plurality of data lines DL and the driving timing for the plurality of gate lines GL.

[0058] The display controller 140 can provide data drive control signals DCS to the data drive circuit 120 to control the data drive circuit 120, and can provide gate drive control signals GCS to the gate drive circuit 130 to control the gate drive circuit 130.

[0059] The display controller 140 can receive input video data from the host system 150 and provide video data DATA to the data driving circuit 120 based on the input video data.

[0060] The display controller 140 may be implemented as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0061] The display controller 140 may be a timing controller used in conventional display technology, a control device that includes a timing controller and performs other control functions, a control device different from the timing controller, or a circuit within the control device. The display controller 140 may be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0062] The display controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 via the printed circuit board, the flexible printed circuit, or the like.

[0063] The display controller 140 can transmit and receive signals to and from the data driving circuit 120 according to one or more predetermined interfaces. For example, the interfaces may include a Low Voltage Differential Signaling (LVDS) interface, an Embedded Clock Point-Point Interface (EPI) interface, a Serial Peripheral Interface (SPI), etc.

[0064] The display device 100 according to the embodiment of the present disclosure may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or a pen, or to detect the touch position, in order to provide not only an image display function but also a touch sensing function.

[0065] The touch sensing circuit may include a touch driving circuit that drives and senses the touch sensor, generates and outputs touch sensing data, and a touch controller that can sense the occurrence of a touch or detect the touch position using the touch sensing data.

[0066] The touch sensor may include a plurality of touch electrodes, and may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to a touch driving circuit.

[0067] The touch sensor may be present in the form of a touch panel outside the display panel 110, or may be present inside the display panel 110. When the touch sensor is present in the form of a touch panel outside the display panel 110, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel 110 can be fabricated separately and combined during an assembly process. The external type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0068] When the touch sensor is present inside the display panel 110, the touch sensor can be formed on a substrate together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0069] The touch drive circuit can supply a touch drive signal to at least one of the plurality of touch electrodes, and sense the at least one of the plurality of touch electrodes to generate touch sensing data.

[0070] The touch sensing circuit can perform touch sensing using a self-capacitance sensing method or a mutual-capacitance sensing method.

[0071] When the touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self-capacitance sensing method, each of the plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all or some of the plurality of touch electrodes and sense all or some of the plurality of touch electrodes.

[0072] When the touch sensing circuit performs touch sensing using a mutual-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes. According to the mutual-capacitance sensing method, the plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0073] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate devices or as a single device, and the touch driving circuit and the data driving circuit may be implemented as separate devices or as a single device.

[0074] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or the touch sensing circuit.

[0075] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smartphone or a tablet, or may be a monitor or television (TV) of various sizes, but is not limited thereto, and may be a display of various types and sizes capable of displaying information or images.

[0076] The display device 100 according to the embodiment of the present disclosure may further include electronic devices such as a camera (image sensor), a sensing sensor, etc. For example, the sensing sensor may be a sensor that receives light such as infrared light, ultrasonic light, or ultraviolet light and senses an object or a human body.

[0077] FIG. 2 shows a display panel 110 according to an embodiment of the present disclosure.

[0078] 2, the display panel 110 may include a substrate 210 disposed in a plurality of sub-pixels SP, and an encapsulation layer 250 on the substrate 210. Here, the encapsulation layer 250 may be a encapsulation substrate or an encapsulation portion.

[0079] Referring to FIG. 2, when the display device 100 according to the embodiment of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting element ED and a sub-pixel circuit unit SPC for driving the light-emitting element ED.

[0080] Referring to FIG. 2, the sub-pixel circuit unit SPC may include a plurality of pixel driving transistors and at least one capacitor for driving the light emitting element ED.

[0081] The plurality of pixel driving transistors may include a first transistor T1, which is a driving transistor for driving the light emitting element ED, and a second transistor T2 for transferring a data signal VDATA to a second node N2 of the first transistor T1.

[0082] The at least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during the frame.

[0083] To drive the sub-pixels SP, a data signal VDATA, which is a video signal, a scan signal SC, which is a gate signal, etc. may be applied to the sub-pixels SP. In addition, to drive the sub-pixels SP, a common pixel driving voltage including a first driving voltage VDD and a second driving voltage VSS may be applied to the sub-pixels SP.

[0084] The light-emitting element ED may include a pixel electrode PE, an element intermediate layer EL, and a common electrode CE. The pixel electrode PE may be an electrode disposed in each sub-pixel SP, and the common electrode CE may be an electrode commonly disposed in a plurality of sub-pixels SP. The element intermediate layer EL may be a layer disposed between the pixel electrode PE and the common electrode CE, and may include an emission layer (EML).

[0085] When the light-emitting element ED is an organic light-emitting element, the element intermediate layer EL may include an emission layer (EML), a first common layer between the anode and the emission layer, and a second common layer between the emission layer and the cathode. The emission layer may be disposed for each subpixel SP, and the first and second common layers may be disposed in common to multiple subpixels SP. The emission layer may be disposed for each light-emitting region, and the first and second common layers may be disposed in common across multiple light-emitting regions and non-light-emitting regions. Here, the anode may be the pixel electrode PE or the common electrode CE, and the cathode may be the common electrode CE or the pixel electrode PE.

[0086] The first common layer may include a hole injection layer (HIL) and a hole transport layer (HTL), and the second common layer may include an electron transport layer (ETL) and an electron injection layer (EIL). The hole injection layer injects holes from the anode into the hole transport layer, the hole transport layer transports the holes to the light-emitting layer, the electron injection layer injects electrons from the cathode into the electron transport layer, and the electron transport layer transports the electrons to the light-emitting layer.

[0087] For example, the common electrode CE may be electrically connected to a second driving voltage line VSSL. A second driving voltage VSS, which is a type of common pixel driving voltage, may be applied to the common electrode CE via the second driving voltage line VSSL. The pixel electrode PE may be electrically connected to a first node N1 of the first transistor T1 of each subpixel SP.

[0088] For example, the pixel electrode PE may be an anode and the common electrode CE may be a cathode. Conversely, the pixel electrode PE may be a cathode and the common electrode CE may be an anode. For convenience of explanation, it is assumed below that the pixel electrode PE is an anode and the common electrode CE is a cathode.

[0089] Each light-emitting element ED may be configured by overlapping portions of a pixel electrode PE, an element intermediate layer EL, and a common electrode CE. Each light-emitting element ED may form a predetermined light-emitting area. For example, the light-emitting area of ​​each light-emitting element ED may include an area where the pixel electrode PE, the element intermediate layer EL, and the common electrode CE overlap.

[0090] For example, the light emitting element ED may be an organic light emitting diode (OLED), an inorganic-based light emitting diode (LED), or a quantum dot light emitting element, etc. For example, when the light emitting element ED is an organic light emitting diode (OLED), the element intermediate layer EL in the light emitting element ED may include an organic element intermediate layer EL containing an organic material.

[0091] The first transistor T1 may be a driving transistor for supplying a driving current to the light emitting element ED, and may be connected between a first driving voltage line VDDL and the light emitting element ED.

[0092] The first transistor T1 may include a first node N1 electrically connected to the light emitting element ED, a second node N2 to which a data signal VDATA is applied, and a third node N3 to which a driving voltage VDD is applied from a driving voltage line DVL.

[0093] In the first transistor T1, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. For convenience of explanation, the following will take as an example a case in which the second node N2 is a gate node, the first node N1 is a source node, and the third node N3 is a drain node in the first transistor T1.

[0094] The second transistor T2 may be a switching transistor for transmitting a data signal VDATA, which is an image signal, to the second node N2, which is the gate node of the first transistor T1, which is a driving transistor.

[0095] The second transistor T2 is turned on and off by a scan signal SC, which is a gate signal applied via a scan line SCL, which is a type of gate line GL, to control an electrical connection between the second node N2 of the first transistor T1 and the data line DL. A drain electrode or a source electrode of the second transistor T2 may be electrically connected to the data line DL, a source electrode or a drain electrode of the second transistor T2 may be electrically connected to the second node N2 of the first transistor T1, and a gate electrode of the second transistor T2 may be electrically connected to the scan line SCL.

[0096] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the first transistor T1. The storage capacitor Cst may include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the first transistor T1, and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the first transistor T1.

[0097] The storage capacitor Cst may be an external capacitor intentionally designed outside the first transistor T1, rather than a parasitic capacitor (e.g., Cgs, Cgd), which is an internal capacitor that may exist between the first node N1 and the second node N2 of the first transistor T1.

[0098] Each of the first transistor T1 and the second transistor T2 may be an n-type transistor or a p-type transistor.

[0099] At least a portion of the sub-pixel circuit portion SPC may overlap at least a portion of the light emitting element ED in the vertical direction, or alternatively, the sub-pixel circuit portion SPC may not overlap the light emitting element ED in the vertical direction.

[0100] The subpixel circuit unit SPC may have a 2T (Transistor) 1C (Capacitor) structure including two transistors T1 and T2 and one capacitor Cst as shown in FIG. 2, and may further include one or more transistors or one or more capacitors in some cases.

[0101] For example, the sub-pixel circuit unit SPC may have a 6T1C structure including six transistors and one capacitor. As another example, the sub-pixel circuit unit SPC may have a 6T2C structure including six transistors and two capacitors. As yet another example, the sub-pixel circuit unit SPC may have a 7T1C structure including seven transistors and one capacitor.

[0102] The type and number of gate lines for supplying gate signals to the sub-pixels SP may vary depending on the structure of the sub-pixel circuit unit SPC.

[0103] Also, the type and number of common pixel driving voltages supplied to the sub-pixels SP may vary depending on the structure of the sub-pixel circuit unit SPC.

[0104] Since the circuit elements (particularly, the light emitting elements ED implemented as organic light emitting diodes (OLEDs) containing organic materials) in each subpixel SP are vulnerable to external moisture and oxygen, an encapsulation layer 250 for preventing external moisture and oxygen from penetrating into the circuit elements (particularly, the light emitting elements ED) may be disposed in the display panel 110. The encapsulation layer 250 may be configured in various forms to prevent the light emitting elements ED from coming into contact with moisture and oxygen.

[0105] The display device 100 according to the embodiment of the present disclosure may have an extremely narrow bezel structure in which the non-display area of ​​the display panel 110 is very small or almost non-existent. The extremely narrow bezel structure of the display panel 110 of the display device 100 according to the embodiment of the present disclosure will be described below.

[0106] FIG. 3 shows a stacked structure of a display panel 110 according to an embodiment of the present disclosure.

[0107] Referring to FIG. 3, a display panel 110 according to an embodiment of the present disclosure may include a substrate 210 , a base circuit layer 320 , a pixel array layer 340 , and an encapsulation layer 250 .

[0108] 3, the pixel array layer 340 may be a layer in which a plurality of sub-pixels SP are formed and disposed on the substrate 210. The pixel array layer 340 may include a plurality of sub-pixels SP arranged in a display area DA where an image is displayed.

[0109] 3, the base circuit layer 320 is a layer in which the gate driving circuit 130 is formed in a gate-in-panel type, and may be located between the substrate 210 and the pixel array layer 340. The base circuit layer 320 may include the gate driving circuit 130 in a gate-in-panel type.

[0110] For example, the base circuit layer 320 may include a gate driving circuit 130 arranged across the entire display area DA. As another example, the base circuit layer 320 may include a gate driving circuit 130 arranged in at least a partial area of ​​the display area DA. The following description will be given taking as an example a case where the gate driving circuit 130 included in the base circuit layer 320 is arranged across the entire display area DA.

[0111] 3, the base circuit layer 320 may be a layer formed with two or more power supply lines to which two or more common pixel driving voltages are applied, which are supplied to the pixel array layer 340. That is, the base circuit layer 320 may further include two or more power supply lines to which two or more common pixel driving voltages are applied, which are supplied to the pixel array layer 340.

[0112] For example, the two or more common pixel driving voltages may include a first driving voltage VDD and a second driving voltage VSS supplied to the pixel array layer 340. The two or more power supply lines may include a first driving voltage line VDDL and a second driving voltage line VSSL. The two or more power supply lines may be electrically connected to a pattern (metal) in the pixel array layer 340. Alternatively, the two or more power supply lines may include a pattern (metal) in the pixel array layer 340.

[0113] 3, the encapsulation layer 250 may be disposed on the pixel array layer 340. The encapsulation layer 250 may prevent the organic film disposed in the pixel array layer 340 from being exposed to moisture or oxygen.

[0114] As mentioned above, in conventional display devices, the gate drive circuit is connected to or formed in the non-display area (bezel), but in the display device 100 according to an embodiment of the present disclosure, the gate drive circuit 130 is arranged within the display area DA, thereby significantly reducing the size of the non-display area (bezel).

[0115] Furthermore, in conventional display devices, various power supply wirings are arranged in the non-display area (bezel), but in the display device 100 according to an embodiment of the present disclosure, various power supply wirings are arranged within the display area DA, thereby making it possible to further reduce the size of the non-display area (bezel).

[0116] Furthermore, even if the gate drive circuit 130 and / or various power supply wirings are arranged within the display area DA, the space for arranging the multiple subpixels SP is not reduced by arranging them so as to vertically overlap the pixel array layer 340. This allows the size of the non-display area (bezel) to be reduced without reducing the aperture ratio of the display area DA of the display panel 110.

[0117] FIG. 4 shows another stacked structure of a display panel 110 according to an embodiment of the present disclosure.

[0118] Referring to FIG. 4, the display panel 110 according to the embodiment of the present disclosure may further include a shielding layer 430 located between the base circuit layer 320 and the pixel array layer 340 .

[0119] The shielding layer 430 can shield the electric field between the base circuit layer 320 and the pixel array layer 340. This prevents the base circuit layer 320 and the pixel array layer 340 from having an undesirable electrical effect on each other.

[0120] Referring to FIG. 4, in order to improve the shielding performance of the shielding layer 430, the shielding layer 430 can be electrically connected to the power line located in the base circuit layer 320.

[0121] For example, the shielding layer 430 may be electrically connected to a first power line among two or more power lines PL1 to PLm located in the base circuit layer 320. Here, the first power line may be a power line to which a first driving voltage VDD is applied to the pixel array layer 340. Thus, the first power line may be electrically connected to a first driving voltage line VDDL located in the pixel array layer 340.

[0122] As another example, the shielding layer 430 may be electrically connected to a second power line among two or more power lines PL1 to PLm located in the base circuit layer 320. Here, the second power line may be a power line to which a second driving voltage VSS is applied to the pixel array layer 340. In this way, the second power line may be electrically connected to the second driving voltage line VSSL located in the pixel array layer 340.

[0123] Referring to FIG. 4, in order to improve the shielding performance of the shielding layer 430, the shielding layer 430 may be electrically connected to a metal located in the pixel array layer 340.

[0124] For example, the shielding layer 430 may be electrically connected to a first metal located in the pixel array layer 340. Here, the first metal may be a metal to which the first driving voltage VDD is applied. Here, the first metal is a metal to which the first driving voltage VDD is applied, and may be a first driving voltage line VDDL or a connection pattern connected to the first driving voltage line VDDL.

[0125] As another example, the shielding layer 430 may be electrically connected to a second metal located in the pixel array layer 340. Here, the second metal is a metal to which the second driving voltage VSS is applied, and may be a second driving voltage line VSSL or a connection pattern connected to the second driving voltage line VSSL.

[0126] Referring to FIG. 4, the shielding layer 430 can electrically connect the metal located in the pixel array layer 340 and the metal located in the base circuit layer 320 .

[0127] For example, the shielding layer 430 may electrically connect a first metal located in the pixel array layer 340 to a first power supply line located in the base circuit layer 320. Here, the first metal may be a metal to which the first driving voltage VDD is applied. Here, the first metal is a metal to which the first driving voltage VDD is applied, and may be a first driving voltage line VDDL or a connection pattern connected to the first driving voltage line VDDL. The first power supply line may be a power supply line to which the first driving voltage VDD supplied to the pixel array layer 340 is applied.

[0128] In this example, the shielding layer 430 may be electrically connected to the light emitting element ED included in each of the plurality of sub-pixels SP and the source electrode or drain electrode of one of the plurality of pixel driving transistors. Referring to the equivalent circuit of the sub-pixel SP illustrated in FIG. 2, the shielding layer 430 may be electrically connected to the third node N3 of the first transistor T1 among the plurality of pixel driving transistors included in each of the plurality of sub-pixels SP. The third node N3 of the first transistor T1 may be the drain electrode or the source electrode.

[0129] As another example, the shielding layer 430 may electrically connect a second metal located in the pixel array layer 340 to a second power supply line located in the base circuit layer 320. Here, the second metal is a metal to which the second driving voltage VSS is applied, and may be the second driving voltage line VSSL or a connection pattern connected to the second driving voltage line VSSL. The second power supply line may be a power supply line to which the second driving voltage VSS supplied to the pixel array layer 340 is applied.

[0130] In this example, the shielding layer 430 may be electrically connected to the common electrode CE of the light emitting element ED included in each of the plurality of sub-pixels SP.

[0131] Referring to FIG. 4, a display panel 110 according to an embodiment of the present disclosure may include a substrate 210, a pixel array layer 340 positioned on the substrate 210 and having a plurality of sub-pixels SP arranged in a display area DA where an image is displayed, a base circuit layer 320 positioned between the substrate 210 and the pixel array layer 340, and a shielding layer 430 positioned between the base circuit layer 320 and the pixel array layer 340.

[0132] The base circuit layer 320 may include an organic film disposed over the gate drive transistors included in the gate drive circuit 130 .

[0133] The base circuit layer 320 may include two or more power supply lines to which two or more common pixel drive voltages are applied, which are supplied to the pixel array layer 340 .

[0134] The shielding layer 430 can electrically connect the metal disposed on the pixel array layer 340 to the metal (power supply line) disposed on the base circuit layer 320 .

[0135] FIG. 5 shows a plurality of unit areas UA#1 to UA#N (N is a natural number equal to or greater than 2) that constitute the base circuit layer 320 in the display area DA of the display panel 110 according to the embodiment of the present disclosure.

[0136] Referring to FIG. 5, the base circuit layer 320 may be disposed in the display area DA and below the pixel array layer 340 .

[0137] The base circuit layer 320 can include a plurality of unit areas UA#1 to UA#N (N is a natural number of 2 or more).

[0138] The base circuit layer 320 can include a plurality of unit areas UA#1 to UA#N (N is a natural number of 2 or more) arranged across the entire display area DA.

[0139] Each of the multiple unit areas UA#1 to UA#N can have the same structure.

[0140] Below, we will look at the structure of the first unit area UA#1 among the multiple unit areas UA#1 to UA#N. Of the multiple unit areas UA#1 to UA#N, the remaining unit areas UA#2 to UA#N, excluding the first unit area UA#1, can have the same structure as the first unit area UA#1.

[0141] 6 shows the structure of a first unit area UA#1 among the plurality of unit areas UA#1 to UA#N constituting the base circuit layer 320 in the display area DA of the display panel 110 according to an embodiment of the present disclosure. Here, the remaining unit areas UA#2 to UA#N, excluding the first unit area UA#1, among the plurality of unit areas UA#1 to UA#N, may have the same structure as the first unit area UA#1.

[0142] 6, each of the unit areas UA#1 to UA#N may include a plurality of sub-circuit areas GCA1 to GCA5 and a plurality of power line areas PLA. The number of the sub-circuit areas GCA1 to GCA5 included in each of the unit areas UA#1 to UA#N may vary depending on the type (number) of gate signals supplied to the sub-pixels SP.

[0143] Referring to FIG. 6, the plurality of sub-circuit areas GCA1 to GCA5 and the plurality of power supply line areas PLA can be arranged alternately.

[0144] 6, the plurality of power supply line areas PLA may include a plurality of power supply lines PL1 to PLm (m is a natural number equal to or greater than 2) to which a constant voltage is applied. In an embodiment of the present disclosure, two or more of the plurality of power supply lines PL1 to PLm may be supplied with the same voltage (e.g., one of VDD, VSS, VREF, and VAR). In another example of the present disclosure, two or more of the plurality of power supply lines PL1 to PLm may be supplied with different voltages (e.g., two or more of VDD, VSS, VREF, and VAR).

[0145] 6, the plurality of sub-circuit areas GCA1 to GCA5 may include a plurality of sub-circuits GIA1 to GIA5 included in the gate drive circuit 130. The plurality of sub-circuits GIA1 to GIA5 may be configured to output different types of gate signals.

[0146] Referring to FIG. 6, since a plurality of power supply lines PL1 to PLm are similarly arranged in each of the plurality of power supply line areas PLA, the widths of the plurality of power supply line areas PLA may all be the same.

[0147] At least one of the plurality of power supply lines PL1 to PLm included in each of the plurality of power supply line areas PLA may have a width different from the rest.

[0148] Referring to FIG. 6, the plurality of sub-circuits GIA1 to GIA5 are configured to output different types of gate signals, so that at least one of the plurality of sub-circuit areas GCA1 to GCA5 can have a width different from the rest.

[0149] Meanwhile, each of the plurality of subpixels SP arranged in the display panel 110 according to the embodiment of the present disclosure may be configured simply as in the equivalent circuit of Fig. 2, or may be configured more complexly than the equivalent circuit of Fig. 2. Hereinafter, an equivalent circuit of a subpixel SP configured more complexly than the equivalent circuit of Fig. 2 will be described as an example with reference to Fig. 7.

[0150] FIG. 7 shows an equivalent circuit of a subpixel SP in a display panel 110 according to an embodiment of the present disclosure.

[0151] 7, each of the sub-pixels SP arranged in the display panel 110 according to the embodiment of the present disclosure may include a light-emitting element ED, six pixel driving transistors T1 to T6, and two capacitors Cst and Ca. The six pixel driving transistors T1 to T6 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The two capacitors Cst and Ca may include a first capacitor C1 and a second capacitor C2.

[0152] The light emitting element ED may include a pixel electrode PE, an element intermediate layer EL, and a common electrode CE. The pixel electrode PE may correspond to a fourth node N4. The common electrode CE may be connected to a second driving voltage line VSSL. A second driving voltage VSS may be applied to the common electrode CE via the second driving voltage line VSSL.

[0153] The first transistor T1 may correspond to a driving transistor. The first transistor T1 may include a first node N1, a second node N2, and a third node N3. In the first transistor T1, the first node N1 may be a source electrode or a drain electrode, the second node N2 may be a gate electrode, and the third node N3 may be a drain electrode or a source electrode.

[0154] The second transistor T2 is turned on or off by a first scan signal SC1 supplied from a first scan line SCL1, and can control the connection between the second node N2 of the first transistor T1 and the data line DL.

[0155] The second transistor T2 is turned on by the first scan signal SC1 having a turn-on level voltage, and can transmit the data signal VDATA supplied from the data line DL to the second node N2 of the first transistor T1.

[0156] The third transistor T3 is turned on and off by a second scan signal SC2 supplied from a second scan line SCL2, and can control the connection between the second node N2 of the first transistor T1 and the reference voltage line VREFL.

[0157] The third transistor T3 is turned on by the second scan signal SC2 having a turn-on level voltage, and can transmit the reference voltage VREF supplied from the reference voltage line VREFL to the second node N2 of the first transistor T1.

[0158] The fourth transistor T4 is turned on or off by a third scan signal SC3 supplied from a third scan line SCL3, and can control the connection between a fourth node N4 corresponding to the pixel electrode PE of the light emitting element ED and a reset voltage line VARL.

[0159] The fourth transistor T4 is turned on by the third scan signal SC3 having a turn-on level voltage, and can transmit the reset voltage VAR supplied from the reset voltage line VARL to the fourth node N4 corresponding to the pixel electrode PE of the light emitting element ED.

[0160] The fifth transistor T5 is turned on or off by a first light emitting control signal EM1 supplied from a first light emitting control line EML1, and can control the connection between the third node N3 of the first transistor T1 and the first driving voltage line VDDL.

[0161] The fifth transistor T5 is turned on by the first light-emitting control signal EM1 having a turn-on level voltage, and can transmit the first driving voltage VDD supplied from the first driving voltage line VDDL to the third node N3 of the first transistor T1.

[0162] The sixth transistor T6 is turned on or off by a second light-emitting control signal EM2 supplied from a second light-emitting control line EML2, and can control the connection between the first node N1 of the first transistor T1 and a fourth node N4 corresponding to the pixel electrode PE of the light-emitting element ED.

[0163] The sixth transistor T6 is turned on by a second light-emitting control signal EM2 having a turn-on level voltage, and can electrically connect the first node N1 of the first transistor T1 to a fourth node N4 corresponding to the pixel electrode PE of the light-emitting element ED.

[0164] The first capacitor C1 may correspond to the storage capacitor Cst.

[0165] The first capacitor C1 may be connected between the second node N2 of the first transistor T1 and the first node N1 of the first transistor T1, and may include a capacitor electrode corresponding to the second node N2 of the first transistor T1 and a capacitor electrode corresponding to the first node N1 of the first transistor T1.

[0166] The second capacitor C2 may be connected between the first node N1 of the first transistor T1 and the first driving voltage line VDDL, and may include a capacitor electrode corresponding to the first node N1 of the first transistor T1 and a capacitor electrode corresponding to the first driving voltage line VDDL.

[0167] To drive one sub-pixel SP, a data signal VDATA corresponding to a video signal and five gate signals may be supplied to the sub-pixel SP, where the five gate signals may include a first scan signal SC1, a second scan signal SC2, a third scan signal SC3, a first light-emitting control signal EM1, and a second light-emitting control signal EM2.

[0168] In addition, four pixel driving voltages can be supplied to one sub-pixel SP to drive it, where the four pixel driving voltages can include a first driving voltage VDD, a second driving voltage VSS, a reference voltage VREF, and a reset voltage VAR.

[0169] To drive one subpixel SP, the subpixel SP may be connected to a data line DL, five gate lines GL, and four pixel driving voltage lines. The five gate lines GL may include a first scan line SCL1, a second scan line SCL2, a third scan line SCL3, a first light-emitting control line EML1, and a second light-emitting control line EML2. The four pixel driving voltage lines may include a first driving voltage line VDDL, a second driving voltage line VSSL, a reference voltage line VREFL, and a reset voltage line VARL.

[0170] In the following, when the equivalent circuit of the sub-pixel SP is as shown in FIG. 7, the structure of each of the plurality of unit areas UA#1 to UA#N included in the base circuit layer 320 will be viewed through the first unit area UA#1.

[0171] 8 exemplarily illustrates the structure of a first unit area UA#1 among the plurality of unit areas UA#1 to UA#N in the base circuit layer 320 in the display area DA of the display panel 110 according to an embodiment of the present disclosure. Here, the remaining unit areas UA#2 to UA#N, excluding the first unit area UA#1, among the plurality of unit areas UA#1 to UA#N, may have the same structure as the first unit area UA#1.

[0172] Fig. 8 shows the structure of a first unit area UA#1 when the subpixel SP has the structure as shown in Fig. 7. As a result, since there are five types (number) of gate signals supplied to the subpixel SP in Fig. 7, the number of sub-circuit areas GCA1 to GCA5 included in each of the unit areas UA#1 to UA#N may be five.

[0173] Referring to FIG. 8, each of the plurality of unit areas UA#1 to UA#N may include five sub-circuit areas GCA1 to GCA5 and a plurality of power line areas PLA.

[0174] Referring to FIG. 8, the five sub-circuit areas GCA1 to GCA5 and the five power supply line areas PLA can be arranged alternately.

[0175] First to fourth power supply lines PL1 to PL4 may be arranged in each of the five power supply line areas PLA. A constant voltage level may be applied to the first to fourth power supply lines PL1 to PL4.

[0176] For example, the first power supply line PL1 may be a power supply line to which the first drive voltage VDD is applied, the second power supply line PL2 may be a power supply to which the second drive voltage VSS is applied, the third power supply line PL3 may be a power supply line to which the reference voltage VREF is applied, and the fourth power supply line PL4 may be a power supply line to which the reset voltage VAR is applied.

[0177] The first power line PL1 and the second power line PL2 may have the same or substantially the same width, and the third power line PL3 and the fourth power line PL4 may have the same or substantially the same width.

[0178] The first and second power lines PL1 and PL2 may have a width greater than that of the third and fourth power lines PL3 and PL4.

[0179] 8, the five sub-circuit areas GCA1 to GCA5 may each include a first sub-circuit GIA1, a second sub-circuit GIA2, a third sub-circuit GIA3, a fourth sub-circuit GIA4, and a fifth sub-circuit GIA5 included in the gate driving circuit 130. The five sub-circuits GIA1 to GIA5 may be configured to output different types of gate signals.

[0180] For example, the first sub-circuit GIA1 arranged in the first sub-circuit area GCA1 may be a third scan circuit SCC3 that generates and outputs a third scan signal SC3. The second sub-circuit GIA2 arranged in the second sub-circuit area GCA2 may be a first light-emitting control circuit EMC1 that generates and outputs a first light-emitting control signal EM1. The third sub-circuit GIA3 arranged in the third sub-circuit area GCA3 may be a first scan circuit SCC1 that generates and outputs the first scan signal SC1. The fourth sub-circuit GIA4 arranged in the fourth sub-circuit area GCA4 may be a second light-emitting control circuit EMC2 that generates and outputs a second light-emitting control signal EM2. The fifth sub-circuit GIA5 arranged in the fifth sub-circuit area GCA5 may be a second scan circuit SCC2 that generates and outputs a second scan signal SC2.

[0181] The first to third scan signals SC1, SC2, SC3 output from the first to third scan circuits SCC1, SCC2, SCC3 and the first and second light emission control signals EM1, EM2 output from the first and second light emission control circuits EMC1, EMC2 can be supplied to subpixels SP arranged in the pixel array layer 340 on the base circuit layer 320.

[0182] FIG. 9 exemplarily illustrates the structure of one drive line region in the base circuit layer 320 in the display area DA of the display panel 110 according to an embodiment of the present disclosure.

[0183] 9, for example, the display area DA of the display panel 110 may include first to eighth unit areas UA#1 to UA#8. Here, the first to eighth unit areas UA#1 to UA#8 may be areas formed on the base circuit layer 320.

[0184] The display area DA of the display panel 110 may include a plurality of drive line areas DRL, each of which may correspond to one subpixel row (or one subpixel column).

[0185] Each of the plurality of drive line regions DRL can include first to eighth blocks BLK1 to BLK8 corresponding to the first to eighth unit regions UA#1 to UA#8.

[0186] The first to eighth blocks BLK1 to BLK8 may be parts of the first to eighth unit areas UA#1 to UA#8, respectively. That is, the first block BLK1 may be part of the first unit area UA#1, the second block BLK2 may be part of the second unit area UA#2, the third block BLK3 may be part of the third unit area UA#3, the fourth block BLK4 may be part of the fourth unit area UA#4, the fifth block BLK5 may be part of the fifth unit area UA#5, the sixth block BLK6 may be part of the sixth unit area UA#6, the seventh block BLK7 may be part of the seventh unit area UA#7, and the eighth block BLK8 may be part of the eighth unit area UA#8.

[0187] This allows the first to eighth blocks BLK1 to BLK8 to have the same structure.

[0188] 9, the combined widths W_BLK of the first to eighth blocks BLK1 to BLK8 may be equal to the row-direction length W of one drive line region DRL. The column-direction length H of one drive line region DRL may correspond to the column-direction length of one subpixel (or one subpixel row).

[0189] Taking the first block BLK1 of the first to eighth blocks BLK1 to BLK8 as an example, the first block BLK1 can include five sub-circuit areas GCA1 to GCA5 and a plurality of power supply line areas PLA. The five sub-circuit areas GCA1 to GCA5 and the five power supply line areas PLA can be arranged alternately.

[0190] First to fourth power supply lines PL1 to PL4 may be arranged in each of the five power supply line areas PLA. A constant voltage may be applied to the first to fourth power supply lines PL1 to PL4.

[0191] For example, the first power supply line PL1 may be a power supply line to which the first drive voltage VDD is applied, the second power supply line PL2 may be a power supply line to which the second drive voltage VSS is applied, the third power supply line PL3 may be a power supply line to which the reference voltage VREF is applied, and the fourth power supply line PL4 may be a power supply line to which the reset voltage VAR is applied.

[0192] The five sub-circuit areas GCA1 to GCA5 may each include a first sub-circuit GIA1, a second sub-circuit GIA2, a third sub-circuit GIA3, a fourth sub-circuit GIA4, and a fifth sub-circuit GIA5 included in the gate drive circuit 130. The five sub-circuits GIA1 to GIA5 may be configured to output different types of gate signals.

[0193] For example, the first sub-circuit GIA1 arranged in the first sub-circuit area GCA1 may be a third scan circuit SCC3 that generates and outputs a third scan signal SC3. The second sub-circuit GIA2 arranged in the second sub-circuit area GCA2 may be a first light-emitting control circuit EMC1 that generates and outputs a first light-emitting control signal EM1. The third sub-circuit GIA3 arranged in the third sub-circuit area GCA3 may be a first scan circuit SCC1 that generates and outputs the first scan signal SC1. The fourth sub-circuit GIA4 arranged in the fourth sub-circuit area GCA4 may be a second light-emitting control circuit EMC2 that generates and outputs a second light-emitting control signal EM2. The fifth sub-circuit GIA5 arranged in the fifth sub-circuit area GCA5 may be a second scan circuit SCC2 that generates and outputs a second scan signal SC2.

[0194] The first to third scan signals SC1, SC2, SC3 output from the first to third scan circuits SCC1, SCC2, SCC3 and the first and second light emission control signals EM1, EM2 output from the first and second light emission control circuits EMC1, EMC2 can be supplied to the sub-pixels SP arranged in the pixel array layer 340 on the base circuit layer 320.

[0195] For example, the first scan circuit SCC1 may have a width greater than the widths of the second scan circuit SCC2, the third scan circuit SCC3, the first light emission control circuit EMC1, and the second light emission control circuit EMC2.

[0196] FIG. 10 exemplarily illustrates a first block BLK1 in two drive line regions DRL#1 and DRL#2 in the base circuit layer 320 in the display area DA of the display panel 110 according to an embodiment of the present disclosure.

[0197] 10, one third scan circuit SCC3 arranged in the first sub-circuit area GCA1 may be arranged across two first blocks BLK1 included in two drive line areas DRL#1 and DRL#2. One first light emission control circuit EM1C arranged in the second sub-circuit area GCA2 may be arranged across two first blocks BLK1 included in two drive line areas DRL#1 and DRL#2. One second light emission control circuit EMC2 arranged in the fourth sub-circuit area GCA4 may be arranged across two first blocks BLK1 included in two drive line areas DRL#1 and DRL#2. One second scan circuit SCC2 arranged in the fifth sub-circuit area GCA5 may be arranged across two first blocks BLK1 included in two drive line areas DRL#1 and DRL#2.

[0198] 10, one first scan circuit SCC1 arranged in the third sub-circuit area GCA3 may be arranged in one first block BLK1 included in the first drive line area DRL#1, and another first scan circuit SCC1 arranged in the third sub-circuit area GCA3 may be arranged in one first block BLK1 included in the second drive line area DRL#2.

[0199] The detailed structures of the third scan circuit SCC3, first light-emitting control circuit EMC1, second light-emitting control circuit EMC2, and second scan circuit SCC2 shown in Fig. 10 will be described with reference to Fig. 11. Next, the detailed structure of the first scan circuit SCC1 shown in Fig. 10 will be described with reference to Fig. 12.

[0200] FIG. 11 is a diagram illustrating the vertical correspondence between the base circuit layer 320 and the pixel array layer 340 in the display area DA of the display panel 110 according to an embodiment of the present disclosure.

[0201] Referring to FIG. 11, the third scan circuit SCC3, the first light-emitting control circuit EMC1, the second light-emitting control circuit EMC2, and the second scan circuit SCC2 may be disposed on the base circuit layer 320, respectively.

[0202] 11, one third scan circuit SCC3 can be arranged in two drive line regions DRL1 and DRL2 in one unit area. One first light emission control circuit EMC1 can be arranged in two drive line regions DRL1 and DRL2 in one unit area. One second light emission control circuit EMC2 can be arranged in two drive line regions DRL1 and DRL2 in one unit area. One second scan circuit SCC2 can be arranged in two drive line regions DRL1 and DRL2 in one unit area.

[0203] Referring to FIG. 11, the region in which any one of the third scan circuit SCC3, the first light emission control circuit EMC1, the second light emission control circuit EMC2, and the second scan circuit SCC2 is formed may include a clock wiring region in which clock wirings CLKL1 and CLKL2 are arranged, and a gate voltage wiring region in which a first gate voltage wiring VGHL transmitting a first gate voltage VGH and a second gate voltage wiring VGLL transmitting a second gate voltage VGL are arranged.

[0204] 11, the region in which any one of the third scan circuit SCC3, the first light emission control circuit EMC1, the second light emission control circuit EMC2, and the second scan circuit SCC2 is formed may further include a gate-in-panel circuit region in which the first gate-in-panel circuit GIPC1 is disposed. Here, the first gate-in-panel circuit GIPC1 is included in the GIP-type gate driving circuit 130.

[0205] Referring to FIG. 11, the gate-in-panel circuit area can be disposed between the clock wiring area and the gate voltage wiring area.

[0206] In the clock wiring region, a first clock wiring CLKL1 for transmitting a first clock signal CLK1 and a second clock wiring CLKL2 for transmitting a second clock signal CLK2 can be arranged.

[0207] The first gate voltage VGH may be a voltage at a higher level than the second gate voltage VGL. For example, the first gate voltage VGH may correspond to a turn-on level voltage of the first gate signal Vout1, and the second gate voltage VGL may correspond to a turn-off level voltage of the first gate signal Vout1. As another example, the first gate voltage VGH may correspond to a turn-off level voltage of the first gate signal Vout1, and the second gate voltage VGL may correspond to a turn-on level voltage of the first gate signal Vout1.

[0208] The first gate-in-panel circuit GIPC1 can correspond to any one of a substantially third scan circuit SCC3, a substantially first light-emitting control circuit EMC1, a substantially second light-emitting control circuit EMC2, and a substantially second scan circuit SCC2.

[0209] The first gate-in-panel circuit GIPC1 can be arranged across the two drive line regions DRL1 and DRL2, and can generate and output two first gate signals Vout1 via two first output nodes Nout1a and Nout1b corresponding to the two drive line regions DRL1 and DRL2.

[0210] The two first gate signals Vout1 may be one of the third scan signal SC3, the first light-emitting control signal EM1, the second light-emitting control signal EM2, and the second scan signal SC2.

[0211] The two first gate signals Vout1 may be applied to two input nodes Nin1 and Nin2, respectively, arranged in the pixel array layer 340. The two input nodes Nin1 and Nin2 may be nodes present in two subpixels SP1 and SP2 arranged in different subpixel rows.

[0212] The two first gate signals Vout1 output from the two first output nodes Nout1a and Nout1b in the base circuit layer 320 can be input to the two input nodes Nin1 and Nin2 in the pixel array layer 340.

[0213] Referring to FIG. 11, the base circuit layer 320 and the pixel array layer 340 may overlap each other in the vertical direction within the display area DA.

[0214] Referring to FIG. 11, two connection patterns may be present between the base circuit layer 320 and the pixel array layer 340, electrically connecting the two first output nodes Nout1a and Nout1b in the base circuit layer 320 to the two input nodes Nin1 and Nin2 in the pixel array layer 340.

[0215] Referring to FIG. 11, two first gate signals Vout1 output from two first output nodes Nout1a and Nout1b in the base circuit layer 320 can be input to two input nodes Nin1 and Nin2 in the pixel array layer 340 via two connection patterns existing between the base circuit layer 320 and the pixel array layer 340.

[0216] FIG. 12 is another diagram illustrating a vertical correspondence structure between the base circuit layer 320 and the pixel array layer 340 in the display area DA of the display panel 110 according to an embodiment of the present disclosure.

[0217] Referring to FIG. 12, the first scan circuit SCC1 can be disposed on the base circuit layer 320.

[0218] Referring to FIG. 12, one first scan circuit SCC1 can be arranged in each of two drive line regions DRL1 and DRL2 in one unit region.

[0219] Referring to FIG. 12, the region in which the first scan circuit SCC1 is formed may include a clock wiring region in which clock wirings CLKL1 and CLKL2 are arranged, and a gate voltage wiring region in which a first gate voltage wiring VGHL transmitting a first gate voltage VGH and a second gate voltage wiring VGLL transmitting a second gate voltage VGL are arranged.

[0220] 12, the region where the first scan circuit SCC1 is formed may further include a gate-in-panel circuit region where a first gate-in-panel circuit GIPC1 and a second gate-in-panel circuit GIPC2 are arranged, where the second gate-in-panel circuit GIPC2 is included in the GIP-type gate driving circuit 130.

[0221] Referring to FIG. 12, the gate-in-panel circuit area can be disposed between the clock wiring area and the gate voltage wiring area.

[0222] In the clock wiring region, a first clock wiring CLKL1 for transmitting a first clock signal CLK1 and a second clock wiring CLKL2 for transmitting a second clock signal CLK2 can be arranged.

[0223] The first gate voltage VGH may be a voltage at a higher level than the second gate voltage VGL. For example, the first gate voltage VGH may correspond to the turn-on level voltage of the gate signals Vout1 and Vout2, and the second gate voltage VGL may correspond to the turn-off level voltage of the gate signals Vout1 and Vout2. As another example, the first gate voltage VGH may correspond to the turn-off level voltage of the gate signals Vout1 and Vout2, and the second gate voltage VGL may correspond to the turn-on level voltage of the gate signals Vout1 and Vout2.

[0224] Each of the first gate-in-panel circuit GIPC1 and the second gate-in-panel circuit GIPC2 can substantially correspond to the first scan circuit SCC1.

[0225] The first gate-in-panel circuit GIPC1 can be arranged in the first drive line area DRL1, and the second gate-in-panel circuit GIPC2 can be arranged in the second drive line area DRL2.

[0226] The first gate-in-panel circuit GIPC1 can generate and output a first gate signal Vout1 through a first output node Nout1 corresponding to the first drive line region DRL1, and the second gate-in-panel circuit GIPC2 can generate and output a second gate signal Vout2 through a second output node Nout2 corresponding to the second drive line region DRL2.

[0227] The first gate signal Vout1 and the second gate signal Vout2 may be a first scan signal SC1. The first gate signal Vout1 and the second gate signal Vout2 may be applied to two input nodes Nin1 and Nin2, respectively, arranged in the pixel array layer 340. The two input nodes Nin1 and Nin2 may be nodes present in two subpixels SP1 and SP2 arranged in different subpixel rows.

[0228] The first gate signal Vout1 output from the first output node Nout1 in the base circuit layer 320 can be input to the first input node Nin1 in the pixel array layer 340, and the second gate signal Vout2 output from the second output node Nout2 in the base circuit layer 320 can be input to the second input node Nin2 in the pixel array layer 340.

[0229] Referring to FIG. 12, the base circuit layer 320 and the pixel array layer 340 may overlap each other in the vertical direction within the display area DA.

[0230] 12 , a first connection pattern electrically connecting a first output node Nout1 in the base circuit layer 320 to a first input node Nin1 in the pixel array layer 340 may exist between the base circuit layer 320 and the pixel array layer 340. A second connection pattern electrically connecting a second output node Nout2 in the base circuit layer 320 to a second input node Nin2 in the pixel array layer 340 may exist between the base circuit layer 320 and the pixel array layer 340.

[0231] 12, a first gate signal Vout1 output from a first output node Nout1 in the base circuit layer 320 may be input to a first input node Nin1 in the pixel array layer 340 via a first connection pattern existing between the base circuit layer 320 and the pixel array layer 340. A second gate signal Vout2 output from a second output node Nout2 in the base circuit layer 320 may be input to a second input node Nin2 in the pixel array layer 340 via a second connection pattern existing between the base circuit layer 320 and the pixel array layer 340.

[0232] FIG. 13 is a simplified diagram of a gate drive circuit 130 according to an embodiment of the present disclosure.

[0233] As described above, the gate driving circuit 130 according to the embodiment of the present disclosure may include a plurality of sub-circuits GIA1 to GIA5. For example, the plurality of sub-circuits GIA1 to GIA5 may be the first to third scan circuits SCC1, SCC2, and SCC3 and the first and second light emission control circuits EMC1 and EMC2.

[0234] Referring to FIG. 13, each of the plurality of sub-circuits GIA1 to GIA5 may include an output buffer 1310 and a control circuit 1320.

[0235] The output buffer 1310 may include a pull-up transistor Tu connected between a clock node Nclk to which a clock signal CLK is input and an output node Nout to which a gate signal Vout is output, and a pull-down transistor Td connected between the output node Nout to which the gate signal Vout is output and a low-voltage node Nvgl to which a second gate voltage VGL is input.

[0236] The gate signal Vout may be one of the first scan signal SC1, the second scan signal SC2, the third scan signal SC3, the first light-emitting control signal EM1, and the second light-emitting control signal EM2.

[0237] The output node Nout can be electrically connected to any one of the first scan line SCL1, the second scan line SCL2, the third scan line SCL3, the first light-emitting control line EML1, and the second light-emitting control line EML2.

[0238] The gate node of the pull-up transistor Tu may correspond to the Q node. Depending on the voltage level of the Q node, the pull-up transistor Tu may be turned on or off.

[0239] The gate node of the pull-down transistor Td can correspond to the QB node. Depending on the voltage level of the QB node, the pull-down transistor Td can be turned on or off.

[0240] The voltage levels of the Q node and the QB node may be reversed. That is, when the voltage level of the Q node is high, the voltage level of the QB node may be low. When the voltage level of the Q node is low, the voltage level of the QB node may be high.

[0241] Since the voltage levels of the Q node and the QB node are opposite to each other, the on / off states of the pull-up transistor Tu and the pull-down transistor Td may be different from each other. That is, when the pull-up transistor Tu is turned on, the pull-down transistor Td may be turned off. When the pull-up transistor Tu is turned off, the pull-down transistor Td may be turned on.

[0242] The control circuit 1320 receives input of control signals such as a start signal STR and a reset signal RST, and can control the voltage levels of the Q node and the QB node.

[0243] The control circuit 1320 may include multiple transistors.

[0244] When the control circuit 1320 causes the voltage level of the Q node to become high and the voltage level of the QB node to become low, the pull-up transistor Tu is turned on, and a gate signal Vout having the high-level voltage of the clock signal CLK can be output to the output node Nout.

[0245] When the control circuit 1320 causes the voltage level of the Q node to become low and the voltage level of the QB node to become high, the pull-down transistor Td is turned on, and a gate signal Vout having a second gate voltage VGL corresponding to a low-level voltage can be output to the output node Nout.

[0246] The transistors Tu and Td included in the output buffer 1310 and the plurality of transistors included in the control circuit 1320 are called gate drive transistors.

[0247] The vertical structure of the display panel 110 according to the embodiment of the present disclosure described above will be described in more detail below with reference to FIGS.

[0248] FIG. 14 is a cross-sectional view of a display area DA of a display panel 110 according to an embodiment of the present disclosure.

[0249] Referring to FIG. 14, the display area DA of the display panel 110 may include a substrate 210 , a base circuit layer 320 , a shielding layer 430 , a pixel array layer 340 and an encapsulation layer 250 .

[0250] The substrate 210 may include a first substrate 1401, an intermediate layer 1402, and a second substrate 1403. The intermediate layer 1402 may be disposed between the first substrate 1401 and the second substrate 1403. For example, at least one of the first substrate 1401 and the second substrate 1403 may be a substrate containing polyimide (PI).

[0251] A base circuit layer 320 may be located on the substrate 210 .

[0252] The base circuit layer 320 may include a lower shield metal 1405, a plurality of gate driving transistors Tg that constitute the gate driving circuit 130, and various insulating films 1410, 1420, 1421 for forming the plurality of gate driving transistors Tg.

[0253] Each of the plurality of gate driving transistors Tg may include a first active layer ACT1, a first source electrode A, a first drain electrode B, and a first gate electrode C.

[0254] The various insulating films 1410 , 1412 , 1420 , and 1421 may include a first buffer layer 1410 , a first gate insulating film 1420 , and a first interlayer insulating film 1421 .

[0255] A bottom shield metal 1405 may be disposed on the substrate 210 .

[0256] A first buffer layer 1410 may be disposed on the bottom shield metal 1405 .

[0257] The first buffer layer 1410 may include a multi-buffer layer 1411 and an active buffer layer 1412. The multi-buffer layer 1411 may be disposed on the lower shield metal 1405, and the active buffer layer 1412 may be disposed on the multi-buffer layer 1411.

[0258] The first active layer ACT1 may be disposed on the active buffer layer 1412.

[0259] A first gate insulating film 1420 may be disposed on the first active layer ACT1.

[0260] The first gate electrode C is disposed on the first gate insulating film 1420 and can overlap a portion of the first active layer ACT1. The portion of the first active layer ACT1 that overlaps with the first gate electrode C may be a channel region.

[0261] The first interlayer insulating film 1421 can be disposed on the first gate electrode C.

[0262] The first source electrode A and the first drain electrode B may be disposed on the first interlayer insulating film 1421. The first source electrode A may be directly or indirectly connected to a first portion of the first active layer ACT1 through a first hole in the first interlayer insulating film 1421. The first drain electrode B may be directly or indirectly connected to a second portion of the first active layer ACT1 through a second hole in the first interlayer insulating film 1421. A region between the first and second portions of the first active layer ACT1 may be a channel region.

[0263] The transistor included in the gate drive circuit 130 is referred to as a gate drive transistor Tg. The transistors included in the gate drive circuit 130 may include a pull-up transistor Tu and a pull-down transistor Td included in the output buffer 1310, and a plurality of transistors included in the control circuit 1320.

[0264] The base circuit layer 320 may include not only the gate driving circuit 130 but also a plurality of power supply lines PL1 to PLm to which a plurality of pixel driving voltages are applied to the pixel array layer 340. The plurality of power supply lines PL1 to PLm may include a second power supply line PL2 to which a second driving voltage VSS is applied to the pixel array layer 340.

[0265] The base circuit layer 320 may include an organic film 1422 disposed on a plurality of gate drive transistors Tg included in the gate drive circuit 130 .

[0266] The organic film 1422 is disposed on the gate driving transistors Tg and the power supply lines PL1 to PLm included in the gate driving circuit 130, and can reduce steps in the base circuit layer 320.

[0267] Additionally, the organic film 1422 can reduce unwanted parasitic capacitance between metal disposed on the base circuit layer 320 and metal disposed within the base circuit layer 340 .

[0268] The top surface of the organic film 1422 may have a smaller step than the back surface of the organic film 1422 .

[0269] The organic film 1422 may have a thickness T that is thicker than the thickness of the first gate insulating film 1420 between the first gate electrode C and the first active layer ACT1 of each of the plurality of gate driving transistors Tg.

[0270] The shielding layer 430 may be disposed on the base circuit layer 320, and the pixel array layer 340 may be disposed on the shielding layer 430. That is, the shielding layer 430 may be located between the base circuit layer 320 and the pixel array layer 340. This allows for shielding of the electric field between the base circuit layer 320 and the pixel array layer 340.

[0271] The shielding layer 430 may be electrically connected to a second power supply line PL2, which is one of the two or more power supply lines PL1 to PLm, through holes in the organic film 1422. The second power supply line PL2 may be a power supply line to which a second driving voltage VSS is applied.

[0272] The power supply lines PL1 to PLm disposed in the base circuit layer 320 may include the same material as the first source electrode A and the first drain electrode B of the gate driving transistor Tg.

[0273] The pixel array layer 340 may include a plurality of pixel driving transistors Tp, a plurality of storage capacitors Cst, and a plurality of light emitting elements ED.

[0274] The pixel array layer 340 may include a second buffer layer 1430, a second interlayer insulating film 1431, a third interlayer insulating film 1432, a second gate insulating film 1433, a fourth interlayer insulating film 1434, a planarization film 1440, a bank 1450, and a spacer 1451. Here, the planarization film 1440 may include a first planarization film 1441 and a second planarization film 1442.

[0275] Each of the plurality of pixel driving transistors Tp may include a second active layer ACT2, a second source electrode D, a second drain electrode E, and a second gate electrode F.

[0276] Each of the plurality of storage capacitors Cst may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.

[0277] Each of the plurality of light emitting elements ED may include a pixel electrode PE, an element intermediate layer EL, and a common electrode CE.

[0278] A second buffer layer 1430 may be disposed on the shielding layer 430 .

[0279] A first capacitor electrode PLT1 may be arranged on the second buffer layer 1430, a second interlayer insulating film 1431 may be arranged on the first capacitor electrode PLT1, and a second capacitor electrode PLT2 may be arranged on the second interlayer insulating film 1431.

[0280] The first capacitor electrode PLT1 and the second capacitor electrode PLT2 may overlap each other to form a storage capacitor Cst.

[0281] A third interlayer insulating film 1432 can be disposed on the second layer capacitor electrode PLT2.

[0282] The second active layer ACT2 can be disposed on the third interlayer insulating film 1432.

[0283] A second gate insulating film 1433 may be disposed on the second active layer ACT2, and a second gate electrode F may be disposed on the second gate insulating film 1433. The second gate electrode F may overlap a portion of the second active layer ACT2. The region of the second active layer ACT2 that overlaps with the second gate electrode F may be a channel region.

[0284] A fourth interlayer insulating film 1434 may be disposed on the second gate electrode F, and a second source electrode E and a second drain electrode D may be disposed on the fourth interlayer insulating film 1434.

[0285] The second source electrode E can be electrically connected to a first portion of the second active layer ACT2 through a first hole in the fourth interlayer insulating film 1434, and the second drain electrode D can be electrically connected to a second portion of the second active layer ACT2 through a second hole in the fourth interlayer insulating film 1434. A region between the first and second portions of the second active layer ACT2 can be a channel region.

[0286] A planarization film 1440 may be disposed on the second source electrode E and the second drain electrode D. The pixel electrode PE may be disposed on the planarization film 1440 and may be electrically connected to the second source electrode E or the second drain electrode D through a hole in the planarization film 1440.

[0287] When the planarization film 1440 includes a first planarization film 1441 and a second planarization film 1442, the first planarization film 1441 is disposed on the second source electrode E and the second drain electrode D, and the relay electrode RE is disposed on the first planarization film 1441 and can be electrically connected to the second source electrode E or the second drain electrode D through a hole in the first planarization film 1441. The second planarization film 1442 can be disposed on the relay electrode RE. The pixel electrode PE is disposed on the second planarization film 1442 and can be electrically connected to the relay electrode RE through a hole in the second planarization film 1442.

[0288] When the subpixel SP has the structure shown in FIG. 2, the pixel driving transistor Tp shown in FIG. 14 includes a second source electrode E electrically connected to the pixel electrode PE of the light-emitting element ED, and therefore the pixel driving transistor Tp shown in FIG. 14 may be the first transistor T1 in FIG. 2.

[0289] When the subpixel SP has the structure shown in FIG. 7, the pixel driving transistor Tp shown in FIG. 14 includes a second source electrode E electrically connected to the pixel electrode PE of the light-emitting element ED, and therefore the pixel driving transistor Tp shown in FIG. 14 may be the fourth transistor T4 or the sixth transistor T6 in FIG. 7.

[0290] The bank 1450 is disposed on the pixel electrode PE and can have an opening corresponding to the light-emitting area EA.

[0291] The element intermediate layer EL is disposed on the bank 1450 and can contact the pixel electrode PE at the opening of the bank 1450. A spacer 1451 can be located on the bank 1450 at some locations (for example, at locations overlapping with the pixel electrode PE or at the boundaries of the light-emitting area EA).

[0292] A common electrode CE can be disposed on the element intermediate layer EL.

[0293] The region where the pixel electrode PE, the element intermediate layer EL, and the common electrode CE overlap without any insulating layer therebetween can form a light-emitting region EA.

[0294] When the light-emitting element ED is an organic light-emitting element, the device intermediate layer EL can include an emission layer (EML) disposed only in and adjacent to the light-emitting region EA, a first common layer between the anode and the emission layer, and a second common layer between the emission layer and the cathode. Here, the anode can be the pixel electrode PE or the common electrode CE, and the cathode can be the common electrode CE or the pixel electrode PE. The first common layer can include a hole injection layer (HIL) and a hole transport layer (HTL), and the second common layer can include an electron transport layer (ETL) and an electron injection layer (EIL). The hole injection layer can inject holes from the anode into the hole transport layer, the hole transport layer can transport holes to the emission layer, the electron injection layer can inject electrons from the cathode into the electron transport layer, and the electron transport layer can transport electrons to the emission layer. The light-emitting layer of the element intermediate layer EL can be disposed for each sub-pixel SP, and the first and second common layers of the element intermediate layer EL can be disposed in common to a plurality of sub-pixels SP.

[0295] The encapsulation layer 250 may be disposed over the pixel array layer 340 .

[0296] The encapsulation layer 250 may include a first encapsulation layer 1461, a second encapsulation layer 1462, and a third encapsulation layer 1463. For example, the first encapsulation layer 1461 and the third encapsulation layer 1463 may be inorganic films, and the second encapsulation layer 1462 may be an organic film.

[0297] The first metal GA in the base circuit layer 320 and the second metal GB in the pixel array layer 340 can be electrically connected through the opening in the shielding layer 430 .

[0298] In addition, the first metal GA in the base circuit layer 320 and the second metal GB in the pixel array layer 340 can be electrically connected via a connection metal GCP separated from the shielding layer 430. Here, the connection metal GCP can include the same material as the shielding layer 430 and be located in the same layer as the shielding layer 430.

[0299] The second metal GB in the pixel array layer 340 may be disposed on the second gate insulating film 1433. The second metal GB may include the same material as the second gate electrode F and may be located in the same layer.

[0300] The first metal GA in the base circuit layer 320 can be disposed on the first interlayer insulating film 1421 .

[0301] The second metal GB in the pixel array layer 340 can be electrically connected to the first metal GA in the base circuit layer 320 through the second buffer layer 1430, the second interlayer insulating film 1431, the third interlayer insulating film 1432, the second gate insulating film 1433, the shielding layer 43, and holes in the organic film 1422.

[0302] The first metal GA in the base circuit layer 320 may be a metal that electrically corresponds to the output nodes Nout1a, Nout1b, Nout1, and Nout2 in the base circuit layer 320 in FIGS.

[0303] The second metal GB in the pixel array layer 340 may be a metal electrically corresponding to the input nodes Nin1 and Nin2 in the pixel array layer 340 of Figures 11 and 12. For example, the second metal GB in the pixel array layer 340 may be one of the first scan line SCL1, the second scan line SCL2, the third scan line SCL3, the first light-emitting control line EML1, and the second light-emitting control line EML2.

[0304] Referring to FIG. 14, the base circuit layer 320 may include a gate driving transistor Tg including a first active layer ACT1, and the pixel array layer 340 may include a pixel driving transistor Tp including a second active layer ACT2.

[0305] The first active layer ACT1 and the second active layer ACT2 may include different semiconductor materials. For example, the first active layer ACT1 may include a silicon-based semiconductor material, and the second active layer ACT2 may include an oxide-based semiconductor material.

[0306] For example, silicon-based semiconductor materials may include amorphous silicon (a-Si) or LTPS (Low-Temperature Polycrystalline Silicon), among others.

[0307] For example, oxide-based semiconductor materials may include IGZO (Indium gallium zinc oxide), IGZTO (Indium gallium zinc tin oxide), ZnO (Zinc oxide), CdO (Cadmium oxide), InO (Indium oxide), ZTO (Zinc tin oxide), ZITO (Zinc indium tin oxide), etc., and may also include LTPO (Low-Temperature Polycrystalline Oxide).

[0308] The first active layer ACT1 and / or the second active layer ACT2 may be a single layer or a multi-layer. For example, when the first active layer ACT1 and / or the second active layer ACT2 are a multi-layer, the multi-layers may be made of the same semiconductor material or two or more different semiconductor materials.

[0309] Referring to FIG. 14, the encapsulation layer 250 and the common electrode CE may overlap the gate driving circuit 130 .

[0310] 14, the common electrode CE may be an electrode that can transmit light, and the pixel electrode PE may be a reflective electrode and may overlap at least a portion of the gate driving circuit 130. As a result, the display panel 110 may have a top emission structure.

[0311] Referring to FIG. 14, a second driving voltage VSS may be applied to the shielding layer 430 included in the display panel 110 according to the embodiment of the present disclosure.

[0312] Referring to FIG. 14, the shielding layer 430 may be electrically connected to a common electrode CE to which a second driving voltage VSS, which is a type of pixel driving voltage, is applied.

[0313] The common electrode CE and the shielding layer 430 may be electrically connected via a first connection pattern CP1 and a second connection pattern CP2.

[0314] The first connection pattern CP1 may be a metal disposed on the fourth interlayer insulating film 1434. The first connection pattern CP1 can be connected to the shielding layer 430 through holes in the second buffer layer 1430, the second interlayer insulating film 1431, the third interlayer insulating film 1432, the second gate insulating film 1433, and the fourth interlayer insulating film 1434.

[0315] The second connection pattern CP2 may be a metal disposed on the first planarization film 1441. The second connection pattern CP2 can be connected to the first connection pattern CP1 through holes in the first planarization film 1441.

[0316] The first connection pattern CP1 and the second connection pattern CP2 may be electrically connected to second driving voltage lines VSSL disposed on the pixel array layer 340. One or more of the first connection pattern CP1 and the second connection pattern CP2 may be the second driving voltage lines VSSL disposed on the pixel array layer 340.

[0317] The common electrode CE in the pixel array layer 340 and the second power line PL2 in the base circuit layer 320 can be electrically connected via the first and second connection patterns CP1 and CP2 and the shielding layer 430.

[0318] FIG. 15 is another cross-sectional view of the display area DA of the display panel 110 according to an embodiment of the present disclosure.

[0319] The display panel 110 of Figure 15 is similar to the display panel 110 of Figure 14 except for the type of voltage applied to the shielding layer 430. Therefore, the following description will focus on the features that are different from the display panel 110 of Figure 14.

[0320] Referring to FIG. 15, a first driving voltage VDD may be applied to the shielding layer 430 included in the display panel 110 according to the embodiment of the present disclosure.

[0321] 15, the shielding layer 430 may be electrically connected to a third connection pattern CP3 to which a first driving voltage VDD, which is another type of pixel driving voltage, is applied. Here, the third connection pattern CP3 may be a first driving voltage line VDDL for transmitting the first driving voltage VDD or a pattern connected to the first driving voltage line VDDL.

[0322] The third connection pattern CP3 may be a metal disposed on the fourth interlayer insulating film 1434. The third connection pattern CP3 can be connected to the shielding layer 430 through holes in the second buffer layer 1430, the second interlayer insulating film 1431, the third interlayer insulating film 1432, the second gate insulating film 1433, and the fourth interlayer insulating film 1434.

[0323] The third connection pattern CP3 may be electrically connected to the first driving voltage line VDDL disposed in the pixel array layer 340 or may be the first driving voltage line VDDL disposed in the pixel array layer 340.

[0324] Alternatively, the third connection pattern CP3 may be electrically connected to the source electrode or the drain electrode of a pixel driving transistor to which the first driving voltage VDD is applied among the plurality of pixel driving transistors.

[0325] 7, the third connection pattern CP3 may be the drain electrode or the source electrode of the fifth transistor T5 to which the first driving voltage VDD is applied. If the subpixel SP has the structure as shown in FIG. 2, the third connection pattern CP3 may be the drain electrode or the source electrode of the first transistor T5 to which the first driving voltage VDD is applied.

[0326] The shielding layer 430 may be electrically connected to the source or drain electrode of one of the pixel drive transistors.

[0327] 15, a first power line PL1 may be disposed in the base circuit layer 320. The first power line PL1 in the base circuit layer 320 may be electrically connected to the shielding layer 430.

[0328] Referring to FIG. 15, the third connection pattern CP3 in the pixel array layer 340 may be electrically connected to the first power line PL1 in the base circuit layer 320 through the shielding layer 430.

[0329] Among the pixel driving transistors arranged in the pixel array layer 340, the source electrode or drain electrode of the pixel driving transistor to which the first driving voltage VDD is applied may be electrically connected to the shielding layer 430.

[0330] The shielding layer 430 can be electrically connected to the first power line PL1 in the base circuit layer 320.

[0331] Among the pixel driving transistors arranged in the pixel array layer 340, the source electrode or drain electrode of the pixel driving transistor to which the first driving voltage VDD is applied may be electrically connected to the first power line PL1.

[0332] FIG. 16 is a plan view of a display panel 110 according to an embodiment of the present disclosure.

[0333] Referring to FIG. 16, the display area DA of the display panel 110 according to the embodiment of the present disclosure may include a general area NA and a first optical area OA1.

[0334] The display device 100 according to the embodiment of the present disclosure may include a first optical-electronic device 1610 located below the substrate 210 of the display panel 110 .

[0335] The first optical-electronic device 1610 can overlap the first optical area OA1, receive light transmitted through the first optical area OA1 of the display panel 110, and perform a predetermined operation based on the received light.

[0336] The first optical area OA1 may have a highly transmissive structure that allows light to pass from the front surface to the rear surface of the display panel 110.

[0337] Referring to FIG. 16, the display area DA of the display panel 110 according to the embodiment of the present disclosure may further include a second optical area OA2 different from the first optical area OA1.

[0338] The display device 100 according to the embodiment of the present disclosure may further include a second optical-electronic device 1620 located below the substrate 210 of the display panel 110 .

[0339] The second optical-electronic device 1620 can overlap the second optical area OA2, receive light transmitted through the second optical area OA2 of the display panel 110, and perform a predetermined operation based on the received light.

[0340] The second optical area OA2 may have a highly transmissive structure that allows light to pass from the front surface to the rear surface of the display panel 110.

[0341] For example, the first optical electronic device 1610 may be a camera (image sensor), and the second optical electronic device 1620 may be a sensing sensor, which may include a proximity sensor, an infrared sensor, etc.

[0342] For example, the first optical-electronic device 1610 may perform a predetermined operation based on light of a first wavelength, and the second optical-electronic device 1620 may perform a predetermined operation based on light of a second wavelength different from the first wavelength, where the first wavelength may be a visible wavelength and the second wavelength may be an infrared wavelength or an ultraviolet wavelength, etc.

[0343] When the display area DA includes both a first optical area OA1 and a second optical area OA2, the structure of the first optical area OA1 and the structure of the second optical area OA2 may be of the same type (first type or second type), or the structure of one of the first optical area OA1 and the second optical area OA2 may be of the first type and the structure of the other may be of the second type.

[0344] FIG. 17 shows a general area NA and a first type optical area OA included in a display area DA of a display panel 110 according to an embodiment of the present disclosure.

[0345] 17, the display area DA may include a general area NA and an optical area OA. For example, the optical area OA may have various shapes, such as a circular, elliptical, polygonal, or irregular shape.

[0346] 17, a plurality of light-emitting elements ED and a plurality of sub-pixel circuits SPC constituting a plurality of sub-pixels SP may be arranged in the optical area OA. When a plurality of light-emitting elements ED and a plurality of sub-pixel circuits SPC are arranged in the optical area OA in this manner, the structure of the optical area OA is referred to as a first type.

[0347] Referring to FIG. 17, when the structure of the optical area OA is of the first type, the optical area OA may include a plurality of transmissive areas TA and low transmissive areas LTA.

[0348] The plurality of transmission regions TA may be regions with high light transmittance or regions capable of transmitting light. The low transmission region LTA may be regions with low light transmittance or regions that do not allow light to be transmitted. The light transmittance of the plurality of transmission regions TA is higher than that of the low transmission region LTA.

[0349] The plurality of transmission areas TA in the optical area OA having the first type structure can also be called a plurality of holes. The first type is also called a hole type.

[0350] 17, a plurality of sub-pixels SP may be arranged in the optical area OA having the first type structure. That is, a plurality of light-emitting elements ED and a plurality of sub-pixel circuits SPC for driving the light-emitting elements ED may be arranged in the optical area OA having the first type structure.

[0351] 17, a plurality of light-emitting elements ED may be disposed in the low-transmission area LTA within the optical area OA, that is, the low-transmission area LTA within the optical area OA may include a plurality of light-emitting areas EA.

[0352] 17, a plurality of sub-pixel circuits SPC may be disposed in the low-transmission region LTA within the optical region OA. Each of the plurality of sub-pixel circuits SPC may include a plurality of pixel driving transistors and one or more capacitors. Thus, the plurality of pixel driving transistors and the one or more capacitors may be disposed in the low-transmission region LTA within the optical region OA.

[0353] 17, some of the data lines DL arranged in the pixel array layer 340 of the display panel 110 may pass through the optical area OA. Some of the data lines DL passing through the optical area OA may be arranged to avoid some of the transmissive areas TA in the optical area OA. Alternatively, some of the data lines DL passing through the optical area OA may be made of transparent wiring and may pass through some of the transmissive areas TA in the optical area OA.

[0354] 17, some of the gate lines GL arranged in the pixel array layer 340 of the display panel 110 may pass through the optical area OA. Some of the gate lines GL passing through the optical area OA may be arranged to avoid some of the transmissive areas TA in the optical area OA. Alternatively, some of the gate lines GL passing through the optical area OA may be made of transparent wiring and may pass through some of the transmissive areas TA in the optical area OA.

[0355] 17, some of the pixel driving voltage lines VDDL, VSSL, VARL, and VREFL arranged in the pixel array layer 340 of the display panel 110 may pass through the optical area OA. Some of the pixel driving voltage lines VDDL, VSSL, VARL, and VREFL passing through the optical area OA may be arranged to avoid some of the transmissive areas TA in the optical area OA. Alternatively, some of the pixel driving voltage lines VDDL, VSSL, VARL, and VREFL passing through the optical area OA may be made of transparent wiring and may pass through some of the transmissive areas TA in the optical area OA.

[0356] Referring to FIG. 17, the light emitting elements ED and the sub-pixel circuits SPC are not arranged in the transmissive regions TA.

[0357] 17, in the optical area OA, the light transmittance of the low transmission area LTA may be lower than that of the transmission area TA, and may be equal to or higher than that of the general area NA.

[0358] Referring to FIG. 17, the arrangement of the light emitting areas EA in the optical area OA may be the same as the arrangement of the light emitting areas EA in the general area NA.

[0359] The areas of the light-emitting areas EA included in the optical area OA may be the same as or different from the areas of the light-emitting areas EA included in the general area NA within a predetermined range.

[0360] The areas of the plurality of light-emitting areas EA included in the optical area OA may be the same as each other or may differ within a predetermined range.

[0361] The common electrode CE can be disposed in common in the general area NA and the optical area OA.

[0362] Optionally, a portion of the common electrode CE disposed in the optical area OA may have a plurality of holes CH. The plurality of holes CH formed in the common electrode CE may correspond in position to the transmission areas TA in the optical area OA.

[0363] Alternatively, a portion of the common electrode CE disposed in the optical area OA may not have the hole CH.

[0364] Since the optical area OA includes a plurality of transmission areas TA, the optical area OA can have a light transmittance higher than that of the general area NA.

[0365] For example, the multiple light-emitting areas EA arranged in the optical area OA may include a first hue light-emitting area that emits light of a first hue, a second hue light-emitting area that emits light of a second hue, and a third hue light-emitting area that emits light of a third hue.

[0366] At least one of the first hue light-emitting region, the second hue light-emitting region, and the third hue light-emitting region can have a different area than the rest.

[0367] The first, second, and third hues may be different from one another and may include various hues, for example, red, green, and blue.

[0368] For example, the first color is red, the second color is green, and the third color is blue, but the present invention is not limited thereto.

[0369] When the first hue is red, the second hue is green, and the third hue is blue, the area of ​​the blue light-emitting region EA_B may be the largest among the areas of the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B.

[0370] The light emitting element ED disposed in the red light emitting region EA_R may include a light emitting layer that emits red light, the light emitting element ED disposed in the green light emitting region EA_G may include a light emitting layer that emits green light, and the light emitting element ED disposed in the blue light emitting region EA_B may include a light emitting layer that emits blue light.

[0371] Among the light emitting layers emitting red light, green light, and blue light, the organic material contained in the light emitting layer emitting blue light may be most susceptible to deterioration in terms of material.

[0372] Since the blue light-emitting region EA_B is designed to have the largest area, the current density supplied to the light-emitting element ED arranged in the blue light-emitting region EA_B may be the smallest. Therefore, the degree of deterioration of the light-emitting element ED arranged in the blue light-emitting region EA_B can be classified into the degree of deterioration of the light-emitting element ED arranged in the red light-emitting region EA_R and the degree of deterioration of the light-emitting element ED arranged in the green light-emitting region EA_G.

[0373] Therefore, the variation in deterioration among the light-emitting elements ED arranged in the red light-emitting region EA_R, the light-emitting elements ED arranged in the green light-emitting region EA_G, and the light-emitting elements ED arranged in the blue light-emitting region EA_B is eliminated or reduced, thereby improving image quality. Furthermore, the variation in deterioration among the light-emitting elements ED arranged in the red light-emitting region EA_R, the light-emitting elements ED arranged in the green light-emitting region EA_G, and the light-emitting elements ED arranged in the blue light-emitting region EA_B is eliminated or reduced, which may have the effect of reducing the variation in lifespan among the light-emitting elements ED arranged in the red light-emitting region EA_R, the light-emitting elements ED arranged in the green light-emitting region EA_G, and the light-emitting elements ED arranged in the blue light-emitting region EA_B.

[0374] FIG. 18 shows a general area NA and a second type optical area OA included in a display area DA of a display panel 110 according to an embodiment of the present disclosure.

[0375] Referring to FIG. 18, the display area DA can include an optical area OA and a surrounding general area NA.

[0376] 18, among the plurality of light-emitting elements ED and the plurality of sub-pixel circuits SPC constituting the plurality of sub-pixels SP, only a plurality of light-emitting elements ED may be arranged in the optical area OA, and the plurality of sub-pixel circuits SPC may not be arranged in the optical area OA. In this way, when only a plurality of light-emitting elements ED among the plurality of light-emitting elements ED and the plurality of sub-pixel circuits SPC are arranged in the optical area OA, the structure of the optical area OA is referred to as a second type.

[0377] 18, when the optical area OA has the second type structure, an optical bezel area OBA can be disposed around the optical area OA. The optical bezel area OBA can also be considered as part of the general area NA.

[0378] When the optical area OA is of the second type, the display area DA can include the optical area OA, a general area NA located on the outer periphery of the optical area OA, and an optical bezel area OBA which is the area between the optical area OA and the general area NA.

[0379] The optical area OA can include multiple light-emitting areas EA and at least one transmissive area TA. The entire area of ​​the optical area OA, excluding the multiple light-emitting areas EA, can be transmissive areas TA. Alternatively, the entire area of ​​the optical area OA, excluding the multiple light-emitting areas EA, can include multiple transmissive areas TA.

[0380] A plurality of light-emitting elements ED can be arranged in the optical area OA having the second type structure, and a plurality of sub-pixel circuits SPC for driving the plurality of light-emitting elements ED arranged in the optical area OA having the second type structure are not arranged in the optical area OA.

[0381] A plurality of sub-pixel circuits SPC for driving a plurality of light-emitting elements ED arranged in the optical area OA having the second type structure can be arranged in the optical bezel area OBA.

[0382] A plurality of light-emitting elements ED and a plurality of sub-pixel circuits SPC for driving them are arranged in the optical bezel area OBA, and a plurality of sub-pixel circuits SPC for driving a plurality of light-emitting elements ED arranged in the optical area OA having a second type structure may also be arranged.

[0383] On the other hand, one subpixel circuit SPC arranged in the optical bezel area OBA can drive one light-emitting element ED arranged in the optical area OA, whereas one subpixel circuit SPC arranged in the optical bezel area OBA can drive two or more light-emitting elements ED arranged in the optical area OA.

[0384] As described above, when the optical area OA has the second type structure, the light-emitting element ED arranged in the optical area OA must be driven by the sub-pixel circuit SPC arranged in the optical bezel area OBA. For this reason, when the optical area OA has the second type structure, the anode for configuring the light-emitting element ED arranged in the optical area OA must extend into the optical bezel area OBA and be electrically connected to the sub-pixel circuit SPC arranged in the optical bezel area OBA. In this sense, the second type can also be called an anode extension type.

[0385] 18, the optical bezel area OBA may be an area located outside the optical area OA. The general area NA may be an area located outside the optical bezel area OBA. The optical bezel area OBA may be disposed between the optical area OA and the general area NA.

[0386] For example, the optical bezel area OBA may be arranged only on the outer periphery of a portion of the optical area OA, or may be arranged on the outer periphery of the entire optical area OA.

[0387] When the optical bezel area OBA is disposed on the outer periphery of the entire edge of the optical area OA, the optical bezel area OBA may have a ring shape surrounding the optical area OA. For example, the optical area OA may have various shapes such as a circular, elliptical, polygonal, or irregular shape. The optical bezel area OBA may have various ring shapes (e.g., a circular ring shape, an elliptical ring shape, a polygonal ring shape, or an irregular ring shape) surrounding the optical area OA having various shapes.

[0388] 18, the display area DA may include a plurality of light-emitting areas EA. Since the optical area OA, the optical bezel area OBA, and the general area NA are areas included in the display area DA, each of the optical area OA, the optical bezel area OBA, and the general area NA may include a plurality of light-emitting areas EA.

[0389] 18, the optical region OA is a transmissive region and should have high transmittance. To this end, the portion of the common electrode CE located in the optical region OA may have a plurality of holes CH. That is, in the optical region OA, the common electrode CE may include a plurality of cathode holes CH.

[0390] 18, the portion of the common electrode CE arranged in the general region NA does not have a hole CH, that is, the common electrode CE does not include a hole CH in the general region NA.

[0391] Furthermore, the portion of the common electrode CE arranged in the optical bezel area OBA does not include the hole CH. That is, in the optical bezel area OBA, the common electrode CE does not include the hole CH.

[0392] The holes CH formed in the portion of the common electrode CE located in the optical area OA can be replaced by a plurality of transmissive areas TA or a plurality of openings. A hole CH can have various shapes, such as a circle, an ellipse, a polygon, or an irregular shape.

[0393] The optical area OA in FIGS. 17 and 18 may be one of the first optical area OA1 and the second optical area OA2 in FIG.

[0394] 17 and 18, the optical region OA overlaps with the optical-electronic device and may be a transmissive region through which light necessary for the operation of the optical-electronic device can pass. Here, the light passing through the optical region OA may include light of a single wavelength band or light of various wavelength bands. For example, the light passing through the optical region OA may include one or more of visible light, infrared light, ultraviolet light, etc.

[0395] The optical-electronic device can receive light transmitted through the optical area OA and perform a predetermined operation using the received light, where the light received by the optical-electronic device through the optical area OA can include at least one of visible light, infrared light, and ultraviolet light.

[0396] For example, if the optical electronic device is a camera, the light transmitted through the optical region OA and utilized in the optical electronic device may include visible light. As another example, if the optical electronic device is an infrared-based sensor, the light transmitted through the optical region OA and utilized in the optical electronic device may include infrared light (also referred to as infrared light).

[0397] 19 is a cross-sectional view of an optical area OA in a display area DA of a display panel 110 according to an embodiment of the present disclosure, except that the structure of the optical area OA in FIG. 19 is of a first type.

[0398] The display panel 110 in Figure 19 has the same or substantially the same vertical structure as the display panel 110 in Figure 14. Therefore, the following description will focus on features that differ from the display panel 110 in Figure 14.

[0399] The cross section of FIG. 14 can also be considered to show the vertical structure of the general area NA, and the cross section of FIG. 19 to show the vertical structure of the optical area OA.

[0400] Referring to FIG. 19, the optical area OA included in the display area DA may include at least one transmissive area TA and a low transmissive area LTA.

[0401] A plurality of sub-pixels SP may be arranged in the optical area OA. That is, a light emitting element ED and a pixel driving transistor Tp included in a sub-pixel circuit SPC for driving the light emitting element ED may be arranged in the optical area OA.

[0402] The light-emitting element ED can be disposed in the low-transmission area LTA in the optical area OA, that is, the low-transmission area LTA in the optical area OA can include the light-emitting area EA.

[0403] The pixel driving transistor Tp included in the sub-pixel circuit SPC can be disposed in the low-transmittance area LTA in the optical area OA.

[0404] Referring to FIG. 19, the gate driving circuit 130 is arranged over the entire display area DA, but can be arranged so as not to overlap at least one transmission area TA in the optical area OA.

[0405] In other words, the gate drive circuit 130 is arranged in an area that is not the at least one transmissive area TA, and the gate drive circuit 130 is not arranged in the at least one transmissive area TA, which can increase the light transmittance of the at least one transmissive area TA in the optical area OA.

[0406] 19, the shielding layer 430 can be arranged so as not to overlap with at least one transmission region TA. In other words, the shielding layer 430 is arranged in an area that is not the at least one transmission region TA, and the shielding layer 430 is not arranged in the at least one transmission region TA.

[0407] The portion of the shielding layer 430 arranged in the optical region OA may include at least one opening. The at least one opening formed in the shielding layer 430 in the optical region OA may positionally correspond to at least one transmission region TA in the optical region OA. This may increase the light transmittance of the at least one transmission region TA in the optical region OA.

[0408] The above-described embodiment of the present disclosure can be briefly described as follows.

[0409] A display device according to an embodiment of the present disclosure may include a substrate, a pixel array layer located on the substrate and including a plurality of sub-pixels arranged in a display area where an image is displayed, and a base circuit layer located between the substrate and the pixel array layer and including a gate drive circuit arranged across the entire display area.

[0410] The base circuit layer may include two or more power supply lines arranged within the display area, to which two or more common pixel driving voltages are applied and which are supplied to the pixel array layer.

[0411] The display device according to the embodiments of the present disclosure may further include a shielding layer located between the base circuit layer and the pixel array layer.

[0412] The shielding layer can be in electrical contact with metal disposed on the pixel array layer.

[0413] For example, the shielding layer may be electrically connected to a source electrode or a drain electrode of one of the pixel driving transistors arranged in the pixel array layer, or to a first driving voltage line arranged in the pixel array layer, where a first driving voltage VDD may be applied to the source electrode or the drain electrode of the one pixel driving transistor, and a first driving voltage VDD, which is another type of pixel driving voltage, may be applied to the first driving voltage line.

[0414] As another example, the shielding layer may be electrically connected to a common electrode of a pixel electrode and a common electrode included in a light emitting element disposed in the pixel array layer, or to a second driving voltage line disposed in the pixel array layer, where a second driving voltage VSS, which is a type of pixel driving voltage, may be applied to the common electrode or the second driving voltage line.

[0415] The shielding layer may be electrically connected to metal located in the base circuit layer.

[0416] The base circuit layer may include two or more power supply lines arranged within the display area, to which two or more common pixel driving voltages are applied and which are supplied to the pixel array layer.

[0417] The shielding layer may be electrically connected to one of two or more power lines.

[0418] For example, the shielding layer may be electrically connected to a first power supply line, among the two or more power supply lines, to which a first driving voltage VDD is applied.

[0419] As another example, the shielding layer may be electrically connected to a second power supply line, to which the second driving voltage VSS is applied, among the two or more power supply lines.

[0420] The shielding layer can electrically connect the metal located in the pixel array layer to the metal located in the base circuit layer.

[0421] The base circuit layer includes a gate driving transistor including a first active layer, and the pixel array layer includes a pixel driving transistor including a second active layer, and the first active layer and the second active layer may include different semiconductor materials.

[0422] The base circuit layer may include a plurality of unit areas arranged across the entire display area.

[0423] Each of the plurality of unit areas may include a plurality of sub-circuit areas and a plurality of power supply line areas, and the plurality of sub-circuit areas and the plurality of power supply line areas may be arranged alternately.

[0424] The multiple power supply line regions may include multiple power supply lines to which a constant voltage level is applied.

[0425] The plurality of sub-circuit regions may include a plurality of sub-circuits included in the gate drive circuit, and the plurality of sub-circuits may be configured to output different types of gate signals.

[0426] The widths of the plurality of power supply line regions are all the same, and at least one of the plurality of power supply lines included in each of the plurality of power supply line regions may have a width different from the others, and at least one of the plurality of sub-circuit regions may have a width different from the others.

[0427] The base circuit layer may include an organic film disposed on a plurality of gate drive transistors included in the gate drive circuit.

[0428] The top surface of the organic film may have a step that is smaller than the back surface of the organic film, and the organic film may have a thickness that is thicker than the gate insulating film between the gate electrode and the active layer of each of the plurality of gate driving transistors.

[0429] The display device according to the embodiments of the present disclosure may further include an encapsulation layer positioned on the pixel array layer.

[0430] The pixel array layer may include a plurality of light emitting elements and a plurality of pixel driving transistors, and each of the plurality of light emitting elements may include a pixel electrode and a common electrode.

[0431] The encapsulation layer and the common electrode may overlap the gate drive circuit, and the pixel electrode may be a reflective electrode and may overlap at least a portion of the gate drive circuit.

[0432] The display area can include a general area and an optical area, where the general area can include a plurality of light-emitting areas and the optical area can include at least one transmissive area.

[0433] The gate drive circuitry can be arranged across the display area and not overlap with at least one transmissive region in the optical area.

[0434] A shielding layer located between the base circuit layer and the pixel array layer can be positioned so as not to overlap the at least one transparent region.

[0435] A display device according to embodiments of the present disclosure may further include an optoelectronic device located below the substrate and overlapping the optical region.

[0436] A display panel according to an embodiment of the present disclosure may include a substrate, a pixel array layer located on the substrate and including a plurality of sub-pixels arranged in a display area where an image is displayed, a base circuit layer located between the substrate and the pixel array layer and on which a gate driving circuit is arranged, and a shielding layer located between the base circuit layer and the pixel array layer.

[0437] The base circuit layer may include an organic film disposed on a gate drive transistor included in the gate drive circuit.

[0438] The base circuit layer may include two or more power supply lines to which two or more common pixel drive voltages are applied that are supplied to the pixel array layer.

[0439] The shielding layer can electrically connect the metal disposed on the pixel array layer to the metal disposed on the base circuit layer.

[0440] A display device according to an embodiment of the present disclosure may include a substrate, a pixel array layer disposed on the substrate and including a plurality of sub-pixels arranged in a display area where an image is displayed, and a base circuit layer disposed between the substrate and the pixel array layer and including a driving circuit. The plurality of sub-pixels may include pixel driving transistors. The driving circuit may include a transistor. One or more of the transistors in the base circuit layer may be respectively connected to one or more of the pixel driving transistors in the pixel array layer.

[0441] The base circuit layer may include one or more power supply lines connecting to at least one of the plurality of subpixels. The drive circuit of the base circuit layer may include a gate drive transistor.

[0442] In embodiments of the present disclosure, the display device can include or be a display device. In embodiments of the present disclosure, the display device can include or be a display panel. In one or more examples, the display device can include or be a device having electronic and optical components.

[0443] According to the above-described embodiments of the present disclosure, it is possible to provide a display panel and a display device in which gate drive circuits are arranged across the entire display area, thereby significantly reducing the bezel size of the display panel.

[0444] According to an embodiment of the present disclosure, a display panel and a display device can be provided in which a gate driving circuit is arranged to vertically overlap a pixel array layer, thereby significantly reducing the bezel size of the display panel.

[0445] According to an embodiment of the present disclosure, it is possible to provide a display panel and a display device having a structure for shielding an electric field between a base circuit layer where a gate driving circuit is arranged and a pixel array layer where sub-pixels are arranged, thereby preventing the base circuit layer and the pixel array layer from adversely affecting each other electrically.

[0446] According to an embodiment of the present disclosure, a display panel and a display device can be provided in which a gate driving circuit and various power supply wirings are arranged in the display area, thereby enabling an extremely narrow bezel structure of the display panel.

[0447] According to an embodiment of the present disclosure, the base circuit layer on which the gate driving circuit and various power supply wiring are arranged is arranged to vertically overlap the pixel array layer, thereby shortening the length of the path through which the gate signal output from the gate driving circuit is supplied to the pixel array layer and shortening the length of the path through which the power supply (pixel driving voltage) output from the various power supply wiring is supplied to the pixel array layer, thereby reducing the amount of metal used in the supply path and enabling the display panel and display device to be lighter.

[0448] The above description merely exemplifies the technical idea of ​​the present disclosure, and various modifications and variations are possible by a person having ordinary skill in the art to which the present disclosure pertains without departing from the essential characteristics of the present disclosure. Furthermore, the examples disclosed in the present disclosure are intended to illustrate, rather than limit, the technical idea of ​​the present disclosure, and the scope of the technical idea of ​​the present disclosure is not limited by such embodiments. [Explanation of symbols]

[0449] 210 Substrate 250 sealing layer 320 Base Circuit Layer SPC Subpixel Circuit

Claims

1. A substrate; a pixel array layer located on the substrate and including a plurality of sub-pixels arranged in a display area where an image is to be displayed; a base circuitry layer located between the substrate and the pixel array layer, the base circuitry layer including gate drive circuitry distributed across the display area; a shielding layer located between the base circuit layer and the pixel array layer; the display area includes a general area and an optical area; the general area includes a plurality of light emitting areas; the optical region includes at least one transmissive region; The display device, wherein the shielding layer is positioned so as not to overlap the at least one transmissive region.

2. The display device according to claim 1 , wherein the base circuit layer includes two or more power supply lines arranged within the display area and to which two or more common pixel driving voltages are applied to the pixel array layer.

3. The display device according to claim 1 , wherein the shielding layer is electrically connected to a metal disposed on the pixel array layer.

4. 2. The display device of claim 1, wherein the shielding layer is electrically connected to a source electrode or a drain electrode of one of a plurality of pixel driving transistors arranged on the pixel array layer, or is electrically connected to a first driving voltage line arranged on the pixel array layer.

5. Each of the plurality of sub-pixels includes a light-emitting element including a pixel electrode and a common electrode; 2. The display device of claim 1, wherein the shielding layer is electrically connected to the common electrode of a pixel electrode and a common electrode included in a light-emitting element arranged on the pixel array layer, or is electrically connected to a second driving voltage line arranged on the pixel array layer.

6. The display device according to claim 1 , wherein the shielding layer is electrically connected to a metal located in the base circuit layer.

7. the base circuit layer includes two or more power supply lines, to which two or more common pixel driving voltages are applied and which are supplied to the pixel array layer, and which are arranged within the display area; The display device according to claim 1 , wherein the shielding layer is electrically connected to one of the two or more power supply lines.

8. The display device according to claim 1 , wherein the shielding layer electrically connects a metal located in the pixel array layer to a metal located in the base circuit layer.

9. 2. The display device of claim 1, wherein the base circuit layer includes a gate driving transistor including a first active layer, and the pixel array layer includes a pixel driving transistor including a second active layer, the first active layer and the second active layer including different semiconductor materials.

10. the base circuit layer includes a plurality of unit areas arranged across the entire display area; each of the plurality of unit areas includes a plurality of sub-circuit areas and a plurality of power supply line areas, the plurality of sub-circuit areas and the plurality of power supply line areas being alternately arranged; the plurality of power supply line regions include a plurality of power supply lines to which a voltage of a certain voltage level is applied, The display device according to claim 1 , wherein the plurality of sub-circuit regions include a plurality of sub-circuits included in the gate drive circuit, and the plurality of sub-circuits are configured to output different types of gate signals from each other.

11. The display device of claim 1 , wherein the base circuit layer comprises an organic film disposed on a plurality of driving transistors included in the gate driving circuit.

12. 2. The display device according to claim 1, wherein the gate drive circuit is arranged across the entire display area so as not to overlap the at least one transmissive area in the optical area.

13. The display device of claim 1 , wherein the base circuit layer includes an organic film disposed on a gate driving transistor included in the gate driving circuit.

14. The display device according to claim 1 , wherein the base circuit layer includes two or more power supply lines to which two or more common pixel driving voltages are applied, the power supply lines being supplied to the pixel array layer.

15. The display device of claim 14 , wherein the shielding layer electrically connects metal located in the pixel array layer and metal located in the base circuit layer.

16. A substrate; a pixel array layer located on the substrate and including a plurality of sub-pixels arranged in a display area where an image is to be displayed; a base circuit layer located between the substrate and the pixel array layer, on which gate drive circuits are disposed; a shielding layer located between the base circuit layer and the pixel array layer; the display area includes a general area and an optical area; the general area includes a plurality of light emitting areas; the optical region includes at least one transmissive region; the base circuit layer includes a plurality of pixel drive transistors; the pixel array layer includes a plurality of transistors; each of the plurality of pixel driving transistors includes a first active layer; Each of the plurality of transistors includes a second active layer different from the first active layer.

17. The display panel of claim 16, wherein the first active layer and the second active layer include different semiconductor materials.

18. 17. The display panel of claim 16, wherein one or more of the plurality of transistors in the base circuit layer are electrically connected to one or more pixel driving transistors in the plurality of pixel driving transistors in the pixel array layer, respectively.

19. 17. The display panel of claim 16, wherein the base circuit layer includes two or more power supply lines to which two or more common pixel driving voltages are applied to the pixel array layer.

Images