Ceramic electronic component and manufacturing method thereof

Abstract

To provide a ceramic electronic component and a manufacturing method thereof that improves reliability.SOLUTION: A ceramic electronic component includes a laminate including a plurality of dielectric layers 11 containing Ba and Ti and a plurality of internal electrode layers 12 containing Ni and Sn and stacked alternately with the plurality of dielectric layers in the stacking direction. In a cross section of the laminate including the stacking direction, at least one of the plurality of internal electrode layers is configured to be discontinued at a discontinuous portion 17. This one internal electrode layer has, on a surface exposed to the discontinuous portion, a high Sn concentration portion in which the Sn concentration is higher than the average Sn concentration of the one internal electrode layer. The discontinuous portion includes a dielectric region containing a dielectric material, and this dielectric region contains Sn.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] In recent years, there has been an increasing demand for ceramic electronic components such as high-end multilayer ceramic capacitors with high capacity and high reliability in in-vehicle and mobile terminals (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2015 / 016309 [Non-patent literature]

[0004] [Non-Patent Document 1] Samantaray, Malay M., et al Journal of the American Ceramic Society 95 1 (2012):264-268 [Non-patent document 2] Hiroshi Kishi et al 2003 Jpn. J. Appl. Phys. 42 1 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, ceramic electronic components have been made thinner in the internal electrode layers and dielectric layers to achieve small size and high capacitance. While this has enabled the achievement of high capacitance, it has also led to problems such as a decrease in insulation resistance due to discontinuities in the internal electrode layers (see, for example, Non-Patent Document 1) and a decrease in the insulating properties of the dielectric layers. To address this issue, methods have been used, such as dissolving different elements in the dielectric material to improve the insulating properties of the dielectric layers (see, for example, Non-Patent Document 2).

[0006] However, the above technology does not solve the problem of deterioration in reliability caused by discontinuities in the internal electrode layers. Also, in general, when allocating insulation resistance, the interfacial resistance component between the internal electrode layer and the dielectric layer is larger than the grain boundary resistance component and intragranular resistance component of the dielectric layer, so when the dielectric layer is made thinner, the grain boundary and intragranular resistance components become smaller, and the above technology seems insufficient.

[0007] The present invention has been made in view of the above-mentioned problems, and has an object to improve the reliability of ceramic electronic components. [Means for solving the problem]

[0008] The ceramic electronic component according to the present invention comprises a laminated structure in which a plurality of dielectric layers containing Ba and Ti and a plurality of internal electrode layers containing Ni and Sn are alternately laminated, and at least one of the plurality of internal electrode layers has a discontinuous portion that is interrupted in a cross section including the stacking direction of the laminated structure, and a high-Sn concentration portion in which the Sn concentration is higher than the average Sn concentration of the one internal electrode layer is formed on a surface exposed to the discontinuous portion.

[0009] In the ceramic electronic component, the high Sn concentration portion may extend from a surface exposed to the discontinuous portion to an interface between the one internal electrode layer and a dielectric layer adjacent to the one internal electrode layer.

[0010] In the ceramic electronic component, two or more of the discontinuous portions may be formed in one of the internal electrode layers, and the Sn high concentration portions extending from the respective discontinuous portions may be spaced apart from each other at the interface between the one of the internal electrode layers and a dielectric layer adjacent to the one of the internal electrode layers.

[0011] In the ceramic electronic component, the concentration of Sn relative to Ni in the one internal electrode layer may be 0.1 at % or less.

[0012] In the ceramic electronic component, the thickness of each internal electrode layer may be 1 μm or less.

[0013] The method for manufacturing a ceramic electronic component according to the present invention is characterized by comprising the steps of: forming a laminate unit by forming an internal electrode pattern containing Ni and Sn on a dielectric green sheet containing Ba and Ti by sputtering; stacking a plurality of the laminate units to form a laminate; and firing the laminate to form, in an internal electrode layer obtained from any of the internal electrode patterns, a discontinuous portion that is interrupted in a cross section including the stacking direction of the laminate unit, and forming, on a surface exposed to the discontinuous portion, a Sn high concentration portion having a Sn concentration higher than the average Sn concentration of the internal electrode layer. [Effects of the Invention]

[0014] According to the present invention, the reliability of ceramic electronic components can be improved. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] 10A and 10B are diagrams illustrating discontinuous portions of internal electrode layers. [Figure 5] 10(a) and 10(b) are diagrams illustrating high Sn concentration portions. [Figure 6] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 7] 1(a) and 1(b) are diagrams illustrating the lamination process. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments will be described with reference to the drawings.

[0017] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom, and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other. In FIG. 1, the X-axis direction (first direction) is the length direction of the laminated chip 10, the direction in which the two end faces of the laminated chip 10 face each other, and the direction in which the external electrodes 20a and 20b face each other. The Y-axis direction (second direction) is the width direction of the internal electrode layers. The Z-axis direction is the stacking direction, and the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0018] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and three or more internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered by cover layers 13. The cover layers 13 are primarily composed of a ceramic material. For example, the material of the cover layers 13 may have the same primary ceramic component as the dielectric layers 11.

[0019] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0020] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-α For example, the ceramic material contains at least barium (Ba) in the A site and at least titanium (Ti) in the B site. For example, BaTiO3 (barium titanate), BaTiO4 (barium titanate), which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc., can be used. The thickness of each dielectric layer 11 is, for example, 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less.

[0021] 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0022] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated.

[0023] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. In other words, the side margins 16 are regions provided so as to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure, which extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0024] The dielectric layer 11 can be formed, for example, by firing a dielectric material containing ceramic powder. The internal electrode layer 12 can be formed, for example, by firing a paste material containing metal powder. During these firing processes, discontinuous portions 17, which are partially interrupted, are generated in the internal electrode layer 12, as illustrated in FIG. 4. Note that FIG. 4 shows a cross-sectional view in the XZ plane, so the internal electrode layer 12 appears to be divided into multiple parts in the X-axis direction by the discontinuous portions 17, but the internal electrode layer 12 may be connected in a cross section taken at a different position on the Y-axis. For example, the discontinuous portions 17 have a hole-like shape when viewed in a plan view from the Z-axis direction. The discontinuous portions 17 may be voids or may be filled with the dielectric material of the dielectric layer 11.

[0025] Electric field concentration is likely to occur at the discontinuous portions 17 of the internal electrode layers 12. Insulation resistance is likely to decrease at the electric field concentration locations. As a result, reliability may decrease. Therefore, for example, it is conceivable to improve the insulation properties of the dielectric layers 11 by dissolving different elements in the dielectric material. However, this method does not solve the deterioration in reliability caused by the discontinuous portions 17 of the internal electrode layers 12. Furthermore, since the distribution of insulation resistance is such that the interface between the internal electrode layers 12 and the dielectric layers 11 is greater than the grain boundaries and intra-grains of the dielectric layers 11, the above method seems insufficient when considering that the grain boundary and intra-grain resistance components become smaller as the dielectric layers 11 are thinned.

[0026] Therefore, in this embodiment, the internal electrode layers 12 contain nickel (Ni) as a main component and tin (Sn). When the internal electrode layers 12 contain Ni and Sn, the moisture resistance of the multilayer ceramic capacitor 100 can be improved. For example, it is thought that alloying of Ni and Sn changes the state of the interface between the internal electrode layers 12 and the dielectric layers 11, thereby improving the moisture resistance of the multilayer ceramic capacitor 100 and improving reliability.

[0027] Furthermore, in at least one of the internal electrode layers 12, the Sn concentration is increased in the vicinity of the discontinuous portion 17. Specifically, as illustrated in Fig. 5(a), in at least one of the internal electrode layers 12, a high Sn concentration portion 18 is provided on the surface exposed to the discontinuous portion 17 (the inner wall of the hole formed in the internal electrode layer 12 by the discontinuous portion 17). The high Sn concentration portion 18 is a portion having a higher Sn concentration than the average Sn concentration of the entire internal electrode layer 12.

[0028] The high concentration of Sn segregated on the surface exposed to the discontinuous portion 17 acts to increase the potential barrier (Schottky barrier) at the interface between the internal electrode layer 12 and the dielectric layer 11 in the vicinity of the discontinuous portion 17, thereby increasing the insulation resistance. This suppresses deterioration of the insulation resistance due to electric field concentration in the vicinity of the discontinuous portion 17. Furthermore, the substitution of Ti ions for Sn ions in the vicinity of the discontinuous portion 17 increases the energy for generating oxygen defects in the vicinity of the discontinuous portion 17, reducing the oxygen defect concentration in the vicinity of the discontinuous portion 17 compared to when Ni diffuses into the dielectric layer 11, and increasing the insulation resistance. As a result, the reliability of the multilayer ceramic capacitor 100 is improved.

[0029] 5(b), the Sn high concentration portion 18 is preferably provided continuously from the surface exposed to the discontinuous portion 17 to at least one of the upper surface and the lower surface of the internal electrode layer 12. That is, the Sn high concentration portion 18 preferably extends from the surface exposed to the discontinuous portion 17 to the interface with the adjacent dielectric layer 11.

[0030] On the other hand, if the Sn high concentration portions 18 cover the entire upper surface and the entire lower surface of the internal electrode layer 12, there is a risk of failure due to interfacial peeling, etc. Therefore, it is preferable that the Sn high concentration portions 18 extending from each discontinuous portion 17 of the internal electrode layer 12 are separated from each other at the interface with the adjacent dielectric layer 11.

[0031] The Sn concentration in the Sn high concentration portion 18 is, for example, at least twice the average Sn concentration per layer of the internal electrode layer 12. For example, if the average Sn concentration per layer of the internal electrode layer 12 is 0.1 at%, the Sn concentration in the Sn high concentration portion 18 relative to Ni in the Sn high concentration portion 18 is 0.2 at% or more.

[0032] If the amount of Sn in the internal electrode layer 12 is too large, the continuity of the internal electrode may be reduced, resulting in a decrease in capacity. Therefore, it is preferable to set an upper limit on the amount of Sn in the internal electrode layer 12. For example, in the entire internal electrode layer 12, the Sn concentration relative to Ni is preferably 0.1 at% or less, more preferably 0.07 at% or less, and even more preferably 0.05 at% or less. Note that the Sn concentration relative to Ni refers to the amount of Sn when Ni + Sn is 100 at%.

[0033] The thickness of each internal electrode layer 12 is, for example, 0.01 μm to 5 μm, or 0.05 μm to 3 μm, or 0.1 μm to 1 μm. For example, if the thickness of the internal electrode layer 12 is 1 μm or less, the continuity rate is likely to decrease due to fracture during firing, and the effect of the configuration according to this embodiment is more pronounced. In the multilayer ceramic capacitor 100, the number of stacked internal electrode layers 12 is, for example, 10 to 5,000, 50 to 4,000, or 100 to 3,000. In addition, the internal electrode layer 12 including the Sn-rich portion 18 is obtained by a firing process after film formation by sputtering, as in the manufacturing method described below, and therefore the internal electrode layer 12 according to this embodiment does not contain a co-material of ceramic particles.

[0034] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0035] (raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered compact of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0036] The resulting ceramic material powder is then doped with a predetermined additive compound depending on the purpose, such as oxides of magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0037] For example, a ceramic material powder is wet-mixed with a compound containing an additive compound, followed by drying and pulverization to prepare a ceramic material powder. For example, the ceramic material powder obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained through the above steps.

[0038] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0039] Next, as illustrated in FIG. 7(a), an internal electrode pattern 53 is formed on a dielectric green sheet 52. In FIG. 7(a), as an example, four layers of internal electrode patterns 53 are formed on the dielectric green sheet 52 at predetermined intervals. The film formation method is sputtering. A NiSn alloy can be used as the sputtering target. Alternatively, simultaneous sputtering using separate targets of Ni and Sn may be performed. The dielectric green sheet 52 on which the internal electrode pattern 53 is formed is used as a lamination unit.

[0040] Next, while peeling the dielectric green sheet 52 from the substrate 51, the lamination units are stacked as shown in FIG. 7(b). Next, a predetermined number of cover sheets (e.g., 2 to 10 layers) are stacked on top and bottom of the laminate obtained by stacking the lamination units, and are thermocompression bonded, and then cut to predetermined chip dimensions (e.g., 1.0 mm x 0.5 mm). In the example of FIG. 7(b), cutting is performed along the dotted lines. The cover sheet may have the same components as the dielectric green sheet 52, or may contain a different additive compound.

[0041] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in an N2 atmosphere, and then a metal paste that would become the base layer of the external electrodes 20a, 20b was applied by dipping. -5 ~10 -8 The mixture is then fired in a reducing atmosphere at 1100 to 1300° C. for 10 minutes to 2 hours at 1 atm. In this way, the multilayer ceramic capacitor 100 is obtained.

[0042] (Reoxidation treatment process) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0043] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, or Sn by plating.

[0044] According to the manufacturing method of this embodiment, an internal electrode pattern 53 containing Ni and Sn is formed by sputtering. Compared to firing a paste material, the firing process of the internal electrode pattern 53 formed by sputtering is more likely to produce discontinuous portions 17. Sn, which is sputtered simultaneously with Ni, easily diffuses into the BaTiO3-based material. However, the amount of BaTiO3-based material in the discontinuous portions 17 is reduced, resulting in an insufficient driving force for diffusion, resulting in Sn remaining in the discontinuous portions 17. As a result, as described with reference to FIG. 5( a) or 5(b), a high-concentration Sn portion 18 is formed near the discontinuous portions 17. Furthermore, compared to discontinuous portions formed by firing a paste material, Sn is more likely to remain in the discontinuous portions formed by firing a sputtered film. This is thought to be because the co-material contained in the paste material suppresses the diffusion of Sn into the dielectric layer 11.

[0045] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may also be used.

[0046] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0047] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 capacity area 15 End Margin 16 Side Margin 17 Discontinuities 18 Sn high concentration area 20a,20b external electrode 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 100 Multilayer ceramic capacitors

Claims

1. a laminate including a plurality of dielectric layers containing Ba and Ti, and a plurality of internal electrode layers containing Ni and Sn, stacked alternately with the plurality of dielectric layers in a stacking direction; In a cross section of the laminate including the stacking direction, at least one internal electrode layer of the plurality of internal electrode layers is configured to be discontinued at a discontinuous portion, the one internal electrode layer has, on a surface exposed to the discontinuous portion, a high Sn concentration portion having a Sn concentration higher than an average Sn concentration in the one internal electrode layer, the discontinuity includes a dielectric region including a dielectric material; The ceramic electronic component is characterized in that the dielectric region contains Sn.

2. 2. The ceramic electronic component according to claim 1, wherein the high Sn concentration portion extends from a surface exposed to the discontinuous portion to an interface between the one internal electrode layer and a dielectric layer adjacent to the one internal electrode layer.

3. 3. The ceramic electronic component according to claim 2, wherein two or more of the discontinuous portions are formed in the one internal electrode layer, and the Sn high concentration portions extending from the respective discontinuous portions are spaced apart from each other at interfaces with the dielectric layers adjacent to the one internal electrode layer.

4. 4. The ceramic electronic component according to claim 1, wherein the concentration of Sn relative to Ni in the one internal electrode layer is 0.1 at % or less.

5. 5. The ceramic electronic component according to claim 1, wherein the thickness of each of the internal electrode layers is 1 μm or less.

6. the first internal electrode layer contains Ti in the vicinity of the dielectric region of the discontinuous portion; The ceramic electronic component according to claim 1 .

7. an oxygen vacancy creation energy in the dielectric region of the discontinuous portion is higher than an oxygen vacancy creation energy in the dielectric layer; The ceramic electronic component according to claim 1 .

8. forming an internal electrode pattern containing Ni and Sn on a dielectric green sheet containing Ba and Ti by sputtering to form a laminate unit; forming a laminate including a plurality of internal electrode patterns by laminating a plurality of the lamination units; a firing step of firing the laminate to obtain a plurality of internal electrode layers from the plurality of internal electrode patterns; Including, In the firing step, the laminate is fired so that at least one of the plurality of internal electrode layers is discontinued at a discontinuous portion, the one internal electrode layer has, on a surface exposed to the discontinuous portion, a high Sn concentration portion having a Sn concentration higher than an average Sn concentration in the one internal electrode layer, the discontinuity includes a dielectric region including a dielectric material; The method for producing a ceramic electronic component, wherein the dielectric region contains Sn.

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