Semiconductor device

Abstract

To provide a semiconductor device capable of improving the characteristics of a field effect transistor.SOLUTION: A semiconductor device includes a source region SR extending along the Y-axis direction, a first drain region DR11, a first gate electrode G11 arranged between the source region SR and the first drain region DR11, a second drain region DR21 located on the opposite side of the first drain region DR11 with respect to the source region SR and extending along the Y-axis direction, and a second gate electrode G21 arranged between the source region SR and the second drain region DR21, and the first gate electrode G11 extends in a zigzag manner along the Y-axis direction, and the second gate electrode G21 extends in a zigzag manner along the Y-axis direction, and a conductive region BR of a conductivity type opposite to that of the source region SR is formed in the source region SR arranged between the first gate electrode G11 and the second gate electrode G21, and the source region SR and the conductive region BR are electrically connected.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a field effect transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 153693

[0004] [overview] The present disclosure provides a semiconductor device capable of improving the characteristics of a field effect transistor.

[0005] The semiconductor device of the present disclosure defines an XYZ three-dimensional Cartesian coordinate system in which the depth direction is the Z-axis direction, and in a planar view seen from the Z-axis direction, comprises: a source region extending along the Y-axis direction; a first drain region extending along the Y-axis direction; a first gate electrode arranged between the source region and the first drain region; a second drain region located on the opposite side of the first drain region with respect to the source region and extending along the Y-axis direction; and a second gate electrode arranged between the source region and the second drain region, wherein the first gate electrode extends in a serpentine manner along the Y-axis direction and the second gate electrode extends in a serpentine manner along the Y-axis direction, and a conductive region of an opposite conductivity type to the source region is formed in the source region arranged between the first gate electrode and the second gate electrode, and the source region and the conductive region are electrically connected. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor chip. [Figure 2] FIG. 2 is a plan view of the device region. [Figure 3] FIG. 3 is a diagram showing a vertical cross-sectional configuration of the device region shown in FIG. 2 taken along the arrow AA. [Figure 4] FIG. 4 is a diagram showing a vertical cross-sectional configuration of the device region taken along the arrow BB shown in FIG. [Figure 5] FIG. 5 is a circuit diagram of a group of parallel-connected transistors. [Figure 6] FIG. 6 is a plan view of the device region. [Figure 7] FIG. 7 is a diagram showing a vertical cross-sectional configuration of the device region shown in FIG. 6 taken along the arrow AA. [Figure 8] FIG. 8 is a diagram showing a vertical cross-sectional configuration of the device region taken along the arrow BB shown in FIG. [Figure 9] FIG. 9 is a circuit diagram of a group of parallel-connected transistors. [Figure 10] FIG. 10 is a plan view of the transistor. [Figure 11] FIG. 11 is a plan view of a semiconductor chip equipped with a BCD circuit.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] FIG. 1 is a plan view of a semiconductor chip.

[0009] The semiconductor chip 100 (semiconductor device) has a rectangular parallelepiped shape. The semiconductor chip 100 has a first main surface 3 on one side. The back surface is located on the opposite side of the first main surface 3. The semiconductor chip 100 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D connecting the first main surface 3 and the back surface. The thickness direction of the semiconductor chip 100 is defined as the Z-axis direction, the direction perpendicular to the Z-axis is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The depth direction of the semiconductor chip 100 is defined as the positive direction of the Z-axis, and the negative direction of the Z-axis indicates the direction from the back surface of the semiconductor substrate toward the first main surface 3 (top surface). When an XYZ three-dimensional Cartesian coordinate system is set in which the depth direction is defined as the Z-axis direction, this figure shows a plan view as seen from the Z-axis direction.

[0010] The first main surface 3 and the back surface are each perpendicular to the Z axis. The planar shape (shape in plan view) of the first main surface 3 when viewed from the normal direction (Z axis direction) of the first main surface 3 is rectangular (quadrilateral). The back surface of the semiconductor substrate also has a rectangular (quadrilateral) shape in plan view. The first side surface 5A and the second side surface 5B, which constitute two opposing sides of the rectangle in plan view, each extend along the X axis direction. The third side surface 5C and the fourth side surface 5D, which constitute the other two opposing sides of the rectangle in plan view, each extend along the Y axis direction. These adjacent side surfaces are orthogonal in plan view, but can also intersect at an angle other than orthogonal.

[0011] The semiconductor chip 100 includes a plurality of device regions 10 provided on the first main surface 3. There is a gap between each device region 10 and each side surface (first side surface 5A to fourth side surface 5D) of the semiconductor chip 100. The number, arrangement, and shape of the device regions 10 are arbitrary and are not limited to a specific number, arrangement, or shape.

[0012] Various devices are formed in each device region 10. In this example, at least one device region 10 includes a device 50.

[0013] An example of the device 50 is a field-effect transistor. A field-effect transistor can also be used as a power transistor. The field-effect transistor in this example is a metal-insulator semiconductor field-effect transistor (MISFET: insulated gate field-effect transistor). A metal-oxide-semiconductor field-effect transistor (MOSFET) can also be used as the MISFET. The MOSFET in this embodiment is an extended drain (ED) MOSFET. An exemplary EDMOS-FET has an N-type well region in which N-type carriers drift on the drain region side. MISFETs with drain-source voltages of high voltage (HV: e.g., 100 V to 1000 V), medium voltage (MV: e.g., 30 V to 100 V), and low voltage (LV: e.g., 1 V to 30 V) are also known.

[0014] FIG. 2 is a plan view of the device region.

[0015] A device 50 is formed in the central portion of the device region 10. The device 50 is a field effect transistor (FET). Surface contact layers are located on the surfaces of the source and drain regions of the device 50, but are not shown in the figure. The surface surrounding the device 50 in the device region 10 is covered with an insulating region 18. The insulating region 18 is a field oxide film or STI (shallow trench isolation), etc. In each semiconductor region, P type is defined as the first conductivity type and N type is defined as the second conductivity type, but these conductivity types are interchangeable.

[0016] In a plan view seen from the Z-axis direction, the device 50 includes a source region SR, a first drain region DR11, a first gate electrode G11, a second drain region DR21, and a second gate electrode G21. The source region SR extends along the Y-axis direction. The first drain region DR11 extends along the Y-axis direction. The first gate electrode G11 is disposed between the source region SR and the first drain region DR11. The second drain region DR21 is located on the opposite side of the source region SR to the first drain region DR11 and extends along the Y-axis direction. The second gate electrode G21 is disposed between the source region SR and the second drain region DR21. A P-type semiconductor layer 1E extending along the Y-axis direction is formed below the source region SR.

[0017] The first gate electrode G11 extends in a zigzag pattern along the Y-axis direction. The second gate electrode G21 extends in a zigzag pattern along the Y-axis direction. A conductive region BR (P-type butting region) of the opposite conductivity type to the source region SR is formed in the source region SR arranged between the first gate electrode G11 and the second gate electrode G21. The conductive regions BR are periodically arranged along the Y-axis. Therefore, the source region SR and the conductive regions BR are electrically connected periodically in the Y-axis direction. The conductive regions BR are arranged in a region where the gap in the X-axis direction between the first gate electrode G11 and the second gate electrode G21 is wide, and no conductive regions BR are arranged in a region where the gap is narrow.

[0018] The conductive region BR can be connected to the back gate of the field-effect transistor. In power transistors, a back gate is used to prevent the parasitic transistor of the field-effect transistor from operating. If the gate electrode is simply arranged in a straight line, the effective channel width decreases and the gate capacitance increases. To suppress the increase in on-resistance and gate capacitance, a structure in which the conductive region is extended along the Y-axis direction can be considered, but this increases the distance between the left and right drain regions (cell pitch), and increases the on-resistance. Narrowing the width of the source region can also be considered, but this reduces manufacturing stability. If the width of the N-type source region or drain region is narrowed too much, the P-type conductive region BR will affect the transistor characteristics.

[0019] Therefore, the first gate electrode G11 and the second gate electrode G21 are formed in a meandering (wavy) shape, and conductive regions BR are selectively arranged in the regions of the source region SR where the distance between the gate electrodes is relatively wide, and are not arranged in the regions where the distance between the gate electrodes is relatively narrow. By forming the first gate electrode G11 and the second gate electrode G21 in a wavy shape, it is possible to increase the gate width per unit area while preventing an increase in pitch. The conductive regions BR are arranged in the shape of isolated islands, which suppresses a decrease in gate width and an increase in gate capacitance, reduces on-resistance, and improves switching efficiency.

[0020] The first electrode portion GP1 is disposed at the end in the negative direction of the Y axis. The second electrode portion GP2 is disposed at the end in the positive direction of the Y axis. The first gate electrode G11 connects the first electrode portion GP1 and the second electrode portion GP2. Similarly, the second gate electrode G21 connects the first electrode portion GP1 and the second electrode portion GP2.

[0021] A part of the first lower drain region DR10, to which a medium voltage is applied, is located between the first drain region DR11 and the source region SR, and the first lower drain region DR10 is also located below the first drain region DR11 in the depth direction. In the transistors in the first row closer to the first electrode portion GP1, a first drain electrode E11 is arranged on the first drain region DR11. Similarly, in the transistors in the odd-numbered row (the (2N-1)th row), a first drain electrode E11 is arranged on the first drain region DR11 (N is a natural number). On the other hand, in the transistors in the even-numbered row (the (2N)th row), a first drain electrode E11b of the even-numbered row is arranged on the first drain region DR11.

[0022] The first drain electrodes E11 in the odd-numbered rows are arranged at positions farther from the source electrode E1 (E1b) than the first drain electrodes E11b in the even-numbered rows.

[0023] A part of the second lower drain region DR20, to which a medium voltage is applied, is located between the second drain region DR21 and the source region SR, and the second lower drain region DR20 is also located below the second drain region DR21 in the depth direction. In the transistors in the first row closer to the first electrode portion GP1, a second drain electrode E21 is arranged on the second drain region DR21. Similarly, in the transistors in the odd-numbered row (the (2N-1)th row), a second drain electrode E21 is arranged on the second drain region DR21 (N is a natural number). On the other hand, in the transistors in the even-numbered row (the (2N)th row), a second drain electrode E21b of the even-numbered row is arranged on the second drain region DR21.

[0024] The second drain electrodes E21 in the odd-numbered rows are arranged at positions farther from the source electrode E1 (E1b) than the drain electrodes 21b in the even-numbered rows.

[0025] A conductive region BR (semiconductor region) is arranged in the source region SR of the odd-numbered rows. No conductive region BR is arranged in the source region SR of the even-numbered rows. In the transistors of the odd-numbered rows, a source electrode E1 is arranged on the source region SR, and the source electrode E1 is also connected to the conductive region BR. Similarly, in the transistors of the even-numbered rows, a source electrode E1b is arranged on the source region SR.

[0026] The source electrodes E1 in the odd-numbered rows are formed on the conductive regions BR, while the source electrodes E1b in the even-numbered rows are not formed on the conductive regions BR below them.

[0027] In this example, the conductivity type of the source region SR, the first drain region DR11, the first lower drain region DR10, the second drain region DR21, and the second lower drain region DR20 is N-type. The conductivity type of the P-type semiconductor layer 1E and the conductive region BR is P-type. The FET including these semiconductor regions is formed in a P-type well region 1C. The P-type well region 1C is formed inside a second N-type semiconductor layer 1D. The second N-type semiconductor layer 1D can form a PN junction with the P-type well region 1C. The first N-type well region 1B is formed in a surface region of the semiconductor substrate 1A.

[0028] FIG. 3 is a diagram showing a vertical cross-sectional configuration of the device region shown in FIG. 2 taken along the arrow AA.

[0029] The figure shows a cross section of a transistor in an odd-numbered row (e.g., the third row) counting from the first electrode portion GP1. In the substrate 1, a first N-type well region 1B is formed on a semiconductor substrate 1A, and a P-type well region 1C is formed on the first N-type well region 1B. The P-type well region 1C is surrounded by a second N-type semiconductor layer 1D in a plan view. The impurity concentration of the second N-type semiconductor layer 1D can be higher than the impurity concentration of the first N-type well region 1B. A source region SR, a first lower drain region DR10, a second lower drain region DR20, and a P-type semiconductor layer 1E are formed in the P-type well region 1C. A first drain region DR11 is formed on the first lower drain region DR10. A second drain region DR21 is formed in the second lower drain region DR20. A source region SR and a conductive region BR are formed in the P-type semiconductor layer 1E. The conductive region BR is connected to the P-type semiconductor layer 1E. The first lower drain region DR10 and the second lower drain region DR20 contribute to increasing the resistance to hot carriers.

[0030] A first surface contact layer E10 is formed on the first drain region DR11. A second surface contact layer E20 is formed on the second drain region DR21. A surface contact layer E0 is formed on the source region SR and the conductive region BR. The surface contact layer E0 electrically connects the source region SR and the conductive region BR. The first surface contact layer E10, the second surface contact layer E20, and the surface contact layer E0 are made of a conductive material. Examples of this conductive material include impurity-doped polysilicon, metal (aluminum, etc.), or silicide (tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, etc.).

[0031] A first drain electrode E11 is formed on the first surface contact layer E10, a second drain electrode E21 is formed on the second surface contact layer E20, and a source electrode E1 is formed on the surface contact layer E0.

[0032] A first gate electrode G11 is formed on a region between the first drain region DR11 and the source region SR with a first gate insulating film G10 interposed therebetween. A second gate electrode G21 is formed on a region between the second drain region DR21 and the source region SR with a second gate insulating film G20 interposed therebetween.

[0033] The first transistor Q11 includes a first drain region DR11 and a source region SR. The second transistor Q12 includes a second drain region DR21 and a source region SR. That is, the source region SR is a common source region of the first transistor Q11 and the second transistor Q12.

[0034] FIG. 4 is a diagram showing a vertical cross-sectional configuration of the device region taken along the arrow BB shown in FIG.

[0035] The figure shows a cross section of a transistor in an even-numbered row (e.g., the second row) counting from the first electrode portion GP1. The difference from the cross section shown in FIG. 3 is that the conductive region BR is not formed in the source region SR, and therefore the width of the source region SR in the X-axis direction is smaller. As the width of the source region SR in the X-axis direction is reduced, the widths of the first lower drain region DR10, the second lower drain region DR20, the first drain region DR11, and the second drain region DR21 in the X-axis direction are increased. The other configurations are the same as those of the device region shown in FIG. 3.

[0036] A first surface contact layer E10b is formed on the first drain region DR11. A second surface contact layer E20b is formed on the second drain region DR21. A surface contact layer E0b is formed on the source region SR. The first surface contact layer E10b, the second surface contact layer E20b, and the surface contact layer E0b are made of a conductive material. Examples of this conductive material include impurity-doped polysilicon, metal (aluminum, etc.), or silicide (tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, etc.).

[0037] A first drain electrode E11b is formed on the first surface contact layer E10b, a second drain electrode E21b is formed on the second surface contact layer E20b, and a source electrode E1b is formed on the surface contact layer E0b.

[0038] The first transistor Q11b includes a first drain region DR11 and a source region SR. The second transistor Q12b includes a second drain region DR21 and a source region SR. That is, the source region SR is a common source region of the first transistor Q11b and the second transistor Q12b.

[0039] FIG. 5 is a circuit diagram of a group of parallel-connected transistors.

[0040] Each field effect transistor shown in the figure is an NMOS (N-channel MOS) FET.

[0041] The gate electrodes of all the transistors (the first transistor Q11 in the odd-numbered row, the first transistor Q11b in the even-numbered row, the second transistor Q12 in the odd-numbered row, and the second transistor Q12b in the even-numbered row) are electrically connected to the gate electrode wiring GW. Similarly, the source electrodes of all the transistors are electrically connected to the source electrode wiring SW. In addition, the drain electrodes of all the transistors are electrically connected to the drain electrode wiring DW. The transistors are connected in parallel and can function as high-voltage transistors.

[0042] FIG. 6 is a plan view of a device area with multiple rows of source regions.

[0043] A device 50 is formed in the central portion of the device region 10. The device 50 is a field effect transistor (FET). Surface contact layers are located on the surfaces of the source and drain regions of the device 50, but are not shown in the figure. The surface surrounding the device 50 in the device region 10 is covered with an insulating region 18. The insulating region 18 is a field oxide film, an STI, or the like.

[0044] The device 50 has two rows (multiple rows) of source regions SR in a plan view seen from the Z-axis direction.

[0045] The right region of the device 50 has basically the same structure as that shown in FIG. 2, but shares the drain region with the left region. That is, the right region of the device 50 includes a common drain region DR31, a first gate electrode G11, a source region SR, a second gate electrode G21, and a second drain region DR21. The source regions SR in the right column extend along the Y-axis direction. The common drain region DR31 extends along the Y-axis direction. The first gate electrode G11 in the right column is disposed between the source region SR and the common drain region DR31. The second drain region DR21 is located on the opposite side of the source region SR in the right column from the common drain region DR31 and extends along the Y-axis direction. The second gate electrode G21 in the right column is disposed between the source region SR and the second drain region DR21. A P-type semiconductor layer 1E extending along the Y-axis direction is formed below the source regions SR in the right column.

[0046] The left region of the device 50 has a structure in which the right region is shifted by half the period of the gate electrode that periodically meanders in the right region. That is, the left region of the device 50 includes a first drain region DR11, a first gate electrode G11, a source region SR, a second gate electrode G21, and a common drain region DR31. The source region SR in the left column extends along the Y-axis direction. The first drain region DR11 is located on the opposite side of the common drain region DR31 with respect to the source region SR in the left column, and extends along the Y-axis direction. The first gate electrode G11 in the left column is disposed between the first drain region DR11 and the source region SR. The second gate electrode G21 in the left column is disposed between the source region SR and the common drain region DR31. A P-type semiconductor layer 1E extending along the Y-axis direction is formed below the source region SR in the left column.

[0047] The first gate electrodes G11 on the right and left columns extend in a zigzag pattern along the Y-axis direction. The second gate electrodes G21 on the right and left columns extend in a zigzag pattern along the Y-axis direction. In the source region SR arranged between the first gate electrode G11 and the second gate electrode G21, a conductive region BR (P-type butting region) of the opposite conductivity type to the source region SR is formed. The conductive regions BR are periodically arranged along the Y-axis. Therefore, the source region SR and the conductive regions BR are electrically connected periodically in the Y-axis direction. The conductive regions BR are arranged in the region where the gap in the X-axis direction between the first gate electrode G11 and the second gate electrode G21 is wide, and no conductive regions BR are arranged in the region where the gap is narrow.

[0048] The first electrode portion GP1 is disposed at the end in the negative direction of the Y axis. The second electrode portion GP2 is disposed at the end in the positive direction of the Y axis. The first gate electrodes G11 in the right and left columns connect the first electrode portion GP1 and the second electrode portion GP2. Similarly, the second gate electrodes G21 in the right and left columns connect the first electrode portion GP1 and the second electrode portion GP2.

[0049] A portion of a first lower drain region DR10 to which a medium voltage is applied is located between the first drain region DR11 and the left-column source region SR, and the first lower drain region DR10 is also located below the first drain region DR11 in the depth direction. A portion of a second lower drain region DR20 to which a medium voltage is applied is located between the second drain region DR21 and the right-column source region SR, and the second lower drain region DR20 is also located below the second drain region DR21 in the depth direction. A portion of a common lower drain region DR30 to which a medium voltage is applied is located between the common drain region DR31 and the left and right source regions SR, and the common lower drain region DR30 is also located below the common drain region DR31 in the depth direction.

[0050] In the transistors in odd-numbered rows (the (2N-1)th row) counting from the first electrode portion GP1, the drain electrodes and source electrodes are arranged as follows (N is a natural number): A first drain electrode E11b is arranged on the first drain region DR11. A source electrode E1b is arranged on the source region SR in the left column. A common drain electrode E31 is arranged on the common drain region DR31. A source electrode E1 is arranged on the source region SR and conductive region BR in the right column. A second drain electrode E21 is arranged on the second drain region DR21.

[0051] In the transistors in the even-numbered rows (the (2N)th row) counting from the first electrode portion GP1, the drain electrodes and source electrodes are arranged as follows (N is a natural number): A first drain electrode E11 is arranged on the first drain region DR11. A source electrode E1 is arranged on the source regions SR and conductive regions BR on the left column. A common drain electrode E31b is arranged on the common drain region DR31. A source electrode E1b is arranged on the source region SR on the right column. A second drain electrode E21b is arranged on the second drain region DR21.

[0052] The first drain electrodes E11b in the odd-numbered rows are arranged closer to the source electrodes E1b (E1) on the left column than the first drain electrodes E11 in the even-numbered rows. The second drain electrodes E21 in the odd-numbered rows are arranged farther from the source electrodes E1 (E1b) on the right column than the second drain electrodes E21b in the even-numbered rows. The common drain electrodes E31 in the odd-numbered rows are arranged farther from the source electrodes E1 (E1b) on the right column than the common drain electrodes E31b in the even-numbered rows.

[0053] A conductive region BR is arranged in the source region SR in the right column of the odd-numbered rows, and a conductive region BR is not arranged in the source region SR in the right column of the even-numbered rows. A conductive region BR is not arranged in the source region SR in the left column of the odd-numbered rows, and a conductive region BR is arranged in the source region SR in the left column of the even-numbered rows.

[0054] A source electrode E1b is arranged on the source region SR in the left column of odd-numbered rows, and a source electrode E1 is arranged on the source region SR in the right column, and the source electrode E1 is also connected to the conductive region BR. A source electrode E1 is arranged on the source region SR in the left column of even-numbered rows, and the source electrode E1 is also connected to the conductive region BR, and a source electrode E1b is arranged on the source region SR in the right column. While the source electrode E1 is formed on the conductive region BR, there is no conductive region BR below the source electrode E1b.

[0055] In this example, the conductivity type of the source region SR, the first drain region DR11, the first lower drain region DR10, the second drain region DR21, the second lower drain region DR20, the common drain region DR31, and the common lower drain region DR30 is N-type. The conductivity type of the P-type semiconductor layer 1E and the conductive region BR is P-type. The FET including these semiconductor regions is formed in a P-type well region 1C. The P-type well region 1C is formed inside a second N-type semiconductor layer 1D. The second N-type semiconductor layer 1D is formed in a first N-type well region 1B. The first N-type well region 1B is formed in a surface region of the semiconductor substrate 1A.

[0056] FIG. 7 is a diagram showing a vertical cross-sectional configuration of the device region shown in FIG. 6 taken along the arrow AA.

[0057] The figure shows a cross section of a transistor in an odd-numbered row (e.g., the third row) counting from the first electrode portion GP1. In the substrate 1, a first N-type well region 1B is formed on a semiconductor substrate 1A, and a P-type well region 1C is formed on the first N-type well region 1B. In a plan view, the P-type well region 1C is surrounded by a second N-type semiconductor layer 1D. The impurity concentration of the second N-type semiconductor layer 1D can be higher than the impurity concentration of the first N-type well region 1B.

[0058] In the P-type well region 1C, a first lower drain region DR10, a left P-type semiconductor layer 1E, a common lower drain region DR30, a right P-type semiconductor layer 1E, and a second lower drain region DR20 are formed.

[0059] A first drain region DR11 is formed on the first lower drain region DR10. A first surface contact layer E10b is formed on the first drain region DR11. A first drain electrode E11b is formed on the first surface contact layer E10b.

[0060] A left source region SR is formed on the left P-type semiconductor layer 1E. A surface contact layer E0b is formed on the left source region SR. A source electrode E1b is formed on the surface contact layer E0b.

[0061] A common drain region DR31 is formed on the common lower drain region DR30. A common surface contact layer E30 is formed on the common drain region DR31. A common drain electrode E31 is formed on the common surface contact layer E30.

[0062] A right source region SR and a conductive region BR are formed on the right P-type semiconductor layer 1E. A surface contact layer E0 is formed on the right source region SR and the conductive region BR. A source electrode E1 is formed on the surface contact layer E0. The surface contact layer E0 electrically connects the right source region SR and the conductive region BR. The conductive region BR is connected to the P-type semiconductor layer 1E.

[0063] A second drain region DR21 is formed in the second lower drain region DR20. A second surface contact layer E20 is formed on the second drain region DR21. A second drain electrode E21 is formed on the second surface contact layer E20.

[0064] The first surface contact layer (E10b), the second surface contact layer (E20), the surface contact layers (E0, E0b), and the common surface contact layer E30 are made of a conductive material, such as impurity-doped polysilicon, metal (aluminum, etc.), or silicide (tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, etc.).

[0065] A first gate electrode G11 is formed on a region between the left source region SR and the left first drain region DR11 with a left first gate insulating film G10 interposed therebetween. A second gate electrode G21 is formed on a region between the left source region SR and the common drain region DR31 with a left second gate insulating film G20 interposed therebetween.

[0066] A first gate electrode G11 is formed on a region between the right source region SR and the common drain region DR31 with a right first gate insulating film G10 interposed therebetween. A second gate electrode G21 is formed on a region between the right source region SR and the right second drain region DR21 with a right second gate insulating film G20 interposed therebetween.

[0067] The first left transistor Q11b includes a first drain region DR11 and a left source region SR. The second left transistor Q12b includes a common drain region DR31 and a left source region SR. That is, the left source region SR is a common source region of the first left transistor Q11b and the second left transistor Q12b.

[0068] The first right transistor Q11 includes a common drain region DR31 and a right source region SR. The second right transistor Q12 includes a second drain region DR21 and a right source region SR. That is, the right source region SR is a common source region of the first right transistor Q11 and the second right transistor Q12.

[0069] FIG. 8 is a diagram showing a vertical cross-sectional configuration of the device region taken along the arrow BB shown in FIG.

[0070] The figure shows a cross section of a transistor in an even-numbered row (e.g., the second row) counting from the first electrode portion GP1. The cross section of FIG. 8 has a structure inverted left and right with respect to the YZ plane passing through the common drain region DR31 in FIG. 7. No conductive region BR is formed in the right source region SR, and a conductive region BR is formed in the left source region SR. Therefore, the width in the X-axis direction of the right source region SR is reduced, and the width in the X-axis direction of the left source region SR is increased. As the width in the X-axis direction of the right source region SR is reduced, the widths in the X-axis direction of the second lower drain region DR20 and the second drain region DR21 are increased.

[0071] A first N-type well region 1B is formed on a semiconductor substrate 1A, and a P-type well region 1C is formed on the first N-type well region 1B. In a plan view, the P-type well region 1C is surrounded by a second N-type semiconductor layer 1D. The impurity concentration of the second N-type semiconductor layer 1D can be made higher than the impurity concentration of the first N-type well region 1B.

[0072] In the P-type well region 1C, a first lower drain region DR10, a left P-type semiconductor layer 1E, a common lower drain region DR30, a right P-type semiconductor layer 1E, and a second lower drain region DR20 are formed.

[0073] A first drain region DR11 is formed on the first lower drain region DR10. A first surface contact layer E10 is formed on the first drain region DR11. A first drain electrode E11 is formed on the first surface contact layer E10.

[0074] A left source region SR and a conductive region BR are formed on the left P-type semiconductor layer 1E. A surface contact layer E0 is formed on the left source region SR and the conductive region BR. A source electrode E1 is formed on the surface contact layer E0. The surface contact layer E0 electrically connects the left source region SR and the conductive region BR. The conductive region BR is connected to the left P-type semiconductor layer 1E.

[0075] A common drain region DR31 is formed on the common lower drain region DR30. A common surface contact layer E30 is formed on the common drain region DR31. A common drain electrode E31 is formed on the common surface contact layer E30.

[0076] A right source region SR is formed on the right P-type semiconductor layer 1E. A surface contact layer E0b is formed on the right source region SR. A source electrode E1b is formed on the surface contact layer E0b.

[0077] A second drain region DR21 is formed on the second lower drain region DR20. A second surface contact layer E20b is formed on the second drain region DR21. A second drain electrode E21b is formed on the second surface contact layer E20b.

[0078] The first surface contact layer (E10), the second surface contact layer (E20b), the surface contact layers (E0, E0b), and the common surface contact layer E30 are made of a conductive material, such as impurity-doped polysilicon, metal (aluminum, etc.), or silicide (tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, etc.).

[0079] A first gate electrode G11 is formed on a region between the left source region SR and the left first drain region DR11 with a left first gate insulating film G10 interposed therebetween. A second gate electrode G21 is formed on a region between the left source region SR and the common drain region DR31 with a left second gate insulating film G20 interposed therebetween.

[0080] A first gate electrode G11 is formed on a region between the right source region SR and the common drain region DR31 with a right first gate insulating film G10 interposed therebetween. A second gate electrode G21 is formed on a region between the right source region SR and the right second drain region DR21 with a right second gate insulating film G20 interposed therebetween.

[0081] The first left transistor Q11 includes a first drain region DR11 and a left source region SR. The second left transistor Q12 includes a common drain region DR31 and a left source region SR. That is, the left source region SR is a common source region of the first left transistor Q11 and the second left transistor Q12.

[0082] The first right transistor Q11b includes a common drain region DR31 and a right source region SR. The second right transistor Q12b includes a second drain region DR21 and a right source region SR. That is, the right source region SR is a common source region of the first right transistor Q11b and the second right transistor Q12b.

[0083] FIG. 9 is a circuit diagram of a group of parallel-connected transistors.

[0084] Each field effect transistor shown in the figure is an NMOS (N-channel MOS) FET. A common drain region DR31 is a common drain region between adjacent second transistors (Q12b, Q12) and first transistors (Q11, Q11b).

[0085] The gate electrodes of the first transistors (Q11, Q11b) and the second transistors (Q12, Q12b) are electrically connected to a gate electrode wiring GW. The source electrodes of the first transistors (Q11, Q11b) and the source electrodes of the second transistors (Q12, Q12b) are electrically connected to a source electrode wiring SW. The drain electrodes of the first transistors (Q11, Q11b) and the drain electrodes of the second transistors (Q12, Q12b) are electrically connected to a drain electrode wiring DW. The transistors are connected in parallel and can function as high-voltage transistors.

[0086] FIG. 10 is a plan view of the transistor.

[0087] This figure shows the structure in the vicinity of the transistors in the odd-numbered rows in Figure 6. Note that the surface contact layers are not shown.

[0088] The first drain region DR11 and the first gate electrode G11 are adjacent to each other in the X-axis direction in a plan view. The direction of each gate electrode is defined as the extension direction of the center position in the width direction. The first gate electrode G11 has a first portion P1 extending in a direction parallel to the Y-axis and a second portion P2 extending at a first angle θ11 (acute angle) with the Y-axis. Similarly, the second gate electrode G21 has a first portion P1 extending in a direction parallel to the Y-axis and a second portion P2 extending at a first angle θ11 (acute angle) with the Y-axis. The first angle θ11 is an acute angle between the Y-axis and the extension direction of the second portion P2. For example, the first angle θ11 satisfies the range 30°≦θ11≦60°. If the first angle θ11 is below the lower limit, the spacing between the conductive regions BR tends to become too large, and if it exceeds the upper limit, the distance tends to be affected by the optical proximity effect. Therefore, the angle is preferably within the above range.

[0089] The first gate electrode G11 on the left side extends such that the distance between it and the source electrode E1b in the X-axis direction decreases as it approaches the source electrode E1b in the Y-axis direction. The second gate electrode G21 on the left side extends such that the distance between it and the source electrode E1b in the X-axis direction decreases as it approaches the source electrode E1b in the Y-axis direction.

[0090] The first gate electrode G11 on the right side extends such that the distance between it and the source electrode E1 along the X-axis direction increases as it approaches the source electrode E1 along the Y-axis direction. The second gate electrode G21 on the right side extends such that the distance between it and the source electrode E1 along the X-axis direction increases as it approaches the source electrode E1 along the Y-axis direction.

[0091] The dimension YE in the Y-axis direction of the drain electrodes (E11b, E31, E21) and the source electrodes (E1b, E1) is larger than the dimension YB in the Y-axis direction of the conductive region BR. As an exemplary dimension, it satisfies 1 μm ≤ YE ≤ 4 μm. This has the effect of reducing the contact resistance between the source region SR and the conductive region BR. The exemplary dimension YB satisfies 0.8 μm ≤ YB ≤ 1.2 μm. This has the effect of suppressing the potential floating of the source region SR. Potential floating means that the actual potential rises higher than the expected potential.

[0092] In the source region SR including the left source electrode E1b, the minimum distance Xmin1 in the X-axis direction between the first gate electrode G11 and the second gate electrode G21, exemplarily, satisfies 0.4 μm ≤ Xmin1 ≤ 0.6 μm. The maximum distance Xmax1 in the X-axis direction between the first gate electrode G11 and the second gate electrode G21 in the left source region SR satisfies Xmin1 < Xmax1. Exemplarily, it satisfies 1 μm ≤ Xmax1 ≤ 1.5 μm. This has the effect of optimizing the area efficiency. The ratio XR1 = (Xmin1 / Xmax1) of these dimensions, exemplarily, satisfies 30% ≤ XR1 ≤ 50%. In other words, the ratio of the minimum value to the maximum value of the distance along the X-axis direction between the first gate electrode and the second gate electrode is 1% or more and 50% or less. This has the effect of optimizing the area efficiency while suppressing the potential floating of the source region SR. The preferred range of XR1 is 35% ≤ XR1 ≤ 45%, and the more preferred range is 38% ≤ XR1 ≤ 42%.

[0093] In a source region SR including a right source electrode E1, the maximum distance Xmax2 in the X-axis direction between a first gate electrode G11 and a second gate electrode G21 illustratively satisfies 1 μm ≤ Xmax2 ≤ 1.5 μm. The minimum distance Xmin2 in the X-axis direction between the first gate electrode G11 and the second gate electrode G21 in the right source region SR satisfies Xmin2 < Xmax2. Illustratively, it satisfies 0.4 μm ≤ Xmin2 ≤ 0.6 μm. The ratio XR2 = (Xmin2 / Xmax2) of these dimensions illustratively satisfies 1% ≤ XR2 ≤ 50%. For the same reasons as in the case of XR1, XR2 can be illustratively set to 30% ≤ XR2 ≤ 50%, preferably 35% ≤ XR2 ≤ 45%, and more preferably 38% ≤ XR2 ≤ 42%.

[0094] The distance along the X-axis direction between the first gate electrode G11 and the second gate electrode G21 varies periodically along the Y-axis direction, and the conductive region BR is arranged in the source region SR at the position giving the maximum value (Xmax2) of the distance along the X-axis direction. The conductive region BR is not arranged in the source region SR at the position giving the minimum value (Xmin2) of the distance along the X-axis direction.

[0095] The conductive region BR is arranged in a region where the interval between the two waveform gate electrodes is wide. In this structure, the effective width through which carriers travel has increased compared to a simple linear gate electrode, and the effective gate width has increased by, for example, about 8% compared to a linear gate electrode. Therefore, the on-resistance per unit area can be reduced by, for example, about 5 to 6%, and the gate capacitance can be reduced by, for example, about 20%.

[0096] The planar shape of the conductive region BR is rectangular, and the dimension XB in the X-axis direction can be made smaller than the dimension Xmin1 (or Xmin2). This has the effect of suppressing the cell pitch. Exemplarily, 0.2 μm ≤ XB ≤ 0.5 μm is satisfied. This has the effect of suppressing the cell pitch. The dimension YB of the conductive region BR in the Y-axis direction can be made smaller than the dimension YE of the source electrode E1 in the Y-axis direction (YB < YE). Exemplarily, 0.7 μm ≤ YB ≤ 1.5 μm may be satisfied. This has the effect of optimizing the area efficiency while suppressing the potential floating of the source region SR.

[0097] Also, the differential dimension DIF = (Xmax2 - XB) can be defined. Exemplarily, 0.6 μm ≤ DIF ≤ 1.1 μm is satisfied. This has the effect of optimizing the area efficiency.

[0098] The gate electrode width XG in the X-axis direction between the respective first gate electrodes G11 and second gate electrodes G21 is, for example, 0.35 μm. The gate electrode width XG satisfies, exemplarily, 0.1 μm ≤ XG ≤ 0.8 μm.

[0099] The X-axis direction width (cell pitch XP1) between the left first drain electrode E11b and the common drain electrode E31 is, for example, 1.74 μm. The X-axis direction width (cell pitch XP2) between the right second drain electrode E21 and the common drain electrode E31 is, for example, 2.54 μm. Note that the cell pitch in this example is set based on the central position of each drain electrode in the X-axis direction.Cell pitch XP1 satisfies, exemplarily, 1.5 μm ≤ XP1 ≤ 2.0 μm. This has the effect of optimizing the area efficiency. Cell pitch XP2 satisfies, exemplarily, 2.0 μm ≤ XP2 ≤ 3 μm. This has the effect of optimizing the area efficiency.

[0100] FIG. 11 is a plan view of a semiconductor chip including a BCD circuit.

[0101] The above-described field-effect transistor structure can also be applied to field-effect transistors in a BCD (BIPOLAR-CMOS-DMOS) chip. The semiconductor chip 100 of this example includes a bipolar transistor region 100B, a CMOS circuit region 100C, and a DMOS transistor region 100D. The bipolar transistor region 100B includes one or more bipolar transistors and is an analog block to which analog signals such as signals from various sensors are input.

[0102] The CMOS circuit region 100C includes a plurality of field-effect transistors that form one or more CMOS (complementary metal-oxide semiconductor) circuits, and is a digital block to which digital signals are input. The DMOS transistor region 100D includes one or more DMOS (double-diffused metal-oxide semiconductor) FETs (field-effect transistors), and is a power block capable of processing high-voltage signals. In a BCD chip, for example, a sensor signal can be input to an analog block, and a control signal can be input to a digital block, and the output signal of the power block can be controlled based on these outputs.

[0103] Each block includes one or more device regions. For example, multiple device regions are defined within the DMOS transistor region 100D, and each device region includes the above-described field-effect transistor surrounded by an isolation structure. The semiconductor chip 100 in this example is a BCD chip, but the structure of the above-described embodiment can also be applied to semiconductor chips of types other than BCD chips.

[0104] When an N-type well region is used in the bipolar transistor or CMOS circuit that constitutes the BCD chip, these regions can be formed in the same process as the process for forming the N-type well region of the DMOS-FET.

[0105] Next, the materials and impurity concentrations of the above-mentioned semiconductor regions will be described.

[0106] The semiconductor material constituting the semiconductor chip 100 described above is silicon (Si). Compound semiconductors can also be used as the semiconductor material constituting the semiconductor chip 100. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. Ga-containing semiconductors such as GaAs and GaN can be used as III-V compound semiconductors. Si-containing semiconductors such as SiC and SiGe can be used as IV-IV compound semiconductors. Impurities can be added to the semiconductor region by ion implantation, but diffusion methods can also be used.

[0107] More specifically, the material of the semiconductor substrate 1A is silicon (Si). The material of the semiconductor substrate 1A can also be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). The conductivity type of the semiconductor substrate 1A is P-type (first conductivity type), and the impurity concentration (C 1A ) is, for example, 1×10 14 cm -3 ~5×10 18 cm -3 The thickness of the semiconductor substrate 1A is, for example, 250 μm to 800 μm.

[0108] The material of the first N-type well region 1B can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the first N-type well region 1B is N-type (second conductivity type), and the impurity concentration (C 1B ) is, for example, 1×10 16 cm -3 ~1×10 18 cm -3 The thickness of the first N-type well region 1B can be set to, for example, 0.5 μm to 4 μm.

[0109] The material of the P-type well region 1C can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the P-type well region 1C is P-type (first conductivity type), and the impurity concentration (C 1C ) is, for example, 1×10 16 cm -3 ~1×1018 cm -3 The thickness of the P-type well region 1C can be set to, for example, 0.5 μm to 4 μm.

[0110] The material of the P-type semiconductor layer 1E can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the P-type semiconductor layer 1E is P-type (first conductivity type), and the impurity concentration (C 1E ) is, for example, 5×10 16 cm -3 ~5×10 18 cm -3 The impurity concentration of the P-type semiconductor layer 1E can be set to be higher than that of the P-type well region 1C. The thickness of the P-type semiconductor layer 1E can be set to be, for example, 0.3 μm to 1 μm.

[0111] The material of the conductive region BR can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the conductive region BR is P type (first conductivity type), and the impurity concentration (C BR ) is, for example, 1×10 19 cm -3 ~5×10 21 cm -3 The impurity concentration of the conductive region BR can be set to, for example, 0.2 μm to 1.0 μm, which can be higher than the impurity concentration of the P-type semiconductor layer 1 E.

[0112] The material of the source region SR and the drain region (DR11, DR21) can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the source region SR and the drain region (DR11, DR21) is N-type (second conductivity type), and the impurity concentration (C SR , C DR ) is, for example, 1×10 19 cm -3 ~5×10 21 cm -3 The thickness of the source region SR and the drain region (DR11, DR21) can be set to, for example, 0.2 μm to 1 μm, but a structure in which the depth is made shallower or deeper is also possible.

[0113] The material of the lower drain regions (DR10, DR20) located below the drain regions (DR11, DR21) can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the lower drain regions (DR10, DR20) is N-type (second conductivity type), and the impurity concentration (C UDR ) is the impurity concentration in the drain region (C DR ), e.g., 1×10 17 cm -3 ~1×10 19 cm -3 The thickness of the lower drain regions (DR10, DR20) can be set to be larger than that of the drain regions (DR11, DR21).

[0114] In the above example, an NMOS-FET was described, but the same effect can be obtained by exchanging the first and second conductivity types and applying the same technique to a PMOS-FET.

[0115] (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0116] [A1] An XYZ three-dimensional orthogonal coordinate system is set with the depth direction being the Z-axis direction, and in a plan view seen from the Z-axis direction, a source region SR extending along the Y-axis direction, a first drain region DR11 extending along the Y-axis direction, a first gate electrode G11 arranged between the source region SR and the first drain region DR11, a second drain region DR21 located on the opposite side of the first drain region DR11 with respect to the source region SR and extending along the Y-axis direction, and a second gate electrode G21 arranged between the source region SR and the second drain region DR21, wherein the first gate electrode G11 extends in a zigzag manner along the Y-axis direction and the second gate electrode G21 extends in a zigzag manner along the Y-axis direction, and a conductive region BR of a conductivity type opposite to that of the source region SR is formed in the source region SR arranged between the first gate electrode G11 and the second gate electrode G21, and the source region SR and the conductive region BR are electrically connected.

[0117] [A2] The semiconductor device according to [A1], wherein the distance along the X-axis direction between the first gate electrode G11 and the second gate electrode G21 varies periodically along the Y-axis direction, and the conductive region BR is disposed within the source region SR at a position that provides the maximum value (Xmax2) of the distance along the X-axis direction, but is not disposed within the source region SR at a position that provides the minimum value (Xmin2) of the distance along the X-axis direction.

[0118] [A3] The semiconductor device according to [A2], wherein the ratio of the minimum value (Xmin2) to the maximum value (Xmax2) of the distance along the X-axis direction between the first gate electrode G11 and the second gate electrode G21 is 1% or more and 50% or less.

[0119] [A4] The semiconductor device according to [A1], wherein the first gate electrode G11 and the second gate electrode G21 each have a first portion P1 extending in a direction parallel to the Y axis and a second portion P2 extending at a first angle θ11 with the Y axis, the first angle θ11 being an acute angle and satisfying 30°≦θ11≦60°.

[0120] [A5] A semiconductor device according to [A1], comprising: a semiconductor substrate 1A of a first conductivity type; a second conductivity type well region (1B) formed on the semiconductor substrate 1A; a first conductivity type well region (1D) formed in the second conductivity type well region; and a first conductivity type semiconductor layer (1E) arranged in the first conductivity type well region (1D), wherein the conductivity type of the conductive region BR is the first conductivity type, the conductive region BR is connected to the semiconductor layer (1E), and the impurity concentration of the conductive region BR is higher than the impurity concentration of the semiconductor layer (1E).

[0121] [A6] An XYZ three-dimensional orthogonal coordinate system is set with the depth direction being the Z-axis direction, and in a plan view seen from the Z-axis direction, a first source region (the source region SR on the left side of FIG. 6) extending along the Y-axis direction, a second source region (the source region SR on the right side of FIG. 6) extending along the Y-axis direction, a first drain region (the first drain region DR11 on the left side of FIG. 6) extending along the Y-axis direction, a second drain region (the second drain region DR21 on the right side of FIG. 6) extending along the Y-axis direction, and a common drain region (the common drain region DR22 at the center of FIG. 6) extending along the Y-axis direction are defined. 6) disposed between the first source region and the first drain region; a first-side first gate electrode (first gate electrode G11 on the left side in FIG. 6) disposed between the first source region and the common drain region; a first-side second gate electrode (second gate electrode G21 on the left side in FIG. 6) disposed between the first source region and the common drain region; a second-side first gate electrode (first gate electrode G11 on the right side in FIG. 6) disposed between the second source region and the common drain region; and a second-side second gate electrode (second gate electrode G21 on the left side in FIG. 6) disposed between the second source region and the second drain region. 6), the first drain region DR11, the first-side first gate electrode (the first gate electrode G11 on the left side in FIG. 6), the first source region (the source region SR on the left side in FIG. 6), the first-side second gate electrode (the second gate electrode G21 on the left side in FIG. 6), the common drain region DR31, the second-side first gate electrode (the first gate electrode G11 on the right side in FIG. 6), the second source region (the source region SR on the right side in FIG. 6), the second-side second gate electrode (the second gate electrode G21 on the right ... common drain region DR31, the second-side second gate electrode (the 6) extends in a zigzag manner along the Y-axis direction, the first-side first gate electrode (the first gate electrode G11 on the left side in FIG. 6) extends in a zigzag manner along the Y-axis direction, the first-side second gate electrode (the second gate electrode G21 on the left side in FIG. 6) extends in a zigzag manner along the Y-axis direction, the second-side first gate electrode (the first gate electrode G11 on the right side in FIG. 6) extends in a zigzag manner along the Y-axis direction, and the second-side second gate electrode (the second gate electrode G21 on the right side in FIG. 6) extends in a zigzag manner along the Y-axis direction,In the first source region (the source region SR on the left side of FIG. 6) disposed between the first-side first gate electrode (the first gate electrode G11 on the left side of FIG. 6) and the first-side second gate electrode (the second gate electrode G21 on the left side of FIG. 6), a first conductive region (the conductive region BR in the left column of FIG. 6) of a conductivity type opposite to that of the first source region is formed, the first source region and the first conductive region are electrically connected, and the second source region (the source region S on the right side of FIG. 6) disposed between the second-side first gate electrode (the first gate electrode G11 on the right side of FIG. 6) and the second-side second gate electrode (the second gate electrode G21 on the right side of FIG. 6) is formed. a second conductive region (conductive region BR in the right column of FIG. 6) of a conductivity type opposite to that of the second source region is formed in a first gate electrode (first gate electrode G11 on the left side of FIG. 6) and a second gate electrode (second gate electrode G21 on the left side of FIG. 6) and the second source region is electrically connected to the second conductive region; and the position in the Y-axis direction that gives the maximum value of the distance between the first-side first gate electrode (first gate electrode G11 on the left side of FIG. 6) and the first-side second gate electrode (second gate electrode G21 on the right side of FIG. 6) is different from the position in the Y-axis direction that gives the maximum value of the distance between the second-side first gate electrode (first gate electrode G11 on the right side of FIG. 6) and the second-side second gate electrode (second gate electrode G21 on the right side of FIG. 6).

[0122] In the semiconductor device described above, the gate electrode is made to meander and has a conductive region BR, which suppresses a decrease in gate width and an increase in gate capacitance, reduces on-resistance, increases switching efficiency, and improves the characteristics of the field-effect transistor. Also, the semiconductor device (see FIG. 6) has at least four or more rows of meandering gate electrodes, and the positions in the Y-axis direction that give the maximum width between these gate electrodes are different, which allows the overall area to be reduced.

[0123] [A7] The semiconductor device according to [A6], wherein the distance along the X-axis direction between the first-side first gate electrode (G11) and the first-side second gate electrode (G21) varies periodically along the Y-axis direction, and the first conductive region (BR) is arranged within the first source region (SR) at a position that provides the maximum value (Xmax1) of the distance along the X-axis direction, and is not arranged within the first source region (SR) at a position that provides the minimum value (Xmin1) of the distance along the X-axis direction.

[0124] The conductive region BR is arranged on the first side (left side) at a position that provides the maximum value of the distance described above, thereby reducing the area without deteriorating the overall function.

[0125] [A8] The semiconductor device according to [A7], wherein the distance along the X-axis direction between the second-side first gate electrode (G11) and the second-side second gate electrode (G21) varies periodically along the Y-axis direction, and the second conductive region (BR) is arranged within the second source region (SR) at a position that gives the maximum value (Xmax2) of the distance along the X-axis direction, and is not arranged within the second source region (SR) at a position that gives the minimum value (Xmin2) of the distance along the X-axis direction.

[0126] The conductive region BR is arranged on the second side (right side) at a position that gives the maximum value of the above distance, thereby reducing the area without deteriorating the overall function.

[0127] [A9] The semiconductor device according to [A6], wherein a ratio (XR1) of the minimum value to the maximum value of the distance along the X-axis direction between the first-side first gate electrode (G11) and the first-side second gate electrode (G21), and a ratio (XR2) of the minimum value to the maximum value of the distance along the X-axis direction between the second-side first gate electrode (G11) and the second-side second gate electrode (G21) are each 1% or more and 50% or less.

[0128] [A9-1] The semiconductor device according to [A9], wherein the ratio (XR1, XR2) is 30% or more and 50% or less.

[0129] [A9-2] The semiconductor device according to [A9], wherein the ratio (XR1, XR2) is 35% or more and 45% or less.

[0130] [A9-3] The semiconductor device according to [A9], wherein the ratio (XR1, XR2) is 38% or more and 42% or less.

[0131] [A10] The semiconductor device described in [A6], wherein the first-side first gate electrode, the first-side second gate electrode, the second-side first gate electrode, and the second-side second gate electrode each have a first portion extending in a direction parallel to the Y-axis and a second portion extending at a first angle θ11 with the Y-axis, the first angle θ11 being an acute angle and satisfying 30°≦θ11≦60°.

[0132] In the ranges of the various parameters described above, the range of any parameter P is P min ≦P≦P max If given by (P min +ΔP)≦P≦(P max -ΔP), ΔP=(P max -P min )×R%, R may be set to 10, or R may be set to 20, R may be set to 30, or R may be set to 40.

[0133] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0134] 1...Substrate 1A...Semiconductor substrate 1B...First N-type well region 1C...P-type well region 1D…Second N-type semiconductor layer 1E...P-type semiconductor layer 3...First main surface 5A…1st side 5B…Second side 5C…Third side 5D…Fourth side 10...Device area 18...Isolation area 50…devices 100...Semiconductor chip 100B...Bipolar transistor area 100C…CMOS circuit area 100D...DMOS transistor area BR…Conductive area DR10: First lower drain region DR20: Second lower drain region DR30...Common lower drain region DR11: First drain region DR21: Second drain region DR31...Common drain region DW: Drain electrode wiring E1, E1b...Source electrodes E11, E11b...first drain electrode E21, E21b...Second drain electrode E31, E31b...Common drain electrode E0, E0b...surface contact layer E10, E10b...first surface contact layer E20, E20b...Second surface contact layer E30...Common surface contact layer G10: First gate insulating film G20: Second gate insulating film G11: First gate electrode G21: Second gate electrode GP1…1st electrode part GP2…Second electrode part GW: Gate electrode wiring P1…first part P2…Second part Q11, Q11b...first transistor Q12, Q12b...Second transistor SR...Source region SW...Source electrode wiring θ11...first angle

Claims

1. An XYZ three-dimensional orthogonal coordinate system is set with the depth direction being the Z-axis direction, and in a plan view seen from the Z-axis direction, a source region extending along the Y-axis direction; a first drain region extending along the Y-axis direction; a first gate electrode disposed between the source region and the first drain region; a second drain region located on the opposite side of the first drain region with respect to the source region and extending along the Y-axis direction; a second gate electrode disposed between the source region and the second drain region; Equipped with the first gate electrode extends in a meandering manner along the Y-axis direction, the second gate electrode extends in a meandering manner along the Y-axis direction, a conductive region of a conductivity type opposite to that of the source region is formed in the source region disposed between the first gate electrode and the second gate electrode, and the source region and the conductive region are electrically connected; Semiconductor device.

2. a distance between the first gate electrode and the second gate electrode along the X-axis direction periodically varies along the Y-axis direction; The conductive region is the source region at a position that provides a maximum distance along the X-axis direction; It is not disposed within the source region at a position that gives the minimum distance along the X-axis direction. The semiconductor device according to claim 1 .

3. a ratio of a minimum value to a maximum value of a distance between the first gate electrode and the second gate electrode along the X-axis direction is 1% or more and 50% or less; The semiconductor device according to claim 2 .

4. the first gate electrode and the second gate electrode each have a first portion extending in a direction parallel to the Y axis and a second portion extending at a first angle θ11 with the Y axis, the first angle θ11 being an acute angle and satisfying 30°≦θ11≦60°; The semiconductor device according to claim 1 .

5. a semiconductor substrate of a first conductivity type; a second conductivity type well region formed on the semiconductor substrate; a first conductivity type well region formed in the second conductivity type well region; a first conductivity type semiconductor layer disposed in the first conductivity type well region; Equipped with the conductive region has a first conductivity type; the conductive region is connected to the semiconductor layer; the impurity concentration of the conductive region is higher than the impurity concentration of the semiconductor layer; The semiconductor device according to claim 1 .

6. An XYZ three-dimensional orthogonal coordinate system is set with the depth direction being the Z-axis direction, and in a plan view seen from the Z-axis direction, a first source region extending along the Y-axis direction; a second source region extending along the Y-axis direction; a first drain region extending along the Y-axis direction; a second drain region extending along the Y-axis direction; a common drain region extending along the Y-axis direction; a first-side first gate electrode disposed between the first source region and the first drain region; a first-side second gate electrode disposed between the first source region and the common drain region; a second-side first gate electrode disposed between the second source region and the common drain region; a second-side second gate electrode disposed between the second source region and the second drain region; Equipped with the first drain region, the first-side first gate electrode, the first source region, the first-side second gate electrode, the common drain region, the second-side first gate electrode, the second source region, the second-side second gate electrode, and the second drain region are sequentially arranged along the X-axis direction, the first-side first gate electrode extends in a meandering manner along the Y-axis direction, the first-side second gate electrode extends in a meandering manner along the Y-axis direction, the second-side first gate electrode extends in a meandering manner along the Y-axis direction, the second-side second gate electrode extends in a meandering manner along the Y-axis direction, a first conductive region of a conductivity type opposite to that of the first source region is formed in the first source region disposed between the first-side first gate electrode and the first-side second gate electrode, and the first source region and the first conductive region are electrically connected; a second conductive region of a conductivity type opposite to that of the second source region is formed in the second source region disposed between the second-side first gate electrode and the second-side second gate electrode, and the second source region and the second conductive region are electrically connected to each other; a position in the Y-axis direction that gives a maximum value of the distance between the first-side first gate electrode and the first-side second gate electrode is different from a position in the Y-axis direction that gives a maximum value of the distance between the second-side first gate electrode and the second-side second gate electrode. Semiconductor device.

7. a distance along the X-axis direction between the first-side first gate electrode and the first-side second gate electrode varies periodically along the Y-axis direction; The first conductive region is the first source region at a position that provides a maximum distance along the X-axis direction, is not disposed in the first source region at a position that gives the minimum value of the distance along the X-axis direction, The semiconductor device according to claim 6.

8. a distance along the X-axis direction between the second-side first gate electrode and the second-side second gate electrode varies periodically along the Y-axis direction; The second conductive region is the second source region at a position that provides the maximum distance along the X-axis direction, It is not disposed in the second source region at a position that gives the minimum value of the distance along the X-axis direction. The semiconductor device according to claim 7 .

9. a ratio of a minimum value to a maximum value of a distance between the first-side first gate electrode and the first-side second gate electrode along the X-axis direction, and a ratio of a minimum value to a maximum value of a distance between the second-side first gate electrode and the second-side second gate electrode along the X-axis direction are each 1% or more and 50% or less. The semiconductor device according to claim 6.

10. the first-side first gate electrode, the first-side second gate electrode, the second-side first gate electrode, and the second-side second gate electrode each have a first portion extending in a direction parallel to the Y axis and a second portion extending at a first angle θ11 with the Y axis, the first angle θ11 being an acute angle and satisfying 30°≦θ11≦60°; The semiconductor device according to claim 6.

Images