Active matrix substrate and display device

Abstract

To provide an active matrix substrate capable of suppressing deterioration of the characteristics of an oxide semiconductor TFT in a gate drive circuit.SOLUTION: An active matrix substrate includes a substrate, a plurality of gate signal lines, and a gate drive circuit. The gate drive circuit includes a shift register having a plurality of stages, and each of the plurality of unit circuits constituting the stages includes a plurality of oxide semiconductor TFTs. The plurality of oxide semiconductor TFTs includes at least one first TFT and at least one second TFT having a mobility lower than that of the first TFT. The at least one second TFT includes an oxide semiconductor TFT whose drain-source electric field strength is highest when each unit circuit is operating.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an active matrix substrate, and more particularly to an active matrix substrate including an oxide semiconductor TFT, and also to a display device including such an active matrix substrate. [Background technology]

[0002] Active matrix substrates used in liquid crystal display devices, organic electroluminescence (EL) display devices, and the like have a display area with a plurality of pixels and a non-display area (sometimes called a "frame area") located around the display area. In the display area, a thin film transistor (hereinafter referred to as "TFT") is provided for each pixel. Conventionally, TFTs with an amorphous silicon film as the active layer (hereinafter referred to as "amorphous silicon TFTs") and TFTs with a polycrystalline silicon film as the active layer (hereinafter referred to as "polycrystalline silicon TFTs") have been widely used as the TFTs provided for each pixel.

[0003] It has been proposed to use oxide semiconductors as the active layer material of TFTs instead of amorphous silicon or polycrystalline silicon. Such TFTs are called "oxide semiconductor TFTs." Oxide semiconductors have higher mobility than amorphous silicon. Therefore, oxide semiconductor TFTs can operate at higher speeds than amorphous silicon TFTs.

[0004] TFT structures are broadly divided into bottom-gate and top-gate structures. Currently, the bottom-gate structure is often adopted for oxide semiconductor TFTs, but the use of a top-gate structure has also been proposed (see, for example, Patent Document 1). With the top-gate structure, the gate insulating layer can be made thin, resulting in high current supply performance.

[0005] Furthermore, peripheral circuits including TFTs may be monolithically (integrally) formed in the non-display area of ​​an active matrix substrate. Monolithically forming peripheral circuits can narrow the non-display area (narrow the frame) and reduce costs by simplifying the mounting process. For example, in the non-display area, a gate driver circuit may be monolithically formed and a source driver circuit may be mounted using a COG (Chip on Glass) method. A monolithically formed gate driver circuit is called a GDM (Gate Driver Monolithic) circuit. Patent Document 2 discloses a liquid crystal display device in which a GDM circuit is formed on an active matrix substrate.

[0006] In this specification, a TFT arranged in each pixel of the display area is referred to as a "pixel TFT." Also, a TFT constituting a peripheral circuit provided in the non-display area is referred to as a "circuit TFT." When the pixel TFT is an oxide semiconductor TFT, it is preferable from the viewpoint of the manufacturing process that the circuit TFT is also an oxide semiconductor TFT. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-21312 [Patent Document 2] International Publication No. 2011 / 055584 Summary of the Invention [Problem to be solved by the invention]

[0008] The present inventors have conducted various studies on active matrix substrates using oxide semiconductor TFTs as circuit TFTs, and have found that there are circuit TFTs in the GDM circuit that are prone to characteristic degradation.

[0009] The embodiments of the present invention have been made in view of the above problems, and have an object to provide an active matrix substrate that can suppress deterioration of the characteristics of oxide semiconductor TFTs in a gate drive circuit. [Means for solving the problem]

[0010] This specification discloses an active matrix substrate and a display device described in the following items.

[0011] [Item 1] A substrate; a plurality of gate signal lines supported by the substrate; a gate drive circuit that drives the plurality of gate signal lines; An active matrix substrate comprising: the gate drive circuit includes a shift register having a plurality of stages associated with the plurality of gate signal lines; each of the plurality of unit circuits constituting the plurality of stages includes a plurality of oxide semiconductor TFTs; The plurality of oxide semiconductor TFTs include at least one first TFT each including a first oxide semiconductor layer; at least one second TFT, each including a second oxide semiconductor layer, having a mobility lower than the mobility of the at least one first TFT; Including, the at least one second TFT is an oxide semiconductor TFT among the plurality of oxide semiconductor TFTs, the oxide semiconductor TFT having the highest drain-source electric field strength when each unit circuit is in operation; and an active matrix substrate.

[0012] [Item 2] the at least one second TFT is n (n is an integer of 2 or more) second TFTs, 2. The active matrix substrate according to item 1, wherein the n second TFTs are oxide semiconductor TFTs having the first to nth highest drain-source electric field strengths when the plurality of oxide semiconductor TFTs are ranked by the drain-source electric field strengths during operation of each unit circuit.

[0013] [Item 3] Each of the at least one first TFT comprises: the first oxide semiconductor layer including a first channel region, and a first source contact region and a first drain contact region located on both sides of the first channel region, respectively; a first gate electrode disposed on the first channel region of the first oxide semiconductor layer via a first gate insulating layer; and Each of the at least one second TFT comprises: the second oxide semiconductor layer including a second channel region, and a second source contact region and a second drain contact region located on both sides of the second channel region, respectively; a second gate electrode disposed on the second channel region of the second oxide semiconductor layer via a second gate insulating layer; 3. The active matrix substrate according to item 1 or 2, comprising:

[0014] [Item 4] the second oxide semiconductor layer is formed as a layer separate from the first oxide semiconductor layer, 4. The active matrix substrate according to any one of items 1 to 3, wherein the mobility of the second oxide semiconductor layer is lower than the mobility of the first oxide semiconductor layer.

[0015] [Item 5] the second gate insulating layer has a stacked structure including a first insulating layer and a second insulating layer disposed on the first insulating layer, the first gate insulating layer includes a third insulating layer formed in the same layer as the second insulating layer, but does not include an insulating layer formed in the same layer as the first insulating layer; 5. The active matrix substrate according to claim 4, further comprising a lower insulating layer formed in the same layer as the first insulating layer and disposed between the first oxide semiconductor layer and the substrate.

[0016] [Item 6] the first oxide semiconductor layer and the second oxide semiconductor layer each contain In and / or Sn; Item 6. The active matrix substrate according to item 4 or 5, wherein the total atomic ratio of In and Sn to all metal elements in the second oxide semiconductor layer is smaller than the total atomic ratio of In and Sn to all metal elements in the first oxide semiconductor layer.

[0017] [Item 7] 6. The active matrix substrate according to item 4 or 5, wherein the first oxide semiconductor layer and the second oxide semiconductor layer both contain an In-Ga-Zn-O based semiconductor, and an atomic ratio of In to all metal elements in the second oxide semiconductor layer is lower than an atomic ratio of In to all metal elements in the first oxide semiconductor layer.

[0018] [Item 8] the first oxide semiconductor layer has a stacked structure including a lower oxide semiconductor layer and an upper oxide semiconductor layer disposed on the lower oxide semiconductor layer and having a mobility lower than that of the lower oxide semiconductor layer; 4. The active matrix substrate according to any one of items 1 to 3, wherein the second oxide semiconductor layer is formed in the same layer as the upper oxide semiconductor layer of the first oxide semiconductor layer.

[0019] [Item 9] the lower oxide semiconductor layer and the upper oxide semiconductor layer each contain In and / or Sn, Item 9. The active matrix substrate according to item 8, wherein the total atomic ratio of In and Sn to all metal elements in the upper oxide semiconductor layer is smaller than the total atomic ratio of In and Sn to all metal elements in the lower oxide semiconductor layer.

[0020] [Item 10] Item 9. The active matrix substrate according to item 8, wherein the lower oxide semiconductor layer and the upper oxide semiconductor layer both contain an In-Ga-Zn-O based semiconductor, and the atomic ratio of In to all metal elements in the upper oxide semiconductor layer is lower than the atomic ratio of In to all metal elements in the lower oxide semiconductor layer.

[0021] [Item 11] 11. The active matrix substrate according to any one of items 1 to 10, wherein the gate drive circuit is monolithically formed on the active matrix substrate.

[0022] [Item 12] 12. A display device comprising the active matrix substrate according to any one of items 1 to 11. [Effects of the Invention]

[0023] According to the embodiment of the present invention, it is possible to provide an active matrix substrate that can suppress deterioration of the characteristics of oxide semiconductor TFTs in a gate drive circuit. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a liquid crystal display device 100 according to an embodiment of the present invention. [Figure 2] FIG. 1 is a schematic plan view showing a liquid crystal display device 100. [Figure 3] 1 is an equivalent circuit diagram of one pixel P of the liquid crystal display device 100. FIG. [Figure 4] 1 is a graph plotting combinations of gate-source voltage Vgs and drain-source electric field Eds for 11 oxide semiconductor TFTs included in a unit circuit UC having a certain configuration when the unit circuit UC is in operation. [Figure 5] 1 is a cross-sectional view schematically showing an active matrix substrate 10 included in a liquid crystal display device 100, with a first TFT 60 shown on the right and a second TFT 70 shown on the left. [Figure 6A] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 6B] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 6C] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 6D] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 6E] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 6F] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 6G] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 6H] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 6I] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 6J] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 7] 1 is a cross-sectional view schematically showing an active matrix substrate 10, showing a first TFT 60A on the right side and a second TFT 70A on the left side. [Figure 8A] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 8B] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 8C] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 8D] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 8E]1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 8F] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 8G] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the active matrix substrate 10. [Figure 9] 1 is a schematic plan view showing a liquid crystal display device 100A including a first gate driver 40A and a second gate driver 40B. [Figure 10] 2 is a diagram showing the overall configuration of a first gate driver 40A and a second gate driver 40B. FIG. [Figure 11] 1 is a schematic circuit diagram showing the configuration of a first gate driver 40A. FIG. [Figure 12] FIG. 1 is a circuit diagram showing the basic configuration of a unit circuit UC including a bistable circuit SR(n). [Figure 13] FIG. 10 is a circuit diagram showing an example of a detailed configuration of a unit circuit UC including a bistable circuit SR(n). DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, although a liquid crystal display device will be exemplified as a display device according to an embodiment of the present invention, the display device according to an embodiment of the present invention is not limited to a liquid crystal display device. For example, a display device according to an embodiment of the present invention may be an organic EL display device. Furthermore, the thin film transistors in the following description are n-type TFTs, and the electrical connection relationship when an n-type TFT is used will be described. Note that the electrical connection between the source and drain of a p-type TFT is opposite to the electrical connection between the source and drain of an n-type TFT.

[0026] [General configuration of liquid crystal display device] First, the schematic configuration of a liquid crystal display device 100 according to an embodiment of the present invention will be described with reference to Figures 1, 2, and 3. Figures 1 and 2 are a schematic cross-sectional view and a schematic plan view, respectively, that show the liquid crystal display device 100. Figure 3 is an equivalent circuit diagram of one pixel P of the liquid crystal display device 100.

[0027] 1, the liquid crystal display device 100 includes a display panel 1. The display panel 1 includes an active matrix substrate (hereinafter also referred to as a "TFT substrate") 10, a counter substrate (sometimes referred to as a "color filter substrate") 20 disposed opposite the TFT substrate 10, and a liquid crystal layer 30 provided between the TFT substrate 10 and the counter substrate 20.

[0028] As shown in FIG. 2, the liquid crystal display device 100 has a display region DR and a non-display region (also called a "peripheral region" or "frame region") FR. The display region DR is defined by a plurality of pixels P. The plurality of pixels P are arranged in a matrix including a plurality of rows and a plurality of columns. The non-display region FR is located on the periphery of the display region DR and does not contribute to display.

[0029] The display panel 1 (more specifically, the TFT substrate 10) of the liquid crystal display device 100 has a plurality (i) of gate bus lines (gate signal lines) GL(1) to GL(i) and a plurality (j) of source bus lines (source signal lines) SL(1) to SL(j). The gate bus lines GL(1) to GL(i) (sometimes collectively referred to as "gate bus lines GL") extend in the row direction, whereas the source bus lines SL(1) to SL(j) (sometimes collectively referred to as "source bus lines SL") extend in the column direction (a direction substantially perpendicular to the row direction). The gate bus lines GL and the source bus lines SL are supported by a substrate 10a, which will be described later.

[0030] As shown in Fig. 3, each pixel P is provided with a thin film transistor (pixel TFT) 2 and a pixel electrode PE. The pixel TFT 2 is supplied with a scanning signal (gate signal) from the corresponding gate bus line GL and with a video signal (source signal) from the corresponding source bus line SL. The pixel TFT 2 is an oxide semiconductor TFT having an oxide semiconductor layer as an active layer. The pixel electrode PE is electrically connected to the pixel TFT 2. A common electrode CE is arranged opposite the pixel electrode PE.

[0031] The liquid crystal display device 100 further includes a gate driver (gate drive circuit) 40 that drives the gate bus lines GL(1) to GL(i) and a source driver (source drive circuit) 50 that drives the source bus lines SL(1) to SL(j). The gate driver 40 and the source driver 50 are arranged in the non-display region FR.

[0032] The gate driver 40 sequentially selects a plurality of gate bus lines GL(1) to GL(i) (i.e., a state in which a high-level potential of a scanning signal is applied). The gate driver 40 has a shift register 41 with a plurality of stages (i stages in this example). The stages correspond to a plurality of gate bus lines GL (i.e., a plurality of pixel rows). The stages are made up of a plurality of unit circuits UC. In the example shown in the figure, each stage is made up of one unit circuit UC. That is, the shift register 41 has i unit circuits UC(1) to UC(i). Here, the gate driver 40 is monolithically formed on the active matrix substrate 10. That is, the gate driver 40 is a GDM circuit. Typically, one unit circuit UC constitutes one stage, but as will be illustrated later, one unit circuit UC may constitute two stages.

[0033] [Unit circuit configuration] Each unit circuit UC includes a plurality of oxide semiconductor TFTs as circuit TFTs, and each oxide semiconductor TFT includes an oxide semiconductor layer as an active layer.

[0034] The multiple oxide semiconductor TFTs of the unit circuit UC include at least one first TFT and at least one second TFT having a mobility lower than that of the first TFT. That is, the unit circuit UC contains a mixture of first TFTs with relatively high mobility and second TFTs with relatively low mobility. The at least one second TFT includes an oxide semiconductor TFT that has the highest drain-source electric field Eds strength when the unit circuit UC is operating, among the multiple oxide semiconductor TFTs in the unit circuit UC.

[0035] According to the inventors' investigations, it was found that there are circuit TFTs in the GDM circuit that are prone to characteristic degradation. Further detailed investigations revealed that characteristic degradation is likely to occur in circuit TFTs in which the drain-source electric field Eds becomes relatively strong during shift register operation.

[0036] As in the embodiment of the present invention, by mixing a first TFT with a relatively high mobility and a second TFT with a relatively low mobility in a unit circuit UC, and using the second TFT as a circuit TFT with a relatively strong drain-source electric field Eds during operation of the unit circuit UC, and using the first TFT as a circuit TFT with a relatively weak drain-source electric field Eds, it is possible to increase the source-drain breakdown voltage of the circuit TFT with a relatively strong drain-source electric field Eds while suppressing an increase in the circuit size of the gate drive circuit (GDM circuit) 40. As a result, deterioration of the characteristics of the oxide semiconductor TFT in the gate drive circuit 40 can be suppressed.

[0037] From the viewpoint of effectively suppressing deterioration of characteristics, as illustrated, it is preferable that at least one second TFT present in the unit circuit UC includes an oxide semiconductor TFT that has the highest strength of the drain-source electric field Eds when the unit circuit UC is in operation. Furthermore, when multiple second TFTs, i.e., n (n is an integer of 2 or greater) TFTs are arranged in the unit circuit UC, it is more preferable that, when the oxide semiconductor TFTs in the unit circuit UC are ranked by the strength of the drain-source electric field Eds when the unit circuit UC is in operation, the oxide semiconductor TFTs with the highest strengths, from 1st to nth, are selected as the second TFT. In other words, it is preferable to give priority to the oxide semiconductor TFT with the highest strength of the drain-source electric field Eds as the second TFT.

[0038] Figure 4 is a graph plotting combinations of gate-source voltage Vgs and drain-source electric field Eds for 11 oxide semiconductor TFTs (denoted as M1, M5, M6, M6+, M8, M9, M10, M10D, M14, M14D, and MS in Figure 4) included in a unit circuit UC having a certain configuration when the unit circuit UC is in operation.

[0039] 4, the strength of the drain-source electric field Eds during operation of the unit circuit UC is highest for M8 and M9, followed by M1. Therefore, when two second TFTs are arranged in the unit circuit UC, it is preferable to use M8 and M9 as the second TFTs, and when three second TFTs are arranged in the unit circuit UC, it is preferable to use M1, M8, and M9 as the second TFTs.

[0040] [Specific examples of the first TFT and the second TFT] A specific example of the first TFT and second TFT described above will be described with reference to FIG. 5. Here, the first TFT and second TFT have a top-gate structure, but the first TFT and second TFT may have a bottom-gate structure. FIG. 5 is a schematic cross-sectional view of an active matrix substrate 10. The right side of FIG. 5 shows a first TFT 60, and the left side of FIG. 5 shows a second TFT 70.

[0041] As already described, the active matrix substrate 10 has at least one first TFT 60 and at least one second TFT 70 in an area corresponding to each unit circuit UC. The first TFT 60 and the second TFT 70 are supported by the substrate 10a.

[0042] The first TFT 60 includes a first oxide semiconductor layer 61 , a first gate insulating layer 62 , a first gate electrode 63 , a first source electrode 64 , and a first drain electrode 65 .

[0043] The first oxide semiconductor layer 61 includes a first channel region 61c and a first source contact region 61s and a first drain contact region 61d located on either side of the first channel region 61c. The first source contact region 61s and the first drain contact region 61d may be low-resistance regions having a lower resistivity than the first channel region 61c. The low-resistance regions may be formed, for example, by performing a resistance reduction process on the first oxide semiconductor layer 61 using the first gate electrode 63 as a mask.

[0044] The first gate insulating layer 62 is provided on at least the first channel region 61c of the first oxide semiconductor layer 61. The first gate electrode 63 is disposed on the first channel region 61c of the first oxide semiconductor layer 61 via the first gate insulating layer 62. Note that, although an example is shown here in which the first gate insulating layer 62 covers the first channel region 61c but does not cover the first source contact region 61s and the first drain contact region 61d, the first gate insulating layer 62 may cover the first source contact region 61s and / or the first drain contact region 61d.

[0045] The first source electrode 64 is electrically connected to the first source contact region 61s of the first oxide semiconductor layer 61. The first drain electrode 65 is electrically connected to the first drain contact region 61d of the first oxide semiconductor layer 61.

[0046] In the illustrated example, a first light-shielding layer 3A is provided on the substrate 10a side of the first oxide semiconductor layer 61. The first light-shielding layer 3A is covered with an underlying insulating layer 4, and the first oxide semiconductor layer 61 is provided on the underlying insulating layer 4. In the illustrated example, a lower insulating layer 5 is interposed between the first oxide semiconductor layer 61 and the underlying insulating layer 4.

[0047] The first light-shielding layer 3A is disposed so as to overlap at least the first channel region 61c of the first oxide semiconductor layer 61 when viewed from the normal direction of the substrate 10a. This makes it possible to suppress deterioration of the characteristics of the first oxide semiconductor layer 61 caused by light (backlight) from the substrate 10a side. When the first light-shielding layer 3A is formed from a conductive material, the first light-shielding layer 3A may be in an electrically floating state (floating) or may be fixed to a GND potential (0 V). Alternatively, the first light-shielding layer 3A may be electrically connected to the first gate electrode 63 and function as a lower gate electrode.

[0048] The second TFT 70 includes a second oxide semiconductor layer 71 , a second gate insulating layer 72 , a second gate electrode 73 , a second source electrode 74 , and a second drain electrode 75 .

[0049] The second oxide semiconductor layer 71 includes a second channel region 71c and a second source contact region 71s and a second drain contact region 71d located on either side of the second channel region 71c. The second source contact region 71s and the second drain contact region 71d may be low-resistance regions having a lower resistivity than the second channel region 71c. The low-resistance regions may be formed, for example, by performing a resistance reduction process on the second oxide semiconductor layer 71 using the second gate electrode 73 as a mask.

[0050] The second gate insulating layer 72 is provided on at least the second channel region 71c of the second oxide semiconductor layer 71. The second gate electrode 73 is disposed on the second channel region 71c of the second oxide semiconductor layer 71 via the second gate insulating layer 72. Note that, although an example is shown here in which the second gate insulating layer 72 covers the second channel region 71c but does not cover the second source contact region 71s or the second drain contact region 71d, the second gate insulating layer 72 may cover the second source contact region 71s and / or the second drain contact region 71d.

[0051] The second source electrode 74 is electrically connected to the second source contact region 71s of the second oxide semiconductor layer 71. The second drain electrode 75 is electrically connected to the second drain contact region 71d of the second oxide semiconductor layer 71.

[0052] In the illustrated example, a second light-shielding layer 3B is provided on the substrate 10a side of the second oxide semiconductor layer 71. The second light-shielding layer 3B is formed in the same layer as the first light-shielding layer 3A, and is covered with the base insulating layer 4. The second oxide semiconductor layer 71 is provided on the base insulating layer 4.

[0053] The second light-shielding layer 3B is disposed so as to overlap at least the second channel region 71c of the second oxide semiconductor layer 71 when viewed from the normal direction of the substrate 10a. This makes it possible to suppress deterioration of the characteristics of the second oxide semiconductor layer 71 caused by light (backlight) from the substrate 10a side. When the second light-shielding layer 3B is formed from a conductive material, the second light-shielding layer 3B may be in an electrically floating state (floating) or may be fixed to a GND potential (0 V). Alternatively, the second light-shielding layer 3B may be electrically connected to the second gate electrode 73 to function as a lower gate electrode.

[0054] In the illustrated example, the second oxide semiconductor layer 71 of the second TFT 70 is formed in a layer separate from the first oxide semiconductor layer 61 of the first TFT 60. More specifically, the second oxide semiconductor layer 71 is formed below the first oxide semiconductor layer 61. The mobility of the second oxide semiconductor layer 71 is lower than the mobility of the first oxide semiconductor layer 61.

[0055] The second gate insulating layer 72 of the second TFT 70 has a layered structure including a first insulating layer L1 and a second insulating layer L2 disposed on the first insulating layer L1. In contrast, the first gate insulating layer 62 of the first TFT 60 includes a third insulating layer L3 formed in the same layer as the second insulating layer L2, but does not include an insulating layer formed in the same layer as the first insulating layer L1. The lower insulating layer 5 disposed between the first oxide semiconductor layer 61 and the substrate 10a (more specifically, between the first oxide semiconductor layer 61 and the base insulating layer 4) is formed in the same layer as the first insulating layer L1.

[0056] An interlayer insulating layer 6 is provided to cover the first oxide semiconductor layer 61, the first gate insulating layer 62, and the first gate electrode 63 of the first TFT 60, and the second oxide semiconductor layer 71, the second gate insulating layer 72, and the second gate electrode 73 of the second TFT 70. The first source electrode 64 and the first drain electrode 65 of the first TFT 60 and the second source electrode 74 and the second drain electrode 75 of the second TFT 70 are formed in the same layer and are disposed on the interlayer insulating layer 6.

[0057] The interlayer insulating layer 6 has a first opening 6a and a second opening 6b exposing the first source contact region 61s and the first drain contact region 61d of the first oxide semiconductor layer 61, and a third opening 6c and a fourth opening 6d exposing the second source contact region 71s and the second drain contact region 71d of the second oxide semiconductor layer 71. The first source electrode 64 is connected to the first source contact region 61s through the first opening 6a, and the first drain electrode 65 is connected to the first drain contact region 61d through the second opening 6b. The second source electrode 74 is connected to the second source contact region 71s through the third opening 6c, and the second drain electrode 75 is connected to the second drain contact region 71d through the fourth opening 6d. An inorganic insulating layer 7 is provided to cover the first source electrode 64, the first drain electrode 65, the second source electrode 74, and the second drain electrode 75.

[0058] By employing the configuration illustrated in FIG. 5, it is possible to easily fabricate the first TFT 60 having a relatively high mobility and the second TFT 70 having a relatively low mobility on the same substrate 10a.

[0059] The composition, crystal structure, thickness, and formation method of the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 are not particularly limited.

[0060] The first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 may have different compositions. Here, "different compositions" means that the types or composition ratios of metal elements contained in each layer are different. For example, the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 may each contain In and / or Sn, and the total atomic ratio of In and Sn to all metal elements in the second oxide semiconductor layer 71 may be smaller than the total atomic ratio of In and Sn to all metal elements in the first oxide semiconductor layer 61.

[0061] Alternatively, both the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 may be In—Ga—Zn—O-based oxide semiconductor layers, and the atomic ratio of In in the second oxide semiconductor layer 71 may be smaller than the atomic ratio of In in the first oxide semiconductor layer 61. In this case, in one of the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71, the atomic ratio of In and the atomic ratio of Zn to all metal elements may be the same.

[0062] Furthermore, the first oxide semiconductor layer 61 may contain Sn, and the second oxide semiconductor layer 71 may not contain Sn. Alternatively, the second oxide semiconductor layer 71 may contain Sn at a lower concentration than the first oxide semiconductor layer 61. In other words, the atomic ratio of Sn to all metal elements in the second oxide semiconductor layer 71 may be smaller than the atomic ratio of Sn in the first oxide semiconductor layer 61.

[0063] For example, an In-Ga-Zn-O based semiconductor layer (In:Ga:Zn=1:1:1, etc.) can be used as the second oxide semiconductor layer 71. For example, an In-Ga-Zn-O based semiconductor layer (In:Ga:Zn=3:1:2, etc.), an In-Sn-Zn-O based semiconductor layer, an In-Al-Sn-Zn-O based semiconductor layer, an In-W-Zn-O based semiconductor layer, an In-Sn-O based semiconductor layer, an In-Zn-O based semiconductor layer, an In-Ga-Sn-O based semiconductor layer, an In-Sn-Ti-Zn-O based semiconductor layer, etc. can be used as the first oxide semiconductor layer 61.

[0064] The first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 may have different crystal structures. For example, one of the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 may be an amorphous oxide semiconductor layer, and the other may be a crystalline oxide semiconductor layer containing a crystalline portion.

[0065] Even if the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 have the same ratio of metal elements, the mobility of these oxide semiconductor layers can be made different by varying the film formation method or film formation conditions. For example, when forming the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 by sputtering to form oxide semiconductor layers having the same ratio of metal elements, the atmosphere in the chamber (e.g., the flow rate ratio of oxygen and Ar supplied to the chamber) may be made different. Specifically, when forming the second oxide semiconductor layer 71, the flow rate ratio of oxygen to Ar may be set high (e.g., 80%), and when forming the first oxide semiconductor layer 61, the flow rate ratio of oxygen to Ar may be set lower than that of the second oxide semiconductor layer 71 (e.g., 20%). This allows the mobility of the second oxide semiconductor layer 71 to be lower than that of the first oxide semiconductor layer 61.

[0066] 6A to 6J, a method for manufacturing the active matrix substrate 10 having the first TFT 60 and the second TFT 70 illustrated in Fig. 5 will be described below. Figs. 6A to 6J are cross-sectional views illustrating the steps in the method for manufacturing the active matrix substrate 10.

[0067] 6A, a first light-shielding layer 3A and a second light-shielding layer 3B are formed on a substrate 10a. Specifically, a conductive film for the light-shielding layer (thickness: for example, 50 nm to 500 nm) is formed on an insulating substrate 10a by a sputtering method or the like, and then the conductive film for the light-shielding layer is patterned to form the first light-shielding layers 3A and 3B.

[0068] The substrate 10a may be, for example, a glass substrate or a heat-resistant plastic substrate (resin substrate).

[0069] The conductive film for the light-shielding layer can be, for example, a metal film containing an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy film containing these elements. A laminated film containing multiple films from these may also be used. Here, a metal film or alloy film containing Cu or Al is used as the conductive film for the light-shielding layer.

[0070] Next, as shown in Fig. 6B, an insulating base layer 4 is formed to cover the first light-shielding layer 3A and the second light-shielding layer 3B. The insulating base layer 4 can be formed by, for example, a CVD method. The thickness of the insulating base layer 4 is, for example, 200 nm or more and 600 nm or less.

[0071] The underlying insulating layer 4 may be a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy;x>y) layer, a silicon nitride oxide (SiNxOy;x>y) layer, or the like. The underlying insulating layer 4 may have a laminated structure. For example, a silicon nitride layer, a silicon nitride oxide layer, or the like may be formed on the substrate 10a side (lower layer) to prevent the diffusion of impurities and the like from the substrate 10a, and a silicon oxide layer, a silicon oxynitride layer, or the like may be formed on the layer above that (upper layer) to ensure insulation.

[0072] 6C, a second oxide semiconductor layer 71 is formed on the underlying insulating layer 4. Specifically, first, an oxide semiconductor film is deposited by sputtering, and then the oxide semiconductor film is patterned to form the second oxide semiconductor layer 71. Here, an In-Ga-Zn-O based semiconductor film (In:Ga:Zn=1:1:1) is used as the oxide semiconductor film for the second oxide semiconductor layer 71. The oxide semiconductor film can be patterned by wet etching using, for example, a PAN-based etching solution containing phosphoric acid, nitric acid, and acetic acid, or an oxalic acid-based etching solution.

[0073] Next, as shown in FIG. 6D, an insulating film (hereinafter referred to as a "first insulating film") F1 is deposited so as to cover the base insulating layer 4 and the second oxide semiconductor layer 71. The first insulating film F1 can be deposited by, for example, a CVD method. Here, a silicon oxide film is used as the first insulating film F1.

[0074] 6E, a first oxide semiconductor layer 61 is formed on the first insulating film F1. Specifically, first, an oxide semiconductor film is deposited by sputtering, and then the oxide semiconductor film is patterned, thereby forming the first oxide semiconductor layer 61. Here, an In-Ga-Zn-O based semiconductor film is used as the oxide semiconductor film for the first oxide semiconductor layer 61. As can be seen from the above description, for example, by making the atomic ratio of In in the first oxide semiconductor layer 61 larger than the atomic ratio of In in the second oxide semiconductor layer 71, the mobility of the first oxide semiconductor layer 61 can be made higher than that of the second oxide semiconductor layer 71 (that is, the mobility of the second oxide semiconductor layer 71 can be made lower than that of the first oxide semiconductor layer 61).

[0075] Next, as shown in FIG. 6F, an insulating film (hereinafter referred to as a "second insulating film") F2 is deposited so as to cover the first insulating film F1 and the first oxide semiconductor layer 61. The second insulating film F2 can be deposited by, for example, a CVD method. Here, a silicon oxide film is used as the second insulating film F2.

[0076] 6G, the first gate electrode 63 and the second gate electrode 73 are formed on the second insulating film F2. Specifically, a gate conductive film (thickness: for example, 50 nm to 500 nm) is formed on the second insulating film F2 by a sputtering method or the like, and then the gate conductive film is patterned to form the first gate electrode 63 and the second gate electrode 73. The gate conductive film may be a conductive film similar to the conductive film for the light-shielding layer.

[0077] 6H, the first insulating film F1 and the second insulating film F2 are patterned. Specifically, the first insulating film F1 and the second insulating film F2 are patterned using the resist mask (not shown) used in patterning the gate conductive film and the first oxide semiconductor layer 61 as a mask. Instead of the resist mask, the first gate electrode 63 and the second gate electrode 73 may be used as a mask.

[0078] The portion of the second insulating film F2 remaining between the first gate electrode 63 and the first oxide semiconductor layer 61 becomes the first gate insulating layer 62. The first gate insulating layer 62 has a single-layer structure including a third insulating layer L3 formed from the second insulating film F3. The portion of the first insulating film F1 and the second insulating film F2 remaining between the second gate electrode 73 and the second oxide semiconductor layer 71 becomes the second gate insulating layer 72. The second gate insulating layer 72 has a stacked structure including a first insulating layer L1 formed from the first insulating film F1 and a second insulating layer L2 formed from the second insulating film F2. The portion of the first insulating film F1 remaining between the first oxide semiconductor layer 61 and the base insulating layer 4 becomes the lower insulating layer 5.

[0079] Thereafter, the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 may be subjected to a resistance reduction treatment. The resistance reduction treatment is, for example, a plasma treatment. As a result of the resistance reduction treatment, the region of the first oxide semiconductor layer 61 that does not overlap with the first gate electrode 63 becomes a low-resistance region (first source contact region 61s and first drain contact region 61d) having a lower resistivity than the region overlapping with the first gate electrode 63 (channel region 61c). Similarly, the region of the second oxide semiconductor layer 71 that does not overlap with the second gate electrode 73 becomes a low-resistance region (second source contact region 71s and second drain contact region 71d) having a lower resistivity than the region overlapping with the second gate electrode 73 (channel region 71c). Note that the method of the resistance reduction treatment is not limited to the example given here.

[0080] Next, as shown in FIG. 6I, an interlayer insulating layer 6 is formed to cover the first oxide semiconductor layer 61, the second oxide semiconductor layer 71, the first gate insulating layer 62, the second gate insulating layer 72, the first gate electrode 63, and the second gate electrode 73. The interlayer insulating layer 6 can be formed by, for example, a CVD method. The interlayer insulating layer 6 can be formed using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. Using an insulating layer that reduces an oxide semiconductor, such as a silicon nitride layer, as the interlayer insulating layer 6 can maintain low resistivity in the regions of the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 that contact the interlayer insulating layer 6.

[0081] Thereafter, a first opening 6a, a second opening 6b, a third opening 6c, and a fourth opening 6d are formed in the interlayer insulating layer 6. Specifically, the first opening 6a, the second opening 6b, the third opening 6c, and the fourth opening 6d can be formed by a photolithography process and etching. The etching can be, for example, dry etching.

[0082] Next, as shown in FIG. 6J, a first source electrode 64 is formed on the interlayer insulating layer 6 and in the first opening 6a, and a first drain electrode 65 is formed on the interlayer insulating layer 6 and in the second opening 6b. At this time, a second source electrode 74 is formed on the interlayer insulating layer 6 and in the third opening 6c, and a second drain electrode 75 is formed on the interlayer insulating layer 6 and in the fourth opening 6d. Specifically, a source conductive film (thickness: e.g., 50 nm to 500 nm) is formed on the interlayer insulating layer 6 and in the first opening 6a, second opening 6b, third opening 6c, and fourth opening 6d, and then the source conductive film is patterned to form the first source electrode 63, first drain electrode 64, second source electrode 73, and second drain electrode 74. The source conductive film can be patterned by, for example, dry etching or wet etching. The source conductive film can be made of, for example, an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy containing these elements. For example, the source conductive film may have a three-layer structure of titanium film-aluminum film-titanium film, or a three-layer structure of molybdenum film-aluminum film-molybdenum film. The source conductive film is not limited to a three-layer structure, but may have a single layer, a two-layer structure, or a stacked structure of four or more layers. Here, a stacked film is used, with a Ti film (thickness: 15 nm to 70 nm) as the lower layer and a Cu film (thickness: 200 nm to 400 nm) as the upper layer.

[0083] Thereafter, an inorganic insulating layer 7 (thickness: e.g., 100 nm to 500 nm) is formed to cover the interlayer insulating layer 6, the first source electrode 63, the first drain electrode 64, the second source electrode 73, and the second drain electrode 74, thereby obtaining the active matrix substrate 10 illustrated in FIG. 5. The inorganic insulating layer 7 can be formed by, for example, a CVD method. For example, the insulating layers exemplified as specific examples of the interlayer insulating layer 6 can be used as the inorganic insulating layer 7. Here, a silicon nitride layer is used as the inorganic insulating layer 7.

[0084] [Other specific examples of the first TFT and the second TFT] Another specific example of the first TFT and the second TFT will be described with reference to FIG. 7. Here, the first TFT and the second TFT have a top-gate structure. FIG. 7 is a schematic cross-sectional view of an active matrix substrate 10. The right side of FIG. 7 shows a first TFT 60A, and the left side of FIG. 7 shows a second TFT 70A. The following description will focus on the differences between the first TFT 60A and the second TFT 70A and the first TFT 60 and the second TFT 70 shown in FIG. 5.

[0085] The first TFT 60A has a first oxide semiconductor layer 61, a first gate insulating layer 62, a first gate electrode 63, a first source electrode 64, and a first drain electrode 65. The first oxide semiconductor layer 61 of the first TFT 60A has a stacked structure including a lower oxide semiconductor layer 61L and an upper oxide semiconductor layer 61U disposed on the lower oxide semiconductor layer 61. The upper oxide semiconductor layer 61U has a mobility lower than that of the lower oxide semiconductor layer 61L.

[0086] The second TFT 70A has a second oxide semiconductor layer 71, a second gate insulating layer 72, a second gate electrode 73, a second source electrode 74, and a second drain electrode 75. The second oxide semiconductor layer 71 of the second TFT 70A is formed in the same layer as the upper oxide semiconductor layer 61U of the first oxide semiconductor layer 61.

[0087] The first gate insulating layer 62 of the first TFT 60A and the second gate insulating layer 72 of the second TFT 70A are formed in the same layer.

[0088] By employing the configuration illustrated in FIG. 7, it is also possible to easily fabricate a first TFT 60A with a relatively high mobility and a second TFT 70A with a relatively low mobility on the same substrate 10a.

[0089] The lower oxide semiconductor layer 61L and the upper oxide semiconductor layer 61U may have different compositions. For example, the lower oxide semiconductor layer 61L and the upper oxide semiconductor layer 61U may each contain In and / or Sn, and the total atomic ratio of In and Sn to all metal elements in the upper oxide semiconductor layer 61U may be smaller than the total atomic ratio of In and Sn to all metal elements in the lower oxide semiconductor layer 61L.

[0090] Alternatively, both the lower oxide semiconductor layer 61L and the upper oxide semiconductor layer 61U may be In—Ga—Zn—O-based oxide semiconductor layers, and the atomic ratio of In in the upper oxide semiconductor layer 61U may be smaller than the atomic ratio of In in the lower oxide semiconductor layer 61L. In this case, the atomic ratio of In and the atomic ratio of Zn to all metal elements may be the same in one of the lower oxide semiconductor layer 61L and the upper oxide semiconductor layer 61U.

[0091] The lower oxide semiconductor layer 61L may contain Sn, and the upper oxide semiconductor layer 61U may not contain Sn. Alternatively, the upper oxide semiconductor layer 61U may contain Sn at a lower concentration than the lower oxide semiconductor layer 61L. In other words, the atomic ratio of Sn to all metal elements in the upper oxide semiconductor layer 61U may be smaller than the atomic ratio of Sn in the lower oxide semiconductor layer 61L.

[0092] The upper oxide semiconductor layer 61U may be, for example, an In-Ga-Zn-O-based semiconductor layer (In:Ga:Zn=1:1:1, etc.). The lower oxide semiconductor layer 61L may be, for example, an In-Ga-Zn-O-based semiconductor layer (In:Ga:Zn=3:1:2, etc.), an In-Sn-Zn-O-based semiconductor layer, an In-Al-Sn-Zn-O-based semiconductor layer, an In-W-Zn-O-based semiconductor layer, an In-Sn-O-based semiconductor layer, an In-Zn-O-based semiconductor layer, an In-Ga-Sn-O-based semiconductor layer, or an In-Sn-Ti-Zn-O-based semiconductor layer.

[0093] The lower oxide semiconductor layer 61L and the upper oxide semiconductor layer 61U may have different crystal structures. For example, one of the lower oxide semiconductor layer 61L and the upper oxide semiconductor layer 61U may be an amorphous oxide semiconductor layer, and the other may be a crystalline oxide semiconductor layer containing a crystalline portion.

[0094] Even if the lower oxide semiconductor layer 61L and the upper oxide semiconductor layer 61U have the same ratio of metal elements, the mobility of these oxide semiconductor layers can be made different by using different film-forming methods or film-forming conditions. For example, when forming the lower oxide semiconductor layer 61L and the upper oxide semiconductor layer 61U by sputtering, oxide semiconductor layers having the same ratio of metal elements may be formed using different atmospheres in the chamber (e.g., the flow rate ratio of oxygen and Ar supplied to the chamber). Specifically, the flow rate ratio of oxygen to Ar may be set high (e.g., 80%) when forming the upper oxide semiconductor layer 61U, and the flow rate ratio of oxygen to Ar may be set low (e.g., 20%) when forming the lower oxide semiconductor layer 61L. This allows the mobility of the upper oxide semiconductor layer 61U to be lower than that of the lower oxide semiconductor layer 61L.

[0095] 8A to 8G, a method for manufacturing the active matrix substrate 10 having the first TFT 60A and the second TFT 70A illustrated in Fig. 7 will be described below. Figs. 8A to 8G are cross-sectional views illustrating the steps in the method for manufacturing the active matrix substrate 10.

[0096] First, in the same manner as described with reference to FIGS. 6A and 6B, the first light-shielding layer 3A, the second light-shielding layer 3B, and the underlying insulating layer 4 are formed on the substrate 10a.

[0097] Next, as shown in FIG. 8A, a lower oxide semiconductor layer 61L is formed on the underlying insulating layer 4. Specifically, first, an oxide semiconductor film is deposited by sputtering, and then the oxide semiconductor film is patterned to form the lower oxide semiconductor layer 61L. Here, a 10-nm-thick In—Ga—Zn—O-based semiconductor film (e.g., In:Ga:Zn=5:1:4) is used as the oxide semiconductor film for the lower oxide semiconductor layer 61L. Alternatively, a film containing Sn, such as a 10-nm-thick In—Sn—Zn—O-based semiconductor film (e.g., In2O3-SnO2-ZnO), may also be used.

[0098] 8B , an upper oxide semiconductor layer 61U is formed on the lower oxide semiconductor layer 61L, and a second oxide semiconductor layer 71 is formed on the base insulating layer 4. Specifically, first, an oxide semiconductor film is deposited by sputtering, and then the oxide semiconductor film is patterned to form the upper oxide semiconductor layer 61U and the second oxide semiconductor layer 71. Here, an In—Ga—Zn—O-based semiconductor film (e.g., In:Ga:Zn=1:1:1 or 4:2:4) having a thickness of 40 nm is used as the oxide semiconductor film for the upper oxide semiconductor layer 61U and the second oxide semiconductor layer 71.

[0099] 8C, an insulating film F is deposited so as to cover the base insulating layer 4, the first oxide semiconductor layer 61, and the second oxide semiconductor layer 71. The insulating film F can be deposited by, for example, a CVD method. Here, a silicon oxide film is used as the insulating film F.

[0100] 8D, the first gate electrode 63 and the second gate electrode 73 are formed on the insulating film F. Specifically, a gate conductive film (thickness: for example, 50 nm to 500 nm) is formed on the insulating film F by a sputtering method or the like, and then the gate conductive film is patterned to form the first gate electrode 63 and the second gate electrode 73. The gate conductive film may be a conductive film similar to the conductive film for the light-shielding layer.

[0101] 8E, the insulating film F is patterned. Specifically, the insulating film F is patterned using the resist mask (not shown) used in patterning the gate conductive film as a mask. The first gate electrode 63 and the second gate electrode 73 may be used as masks instead of the resist mask. Of the insulating film F, the portion remaining between the first gate electrode 63 and the first oxide semiconductor layer 61 becomes the first gate insulating layer 62, and the portion remaining between the second gate electrode 73 and the second oxide semiconductor layer 71 becomes the second gate insulating layer 72.

[0102] Thereafter, the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 may be subjected to a resistance reduction treatment. The resistance reduction treatment is, for example, a plasma treatment. As a result of the resistance reduction treatment, the region of the first oxide semiconductor layer 61 that does not overlap with the first gate electrode 63 becomes a low-resistance region (first source contact region 61s and first drain contact region 61d) having a lower resistivity than the region overlapping with the first gate electrode 63 (channel region 61c). Similarly, the region of the second oxide semiconductor layer 71 that does not overlap with the second gate electrode 73 becomes a low-resistance region (second source contact region 71s and second drain contact region 71d) having a lower resistivity than the region overlapping with the second gate electrode 73 (channel region 71c). Note that the method of the resistance reduction treatment is not limited to the example given here.

[0103] Next, as shown in FIG. 8F , an interlayer insulating layer 6 is formed to cover the first oxide semiconductor layer 61, the second oxide semiconductor layer 71, the first gate insulating layer 62, the second gate insulating layer 72, the first gate electrode 63, and the second gate electrode 73. The interlayer insulating layer 6 can be formed by, for example, a CVD method. The interlayer insulating layer 6 can be formed using, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. Using an insulating layer that reduces an oxide semiconductor, such as a silicon nitride layer, as the interlayer insulating layer 6 can maintain low resistivity in the regions of the first oxide semiconductor layer 61 and the second oxide semiconductor layer 71 that contact the interlayer insulating layer 6.

[0104] Thereafter, a first opening 6a, a second opening 6b, a third opening 6c, and a fourth opening 6d are formed in the interlayer insulating layer 6. Specifically, the first opening 6a, the second opening 6b, the third opening 6c, and the fourth opening 6d can be formed by a photolithography process and etching. The etching can be, for example, dry etching.

[0105] Next, as shown in FIG. 8G, a first source electrode 64 is formed on the interlayer insulating layer 6 and in the first opening 6a, and a first drain electrode 65 is formed on the interlayer insulating layer 6 and in the second opening 6b. At this time, a second source electrode 74 is formed on the interlayer insulating layer 6 and in the third opening 6c, and a second drain electrode 75 is formed on the interlayer insulating layer 6 and in the fourth opening 6d. Specifically, a source conductive film (thickness: e.g., 50 nm to 500 nm) is formed on the interlayer insulating layer 6 and in the first opening 6a, second opening 6b, third opening 6c, and fourth opening 6d, and then the source conductive film is patterned to form the first source electrode 63, first drain electrode 64, second source electrode 73, and second drain electrode 74. The source conductive film can be patterned by, for example, dry etching or wet etching. The source conductive film can be made of, for example, an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy containing these elements. For example, the source conductive film may have a three-layer structure of titanium film-aluminum film-titanium film, or a three-layer structure of molybdenum film-aluminum film-molybdenum film. The source conductive film is not limited to a three-layer structure, but may have a single layer, a two-layer structure, or a stacked structure of four or more layers. Here, a stacked film is used, with a Ti film (thickness: 15 nm to 70 nm) as the lower layer and a Cu film (thickness: 200 nm to 400 nm) as the upper layer.

[0106] Thereafter, an inorganic insulating layer 7 (thickness: e.g., 100 nm to 500 nm) is formed to cover the interlayer insulating layer 6, the first source electrode 63, the first drain electrode 64, the second source electrode 73, and the second drain electrode 74, thereby obtaining the active matrix substrate 10 illustrated in FIG. 7. The inorganic insulating layer 7 can be formed by, for example, a CVD method. For example, the insulating layers exemplified as specific examples of the interlayer insulating layer 6 can be used as the inorganic insulating layer 7. Here, a silicon nitride layer is used as the inorganic insulating layer 7.

[0107] [Gate driver configuration] A specific example of the configuration of the gate driver will be described. The gate driver may have various known configurations, but the configuration disclosed in U.S. Patent Application Publication No. 2020 / 0135132 will be used as an example.

[0108] FIG. 9 is a schematic plan view illustrating a liquid crystal display device 100A provided with a first gate driver 40A and a second gate driver 40B having the configuration disclosed in US Patent Application Publication No. 2020 / 0135132.

[0109] 9, the liquid crystal display device 100A has a display region DR defined by a plurality of pixels P, and a non-display region FR located on the periphery of the display region DR. The liquid crystal display device 100A also includes a first gate driver 40A and a second gate driver 40B that drive gate bus lines GL(1) to GL(i), and a source driver 50 that drives source bus lines SL(1) to SL(j).

[0110] The first gate driver 40A, the second gate driver 40B, and the source driver 50 are arranged in the non-display region FR. The first gate driver 40A and the second gate driver 40B are GDM circuits. The first gate driver 40A is arranged on the left side of the display region DR, and the second gate driver 40B is arranged on the right side of the display region DR. In other words, the first gate driver 40A and the second gate driver 40B are arranged on one end side and the other end side of the gate bus lines GL(1) to GL(i), respectively.

[0111] FIG. 10 is a diagram showing the overall configuration of the first gate driver 40A and the second gate driver 40B.

[0112] The first gate driver 40A and the second gate driver 40B each operate based on a four-phase clock signal consisting of a first gate clock signal GCK1, a second gate clock signal GCK2, a third gate clock signal GCK3, and a fourth gate clock signal GCK4.

[0113] The first gate driver 40A has a first shift register 41A including a first bistable circuit section 42A and a first buffer circuit section 43A. The first bistable circuit section 42A has a plurality of cascaded bistable circuits SR (denoted as SR(n-2), SR(n), SR(n+2), SR(n+4) in FIG. 10). The first buffer circuit section 43A has a plurality of buffer circuits Buff (denoted as Buff(n-2), Buff(n-1), Buff(n), Buff(n+1), Buff(n+2), Buff(n+3) in FIG. 10).

[0114] The number of bistable circuits SR in the first bistable circuit unit 42A is half the number i of pixel rows (i.e., i / 2). In contrast, the number of buffer circuits Buff in the first buffer circuit unit 43A is the same as the number i of pixel rows (i.e., i). Each bistable circuit SR in the first bistable circuit unit 42A corresponds to two buffer circuits Buff and controls the two buffer circuits Buff by providing its output signal to the two buffer circuits Buff.

[0115] The second gate driver 40B has a second shift register 41B including a second bistable circuit section 42B and a second buffer circuit section 43B. The second bistable circuit section 42B has a plurality of cascaded bistable circuits SR (denoted as SR(n-1), SR(n+1), SR(n+3) in FIG. 10). The second buffer circuit section 43B has a plurality of buffer circuits Buff (denoted as Buff(n-2), Buff(n-1), Buff(n), Buff(n+1), Buff(n+2), Buff(n+3) in FIG. 10).

[0116] The number of bistable circuits SR in the second bistable circuit section 42B is half the number i of pixel rows (i.e., i / 2). In contrast, the number of buffer circuits Buff in the second buffer circuit section 43B is the same as the number i of pixel rows (i.e., i). Each bistable circuit SR in the second bistable circuit section 42B corresponds to two buffer circuits Buff and controls the two buffer circuits Buff by providing its output signal to the two buffer circuits Buff.

[0117] As described above, the first buffer circuit unit 43A of the first gate driver 40A and the second buffer circuit unit 43B of the second gate driver 40B each have the same number of buffer circuits Buff as the number of pixel rows, so that the buffer circuits Buff are connected to both ends of each gate bus line GL. A four-phase clock signal is supplied to each of the first gate driver 40A and the second gate driver 40B. The same gate clock signal is supplied to two buffer circuits Buff connected to the same gate bus line GL. Each buffer circuit Buff receives the output signal of the corresponding bistable circuit SR and the corresponding gate clock signal, and generates a scanning signal to be supplied to the corresponding gate bus line GL. For example, in the first buffer circuit unit 43A, the buffer circuit Buff(n) corresponding to the nth gate bus line GL(n) receives the output signal of the bistable circuit S(n) and the first gate clock signal GCK1 to generate a scanning signal and supply it to the nth gate bus line GL(n). In addition, the buffer circuit Buff(n-1) corresponding to the (n-1)th gate bus line GL(n-1) receives the output signal of the bistable circuit S(n) and the fourth gate clock signal GCK4 to generate a scanning signal, which is supplied to the (n-1)th gate bus line GL(n-1).

[0118] Next, the configuration of the gate drivers will be described in more detail using the first gate driver 40A as an example. Figure 11 is a schematic circuit diagram showing the configuration of the first gate driver 40A.

[0119] The first bistable circuit section 42A of the first gate driver 40A includes cascaded bistable circuits SR(n) and SR(n+2). The output terminal of the bistable circuit SR(n) is connected to the input terminal of a buffer circuit Buff(n-1) corresponding to the (n-1)th gate bus line GL(n-1) and the input terminal of a buffer circuit Buff(n) corresponding to the nth gate bus line GL(n). The output terminal of the bistable circuit SR(n+2) is connected to the input terminal of a buffer circuit Buff(n+1) corresponding to the (n+1)th gate bus line GL(n+1) and the input terminal of a buffer circuit Buff(n+2) corresponding to the (n+2)th gate bus line GL(n+2). The fourth gate clock signal GCK4, the first gate clock signal GCK1, the second gate clock signal GCK2, and the third gate clock signal GCK3 are input to the buffer circuits Buff(n-1), Buff(n), Buff(n+1), and Buff(n+2), respectively.

[0120] 11, one bistable circuit SR and its corresponding two buffer circuits Buff constitute one unit circuit UC. The bistable circuit SR(n) and the buffer circuits Buff(n-1) and Buff(n) constitute one unit circuit UC, and the bistable circuit SR(n+2) and the buffer circuits Buff(n+1) and Buff(n+2) constitute another unit circuit UC.

[0121] The basic configuration of each unit circuit UC will be described with reference to Fig. 12. Fig. 12 is a circuit diagram showing the basic configuration of a unit circuit UC including a bistable circuit SR(n). The unit circuit UC shown in Fig. 12 includes the bistable circuit SR(n) and buffer circuits Buff(n-1) and Buff(n).

[0122] The bistable circuit SR(n) includes two N-channel thin-film transistors TA1 and TA2. The drain terminal of the thin-film transistor TA1 is connected to a high-level power supply line VDD, and the source terminal of the thin-film transistor TA2 is connected to a low-level power supply line VSS. The source terminal of the thin-film transistor TA1 and the drain terminal of the thin-film transistor TA2 are connected to each other, and the connection point between them corresponds to the output terminal of the bistable circuit SR(n). Node NAA(n), which includes this output terminal, will be referred to below as the "first state node."

[0123] The gate terminal of the thin-film transistor TA1 corresponds to the set terminal S, and the gate terminal of the thin-film transistor TA2 corresponds to the reset terminal R. The set terminal S is connected to the (n-2)th gate bus line GL(n-2), and the reset terminal R is connected to the (n+3)th gate bus line GL(n+3).

[0124] The bistable circuit SR(n) enters either a "set state" or a "reset state" by charging or discharging an electric charge in the capacitance connected to the first state node NAA(n). Specifically, when a high-level voltage is applied to the set terminal S, the bistable circuit SR(n) enters the "set state," in which the voltage of the first state node NAA(n) is high. When a high-level voltage is applied to the reset terminal R, the bistable circuit SR(n) enters the "reset state," in which the voltage of the first state node NAA(n) is low. A high-level signal is output from the output terminal of a bistable circuit SR(n) in the "set state."

[0125] The buffer circuit Buff(n-1) includes a buffer transistor TB1, which is an N-channel thin-film transistor, and a boost capacitor CbsA. A fourth gate clock signal GCK4 is applied to the drain terminal of the buffer transistor TB1. The gate terminal of the buffer transistor TB1 corresponds to the input terminal of the buffer circuit Buff(n-1) and is connected to the first state node NAA(n). The source terminal of the buffer transistor TB1 corresponds to the output terminal of the buffer circuit Buff(n-1) and is connected to the gate terminal of the buffer transistor TB1 via the boost capacitor CbsA and to the (n-1)th gate bus line GL(n-1).

[0126] The buffer circuit Buff(n) includes a buffer transistor TB2, which is an N-channel thin-film transistor, and a boost capacitor CbsB. The buffer circuit Buff(n) further includes an N-channel thin-film transistor MS. A first gate clock signal GCK1 is applied to the drain terminal of the buffer transistor TB2. The gate terminal of the buffer transistor TB2 is connected to the first-state node NAA(n) via the thin-film transistor MS. Of the conduction terminals of the thin-film transistor MS, the terminal connected to the first-state node NAA(n) corresponds to the input terminal of the buffer circuit Buff(n). The source terminal of the buffer transistor TB2 corresponds to the output terminal of the buffer circuit Buff(n), and is connected to the gate terminal of the buffer transistor TB2 via the boost capacitor CbsB, as well as to the (n)th gate bus line GL(n).

[0127] The gate terminal of the thin-film transistor MS is connected to a high-level power supply line VDD. Hereinafter, the voltage of the high-level power supply line VDD will be referred to as the "high-level power supply voltage" and will be denoted by the same reference symbol "VDD." If the thin-film transistor MS has a threshold voltage Vth(MS), it is in an off state when the voltages of both its source terminal and drain terminal are higher than VDD-Vth(MS).

[0128] Therefore, even if a pulse of the first gate clock signal GCK1 increases the voltage of the gate terminal of the buffer transistor TB2 of the buffer circuit Buff(n) via the boost capacitor CbsB, i.e., the voltage of the node (hereinafter referred to as the "second-state node") NAB(n) including the gate terminal, when the buffer transistor TB2 of the buffer circuit Buff(n) is in the on state, the voltage increase does not affect the voltage of the first-state node NAA(n). Also, even if a pulse of the fourth gate clock signal GCK4 increases the voltage of the gate terminal of the buffer transistor TB1 of the buffer circuit Buff(n-1) via the boost capacitor CbsA, i.e., the voltage of the first-state node NAA(n), when the buffer transistor TB1 of the buffer circuit Buff(n-1) is in the on state, the voltage increase does not affect the voltage of the second-state node NAB(n).

[0129] This is because the thin-film transistor MS, based on its characteristics as a field-effect transistor, operates as a transmission gate that transmits voltages equal to or less than VDD-Vth(MS) and does not transmit voltages exceeding VDD-Vth(MS). Operating as such a transmission gate, the thin-film transistor MS functions to prevent the boost effect at one of the first-state node NAA(n) and the second-state node NAB(n) from affecting the other node. Hereinafter, the thin-film transistor MS will also be referred to as a "boost isolation transistor."

[0130] Fig. 13 is a circuit diagram showing an example of the detailed configuration of a unit circuit UC including a bistable circuit SR(n). In the example shown in Fig. 13, the bistable circuit SR(n) has N-channel thin-film transistors M1, M2, M3, M5, M6, M6+, M8, M9, and M14. The set terminal S is connected to the (n-2)th gate bus line GL(n-2), and the reset terminal R is connected to the (n+3)th gate bus line GL(n+3).

[0131] The thin-film transistors M1 and M9 correspond to the thin-film transistors TA1 and TA2, respectively, shown in Fig. 12. The connection point of the thin-film transistors M1 and M9 forms the output terminal of the bistable circuit SR(n), and the node including this output terminal is the first-state node NAA(n).

[0132] The bistable circuit SR(n) also has a clear terminal CLR as an input terminal for a clear signal for initialization, and the gate terminals of the thin-film transistors M2 and M3 are connected to the clear terminal CLR. Note that, hereinafter, the node NB(n) including the connection point of the thin-film transistors M5 and M6 will be referred to as the "third state node."

[0133] The buffer circuit Buff(n-1) has the same configuration as the buffer circuit Buff(n-1) shown in FIG. 12 and includes an N-channel thin-film transistor (buffer transistor) M10A and a boost capacitor CbsA. A fourth gate clock signal GCK4 is applied to the drain terminal of the buffer transistor M10A. A source terminal of the buffer transistor M10A is connected to the (n-1)th gate bus line GL(n-1).

[0134] The buffer circuit Buff(n) has the same configuration as the buffer circuit Buff(n) shown in FIG. 12 and includes an N-channel thin-film transistor (buffer transistor) M10B, an N-channel thin-film transistor (boost isolation transistor) MS, and a boost capacitor CbsB. A first gate clock signal GCK1 is applied to the drain terminal of the buffer transistor M10B. The source terminal of the buffer transistor M10A is connected to the (n)th gate bus line GL(n). The gate terminal of the buffer transistor M10B is connected to the first-state node NAA(n) via the boost isolation transistor MS, and the node including this gate terminal is the second-state node NAB(n).

[0135] The operation of the gate driver having the configuration illustrated here is disclosed in U.S. Patent Application Publication No. 2020 / 0135132, and therefore will not be described here, the entire disclosure of which is incorporated herein by reference.

[0136] [Examples of application of the first and second TFTs] An example in which the above-described first TFT and second TFT are applied to a unit circuit UC shown in FIG. 13 will be described.

[0137] 13, a high-level power supply voltage is applied to one of the source terminal and drain terminal of the thin-film transistor M1, and a low-level voltage is applied to the other terminal for most of one frame. Also, a voltage exceeding the peak-to-peak voltage Vpp of the gate clock signal is applied between the source and drain of the thin-film transistors M2, M8, and M9.

[0138] Therefore, the thin film transistors M1, M2, M8, and M9 can be said to be circuit TFTs for which a particularly high source-drain breakdown voltage is desired (i.e., the strength of the drain-source electric field Eds becomes particularly high when the unit circuit UC is in operation), and therefore it is preferable to use the thin film transistors M1, M2, M8, and M9 as the second TFTs.

[0139] [About oxide semiconductors] The oxide semiconductor (also referred to as a metal oxide or an oxide material) contained in the oxide semiconductor layer of the oxide semiconductor TFT may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor whose c-axis is oriented substantially perpendicular to the layer surface.

[0140] The materials, structures, film formation methods, and configurations of oxide semiconductor layers having a stacked structure of the amorphous oxide semiconductor and the above-mentioned crystalline oxide semiconductors are described in, for example, JP 2014-0073911 A. The entire disclosure of JP 2014-0073911 A is incorporated herein by reference.

[0141] The oxide semiconductor layer may contain at least one metal element selected from the group consisting of In, Ga, and Zn. In this embodiment, the oxide semiconductor layer contains, for example, an In—Ga—Zn—O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such an oxide semiconductor layer can be formed from an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.

[0142] The In-Ga-Zn-O based semiconductor may be amorphous or crystalline, and a crystalline In-Ga-Zn-O based semiconductor in which the c-axis is oriented approximately perpendicular to the layer plane is preferred as the crystalline In-Ga-Zn-O based semiconductor.

[0143] The crystal structure of crystalline In-Ga-Zn-O-based semiconductors is disclosed, for example, in the aforementioned Japanese Patent Application Laid-Open Nos. 2014-0073911, 2012-134475, and 2014-2090627. For reference, the entire disclosures of Japanese Patent Application Laid-Open Nos. 2012-134475 and 2014-2090627 are incorporated herein by reference. TFTs having an In-Ga-Zn-O-based semiconductor layer have high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one-hundredth that of an a-Si TFT). Therefore, they are suitable for use as driver TFTs (e.g., TFTs included in a driver circuit provided on the same substrate as a display area, around a display area including multiple pixels) and pixel TFTs (TFTs provided in pixels).

[0144] The oxide semiconductor layer may contain other oxide semiconductors instead of In-Ga-Zn-O-based semiconductors. For example, it may contain In-Sn-Zn-O-based semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). In-Sn-Zn-O-based semiconductors are ternary oxides of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include an In-Al-Zn-O based semiconductor, an In-Al-Sn-Zn-O based semiconductor, a Zn-O based semiconductor, an In-Zn-O based semiconductor, a Zn-Ti-O based semiconductor, a Cd-Ge-O based semiconductor, a Cd-Pb-O based semiconductor, CdO (cadmium oxide), an Mg-Zn-O based semiconductor, an In-Ga-Sn-O based semiconductor, an In-Ga-O based semiconductor, a Zr-In-Zn-O based semiconductor, an Hf-In-Zn-O based semiconductor, an Al-Ga-Zn-O based semiconductor, a Ga-Zn-O based semiconductor, an In-Ga-Zn-Sn-O based semiconductor, an In-W-Zn-O based semiconductor, or the like. [Industrial Applicability]

[0145] According to the embodiment of the present invention, it is possible to provide an active matrix substrate that can suppress deterioration of the characteristics of oxide semiconductor TFTs in a gate drive circuit. [Explanation of symbols]

[0146] 1 Display panel 2 pixel TFT 3A 1st light shielding layer 4. Undercoat insulation layer 5 Lower insulating layer 6 Interlayer insulation layer 6a 1st opening 6b 2nd opening 6c 3rd opening 6d 4th opening 7. Inorganic insulating layer 10 Active matrix substrate (TFT substrate) 10a substrate 12 Light blocking layer 13 Lower insulating layer 19 Upper insulating layer 20 Counter substrate (color filter substrate) 30 Liquid crystal layer 40 Gate drive circuit (gate driver) 40A 1st Gate Driver 40B Second gate driver 41A First shift register 41B Second shift register 42A 1st bistable circuit section 42B 2nd bistable circuit section 43A First buffer circuit section 43B Second buffer circuit section 50 Source driver circuit (source driver) 60, 60A 1st TFT 61 First oxide semiconductor layer 61c First channel region 61s First source contact region 61d First drain contact region 61L Lower oxide semiconductor layer 61U Upper oxide semiconductor layer 62 First gate insulating layer 63 First gate electrode 64 First source electrode 65 First drain electrode 70, 70A 2nd TFT 71 Second oxide semiconductor layer 71c Second channel region 71s Second source contact area 71d Second drain contact region 72 Second gate insulating layer 73 Second gate electrode 74 Second source electrode 75 Second drain electrode 100 LCD display device DR display area FR hidden area P pixel GL Gate signal line (gate bus line) SL Source signal line (source bus line) PE pixel electrode CE common electrode UC Unit Circuit L1 First insulating layer L2 Second insulating layer L3 Third insulating layer F1 First insulating film F2 Second insulating film

Claims

1. A substrate; a plurality of gate signal lines supported by the substrate; a gate drive circuit that drives the plurality of gate signal lines; An active matrix substrate comprising: the gate drive circuit includes a shift register having a plurality of stages associated with the plurality of gate signal lines; each of the plurality of unit circuits constituting the plurality of stages includes a plurality of oxide semiconductor TFTs; The plurality of oxide semiconductor TFTs include at least one first TFT each including a first oxide semiconductor layer; at least one second TFT, each including a second oxide semiconductor layer, having a mobility lower than the mobility of the at least one first TFT; Including, the at least one second TFT includes an oxide semiconductor TFT, among the plurality of oxide semiconductor TFTs, that has the highest drain-source electric field strength when each unit circuit is in operation.

2. the at least one second TFT is n (n is an integer of 2 or more) second TFTs, 2. The active matrix substrate according to claim 1, wherein the n second TFTs are oxide semiconductor TFTs having the first to nth highest drain-source electric field strengths when the plurality of oxide semiconductor TFTs are ranked by the drain-source electric field strengths during operation of each unit circuit.

3. Each of the at least one first TFT comprises: the first oxide semiconductor layer including a first channel region, and a first source contact region and a first drain contact region located on both sides of the first channel region, respectively; a first gate electrode disposed on the first channel region of the first oxide semiconductor layer via a first gate insulating layer; and Each of the at least one second TFT comprises: the second oxide semiconductor layer including a second channel region, and a second source contact region and a second drain contact region located on both sides of the second channel region, respectively; a second gate electrode disposed on the second channel region of the second oxide semiconductor layer via a second gate insulating layer; 3. The active matrix substrate according to claim 1, wherein:

4. the second oxide semiconductor layer is formed as a layer separate from the first oxide semiconductor layer, The active matrix substrate according to claim 1 , wherein the mobility of the second oxide semiconductor layer is lower than the mobility of the first oxide semiconductor layer.

5. the second gate insulating layer has a stacked structure including a first insulating layer and a second insulating layer disposed on the first insulating layer, the first gate insulating layer includes a third insulating layer formed in the same layer as the second insulating layer, but does not include an insulating layer formed in the same layer as the first insulating layer; The active matrix substrate according to claim 4 , further comprising a lower insulating layer formed in the same layer as the first insulating layer and disposed between the first oxide semiconductor layer and the substrate.

6. the first oxide semiconductor layer and the second oxide semiconductor layer each contain In and / or Sn; 5. The active matrix substrate according to claim 4, wherein a total atomic ratio of In and Sn to all metal elements in the second oxide semiconductor layer is smaller than a total atomic ratio of In and Sn to all metal elements in the first oxide semiconductor layer.

7. 5. The active matrix substrate according to claim 4, wherein the first oxide semiconductor layer and the second oxide semiconductor layer both contain an In—Ga—Zn—O-based semiconductor, and an atomic ratio of In to all metal elements in the second oxide semiconductor layer is lower than an atomic ratio of In to all metal elements in the first oxide semiconductor layer.

8. the first oxide semiconductor layer has a stacked structure including a lower oxide semiconductor layer and an upper oxide semiconductor layer disposed on the lower oxide semiconductor layer and having a mobility lower than that of the lower oxide semiconductor layer; 3. The active matrix substrate according to claim 1, wherein the second oxide semiconductor layer is formed in the same layer as the upper oxide semiconductor layer of the first oxide semiconductor layer.

9. the lower oxide semiconductor layer and the upper oxide semiconductor layer each contain In and / or Sn, 9. The active matrix substrate according to claim 8, wherein a total atomic ratio of In and Sn to all metal elements in the upper oxide semiconductor layer is smaller than a total atomic ratio of In and Sn to all metal elements in the lower oxide semiconductor layer.

10. 9. The active matrix substrate according to claim 8, wherein the lower oxide semiconductor layer and the upper oxide semiconductor layer both contain an In—Ga—Zn—O-based semiconductor, and an atomic ratio of In to all metal elements in the upper oxide semiconductor layer is lower than an atomic ratio of In to all metal elements in the lower oxide semiconductor layer.

11. 3. The active matrix substrate according to claim 1, wherein the gate drive circuit is monolithically formed on the active matrix substrate.

12. A display device comprising the active matrix substrate according to claim 1 or 2.

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