Display device and method of manufacturing display device

Abstract

To improve a yield of a display device.SOLUTION: According to an embodiment, a display device includes: first and second subpixels arrayed in a first direction; a rib layer having first and second pixel apertures; and a partition located between the first subpixel and the second subpixel and disposed above the rib layer. The partition is split into first partition on the first subpixel side and a second partition on the second subpixel side by a slit extending in a second direction intersecting the first direction. The first partition includes: a lower portion having first side surface on the first subpixel side and a second side surfaces on the slit side; and an upper portion having a first end portion on the first subpixel side and a second end portion on the slit side, and being disposed on the lower portion. The first end portion protrudes from the first side surface. The second end portion does not protrude from the second side surface or protrudes from the second side surface with a protrusion length shorter than a protrusion length of the first end portion from the first side surface.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Techniques for improving the yield of such display devices are needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a manufacturing method thereof that can improve yield. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device includes first and second subpixels aligned in a first direction, a rib layer having a first pixel opening located in the first subpixel and a second pixel opening located in the second subpixel, and a partition wall located between the first and second subpixels and disposed above the rib layer. The partition wall is divided into a first partition wall on the first subpixel side and a second partition wall on the second subpixel side by a slit extending in a second direction intersecting the first direction. The first partition wall includes a lower portion having a first side surface on the first subpixel side and a second side surface on the slit side, and an upper portion having a first end portion on the first subpixel side and a second end portion on the slit side and disposed above the lower portion. The first end portion protrudes from the first side surface. The second end portion does not protrude from the second side surface or protrudes from the second side surface by a protrusion length shorter than the protrusion length of the first end portion from the first side surface.

[0006] Moreover, according to an embodiment, a manufacturing method of a display device includes forming a first lower electrode and a second lower electrode in a first subpixel and a second subpixel aligned in a first direction, respectively; forming a rib layer covering the first lower electrode and the second lower electrode; forming a first partition on the first subpixel side and a second partition on the second subpixel side between the first subpixel and the second subpixel, each of which includes a lower portion located above the rib layer and an upper portion whose both ends protrude from side surfaces of the lower portion, and which is separated by a slit extending in a second direction intersecting the first direction; and removing an end portion of the upper portion along the slit in at least one of the first partition and the second partition. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4]FIG. 4 is a schematic plan view showing some elements of the display device according to the first embodiment. [Figure 5] FIG. 5 is a schematic plan view showing an example of a configuration applicable to the partition wall according to the first embodiment. [Figure 6] FIG. 6 is a schematic plan view showing an example of a configuration applicable to the partition wall and the sealing layer according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view of the display device taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a schematic enlarged cross-sectional view of the first partition wall according to the first embodiment. [Figure 9] FIG. 9 is a flowchart showing an example of a method for manufacturing the display device according to the first embodiment. [Figure 10A] FIG. 10A is a schematic cross-sectional view showing a manufacturing process of the display device according to the first embodiment. [Figure 10B] FIG. 10B is a schematic cross-sectional view showing a step subsequent to FIG. 10A. [Figure 10C] FIG. 10C is a schematic cross-sectional view showing a step subsequent to FIG. 10B. [Figure 10D] FIG. 10D is a schematic cross-sectional view showing a step subsequent to FIG. 10C. [Figure 11A] FIG. 11A is a schematic cross-sectional view showing the partition wall immediately after its formation. [Figure 11B] FIG. 11B is a schematic cross-sectional view showing a step of removing the upper edge along the slit. [Figure 11C] FIG. 11C is a schematic cross-sectional view showing a step subsequent to FIG. 11B. [Figure 11D] FIG. 11D is a schematic cross-sectional view showing a step subsequent to FIG. 11C. [Figure 11E] FIG. 11E is a schematic cross-sectional view showing a step subsequent to FIG. 11D. [Figure 12A] FIG. 12A is a schematic cross-sectional view showing a step for providing pixel openings in a rib layer. [Figure 12B] FIG. 12B is a schematic cross-sectional view showing a step subsequent to FIG. 12A. [Figure 13A] FIG. 13A is a schematic cross-sectional view showing a step for removing the rib layer in the terminal portion. [Figure 13B] FIG. 13B is a schematic cross-sectional view showing a step subsequent to FIG. 13A. [Figure 14A] FIG. 14A is a schematic cross-sectional view showing a process for forming a display element. [Figure 14B] FIG. 14B is a schematic cross-sectional view showing a step subsequent to FIG. 14A. [Figure 14C] FIG. 14C is a schematic cross-sectional view showing a step subsequent to FIG. 14B. [Figure 14D] FIG. 14D is a schematic cross-sectional view showing a step subsequent to FIG. 14C. [Figure 15] FIG. 15 is a diagram for explaining the effects of the first embodiment. [Figure 16] FIG. 16 is a diagram for explaining the effects of the first embodiment. [Figure 17] FIG. 17 is a schematic cross-sectional view of a first partition wall according to the second embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view of a first partition wall according to the third embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view of a first partition wall according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for clarity of explanation, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to circular, and may be other shapes such as rectangular, square, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1 (first subpixel), a green subpixel SP2 (second subpixel), and a red subpixel SP3 (third subpixel). The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] In the display area DA, a plurality of scanning lines G that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines S that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL are arranged. In Fig. 1, the scanning lines G and the power supply lines PL extend in the X direction, and the signal lines S extend in the Y direction, but this is not limiting.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line G. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line S, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3 that constitute one pixel PX. In the example of Fig. 2, the subpixels SP1 and SP3 are aligned in the Y direction. Furthermore, the subpixels SP1 and SP3 are aligned with the subpixel SP2 in the X direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 (first to third pixel openings) in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel openings AP1 and AP3 are quadrangles with the same area. On the other hand, the pixel opening AP2 is a rectangle that is longer in the Y direction than the pixel openings AP1 and AP3. However, the shapes of the pixel openings AP1, AP2, and AP3 are not limited to this example.

[0022] The subpixel SP1 includes a lower electrode LE1 (first lower electrode), an upper electrode UE1 (first upper electrode), and an organic layer OR1 (first organic layer) that overlap with the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2 (second lower electrode), an upper electrode UE2 (second upper electrode), and an organic layer OR2 (second organic layer) that overlap with the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3 (third lower electrode), an upper electrode UE3 (third upper electrode), and an organic layer OR3 (third organic layer) that overlap with the pixel aperture AP3.

[0023] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 (first display element) of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 (second display element) of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 (third display element) of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] A conductive partition wall 6 is disposed above the rib layer 5. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6 entirely overlaps the rib layer 5 and has the same planar shape as the rib layer 5. The partition wall 6 surrounds the subpixels SP1, SP2, and SP3.

[0025] As will be described in detail later, the partition wall 6 has a plurality of slits SL extending in the Y direction. In the example of Fig. 2, the sub-pixels SP1, SP2, and SP3 that make up one pixel PX are arranged between two slits SL. However, the arrangement of the slits SL is not limited to this example.

[0026] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines G, signal lines S, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0027] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The peripheral edges of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0028] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. That is, the partition wall 6 has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0029] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0030] 3, the upper portion 62 includes a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, the present invention is not limited to this, and the first top layer 65 and the second top layer 66 may have the same width.

[0031] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0032] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0033] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0034] Sealing layers SE11, SE12, and SE13 (first to third sealing layers) are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6 around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6 around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6 around it.

[0035] 3, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6. In addition, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6.

[0036] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0037] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0038] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive). Electrodes constituting the touch panel may be disposed on the sealing layer SE2.

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0040] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0041] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0042] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0045] The first top layer 65 of the partition wall 6 is formed of, for example, a metal material. The second top layer 66 of the partition wall 6 is formed of, for example, a conductive oxide. Examples of the metal material that can be used to form the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the second top layer 66 include ITO or IZO. The upper portion 62 may include three or more layers or may be formed of a single layer. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0046] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal of the signal line S is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0049] 4 is a schematic plan view showing some elements of the display device DSP. The partition walls 6 and the upper electrodes UE1, UE2, and UE3 constitute a common electrode CE that applies a common voltage to the display elements DE1, DE2, and DE3. The common electrode CE has, for example, a circular shape and entirely overlaps the display area DA.

[0050] The common electrode CE has a plurality of slits SL, at least one end of which reaches the outer edge (the outline in a plan view) of the common electrode CE. In the example of Fig. 4, both ends of the slits SL reach the outer edge of the common electrode CE. This divides the common electrode CE into a plurality of segments SG spaced apart by each slit SL.

[0051] 4, the slits SL extend in the Y direction. As another example, the slits SL may extend parallel to the X direction. There is no particular limitation on the number of slits SL provided in the common electrode CE.

[0052] The intervals between the slits SL in the X direction are, for example, constant. In this case, the width of each segment SG in the X direction is also constant. As another example, the intervals between the slits SL and the width of the segments SG do not have to be constant.

[0053] Each segment SG has a first end Ea and a second end Eb in the extension direction of the slit SL (Y direction in this embodiment). The first end Ea is connected to a power supply line PW provided in the peripheral area SA. The power supply line PW is connected to a terminal portion T. A common voltage is applied to each segment SG from the terminal portion T via the power supply line PW. In the example of FIG. 4, the second ends Eb of each segment SG are separated by the slit SL and are not connected by a conductive member such as the power supply line PW.

[0054] 5 is a schematic plan view showing an example of a configuration applicable to the partition wall 6 according to this embodiment. The slit SL is provided in a portion of the partition wall 6 that extends parallel to the Y direction.

[0055] 5, a slit SL is provided in each portion of the partition wall 6 that is located between pixels PX adjacent in the X direction. That is, each slit SL passes between one subpixel SP1, SP3 and the other subpixel SP2 of two pixels PX adjacent in the X direction.

[0056] The form of the slits SL is not limited to the example in Fig. 5. For example, two or more pixels PX aligned in the X direction may be positioned between adjacent slits SL.

[0057] 6 is a schematic plan view showing an example of the relationship between the sealing layers SE11, SE12, and SE13 and the slits SL. The sealing layers SE11 and SE12 are formed in an island shape in the subpixels SP1 and SP3, respectively. The sealing layer SE12 is formed continuously across, for example, multiple subpixels SP2 aligned in the Y direction. As another example, the sealing layer SE12 may be formed for each subpixel SP2.

[0058] The ends of the sealing layers SE11, SE12, and SE13 are entirely located above the partition wall 6. In the example of Fig. 6, none of the sealing layers SE11, SE12, and SE13 overlaps with the slit SL. However, at least one of the sealing layers SE11, SE12, and SE13 may overlap with the slit SL.

[0059] The slits SL extend in the Y direction between the sealing layers SE11 and SE12 and between the sealing layers SE13 and SE12. The portion of the partition 6 where the slits SL are provided is divided by the slits SL into a first partition 6A on the subpixel SP1 side (or subpixel SP3 side) and a second partition 6B on the subpixel SP2 side.

[0060] Fig. 7 is a schematic cross-sectional view of the display device DSP taken along line VII-VII in Fig. 6. In this figure, elements below the organic insulating layer 12 and elements above the resin layer RS1 are omitted.

[0061] 7, each of the partition walls 6A and 6B includes a lower portion 61 and an upper portion 62. In each of the partition walls 6A and 6B, the lower portion 61 includes a bottom layer 63 and an axial layer 64, and the upper portion 62 includes a first top layer 65 and a second top layer 66.

[0062] An end E11 of the sealing layer SE11 is located above the first partition 6A. An end E12 of the sealing layer SE12 is located above the second partition 6B. The sealing layer SE11 continuously covers the stacked film FL1 of the subpixel SP1 and a part of the first partition 6A. The sealing layer SE12 continuously covers the stacked film FL2 of the subpixel SP2 and a part of the second partition 6B.

[0063] For example, the rib layer 5 does not open at the slits SL. In this case, the slits SL entirely overlap the rib layer 5. For example, the slits SL are filled with the resin layer RS1. The resin layer RS1 contacts the rib layer 5 at the slits SL.

[0064] The lower electrodes LE1, LE2, and LE3 do not overlap the slits SL, so that external light L incident on the slits SL is transmitted downward without being blocked by the partition walls 6 and the lower electrodes LE1, LE2, and LE3.

[0065] 8 is a schematic enlarged cross-sectional view of a first partition 6A according to this embodiment. The axis layer 64 of the first partition 6A has a first side surface 64a on the subpixel SP1 side and a second side surface 64b on the slit SL side. The upper portion 62 of the first partition 6A has a first end portion 62a on the subpixel SP1 side and a second end portion 62b on the slit SL side. The bottom layer 63 of the first partition 6A has a third end portion 63a on the subpixel SP1 side and a fourth end portion 63b on the slit SL side.

[0066] The first end 62a and the second end 62b include the ends of the first top layer 65 and the second top layer 66. In the example of FIG. 8 , the end of the second top layer 66 is slightly set back from the end of the first top layer 65 at the first end 62a. Furthermore, the end of the first top layer 65 and the end of the second top layer 66 are aligned at the second end 62b. This example is not limiting, and the end of the first top layer 65 and the end of the second top layer 66 may be aligned at the first end 62a. Furthermore, the end of the first top layer 65 and the end of the second top layer 66 may be misaligned at the second end 62b.

[0067] The first end 62a protrudes from the first side surface 64a. That is, the portion of the first partition 6A on the subpixel SP1 side has an overhanging shape similar to the partition 6 shown in FIG. 3. On the other hand, the second end 62b does not protrude from the second side surface 64b. In the example of FIG. 8, the second end 62b is aligned with the second side surface 64b. As another example, the second end 62b may be recessed from the second side surface 64b.

[0068] The third end 63a protrudes from the first side surface 64a. On the other hand, the fourth end 63b does not protrude from the second side surface 64b. In the example of FIG. 8, the fourth end 63b is aligned with the second side surface 64b. As another example, the fourth end 63b may be recessed from the second side surface 64b.

[0069] At least a portion of the third end 63a is covered by the upper electrode UE1. In the example of FIG. 8, a portion of the first side surface 64a is also covered by the upper electrode UE1. The portion of the first side surface 64a that is not covered by the upper electrode UE1 and the first end 62a are covered by the sealing layer SE11. As in the example of FIG. 3, a gap may be formed between the sealing layer SE11 and the upper portion 62. As another example, the stacked film FL1 may be present in at least a portion of this gap. The second end 62b, the fourth end 63b, and the second side surface 64b are covered by the resin layer RS1 (see FIG. 7).

[0070] The second partition 6B has a shape symmetrical to the first partition 6A with respect to the slit SL. That is, the side of the second partition 6B on the subpixel SP2 side is an overhang, and the side on the slit SL side is not an overhang.

[0071] Next, an example of a manufacturing method of the display device DSP will be described. Fig. 9 is a flowchart showing an example of a manufacturing method of the display device DSP. Figs. 10A to 10D, 11A to 11E, 12A and 12B, 13A and 13B, and 14A to 14D are schematic cross-sectional views showing the manufacturing process of the display device DSP. In these cross-sectional views, elements below the organic insulating layer 12 are omitted.

[0072] In manufacturing the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10 (step PR1 in FIG. 9). Next, as shown in FIG. 10A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR2 in FIG. 9).

[0073] 10B, a rib layer 5 is formed to cover the lower electrodes LE1, LE2, and LE3 (step PR3 in FIG. 9). At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0074] After the formation of the rib layer 5, a step for forming the partition walls 6 is performed (step PR4 in FIG. 9). In step PR4, as shown in FIG. 10C, a first layer L1 to be processed into the bottom layer 63, a second layer L2 to be processed into the shaft layer 64, a third layer L3 to be processed into the first top layer 65, and a fourth layer L4 to be processed into the second top layer 66 are formed in this order on the rib layer 5. Furthermore, a resist R0 is disposed on the fourth layer L4. The resist R0 is patterned into the shape of the partition walls 6. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed by, for example, sputtering.

[0075] Then, using the resist R0 as a mask, the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 are patterned. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, the patterning may include wet etching to remove portions of the fourth layer L4 exposed by the resist R0, dry etching to remove portions of the first layer L1, the second layer L2, and the third layer L3 exposed by the resist R0, and wet etching to reduce the width of the second layer L2.

[0076] After step PR4, the partition walls 6 are formed as shown in FIG. 10D. After the partition walls 6 are formed, the resist R0 is removed (peeled off). In the wet etching that reduces the width of the second layer L2 described above, the second top layer 66 (fourth layer L4) may also be slightly eroded. When this erosion occurs, the width of the second top layer 66 becomes smaller than the width of the first top layer 65.

[0077] The above-described partition walls 6A and 6B are also formed by the steps shown in Figures 10C and 10D. Figure 11A shows the partition walls 6A and 6B immediately after formation. At this point, in both partition walls 6A and 6B, the second end 62b of the top layer 62 and the fourth end 63b of the bottom layer 63 both protrude from the second side surface 64b of the shaft layer 64.

[0078] After step PR4, the end portions of the upper portions 62 of the partition walls 6A and 6B along the slits SL are removed (step PR5 in FIG. 9). In step PR5, for example, the method shown in FIGS. 11B to 11E can be applied.

[0079] 11B, a resist R1 (first resist) is formed to cover the rib layer 5 and the partition walls 6A and 6B. The resist R1 has a groove GR1 shaped to correspond to the second end 62b (portion protruding from the second side surface 64b) of the upper portion 62. The second end 62b is exposed from the resist R1 through the groove GR1. Meanwhile, the first end 62a of the upper portion 62 is covered by the resist R1. The groove GR1 extends, for example, in the Y direction along the slit SL.

[0080] Next, the portions of the upper portion 62 that are exposed from the resist R1 through the grooves GR1 are removed by a first etching. After the first etching, the resist R1 is removed (peeled off). As a result, as shown in FIG. 11C, the second ends 62b of the partition walls 6A and 6B are retracted to a position where they are aligned with the second side surfaces 64b.

[0081] The first etch may be a wet or dry etch that attacks both the first top layer 65 and the second top layer 66. As another example, the first etch may include a wet or dry etch on the second top layer 66 and a wet or dry etch on the first top layer 65.

[0082] 11D, a resist R2 (second resist) is formed to cover the rib layer 5 and the partition walls 6A and 6B. The resist R2 has a groove GR2 shaped to correspond to the fourth end 63b (portion protruding from the second side surface 64b) of the bottom layer 63. The fourth end 63b is exposed from the resist R2 through the groove GR2. Meanwhile, the third end 63a of the bottom layer 63 is covered by the resist R2. The groove GR2 extends, for example, in the Y direction along the slit SL.

[0083] Next, the portions of the bottom layer 63 exposed from the resist R2 through the grooves GR2 are removed by a second etching. After the second etching, the resist R2 is removed (peeled off). As a result, as shown in FIG. 11E, the fourth ends 63b of the partition walls 6A and 6B are retracted to a position where they are aligned with the second side surfaces 64b.

[0084] 11A to 11E is performed on, for example, all of the partitions 6A, 6B separated by the slits SL provided in the partitions 6. As another example, the step PR5 may be performed on only some of the partitions 6A, 6B separated by some of the slits SL.

[0085] Note that a portion of the first groove portion GR1 and the second groove portion GR2 may overlap with the shaft layer 64 in a plan view. In this case, the portion of the shaft layer 64 that overlaps with the first groove portion GR1 or the second groove portion GR2 may be eroded during the first etching or the second etching.

[0086] After step PR5, a step for providing pixel openings AP1, AP2, and AP3 is performed (step PR6 in FIG. 9). FIGS. 12A and 12B show an example of the flow of step PR6. In step PR6, as shown in FIG. 12A, a resist R3 is formed to cover the partition wall 6. The resist R3 has openings APx1, APx2, and APx3 that overlap with the lower electrodes LE1, LE2, and LE3, respectively.

[0087] Furthermore, the rib layer 5 is etched using the resist R3 as a mask. The etching is, for example, dry etching, but may be a combination of dry etching and wet etching. By this etching, pixel openings AP1, AP2, and AP3 having shapes corresponding to the openings APx1, APx2, and APx3 are formed in the rib layer 5, as shown in FIG. 12B. Thereafter, the resist R3 is removed (peeled off).

[0088] After step PR6, a step is performed to remove the rib layer 5 from the terminal portion T (step PR7 in FIG. 9). FIGS. 13A and 13B show an example of the flow of step PR7.

[0089] 13A and 13B, the terminal portion T includes a conductive pad PD. The pad PD is disposed on an insulating layer 110 made of, for example, an inorganic insulating material. The pad PD and the insulating layer 110 are included in, for example, the circuit layer 11 shown in FIG. 3. For example, the periphery of the pad PD is covered with an organic insulating layer 12.

[0090] 13A, when step PR6 is completed, the pads PD are covered with the rib layer 5. In step PR7, a resist R4 having an opening above the pads PD is placed on the rib layer 5. The resist R4 has an opening APt0 that overlaps with the pads PD.

[0091] Furthermore, the rib layer 5 is etched using the resist R4 as a mask. The etching is, for example, dry etching. As a result, as shown in FIG. 13B, a terminal opening APt that exposes the pad PD is formed in the rib layer 5. After the dry etching, the resist R4 is removed (peeled off).

[0092] In addition, the process PR7 may be to form openings in the rib layer 5 to expose pads other than the terminal portions T. Examples of such pads include test pads for testing image display.

[0093] After step PR7, steps for forming display elements DE1, DE2, and DE3 are performed (steps PR8, PR9, and PR10 in FIG. 9). Figures 14A to 14D show an example of the flow of steps PR8, PR9, and PR10.

[0094] To form the display element DE1, first, as shown in FIG. 14A, a laminated film FL1 and a sealing layer SE11 are formed over the entire substrate 10. As shown in FIG. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD. The laminated film FL1 is divided into multiple portions by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided portion of the laminated film FL1 and the partition walls 6.

[0095] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R5 is disposed on the sealing layer SE11, as shown in Fig. 14A. The resist R5 covers the subpixel SP1 and part of the partition wall 6 around it.

[0096] Then, etching is performed using the resist R5 as a mask. As shown in FIG. 14B, this etching removes the stacked film FL1 and the sealing layer SE11 in portions exposed by the resist R5. This forms a display element DE1 in the subpixel SP1. This etching may include wet etching or dry etching, which is performed sequentially on the sealing layer SE11, cap layer CP1, upper electrode UE1, and organic layer OR1. After this etching, the resist R5 is removed (peeled off).

[0097] Display elements DE2 and DE3 can be formed using the same procedure as display element DE1. That is, when display element DE2 is formed, a laminated film FL2 and a sealing layer SE12 are formed over the entire mother substrate MB. As shown in FIG. 3, the laminated film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2. By patterning the laminated film FL2 and the sealing layer SE2, display element DE2 is formed in subpixel SP2, as shown in FIG. 14C.

[0098] In forming the display element DE3, a laminated film FL3 and a sealing layer SE13 are formed over the entire mother substrate MB. As shown in Fig. 3, the laminated film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3. By patterning the laminated film FL3 and the sealing layer SE13, the display element DE3 is formed in the subpixel SP3, as shown in Fig. 14D.

[0099] Although it is assumed here that the display elements DE1, DE2, and DE3 are formed in this order, the display elements DE1, DE2, and DE3 may be formed in a different order.

[0100] After step PR10, a resin layer RS1, a sealing layer SE2, and a resin layer RS2 are formed in this order (step PR11 in FIG. 9). The resin layers RS1 and RS2 can be formed by, for example, an inkjet method. The sealing layer SE2 can be formed by, for example, CVD. The display device DSP is completed through the above steps.

[0101] Here, some effects achieved by the display device DSP according to this embodiment will be described. 15 and 16 are diagrams for explaining the effects of the display device DSP according to this embodiment. An electronic device incorporating the display device DSP may include an antenna AT1 for near-field communication (NFC). The antenna AT1 is disposed, for example, facing the rear surface of the display device DSP (the lower surface of the substrate 10 shown in FIG. 3), and wirelessly communicates with an antenna AT2 of another electronic device via the display device DSP.

[0102] During wireless communication between the antennas AT1 and AT2, the magnetic field M1 generated by the antenna AT1 generates an eddy current I in the common electrode CE. The eddy current I generates a magnetic field M2 that cancels out the magnetic field M1, thereby attenuating the signal strength. This can reduce communication sensitivity when wireless communication is performed via the display device DSP. In particular, when the lattice-shaped partition walls 6, primarily made of a metal material, are formed over the entire display area DA, the common electrode CE has low resistance. This generates a large eddy current I and the accompanying strong magnetic field M2, which can easily reduce communication sensitivity.

[0103] In contrast, in this embodiment, the common electrode CE is divided into multiple segments SG by slits SL. In this case, large eddy currents are less likely to occur in the common electrode CE, thereby suppressing a decrease in communication sensitivity. Although eddy currents may occur in each segment SG, the impact of these eddy currents on communication sensitivity is minor compared to the eddy current I that occurs throughout the entire undivided common electrode CE.

[0104] Furthermore, electronic devices incorporating the display device DSP may include an optical sensor SN, such as an illuminance sensor, that detects external light. When such an optical sensor SN is disposed on the rear side of the display device DSP, the display device DSP needs to be translucent.

[0105] However, each of the lower electrodes LE1, LE2, and LE3 includes the above-mentioned reflective layer. Furthermore, the partition wall 6, at least a part of which is made of a metal material, has a light-shielding property. Therefore, most of the light incident on the display surface of the display device DSP can be reflected or blocked without being transmitted to the rear surface.

[0106] In contrast, when the partition walls 6 are provided with slits SL as in this embodiment, part of the light incident on the display surface, such as external light L shown in Fig. 7, is transmitted through the slits SL to the rear surface side of the display device DSP, thereby improving the light transmittance of the display device DSP.

[0107] As described above, according to this embodiment, it is possible to provide a display device DSP that is compatible with antennas and optical sensors for wireless communication. Furthermore, as will be described below, according to this embodiment, it is possible to improve the yield of the display device DSP.

[0108] In this embodiment, step PR5 shown in FIGS. 11A to 11E retracts the second end 62b of the partition walls 6A and 6B along the slit SL to near the second side surface 64b. If this step were not included, steps PR8 to PR10 would result in the stacked films FL1, FL2, and FL3, the sealing layers SE11, SE12, and SE13, and the resist for processing these layers being formed on the partition walls 6A and 6B, which have overhanging side portions, as shown in FIG. 11A. In this case, air bubbles may be trapped below the second end 62b along the slit SL. If these air bubbles burst during the drying of the resist under reduced pressure, areas that should be covered by the resist are exposed, and these areas may be damaged by subsequent etching.

[0109] Furthermore, if the side portions of the partition walls 6A, 6B along the slits SL are overhanging, air bubbles may be trapped below the second end portion 62b during the formation of the resin layer RS1. Such air bubbles may cause the resin layer RS1 to have an abnormal shape. For example, if air bubbles escape from the resin layer RS1, a depression along the slits SL may be formed in the resin layer RS1.

[0110] In contrast, when the second ends 62b of the partition walls 6A, 6B along the slits SL are recessed in step PR5 as in this embodiment, the above-mentioned bubbles are less likely to get mixed into the resist or below the resin layer RS1, which suppresses shape abnormalities near the slits SL due to bubbles and improves the yield of the display devices DSP.

[0111] 11D and 11E, in this embodiment, the fourth end 63b of the bottom layer 63 along the slit SL also retreats to the vicinity of the second side surface 64b. In this case, the transmission area of ​​the slit SL increases, and the light transmittance of the display device DSP can be further improved.

[0112] [Second embodiment] 11A to 11E is performed between step PR4 of forming the partition walls 6 and step PR6 of forming pixel openings AP1, AP2, and AP3 in the rib layer 5. However, the timing of performing step PR5 is not limited to this example.

[0113] Step PR5 can also be performed together with one or both of step PR6 for forming pixel openings AP1, AP2, AP3 in the rib layer 5 and step PR7 for forming a terminal opening APt in the rib layer 5.

[0114] For example, the first etching performed on the upper layer 62 in step PR5 may be the same as the etching performed to form pixel openings AP1, AP2, and AP3 in the rib layer 5 in step PR6. Furthermore, the second etching performed on the bottom layer 63 in step PR5 may be the same as the etching performed to form terminal openings APt in the rib layer 5 in step PR7. In these cases, the resist R3 shown in FIGS. 12A and 12B may be used as the resist R1 (first resist) shown in FIG. 11B. The resist R4 shown in FIG. 13A may be used as the resist R2 (second resist) shown in FIG. 11D.

[0115] As another example, the first etching may be performed in step PR7 to form the terminal opening APt in the rib layer 5, and the second etching may be performed after step PR7. In this case, the resist R4 shown in FIG. 13A may be used as the resist R1 shown in FIG. 11B.

[0116] As yet another example, the first etching may be performed before step PR6, and the second etching may be performed in step PR6 to form pixel openings AP1, AP2, and AP3 in the rib layer 5. In this case, the resist R3 shown in FIG. 12A may be used as the resist R2 shown in FIG. 11D.

[0117] As described above, at least one of the etching steps for the rib layer 5 in steps PR6 and PR7 serves as at least one of the first etching and the second etching, so that it is possible to reduce the number of manufacturing steps for the display device DSP.

[0118] The shapes of the partition walls 6A and 6B are not limited to those shown in Figures 7 and 8. In the following third to fifth embodiments, other shapes that can be applied to the partition walls 6A and 6B will be disclosed.

[0119] [Third embodiment] 17 is a schematic cross-sectional view of a first partition wall 6A according to the third embodiment. In this figure, elements other than the organic insulating layer 12, the lower electrode LE1, the rib layer 5, and the first partition wall 6A are omitted. The second partition wall 6B can have the same configuration as the first partition wall 6A.

[0120] 17, the second end 62b of the top layer 62 protrudes from the second side surface 64b of the shaft layer 64. Also, the fourth end 63b of the bottom layer 63 protrudes from the second side surface 64b.

[0121] Here, the protruding length of the first end 62a from the first side surface 64a is defined as L1a, the protruding length of the second end 62b from the second side surface 64b is defined as L1b, the protruding length of the third end 63a from the first side surface 64a is defined as L2a, and the protruding length of the fourth end 63b from the second side surface 64b is defined as L2b.

[0122] In the example of FIG. 17, the protruding length L1a is greater than the protruding length L2a (L1a > L2a). Also, the protruding length L1b is smaller than the protruding length L1a (L1b < L1a). Further, the protruding length L2b is smaller than the protruding length L2a (L2b < L2a). For example, the protruding lengths L1b and L2b are equal.

[0123] Thus, even when the second end portion 62b and the fourth end portion 63b protrude from the second side surface 64b, when the protruding length L1b is small, generation of bubbles during formation of a resist or the resin layer RS1 that covers the partition walls 6A and 6B can be suppressed as in the first embodiment. Further, when the protruding length L2b is also small, improvement in the transmittance in the slit SL can be expected.

[0124] [Fourth Embodiment] FIG. 18 is a schematic cross-sectional view of the first partition wall 6A according to the fourth embodiment. In this figure, elements other than the organic insulating layer 12, the lower electrode LE1, the rib layer 5, and the first partition wall 6A are omitted. The same configuration as that of the first partition wall 6A can also be applied to the second partition wall 6B.

[0125] In the example of FIG. 18, the second end portion 62b of the upper portion 62 is aligned with the second side surface 64b of the shaft layer 64. On the other hand, the fourth end portion 63b of the bottom layer 63 protrudes from the second side surface 64b.

[0126] For example, the protruding length L2b of the fourth end portion 63b from the second side surface 64b is equal to the protruding length L2a of the third end portion 63a from the first side surface 64a. In this case, in the manufacturing process of the display device DSP, formation of the resist R2 and the second etching shown in FIG. 11D may be omitted.

[0127] Even in the configuration of FIG. 18, generation of bubbles during formation of a resist or the resin layer RS1 that covers the partition walls 6A and 6B can be suppressed as in the first embodiment.

[0128] [Fifth Embodiment] 19 is a schematic cross-sectional view of a first partition wall 6A according to the fifth embodiment. In this figure, elements other than the organic insulating layer 12, the lower electrode LE1, the rib layer 5, and the first partition wall 6A are omitted. The same configuration as the first partition wall 6A can be applied to the second partition wall 6B.

[0129] In the example of Fig. 19, the second end 62b of the top layer 62 is aligned with the second side surface 64b of the axial layer 64. Meanwhile, the fourth end 63b of the bottom layer 63 protrudes from the second side surface 64b. As in the example of Fig. 17, the second end 62b may protrude slightly from the second side surface 64b.

[0130] In the example of FIG. 19, the third end 63a of the bottom layer 63 has a thickness Ta. The fourth end 63b has a thickness Tb that is smaller than the thickness Ta (Tb <Ta)。

[0131] 19, as in the first embodiment, it is possible to suppress the generation of bubbles during the formation of the resist or resin layer RS1 that covers the partition walls 6A, 6B. Furthermore, if the fourth end portion 63b is sufficiently thin, external light can pass through the fourth end portion 63b. Therefore, it is expected that the transmittance of the slit SL will also be improved.

[0132] All display devices and manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display devices and manufacturing methods disclosed in the above embodiments also fall within the scope of the present invention as long as they include the gist of the present invention.

[0133] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0134] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0135] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, SL...slit, 5...rib layer, 6A, 6B...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer.

Claims

1. a first subpixel and a second subpixel aligned in a first direction; a rib layer having a first pixel opening located in the first subpixel and a second pixel opening located in the second subpixel; a partition wall located between the first subpixel and the second subpixel and disposed above the rib layer; Equipped with the partition wall is divided into a first partition wall on the first subpixel side and a second partition wall on the second subpixel side by a slit extending in a second direction intersecting the first direction, The first partition wall is a lower portion having a first side surface on the first subpixel side and a second side surface on the slit side; an upper portion having a first end portion on the first subpixel side and a second end portion on the slit side, the upper portion being disposed on the lower portion; Equipped with the first end protrudes from the first side; The second end does not protrude from the second side surface, or protrudes from the second side surface by a length that is shorter than a length that the first end protrudes from the first side surface. Display device.

2. The lower portion of the first partition wall is a shaft layer having the first side and the second side; a bottom layer located between the rib layer and the axis layer, the bottom layer having a third end on the first subpixel side and a fourth end on the slit side; Equipped with The third end protrudes from the first side. The display device according to claim 1 .

3. The fourth end does not protrude from the second side surface. The display device according to claim 2 .

4. The fourth end protrudes from the second side surface. The display device according to claim 2 .

5. a protruding length of the fourth end from the second side surface is shorter than a protruding length of the third end from the first side surface; The display device according to claim 4 .

6. The fourth end is thinner than the third end. The display device according to claim 4 .

7. The first subpixel is a first lower electrode overlapping the first pixel opening and having a peripheral edge covered by the rib layer; a first organic layer that covers the first lower electrode through the first pixel opening and emits light in response to application of a voltage; a first upper electrode covering the first organic layer and in contact with the lower portion of the first partition; Equipped with 7. The display device according to claim 1.

8. a first sealing layer formed of an inorganic insulating material and disposed above the first upper electrode; the first sealing layer covers the first side surface and the first end portion; The display device according to claim 7 .

9. an end portion of the first sealing layer is located above the first partition wall; The display device according to claim 8 .

10. Further, a resin layer covering the first sealing layer is provided. the second side surface and the second end portion are covered with the resin layer; The display device according to claim 9 .

11. The resin layer and the rib layer are in contact with each other at the slits. The display device according to claim 10.

12. The second subpixel is a second lower electrode overlapping the second pixel opening and having a peripheral edge covered by the rib layer; a second organic layer that covers the second lower electrode through the second pixel opening and emits light in response to application of a voltage; a second upper electrode covering the second organic layer and in contact with the second partition wall; Equipped with The display device according to claim 7 .

13. the slit does not overlap with the first lower electrode and the second lower electrode; The display device according to claim 12.

14. forming a first lower electrode and a second lower electrode in a first subpixel and a second subpixel aligned in a first direction, respectively; forming a rib layer covering the first lower electrode and the second lower electrode; a first partition wall on the first sub-pixel side and a second partition wall on the second sub-pixel side, each of which includes a lower portion located above the rib layer and an upper portion whose both ends protrude from side surfaces of the lower portion, and which are separated by a slit extending in a second direction intersecting with the first direction, are formed between the first sub-pixel and the second sub-pixel; removing an end portion of the upper portion of at least one of the first partition wall and the second partition wall along the slit; A method for manufacturing a display device, comprising:

15. the lower portion of the first partition has a first side surface on the first subpixel side and a second side surface on the slit side, the upper portion of the first partition wall has a first end portion on the first subpixel side and a second end portion on the slit side, The removing step includes: disposing a first resist covering the first end and exposing the second end; removing at least a portion of the second end portion exposed from the first resist by a first etching; Including, The method for manufacturing a display device according to claim 14 .

16. The lower portion of the first partition wall is a shaft layer having the first side and the second side; a bottom layer positioned between the rib layer and the shaft layer, the bottom layer having a third end protruding from the first side surface and a fourth end protruding from the second side surface; Equipped with The removing step includes: After the first etching, the first resist is removed; disposing a second resist that covers the third end and exposes the fourth end; removing at least a portion of the fourth end portion exposed from the second resist by a second etching; Including, The method for manufacturing a display device according to claim 15.

17. the first resist has openings overlapping the first lower electrode and the second lower electrode; the first etching removes the rib layer exposed through the opening, thereby forming a first pixel opening overlapping the first lower electrode and a second pixel opening overlapping the second lower electrode in the rib layer; The method for manufacturing a display device according to claim 15.

18. the rib layer covers a conductive pad disposed outside a display area including the first subpixel and the second subpixel; the first resist has an opening overlapping the pad; the first etching removes the rib layer exposed through the opening, thereby forming a terminal opening in the rib layer that overlaps with the pad; The method for manufacturing a display device according to claim 15.

19. forming a first organic layer that emits light in response to application of a voltage in the first subpixel; forming a first upper electrode covering the first organic layer and in contact with the lower portion of the first partition; forming a first sealing layer made of an inorganic insulating material above the first upper electrode; further comprising: A method for manufacturing a display device according to any one of claims 14 to 18.

20. forming a resin layer that covers the first sealing layer and contacts the rib layer at the slits; The method for manufacturing a display device according to claim 19.

Images