Image sensor and manufacturing method of the same

Abstract

To provide an image sensor with improved electrical and optical properties.SOLUTION: An image sensor according to the present invention includes a substrate, a pixel region defined by a pixel isolation portion in the substrate, a first floating diffusion region on the pixel region, a source follower gate electrode on the substrate, and a first buried wiring on the pixel isolation portion. The first buried wiring electrically connects the first floating diffusion region and the source follower gate electrode to each other, the first buried wiring is disposed in the substrate, the first buried wiring includes a first portion extending from the first floating diffusion region in a first direction and a second portion extending from the source follower gate electrode in a second direction, and the first direction and the second direction are orthogonal to each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor having improved electrical and optical characteristics and a method for manufacturing the same. [Background technology]

[0002] An image sensor converts an optical image into an electrical signal. In recent years, with the development of the computer and communication industries, there has been an increasing demand for image sensors with improved performance in various fields, such as digital cameras, video cameras, PCS (Personal Communication Systems), game consoles, security cameras, and medical micro cameras.

[0003] Image sensors include charge coupled devices (CCDs) and CMOS image sensors. Among these, CMOS image sensors have a simple driving method and can integrate signal processing circuits onto a single chip, making it possible to miniaturize products. CMOS image sensors also have very low power consumption, making them suitable for use in products with limited battery capacity. In addition, CMOS image sensors can be used interchangeably with CMOS process technology, which reduces manufacturing costs.

[0004] Therefore, as CMOS image sensors have become capable of achieving higher resolution with technological development, their use has increased dramatically, and further improvements in electrical and optical characteristics have become a challenge. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 10,728,482 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in view of the above-mentioned problems with conventional image sensors, and an object of the present invention is to provide an image sensor having improved electrical and optical characteristics. Another object of the present invention is to provide a method for manufacturing an image sensor having improved electrical and optical characteristics. [Means for solving the problem]

[0007] In order to achieve the above object, an image sensor according to the present invention includes a substrate, a pixel region defined by a pixel isolation portion in the substrate, a first floating diffusion region on the pixel region, a source follower gate electrode on the substrate, and a first buried interconnection on the pixel isolation portion, wherein the first buried interconnection electrically connects the first floating diffusion region and the source follower gate electrode to each other, the first buried interconnection being disposed within the substrate, and including a first portion extending from the first floating diffusion region in a first direction and a second portion extending from the source follower gate electrode in a second direction, and the first direction and the second direction being perpendicular to each other.

[0008] In order to achieve the above object, an image sensor according to the present invention includes a substrate, a pixel region defined by a pixel isolation portion in the substrate, a first floating diffusion region on the pixel region, a source follower gate electrode on the substrate, a first buried interconnection on the pixel isolation portion, and a first source follower contact on the source follower gate electrode, wherein the first buried interconnection electrically connects the first floating diffusion region and the source follower gate electrode to each other, and the first source follower contact is in contact with the source follower gate electrode and the first buried interconnection, respectively.

[0009] According to another embodiment of the present invention, an image sensor includes a substrate including a first pixel group and a second pixel group adjacent to each other in a first direction, each of the first and second pixel groups including pixels arranged in a 2×2 array, a pixel separator disposed in the substrate and separating the first and second pixel groups and the pixels, a first floating diffusion region located at a center of the first pixel group, a second floating diffusion region located at a center of the second pixel group, a source follower gate electrode disposed on the substrate in one of the pixels of the first pixel group, a photoelectric conversion unit disposed in the substrate in each of the pixels, a first transmission gate electrode adjacent to the first floating diffusion region in each of the pixels of the first pixel group, a second transmission gate electrode adjacent to the second floating diffusion region in each of the pixels of the second pixel group, a first buried interconnection disposed in the substrate, the first buried interconnection electrically connecting the first floating diffusion region and the source follower gate electrode to each other, and a first source follower contact on the source follower gate electrode, the first floating diffusion region electrically connected to the first source follower contact through the first buried interconnection.

[0010] In order to achieve the above object, a method for manufacturing an image sensor according to the present invention includes the steps of: forming a pixel region defined by a pixel isolation region on a substrate; forming a first floating diffusion region and a first buried interconnection in the substrate; and forming a source follower gate electrode on the pixel region, wherein the first buried interconnection electrically connects the first floating diffusion region and the source follower gate electrode to each other, and forming a first source follower contact on the source follower gate electrode, wherein the step of forming the first floating diffusion region and the first buried interconnection includes the steps of etching an upper portion of the substrate and an upper portion of the pixel isolation region to form a first etching portion; and filling a semiconductor material in the first etching portion. [Effects of the Invention]

[0011] In accordance with the image sensor and manufacturing method thereof according to the present invention, the floating diffusion region, the source follower gate electrode, and the buried wiring are electrically connected to each other, the buried wiring is disposed within the upper part of the substrate and extends along the pixel separating portion, and a source follower contact is disposed on the source follower gate electrode, and the source follower contact is electrically connected to the floating diffusion region through the buried wiring. Therefore, the contact directly connected to the floating diffusion region is omitted, thereby preventing / reducing 'junction leakage' occurring between the floating diffusion region and the contact. Furthermore, by embedding the wiring in the substrate, the degree of freedom in the layout design of the wiring can be increased. Furthermore, a ground region is formed on the buried wiring. Therefore, the gate electrode of the existing dummy transistor in the pixel region can be used as the gate electrode of the drive transistor. As a result, the electrical characteristics of the image sensor can be further improved. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 2] FIG. 2 is a plan view showing a shape in which wiring is added to the image sensor of FIG. 1. [Figure 3] FIG. 3 is a partial perspective view of the image sensor of FIG. 2. [Figure 4] FIG. 3 is a circuit diagram of the image sensor of FIG. 2. [Figure 5] FIG. 3 is a cross-sectional view taken along line AA' in FIG. 2. [Figure 6] FIG. 3 is a cross-sectional view taken along line BB' in FIG. 2. [Figure 7A] FIG. 7 is an enlarged cross-sectional view of area M of FIG. 6 according to an embodiment of the present invention. [Figure 7B] 7 is an enlarged cross-sectional view of region M in FIG. 6 according to another embodiment of the present invention. [Figure 8A]1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 8B] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 9A] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 9B] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 10A] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 10B] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 11A] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 11B] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 12A] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 12B] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 13A] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 13B] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 14A] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 14B] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 15A] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 15B]1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 16A] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 16B] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 17] FIG. 10 is a plan view showing a schematic configuration of an image sensor according to another embodiment of the present invention. [Figure 18] FIG. 10 is a plan view showing a schematic configuration of an image sensor according to another embodiment of the present invention. [Figure 19] FIG. 10 is a plan view showing a schematic configuration of an image sensor according to another embodiment of the present invention. [Figure 20] 1 is a cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 21] 1 is a cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] Next, specific examples of embodiments for carrying out the image sensor and the manufacturing method thereof according to the present invention will be described with reference to the drawings.

[0014] In this specification, terms indicating a sequence such as first, second, etc. are used to distinguish components having the same / similar functions from each other, and the numbers may be changed according to the order in which they are mentioned.

[0015] FIG. 1 is a plan view showing a schematic configuration of an image sensor according to an embodiment of the present invention, FIG. 2 is a plan view showing the shape of the image sensor of FIG. 1 with wiring added, FIG. 3 is a partial perspective view of the image sensor of FIG. 2, FIG. 4 is a circuit diagram of the image sensor of FIG. 2, FIG. 5 is a cross-sectional view taken along line A-A' in FIG. 2, and FIG. 6 is a cross-sectional view taken along line B-B' in FIG. 2.

[0016] 1 to 6, in an image sensor 100 according to the present invention, a substrate 1 is provided. The substrate 1 includes a plurality of pixels PX arranged two-dimensionally along a first direction D1 and a second direction D2 that intersect (are orthogonal to) each other. FIG. 1 shows one pixel PX as an example. The substrate 1 includes a first surface 1a and a second surface 1b facing each other. Light enters the substrate 1 through the second surface 1b. The substrate 1 can be a single crystal wafer or epitaxial layer containing silicon and / or germanium, or an SOI (Silicon on Insulator) substrate. In the substrate 1, a well region PW is formed. The well region PW is doped with impurities of the first conductivity type. The first conductivity type is, for example, a P type. The impurity of the first conductivity type is, for example, boron.

[0017] Within the substrate 1, a pixel separating section 10 is arranged to separate and define the pixels PX from one another. The pixel separating section 10 has a mesh shape in plan view. The pixel separating portion 10 includes an isolation conductive pattern disposed therein, and an isolation insulating pattern between the isolation conductive pattern and the substrate 1. The pixel separating portion 10 penetrates the substrate 1 . The pixels PX that make up the 2×2 array make up one pixel group (GRP1, GRP2). A plurality of pixel groups (GRP1, GRP2) are provided and arranged along a first direction D1 and a second direction D2. 1 and 2, the pixel groups (GRP1, GRP2) include a first pixel group GRP1 and a second pixel group GRP2 arranged along a first direction D1.

[0018] The first pixel group GRP1 includes first to fourth pixels (PX(1) to PX(4)) arranged clockwise. The second pixel group GRP2 includes the fifth to eighth pixels (PX(5) to PX(8)) arranged clockwise. The pixel separating unit 10 separates the pixel groups (GRP1, GRP2) from each other. The pixel separating unit 10 separates the pixels PX from each other in each of the pixel groups (GRP1, GRP2). There is no pixel separator 10 at the center of each of the pixel groups (GRP1, GRP2).

[0019] In each pixel PX, a photoelectric conversion unit PD is disposed in the substrate 1. The photoelectric conversion unit PD is doped with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type is, for example, an N type. The impurity of the second conductivity type may be, for example, phosphorus or arsenic. The photoelectric conversion portion PD, which is an N-type impurity region, forms a PN junction with the well region PW, which is a P-type impurity region, to form a photodiode. When light is incident on a PN junction, electron-hole pairs are generated. The electrons move to the photoelectric conversion unit PD, which is an N-type impurity region, and are accumulated there.

[0020] In each of the pixels PX, an isolation portion 20 is disposed adjacent to the first surface 1a in the substrate 1 to define first and second active regions (ACT1, ACT2). The isolation portion 20 can be formed by a shallow trench isolation (STI) method. The isolation region 20 is formed of a single layer or a multi-layer structure of at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the element isolation portion 20 is formed by doping with impurities of the first conductivity type, which is the same as the impurities doped into the substrate 1, and has a doping concentration higher than that of the impurities doped into the substrate 1. The pixel isolation section 10 penetrates the element isolation section 20 . There is no element isolation portion 20 at the center of each of the pixel groups (GRP1, GRP2).

[0021] Transfer transistors (T1 to T8) are arranged in the first active regions ACT1 of the first to eighth pixels (PX(1) to PX(8)), respectively. In each pixel PX, one end of the transfer transistor (T1 to T8) is connected to the photoelectric conversion unit PD. Each of the transfer transistors (T1 to T8) includes a floating diffusion region FD disposed in the substrate 1 and a transfer gate electrode TG disposed beside the floating diffusion region FD. The transmission gate electrode TG includes a first sub-transmission gate Ta and a second sub-transmission gate Tb that are separated from each other. The floating diffusion region FD is doped with impurities of the second conductivity type.

[0022] In the center of the first pixel group GRP1, the floating diffusion regions FD of the first to fourth pixels (PX(1) to PX(4)) are connected to each other to form a first common floating diffusion region FDC1. In the center of the second pixel group GRP2, the floating diffusion regions FD of the fifth to eighth pixels (PX(5) to PX(8)) are connected to each other to form a second common floating diffusion region FDC2. The first to fourth pixels (PX(1) to PX(4)) share a first common floating diffusion region FDC1. The fifth to eighth pixels (PX(5) to PX(8)) share a second common floating diffusion region FDC2. The first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 are doped with the same second conductivity type impurity as the floating diffusion region FD at the same concentration.

[0023] For clarity of explanation, some of the floating diffusion regions FD are named the first and second common floating diffusion regions (FDC1, FDC2), but the first and second common floating diffusion regions (FDC1, FDC2) are substantially identical to the floating diffusion region FD, there is no boundary between them, and they can be used interchangeably. The first and second common floating diffusion regions (FDC1, FDC2) may also be referred to as floating diffusion regions FD. In each of the second active regions ACT2 of the first to eighth pixels (PX(1) to PX(8)), a gate electrode of a driving transistor or a gate electrode of a dummy transistor is disposed. The second active region ACT2 has an L-shape in plan view. Specifically, referring to FIG. 1, the gate electrode GE of the driving transistor is disposed in the center of the second active region ACT2 of the first pixel PX(1) of the first pixel group GRP1. The gate electrode GE is formed so that the gate electrodes of the transistors of the second sub-chip CH2 can be arranged instead of the first and second dummy gate electrodes (DM1, DM2) by arranging the first and second ground regions (GN1, GN2) described later on the first buried wiring. On either side of the gate electrode GE, source / drain regions SD doped with impurities of a second conductivity type are arranged in the substrate 1 .

[0024] As another example, a first dummy gate electrode DM1 is disposed in the center of the second active region ACT2 of the first pixel PX(1) in the first pixel group GRP1. A first ground region GN1 is disposed in the substrate 1 on one side of the first dummy gate electrode DM1. The first ground region GN1 is doped with impurities of the first conductivity type at a higher concentration than the well region PW of the substrate 1. The first ground region GN1 contacts the well region PW of the first pixel group GRP1. A source / drain region SD doped with impurities of a second conductivity type is disposed in the substrate 1 on the other side of the first dummy gate electrode DM1. A second double conversion gate electrode DCG2 is disposed at the center of the second active region ACT2 of the second pixel PX(2) of the first pixel group GRP1. On either side of the second double conversion gate electrode DCG2, a source / drain region SD doped with impurities of the second conductivity type is arranged in the substrate 1, and together with the second double conversion gate electrode DCG2, forms the second double conversion transistor DCX2 of Figure 4.

[0025] A first double conversion gate electrode DCG1 is disposed in the center of the second active region ACT2 of the third pixel PX(3) of the first pixel group GRP1. On either side of the first double conversion gate electrode DCG1, a source / drain region SD doped with impurities of the second conductivity type is arranged in the substrate 1, and together with the first double conversion gate electrode DCG1, forms the first double conversion transistor DCX1 of Figure 4. A first source follower gate electrode SF1 is disposed in the center of the second active region ACT2 of the fourth pixel PX(4) of the first pixel group GRP1. On either side of the first source follower gate electrode SF1, a source / drain region SD doped with impurities of the second conductivity type is arranged in the substrate 1, and together with the first source follower gate electrode SF1, constitutes the first source follower transistor S1 of FIG. 4.

[0026] The fifth pixel PX(5) of the second pixel group GRP2 is located next to the fourth pixel PX(4) of the first pixel group GRP1 in the first direction D1. A second source follower gate electrode SF2 is disposed in the center of the second active region ACT2 of the fifth pixel PX(5) in the second pixel group GRP2. On either side of the second source follower gate electrode SF2, a source / drain region SD doped with impurities of the second conductivity type is arranged in the substrate 1, and together with the second source follower gate electrode SF2, constitutes the second source follower transistor S2 of FIG. In this embodiment, the second source follower gate electrode SF2 is integrally connected to the first source follower gate electrode SF1 to form one source follower gate electrode SF. That is, the source follower gate electrode SF crosses the pixel isolation portion 10 between the first pixel group GRP1 and the second pixel group GRP2.

[0027] A selection gate electrode SEL is disposed at the center of the second active region ACT2 of the sixth pixel PX(6) in the second pixel group GRP2. On either side of the select gate electrode SEL, source / drain regions SD doped with impurities of the second conductivity type are arranged in the substrate 1, and together with the select gate electrode SEL, form the select transistor SE of FIG. A reset gate electrode RG is disposed at the center of the second active region ACT2 of the seventh pixel PX(7) in the second pixel group GRP2. On either side of the reset gate electrode RG, a source / drain region SD doped with impurities of the second conductivity type is disposed in the substrate 1, and together with the reset gate electrode RG, constitutes the reset transistor RX of FIG. The gate electrode GE of the drive transistor is disposed in the center of the second active region ACT2 of the eighth pixel PX(8) of the second pixel group GRP2. The gate electrode GE is formed by arranging the first and second ground regions (GN1, GN2) described later on the first buried wiring, so that the gate electrodes of the transistors of the second sub-chip CH2 can be arranged instead of the first and second dummy gate electrodes (DM1, DM2). On either side of the gate electrode GE, source / drain regions SD doped with impurities of a second conductivity type are arranged in the substrate 1 .

[0028] As another example, a second dummy gate electrode DM2 is disposed in the center of the second active region ACT2 of the eighth pixel PX(8) in the second pixel group GRP2. A second ground region GN2 is disposed in the substrate 1 on one side of the second dummy gate electrode DM2. The second ground region GN2 is doped with the first conductivity type impurity at a higher concentration than the well region PW of the substrate 1. The second ground region GN2 contacts the well region PW of the second pixel group GRP2. A source / drain region SD is disposed in the substrate 1 on the other side of the second dummy gate electrode DM2.

[0029] 2 and 3, the transmission gate connection wiring TGL connects the first sub-transmission gate Ta and the second sub-transmission gate Tb adjacent to each other on one first active region ACT1. Referring to FIG. 2, the source / drain regions SD on one side of the first source follower gate electrode SF1 and the second source follower gate electrode SF2 are connected to a pixel voltage line MPL. The source / drain region SD on one side of the sub-gate electrode GE is connected to the pixel voltage line MPL. The source / drain regions SD on the other side of the first source-follower gate electrode SF1 and the second source-follower gate electrode SF2 and the source / drain region SD on one side of the select gate electrode SEL are connected to the SF-SEL connecting line SSL. The SF-SEL connection line SSL has an L-shape in plan view. The source / drain region SD on the other side of the select gate electrode SEL is connected to an output line Vout. The other connections between the transistors are the same as those in FIG.

[0030] Referring to Figures 1 to 4, in the image sensor 100 according to this embodiment, the first to eighth pixels (PX(1) to PX(8)) arranged in the first and second pixel groups (GRP1, GRP2) share the first and second source follower transistors (S1, S2), the reset transistor RX, the first and second dual conversion transistors (DCX1, DCX2), and the selection transistor SE with each other. In one of the pixels PX, a transfer transistor (one of T1 to T8) is turned on to move electrons accumulated in the photoelectric conversion unit PD to the floating diffusion region FD. Therefore, the voltage level of the floating diffusion region FD fluctuates. The reset transistor RX resets the floating diffusion region FD. For example, with the first and second double conversion transistors (DCX1, DCX2) turned on, the reset transistor RX electrically connects the floating diffusion region FD to the power supply voltage Vpix based on an electrical signal (reset signal) applied to the reset gate electrode RG. The reset transistor RX drives the voltage level of the floating diffusion region FD to the power supply voltage Vpix based on a reset signal, thereby removing or releasing electrons stored in the floating diffusion region FD.

[0031] The first and second source follower transistors S1 and S2 are connected in a parallel configuration to form a fingered type source follower transistor SX. The source follower transistor SX has a source follower gate electrode SF to which the first source follower gate electrode SF1 and the second source follower gate electrode SF2 are connected. The source follower gate electrode SF is connected to the floating diffusion region FD. The source follower transistor SX is connected between the power supply voltage Vpix and the select transistor SE. The voltage level of one end of the source follower transistor SX varies depending on the voltage level of the floating diffusion region FD, and when the selection transistor SE is turned on, an output signal is transmitted through the output line Vout.

[0032] The source follower transistor is more sensitive than the other transfer, reset, and select transistors to the effects of thermal and flicker noise inherent in the transistor elements. Noise generated in the source follower transistor element is directly transmitted to the internal circuit, resulting in a degradation of image quality. Forming the source follower transistor as a fingered type reduces the influence of thermal noise and flicker noise inherent to such transistor elements, and helps to faithfully read out the potential of the floating diffusion region FD. Also, the amount of current in the source follower transistor SX is increased. Therefore, the linearity of the voltage-current graph of the source follower transistor SX is improved, and noise such as "random noise" and "random telegraphy signal" is reduced.

[0033] First and second dual conversion transistors (DCX1, DCX2) are connected between the floating diffusion region FD and the reset transistor RX. If the first and second dual conversion transistors DCX1 and DCX2 are turned off, the full well capacity (FWC) of the pixel PX can be the capacitance of the floating diffusion region FD. If at least one of the first and second dual conversion transistors DCX1 and DCX2 is turned on, the FWC of the pixel PX increases more than the capacitance of the floating diffusion region FD. At low illumination, all of the first and second dual conversion transistors (DCX1, DCX2) are turned off. At medium illumination, the first double conversion transistor DCX1 is turned on and the second double conversion transistor DCX2 is turned off. At high illumination, both the first and second dual conversion transistors (DCX1, DCX2) are turned on. In this way, the first and second dual conversion transistors (DCX1, DCX2) are turned on / off depending on the illuminance, thereby varying the conversion gain of the pixel PX. Therefore, it is possible to realize a clear image with improved HDR (high dynamic range) characteristics.

[0034] In the full mode, the image sensor 100 sequentially applies a turn-on voltage to each of the first to eighth transmission gate electrodes (TG(1) to TG(8)) to output signals from the pixels PX. Alternatively, in the binning mode, a turn-on voltage is simultaneously applied to the transmission gate electrodes TG for each pixel group to output a signal for each pixel group.

[0035] In the upper part of the substrate 1, a first buried wiring BFD is provided. The first buried wiring BFD is provided on the upper surface of the pixel separating section 10 . The first buried wiring BFD extends along the pixel separating portion 10. The first embedding pattern BFD has a mesh shape in plan view. The upper surface of the first buried wiring BFD is substantially coplanar with the upper surfaces of the first and second common floating diffusion regions (FDC1, FDC2). The first buried wiring BFD and the first and second common floating diffusion regions (FDC1, FDC2) form the connection wiring FDL. The upper surface of the first buried wiring BFD is located at a level lower than the upper surface of the source follower gate electrode SF and the upper surface of the transmission gate electrode TG. The bottom surface of the first buried wiring BFD is located at a level higher than the bottom surface of the transmission gate electrode TG. The transmission gate connecting wiring TGL and the pixel voltage line MPL are located at a higher level than the first buried wiring BFD.

[0036] The first buried wiring BFD is in direct contact with each of the first common floating diffusion region FDC1, the second common floating diffusion region FDC2, and the source follower gate electrode SF. The first buried wiring BFD electrically connects the first common floating diffusion region FDC1, the second common floating diffusion region FDC2, and the source follower gate electrode SF to one another. The boundaries of the first buried wiring BFD with the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 may be unclear. The first buried wiring BFD includes a first buried portion B1 extending from the first common floating diffusion region FDC1 in a first direction D1. The first buried wiring BFD includes a second buried portion B2 extending in the second direction D2 from the source follower gate electrode SF to the first buried portion B1. The first embedded portion B1 and the second embedded portion B2 extend in directions intersecting each other and meet.

[0037] The first and second buried portions (B1, B2) extend along the pixel separating portion 10. The width of the first and second buried portions (B1, B2) in the second direction D2 is smaller than the width of the first and second common floating diffusion regions (FDC1, FDC2) in the second direction D2. The first buried portion B1 extends in a first direction D1 to electrically connect the first common floating diffusion region FDC1 and the second common floating diffusion region FDC2 to each other. At least a part of the second buried portion B1 vertically overlaps with the source follower gate electrode SF. As another example, the first buried wiring BFD is extended and connected to the source / drain region SD on one side of the first double conversion gate electrode DCG1. The first buried wiring BFD includes the same material as the first and second floating diffusion regions (FDC1, FDC2). The first buried wiring BFD includes a semiconductor material. As an example, the first buried wiring BFD includes silicon.

[0038] 3, 5, and 6, a gate insulating film Gox is interposed between the transmission gate electrode TG and the substrate 1. As shown in FIG. The gate insulating film Gox is also interposed between the gate electrodes (RG, DCG1, DCG2, SF1, SF2, SEL, GE) of the other driving transistors and the substrate 1. The gate insulating film Gox may include a single film or multiple films of at least one of silicon oxide, metal oxide, silicon nitride, and silicon oxynitride. The transmission gate electrode TG and the gate electrodes (RG, DCG1, DCG2, SF1, SF2, SEL, GE) may be made of at least one of impurity-doped polysilicon and a metal such as tungsten or aluminum. Preferably, the transmission gate electrode TG and the gate electrodes (RG, DCG1, DCG2, SF1, SF2, SEL, GE) are made of polysilicon doped with impurities.

[0039] The photoelectric conversion unit PD arranged in the substrate 1 in one pixel PX overlaps one transmission gate electrode TG and one of the gate electrodes (RG, DCG1, DCG2, SF1, SF2, SEL, GE). The side surfaces of the transmission gate electrode TG are covered with spacers 25 . The spacer 25 may include a single layer or multiple layers of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first surface 1a of the substrate 1 and the gate electrodes (TG, RG, DCG1, DCG2, SF1, SF2, SEL, and GE) are covered with a first interlayer insulating film IL1. The first interlayer insulating film IL1 includes an etching stopper film 3 and a planarizing film 5. The etching stop film 3 is formed conformally. The planarization film 5 fills the spaces between the gate electrodes (TG, RG, DCG1, DCG2, SF1, SF2, SEL, and GE). The upper surface of the planarization film 5 is coplanar with the upper surface of the etching stop film 3 on the gate electrodes (TG, RG, DCG1, DCG2, SF1, SF2, SEL, GE). The etching stop film 3 has etching selectivity with respect to the planarizing film 5 . The etching stop film 3 may be made of, for example, SiN, SiCN, or SiON. The planarization film 5 may be made of, for example, silicon oxide or a porous insulating material.

[0040] The first contact plugs (15a, 15b, 15c) penetrate the first interlayer insulating film IL1. The first contact plugs (15a, 15b, 15c) include a first gate contact plug 15a, a second gate contact plug 15b, and a first source follower contact 15c. The first gate contact plug 15a penetrates the etching stopper film 3 and the planarization film 5 of the first interlayer insulating film IL1 and contacts the gate electrodes (TG, RG, DCG1, DCG2, SF1, SF2, SEL). The second gate contact plug 15b penetrates the etching stop layer 3 and the planarization layer 5 of the first interlayer insulating layer IL1 to contact the source / drain region SD. The first and second gate contact plugs 15a and 15b include a conductive material. For example, the first and second gate contact plugs (15a, 15b) include tungsten. In one embodiment, the first and second gate contact plugs (15a, 15b) may be formed of impurity-doped polysilicon.

[0041] FIG. 7A is an enlarged view of region M of FIG. 6 according to an embodiment of the present invention. The first source follower contact 15c will now be described in more detail with reference to Figures 6 and 7A. 6 and 7A, a gate insulating film Gox is provided on the isolation portion 20 and the first buried wiring BFD.

[0042] The gate insulating film Gox may include a single film or multiple films of at least one of silicon oxide, metal oxide, silicon nitride, and silicon oxynitride. A source follower gate electrode SF and a spacer 25 are provided on the gate insulating film Gox. The spacer 25 covers the side surface of the source follower gate electrode SF. A first interlayer insulating film IL1 is provided on the source follower gate electrode SF and the gate insulating film Gox. Specifically, an etching stop film 3 and a planarization film 5 are sequentially provided on the upper surfaces of the source follower gate electrode SF and the gate insulating film Gox, respectively.

[0043] The first source follower contact 15c penetrates the etching stop film 3 and the planarizing film 5 of the first interlayer insulating film IL1 and contacts the source follower gate electrode SF and the first buried wiring BFD. The bottom surface CTS1 of the first source follower gate electrode SF is in contact with the second buried portion B2 of the first buried wiring BFD. The level of the bottom surface CTS1 of the first source follower gate electrode SF is lower than the level of the upper surface of the first buried wiring BFD. The width of the first source follower contact 15c in the second direction D2 is greater than the width of the first and second gate contact plugs (15a, 15b).

[0044] The first source follower gate electrode SF includes a first portion PT1 and a second portion PT2 on the first portion PT1. The first portion PT1 is a portion that is in direct contact with the first buried wiring BFD. The lower part of the first part PT1 is embedded in the first embedded wiring BFD. The second portion PT2 includes a portion in direct contact with the source follower gate electrode SF. The first portion PT1 has a first sidewall SW1 adjacent to the source follower gate electrode SF. The second portion PT2 has a second sidewall SW1 adjacent to the source follower gate electrode. The first side wall SW1 is offset from the second side wall SW2 in the second direction D2. The first side wall SW1 is spaced apart from the second side wall SW2 in the second direction D2. At least a portion of the first side wall SW1 contacts the spacer 25. The first sidewall SW1 is spaced apart from the source follower gate electrode SF in the second direction D2.

[0045] At least a part of the second sidewall SW2 is in direct contact with the source follower gate electrode SF and the etching stop film 3 of the first interlayer insulating film IL1. The second portion PT2 includes a first connecting outer wall CTS2 extending in the second direction D2. The first connecting outer wall CTS2 connects the first side wall SW1 and the second side wall SW2. The first connection outer wall CTS2 contacts the source follower gate electrode SF and the spacer 25. The level of the first connection outer wall CTS2 is lower than the level of the upper surface of the source follower gate electrode ST. The level of the first connection outer wall CTS2 is higher than the level of the upper surface of the first buried wiring BFD. The first connecting outer wall CTS2 is located on the boundary between the first portion PT1 and the second portion PT2.

[0046] The widths (WD1, WD2) of the first portion PT1 and the second portion PT2 increase as they move away from the bottom surface CTS1 of the first source follower contact 15c in the vertical direction D3. The maximum width of the first portion PT1 is smaller than the minimum width of the second portion PT2. The difference between the maximum width of the first portion PT1 and the minimum width of the second portion PT2 may be the same as the width of the first connecting outer wall CTS2. The width of the first source follower contact 15c may vary discontinuously on the boundary between the first portion PT1 and the second portion PT2. The upper surface of the first source follower gate contact 15c contacts the etching stop film 3 of the second interlayer insulating film IL2, which will be described later. The first wiring layer M1 on the first source follower gate contact 15c may be omitted. This increases the degree of freedom in the wiring layers in the second to fourth interlayer insulating films (IL2, IL3, IL4). As another example, a first wiring layer M1 is provided on the first source follower gate contact 15c.

[0047] FIG. 7B is an enlarged view of region M of FIG. 6 according to another embodiment of the present invention. Referring to FIG. 7B, the third portion PT3 is interposed between the first portion PT1 and the second portion PT2. The third portion PT3 includes a third sidewall SW3 in contact with the source follower gate electrode SF. The third side wall SW3 is offset from the second side wall SW2 in the second direction D2. The third side wall SW3 is spaced apart from the second side wall SW2 in the second direction D2. The first side wall SW1 is spaced apart from the third side wall SW3 in the second direction D2. The third portion PT3 includes a second connecting outer wall CTS3 extending in the second direction D2. At least a portion of the second connecting outer wall CTS3 is in contact with the spacer 25. The second connecting outer wall CTS3 connects the first side wall SW1 and the third side wall SW3. The level of the second connecting outer wall CTS3 is lower than the level of the first connecting outer wall CTS3. The level of the second connection outer wall CTS3 is located between the level of the first connection outer wall CTS3 and the level of the bottom surface CTS1 of the first source follower contact 15c.

[0048] The width WD3 of the third portion PT3 increases as it moves away from the bottom surface CTS1 of the first source follower contact 15c in the vertical direction D3. The minimum width of the third portion PT3 is greater than the maximum width of the first portion PT1. The maximum width of the third portion PT3 is smaller than the minimum width of the second portion PT2. The difference between the minimum width of the third portion PT3 and the maximum width of the first portion PT1 is the same as the width of the second connecting outer wall CTS3. The width between the maximum width of the third portion PT3 and the minimum width of the second portion PT2 is the same as the width of the first connecting outer wall CTS2. The width of the first source follower contact 15c changes discontinuously on the boundary between the first portion PT1 and the third portion PT3. On the boundary between the second portion PT2 and the third portion PT3, the width of the first source follower contact 15c changes discontinuously. Therefore, the first source follower contact 15c includes at least one discontinuous width change. The first and second common floating diffusion regions (FDC1, FDC2) are electrically connected to the first source follower contact 15c through a first buried wiring BFD. Therefore, the gate contacts on the first and second common floating diffusion regions (FDC1, FDC2) can be omitted.

[0049] 1 to 6, the image sensor according to the present invention includes a source follower gate electrode SF and a first buried wiring BFD connecting the first and second common floating diffusion regions FDC1 and FDC2 to each other. Since the first buried wiring BFD is buried in the substrate 1, the degree of freedom in the layout design of the wiring increases. Also, the gate contacts directly connected to the first and second common floating diffusion regions (FDC1, FDC2) on the first and second common floating diffusion regions (FDC1, FDC2) may be omitted. Therefore, it is possible to prevent / reduce 'junction leakage' that occurs between the first and second common floating diffusion regions (FDC1, FDC2) and the gate contact.

[0050] Second to fourth interlayer insulating films (IL2, IL13, IL4) are sequentially stacked on the first interlayer insulating film IL1. At least some of the second to fourth interlayer insulating films (IL2, IL13, IL4) include an etching stopper film 3 and a planarizing film 5 that are stacked in this order. The transfer gate connecting wiring TGL, the SF-SEL connecting line SSL, and the first wiring M1 are disposed in the second interlayer insulating film IL2. The second contact plug 23 penetrates the third interlayer insulating film IL3 and is connected to at least one of the first wirings M1. The second wiring M2 is disposed on the third interlayer insulating film IL3.

[0051] A fixed charge film 24 is disposed on the second surface 1b of the substrate 1 and is in contact with the second surface 1b. The fixed charge film 24 contacts the second surface 1b. The fixed charge film 24 can be made of a metal oxide film or a metal fluoride film containing oxygen or fluorine in an amount insufficient compared to the stoichiometric ratio. Therefore, the fixed charge film 24 has a negative fixed charge. The fixed charge film 24 may be made of a metal oxide or a metal fluoride containing at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides. Hole accumulation occurs around the fixed charge film 24 . Therefore, the occurrence of dark current and white spots can be effectively reduced. Preferably, the fixed charge film 24 can be at least one of an aluminum oxide film and a hafnium oxide film.

[0052] An anti-reflection film 42 is disposed below the fixed charge film 24 . The anti-reflective coating 42 includes, for example, silicon nitride. On the anti-reflection film 42, a first grid pattern 48a and a second grid pattern 50a are sequentially laminated. The first grid pattern 48a and the second grid pattern 50a have a mesh shape in a plan view. The first grid pattern 48a and the second grid pattern 50a expose the anti-reflection film 42. The sidewalls of the second grid pattern 50a are aligned with the sidewalls of the first grid pattern 48a. The first grid pattern 48a and the second grid pattern 50a can prevent crosstalk between adjacent pixels. The first grid pattern 48a may be made of a material that does not transmit light, such as titanium or tungsten. The second grid pattern 50a includes an organic material. The second grid pattern 50a has a refractive index smaller than that of the color filters (CF1, CF2). For example, the second grid pattern 50a has a refractive index of about 1.3 or less.

[0053] Color filters (CF1, CF2) are disposed on the anti-reflection film . The color filters CF1 and CF2 have different colors for the pixel groups GRP1 and GRP2. That is, the first color filter CF1 is disposed under the first pixel group GRP1. The first to fourth pixels (PX(1) to PX(4)) of the first pixel group GRP1 are covered with a first color filter CF1 of the same color. A second color filter CF2 is disposed below the second pixel group GRP2. The fifth to eighth pixels (PX(5) to PX(8)) of the second pixel group GRP2 are covered with a second color filter CF2 of the same color. The color filters (CF1, CF2) may comprise photoresist material doped with dyes or pigments.

[0054] A plurality of color filters CF1 and CF2 are provided and arranged two-dimensionally along a first direction D1 and a second direction D2 to form a color filter array. The color filter array has an RGB pattern consisting of red (R), green (G), and blue (B) colors, or an RGBW pattern including white pixels. A white pixel can be a pixel that is sensitive to all colors of light or all visible light. There may be no color filter on the white pixel, and a part of the microlens ML may be placed in place of the color filter. The color filter array has a complementary color pattern of cyan, yellow, and magenta. The color filter array can have a Bayer pattern, a 2x2 Tetra pattern, a 3x3 Nona pattern, or a 4x4 hexadeca pattern.

[0055] Microlenses ML are arranged below the color filters (CF1, CF2). The ends of the microlenses ML are in contact with each other and connected. The first pixel group GRP1 is covered by one microlens ML. The second pixel group GRP2 is covered by another microlens ML. The image sensor 100 can perform an autofocus function by shifting the phases of output values ​​of pixels PX at different positions in one pixel group (GRP1 or GRP2). The image sensor 100 can also operate in a global shutter mode. For this purpose, the image sensor 100 may further include a precharge transistor, a sampling transistor, and / or a capacitor connected to the output line Vout.

[0056] 8A to 16B are diagrams illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. Specifically, Figures 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, and 16A are cross-sectional views taken along line A-A' in Figure 2, and Figures 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, and 16B are cross-sectional views taken along line B-B' in Figure 2.

[0057] Referring to Figures 1, 8A and 8B, a substrate 1 is provided, which includes a first surface 1a and a second surface 1b opposite to each other. In the substrate 1, a well region PW, a pixel isolation section 10, an element isolation section 20, and a photoelectric conversion section PD are formed. The lower surface of the pixel separating section 10 is spaced apart from the second surface 1 b of the substrate 1. In the substrate 1, source / drain regions SD are formed. On the first surface 1a of the substrate 1, an etching stop layer 3, a first mold layer ML1, a second mold layer ML2, and a third mold layer ML3 are formed in sequence. The first mold layer ML1 includes a material having etching selectivity with the etching stop layer 3 and the pixel separating portion 10. For example, the first mold film ML1 is SOH (Spin on Hardmask). The second and third mold films (ML2, ML3) include a material having etching selectivity with the first mold film ML1. A first mask pattern MP1 is formed on the third mold film ML3. The first mask pattern MP1 includes a material having etching selectivity with respect to the first mold layer ML1.

[0058] 9A and 9B, an etching process is performed using the first mask pattern MP1 as a mask to etch the first to third mold layers ML1, ML2, and ML3. Thereafter, the second and third mold films (ML2, ML3) are removed. The height of the first mold film ML1 decreases. An etching step is performed using the first mold film ML1 as a mask. The etching stopper layer 3, the upper portion of the pixel separating portion 10, and the upper portion of the substrate 1 are etched by an etching process to form a first etching portion (FD_R). The first etching portion (FD_R) includes a first recess R1 exposing the etched substrate 1 and a second recess R2 exposing the etched pixel separating portion 10. The bottom surface of the first recess R1 and the bottom surface of the second recess R2 are located at the same level. Alternatively, the bottom surface of the first recess R1 and the bottom surface of the second recess R2 may be located at different levels. The second recess R2 includes a first recess portion and a second recess portion. The first recessed portion corresponds to the first buried portion B1 in FIG. 1, and the second recessed portion corresponds to the second buried portion B2 in FIG. The first recess portion extends from the first recess R1 in a first direction D1. The second recessed portion extends from the first recessed portion in a second direction D2.

[0059] Referring to FIGS. 10A and 10B, a diffusion film PFD is formed on the etching stop film 3 and the first etching portion FD_R. The diffusion film PFD includes a semiconductor material. For example, the diffusion film PFD includes polysilicon.

[0060] 11A and 11B, the diffusion film PFD is etched and an etch-back and / or CMP (Chemical Mechanical Polishing) process is performed on the diffusion film PFD to form the connection wiring FDL. Specifically, forming the connection wiring FDL includes forming first and second common floating diffusion regions (FDC1, FDC2) in the first recess R1, and forming a first buried wiring BFD in the second recess R2.

[0061] 12A and 12B, the etching stop layer 3 on the substrate 1 is removed, and a second mask pattern MP2 is formed. The second mask pattern MP2 includes a material having etching selectivity with respect to the substrate 1. For example, the second mask pattern MP2 includes SiON. Using the second mask pattern MP2 as a mask, the upper part of the substrate 1 is etched to form a gate hole GH1. The level of the bottom surface of the gate hole GH1 is lower than the level of the bottom surface of the first buried wiring BFD.

[0062] 13A and 13B, a gate insulating film Gox is conformally formed on the first surface 1a of the substrate 1 and the gate hole GH1. The gate insulating film Gox may include a single film or multiple films of at least one of silicon oxide, metal oxide, silicon nitride, and silicon oxynitride. A preliminary gate film PGL is formed on the gate insulating film Gox. The preliminary gate film PGL includes a metal material. For example, the preliminary gate film PGL may include at least one of impurity-doped polysilicon, tungsten, and aluminum.

[0063] 14A and 14B, a patterning process is performed to etch the gate insulating film Gox and the preliminary gate film PGL to form gate electrodes RG, DCG1, DCG2, SF, SEL, and GE of the driving transistors. A spacer film 25 is conformally formed on the front surface of the substrate 1 . The spacer film 25 covers the upper surfaces and side walls of the transmission gate electrode TG and the source follower gate electrode SF. The spacer film 25 may include a single film or multiple films of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0064] 15A and 15B), a patterning process is performed to etch the spacer film 25 to form the spacers 25. The spacers 25 are formed on the sidewalls of each of the gate electrodes (RG, DCG1, DCG2, SF, SEL, GE) of the drive transistors. An etching stop film 3 is conformally laminated on the first surface 1 a of the substrate 1 . A planarization film 5 is stacked on the etching stop film 3, and a CMP (Chemical Mechanical Polishing) process is performed to expose the upper end of the etching stop film 3. The planarization film 5 is formed to fill the space between the transfer gate electrode TG and the gate electrodes (RG, DCG1, DCG2, SF1, SF2, SEL, DM1, DM2) and has a flat upper surface. Therefore, the first interlayer insulating film IL1 is formed by the etching stopper film 3 and the planarizing film 5.

[0065] 16A and 16B, a patterning process is performed to etch the first interlayer insulating film IL1, thereby forming a first contact hole HL1, a second contact hole HL2, and a third contact hole HL3. The first contact holes HL1 penetrate the planarization layer 5 and the etch stop layer 3 of the first interlayer insulating layer IL1 to expose the source / drain regions SD. The second contact holes HL2 penetrate the planarization film 5 and the etching stop film 3 of the first interlayer insulating film IL1 to expose the gate electrodes (RG, DCG1, DCG2, SEL, GE) of the driving transistors. The third contact hole HL3 penetrates the planarization film 5 and the etching stop film 3 of the first interlayer insulating film IL1 to expose the source follower gate electrode SF and the first buried wiring BFD. The width of the third contact hole HL3 decreases as it approaches the bottom surface of the first buried wiring BFD. The width of the third contact hole HL3 may vary discontinuously. This is because the source follower gate electrode SF, the spacer 25, and the first buried wiring BFD have different etching selectivities in the etching step of the patterning process.

[0066] Referring again to FIG. 5, the first to third contact holes HL1, HL2, and HL3 are filled with a conductive material to form first contact plugs 15a and 15b and a first source follower contact 15c, respectively. A second interlayer insulating film IL2 is formed on the first interlayer insulating film IL1. An etching process, a plating process, a CMP process, etc. are performed to form the transfer gate connecting wiring TGL, the SF-SEL connecting line SSL, and the first wiring M1 in the second interlayer insulating film IL2. A third interlayer insulating film IL3, a second contact plug 23, a fourth interlayer insulating film IL4, a second wiring M2, and the like are formed on the second interlayer insulating film IL2. A backgrinding process is performed on the second surface 1b of the substrate 1 to remove a part of the substrate 1, thereby exposing the pixel separating portion 10. Referring again to FIG. 5, on the second surface 1b of the substrate 1, a fixed charge film 24, an anti-reflection film 42, a first grid pattern 48a, a second grid pattern 50a, color filters (CF1, CF2), microlenses ML, etc. are formed.

[0067] FIG. 17 is a plan view showing a schematic configuration of an image sensor according to another embodiment of the present invention. 17, a third pixel group GRP3 adjacent to the first pixel group GRP1 in the second direction D2 and a fourth pixel group GRP4 adjacent to the second pixel group GRP2 in the second direction D2 are arranged on a substrate 1. The fourth pixel group GRP4 is disposed below the third pixel group GRP3. A third common floating diffusion region FDC3 is provided at the center of the third pixel group GRP3. A fourth common floating diffusion region FDC4 is provided at the center of the fourth pixel group GRP4. The third and fourth common floating diffusion regions (FDC3, FDC4) are substantially identical to the first and second common floating diffusion regions (FDC1, FDC2). The first to fourth pixel groups (GRP1 to GRP4) form a first shared group. A first embedding pattern FDC5 is provided at the center of the first sharing group. The first buried pattern FDC5 is an extended and expanded portion of the first buried wiring BFD. The first buried pattern FDC5 includes polysilicon.

[0068] A common ground region GN is provided on the first buried pattern FDC5. The ground region GN is doped with impurities of the first conductivity type. The ground region GN is doped with impurities of a different conductivity type from that of the first and second common floating diffusion regions FDC1 and FDC2. The impurity concentration of the common ground region GN is higher than the impurity concentration of the well region PW of the substrate 1. The common ground region GN is formed by connecting the ground regions GN of the first to fourth pixel groups (GRP1 to GRP4) to each other. The common ground region GN is connected to a ground line GNL through a ground contact 16 . The ground contact 16 penetrates the first interlayer insulating film IL1 and is connected to the common ground region GN. The ground line GNL is provided in the second interlayer insulating film IL2.

[0069] According to this embodiment, by forming the common ground region GN on the first buried pattern FDC5, the common ground region GN can be omitted from the pixel regions of the first to fourth pixel groups (GRP1 to GRP4). Therefore, the gate electrode of the existing dummy transistor can be used as the gate electrode of the drive transistor.

[0070] 18 and 19 are plan views showing a schematic configuration of an image sensor according to another embodiment of the present invention. 18 and 19 are plan views of the image sensor corresponding to FIG. 18 and 19, the planar profiles of the first and second common floating diffusion regions (FDC1, FDC2) may vary. The first and second common floating diffusion regions (FDC1, FDC2) have a rectangular profile with no center. The first and second common floating diffusion regions (FDC1, FDC2) vertically overlap the first active regions ACT1 of the first to fourth pixels (PX(1) to PX(4)). As another example, the first and second common floating diffusion regions (FDC1, FDC2) may have a donut-shaped profile. The first and second common floating diffusion regions (FDC1, FDC2) have opposing sidewalls each having a profile that is recessed toward the center. Additionally, the first and second common floating diffusion regions (FDC1, FDC2) may have various polygonal profiles.

[0071] FIG. 20 is a cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. Referring to FIG. 20, an image sensor 102 according to an embodiment of the present invention includes a substrate 1 having a pixel array area APS, an optical black area OB, and a pad area PR, a wiring layer 200 on a first surface 1a of the substrate 1, and a base substrate 400 on the wiring layer 200. The wiring layer 200 includes an upper wiring layer 221 and a lower wiring layer 223 . The pixel array region APS includes the pixels PX described with reference to FIGS.

[0072] In the optical black area OB, a first connecting structure 50, a first conductive pad 81 and a bulk color filter 90 are provided on the substrate 1. The first connection structure 50 includes a first light-shielding pattern 51 , an insulating pattern 53 , and a first capping pattern 55 . The first light-shielding pattern 51 is made of a conductive material. The first light-shielding pattern 51 may include, for example, titanium or tungsten. A first light-shielding pattern 51 is provided on the second surface 1b of the substrate 1. The first light-shielding pattern 51 conformally covers the inner walls of the third trench TR3 and the fourth trench TR4. The first light-shielding pattern 51 penetrates the photoelectric conversion layer 150 and the upper wiring layer 221 to connect the photoelectric conversion layer 150 and the wiring layer 200 . The first light-shielding pattern 51 contacts the separating conductive pattern of the pixel separating portion 10 in FIG.

[0073] The first conductive pad 81 is electrically connected to the separating conductive pattern of the pixel separating section 10 . The first light-blocking pattern 51 blocks light incident into the optical black area OB. A first conductive pad 81 is provided inside the third trench TR3 and fills the remaining portion of the third trench TR3. The first conductive pad 81 includes a metal material, for example, aluminum. A negative bias voltage can be applied to the isolated conductive pattern through the first conductive pad 81. Therefore, problems such as white spots and dark current can be prevented / reduced.

[0074] An insulating pattern 53 fills the remaining part of the fourth trench TR4. The insulating pattern 53 passes through the photoelectric conversion layer 150 and the wiring layer 200 entirely or partially. A first capping pattern 55 may be provided on the upper surface of the insulating pattern 53. The first capping pattern 55 is provided on the insulating pattern 53. A bulk color filter 90 is provided on the first conductive pad 81 , the first light-blocking pattern 121 and the first capping pattern 125 . The bulk color filter 90 covers the first conductive pad 81 , the first light-shielding pattern 51 and the first capping pattern 55 . A first protective film 71 is provided on the bulk color filter 90 to seal the bulk color filter 90 .

[0075] A plurality of pixels PX are also arranged in the optical black area OB, and the first reference photoelectric conversion unit PD' and the second reference area 111 are arranged in the pixels PX. The first reference photoelectric conversion unit PD' provides a first reference charge amount that is generated in a state where light is blocked. The first reference charge amount is a relative reference value when calculating the charge amount generated from the pixel PX. The second reference region 111 provides a second reference charge amount that is generated in the absence of the photoelectric conversion unit PD. The second reference charge amount is used as information for removing process noise. In the pad region PR, a second connection structure 60, a second conductive pad 83, and a second protective film 73 are provided on the substrate 1. The second connection structure 60 includes a second light-shielding pattern 61 , an insulating pattern 63 , and a second capping pattern 65 .

[0076] A second light-shielding pattern 61 is provided on the second surface 1 b of the substrate 1 . The second light-shielding pattern 61 conformally covers the inner walls of the fifth trench TR5 and the sixth trench TR6. The second light-shielding pattern 61 penetrates the photoelectric conversion layer 150 and the upper wiring layer 221 to connect the photoelectric conversion layer 150 and the wiring layer 200 to each other. The second light-shielding pattern 61 contacts the wiring in the lower wiring layer 223 . The second light-shielding pattern 61 is electrically connected to the wiring in the wiring layer 200 . The second light-blocking pattern 61 may include a metal material, such as titanium or tungsten.

[0077] A second conductive pad 83 is provided inside the fifth trench TR5 and fills the remaining portion of the fifth trench TR5. The second conductive pad 83 includes a metal material, for example, aluminum. The second conductive pad 83 serves as an electrical connection path between the image sensor device and the outside. An insulating pattern 63 fills the remaining part of the sixth trench TR6. The insulating pattern 63 passes through the photoelectric conversion layer 150 and the wiring layer 200 entirely or partially. A second capping pattern 65 is provided on the insulating pattern 63 . The second protective film 73 covers a part of the second light-blocking pattern 61 and the second capping pattern 65 . The structure of the image sensor described with reference to FIGS. 1 to 6 can also be applied to an image sensor having a 3-chip structure as shown in FIG. 21 below.

[0078] FIG. 21 is a cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. Referring to FIG. 21, an image sensor 103a according to this embodiment has a structure in which first to third sub-chips (CH1 to CH3) are stacked in order. The first sub-chip CH1 includes a first substrate SB1 and a first interlayer insulating film IL1 covering the front surface of the first substrate SB1. The first substrate SB1 can be a semiconductor substrate or an insulating substrate. The first interlayer insulating film IL1 may have a single film or a multi-film structure made of at least one of SiO2, SiN, SiCN, SiON, and SiOCH. A logic circuit is arranged on the first sub-chip CH1. The logic circuitry may include a row driver, a row decoder, a column decoder, a timing generator, a correlated double sampler (CDS), an analog to digital converter (ADC), and the like.

[0079] A first peripheral transistor PTR1, a first contact plug CT1, and a first wiring IT1 are arranged on the first substrate SB1 to form a logic circuit. A first isolation portion ST1 is disposed in the first substrate SB1 to define an active region for the first peripheral transistor PTR1. A first conductive pad CP1 is disposed on the upper end of the first interlayer insulating film IL1. The second sub-chip CH2 is bonded onto the first sub-chip CH1. The second sub-chip CH2 includes a second substrate SB2. The front surface (SB2_F) of the second substrate SB2 is covered with a second interlayer insulating film IL2. The front surface (SB2_F) of the second substrate SB2 faces the first sub-chip CH1.

[0080] In the main area of ​​the second sub-chip CH2, the driving transistors RX, DCX1, DCX2, SX, and SE shown in FIG. 4 are arranged on the front surface SB2_F of the second substrate SB2. Each of the gate electrodes (RG, DCG1, DCG2, SF1, SF2, SEL) can have a "planar type" or "vertical type" shape. The drive transistors (RX, DCX1, DCX2, S1, S2, SE) can be fin field-effect transistors (FinFETs), multi-bridge channel FETs (MBCFETs), or gate all around FETs (GAAFETs). A second peripheral transistor PTR2 is disposed on the front surface (SB2_F) of the second substrate SB2 in an edge region of the second sub-chip CH2. A second isolation portion ST2 is disposed on the front surface SB2_F of the second substrate SB2 to define active regions for the driving transistors RX, DCX1, DCX2, SX, and SE and the second peripheral transistor PTR2.

[0081] A second contact plug CT2 and a second wiring IT2 are disposed in the second interlayer insulating film IL2. A second conductive pad CP2 is disposed at the lower end of the second interlayer insulating film IL1. The lower surface of the second interlayer insulating film IL1 contacts the upper surface of the first interlayer insulating film IL1. The second conductive pads CP2 are in contact with the first conductive pads CP1, respectively. There may be no boundary surface between the second conductive pad CP2 and the corresponding first conductive pad CP1, and the corresponding pads may be integral with each other.

[0082] The rear surface (SB2_B) of the second substrate SB2 is sequentially covered with first and second rear insulating films (BL1, BL2). The fourth wiring IT4 is disposed in the second back surface insulating film BL2. A third bonding pad CP3 is disposed on the upper end of the second back insulating film BL2. The through vias TV penetrate the first rear insulating film BL1, the second substrate SB2, the second element isolation portion ST2, and a part of the second interlayer insulating film IL2 to be in contact with the first landing wires LT1. The through via TV has a width that narrows downward. A via insulating film TL is interposed between the through via TV and the second substrate SB2.

[0083] The third sub-chip CH3 is bonded onto the second sub-chip CH2. The third sub-chip CH3 includes a third substrate SB3. The third substrate SB3 includes a pixel array region APS and an edge region ER. The pixel array region APS includes a plurality of pixels PX. A pixel separating section 10 is disposed on the third substrate SB3 to separate the pixels PX from each other. In each of the pixels PX, a photoelectric conversion unit PD is arranged in the third substrate SB3. The front surface (SB3_F) of the third substrate SB3 faces the second sub-chip CH2. A third isolation portion ST3 is disposed on the front surface (SB3_F) of the third substrate SB3 to define active regions for transfer transistors (T1 to T8 in FIG. 4).

[0084] A transfer gate TG and a floating diffusion region FD are disposed on the front surface (SB3_F) of the third substrate SB3. The front surface (SB3_F) of the third substrate SB3 is covered with a third interlayer insulating film IL3. In the third interlayer insulating film IL3, a third contact plug CT3, a third wiring IT3, and the like are arranged. The floating diffusion region FD of the third sub-chip CH3 is connected to the source follower gate electrode SF of the source follower transistor SX of the second sub-chip CH2. The sub-gate electrodes GE of the third sub-chip CH3 can be replaced with gate electrodes of transistors of the second sub-chip CH2. The lower surface of the third interlayer insulating film IL3 contacts the upper surface of the second back surface insulating film BL2 of the second sub-chip CH2. A fourth conductive pad CP4 is disposed at the lower end of the third interlayer insulating film IL3. The fourth conductive pads CP4 are in contact with the third conductive pads CP3, respectively. There may be no boundary surface between the fourth conductive pad CP4 and the corresponding third conductive pad CP3, and the corresponding pads may be integral with each other.

[0085] The rear surface (SB3_B) of the third substrate SB3 is covered with a third rear insulating film FL. The third rear insulating film FL may include at least one of a fixed charge film, an anti-reflection film, a planarizing film, and a protective film. In the pixel array region APS, a grid pattern WG, color filters (CF1, CF2), and microlenses ML are arranged on the fixed charge film FL. In the edge region ER, a first optical black pattern BT, a second optical black pattern CFB, and a lens remaining layer MLR are sequentially disposed on the fixed charge film FL. The first optical black pattern BT has the same material and thickness as the grid pattern WG. The second optical black pattern CFB may be made of a blue color filter.

[0086] The lens remainder layer MLR has the same material as the microlenses ML. The rest of the structure may be the same or similar to that described above. The positions of the conductive pads CP1 to CP4 and the through electrodes TV are not limited to those shown in FIG. 21 and may vary. The arrangement of the transfer transistors (T1 to T8) and the drive transistors (RX, DCX1, DCX2, S1, S2, SE) is not limited to that shown in FIG. 21 and may be various. A precharge transistor, a sampling transistor, and / or a capacitor, etc., not shown in FIG. 4, may be disposed in at least one of the first and second sub-chips (CH1, CH2).

[0087] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. The embodiments of Figures 1 to 10B can be combined with one another. [Explanation of symbols]

[0088] 1 board 3. Etching stop film 5 Planarization film 10 Pixel separation section 15a First gate contact plug 15b Second gate contact plug 15c First Source Follower Contact 20 Element isolation section 23 Second contact plug 24 Fixed charge membrane 25 spacer 42 Anti-reflection coating 48a 1st grid pattern 50a Second Grid Pattern 100 image sensors ACT1 1st active region ACT2 2nd active region B1 First embedded part B2 Second embedded part BFD 1st embedded wiring CF1, CF2 color filters DCG1 First double conversion gate electrode DCG2 Second double conversion gate electrode FD Floating diffusion region FDC1 First common floating diffusion region FDC2 Second common floating diffusion region FDL connection wiring GE gate electrode GN common ground area GN1 1st ground area GN2 2nd ground area Gox gate insulating film GRP1 1st pixel group GRP2 2nd pixel group IL1 to IL4 (1st to 4th) interlayer insulating films M1, M2 (1st, 2nd) wiring ML Micro Lens MPL Pixel Voltage Line PD photoelectric conversion unit PW well region PX(1)~PX(8) 1st to 8th pixels SD source / drain region SEL Select gate electrode SF Source follower gate electrode SF1 First source follower gate electrode SF2 Second source follower gate electrode SSL SF-SEL connection line Ta 1st sub-transmission gate Tb Second sub-transmission gate TG Transmission gate electrode TGL Transmission gate connection wiring

Claims

1. A substrate; a pixel region defined by a pixel separating portion within the substrate; a first floating diffusion region on the pixel region; a source follower gate electrode overlying the substrate; a first embedded wiring on the pixel separating portion, the first buried wiring electrically connects the first floating diffusion region and the source follower gate electrode to each other; the first buried wiring is disposed within the substrate; The first buried wiring is a first portion extending in a first direction from the first floating diffusion region; a second portion extending in a second direction from the source follower gate electrode, The image sensor, wherein the first direction and the second direction are perpendicular to each other.

2. a second floating diffusion region spaced apart from the first floating diffusion region; The image sensor of claim 1 , wherein the first buried wiring electrically connects the first floating diffusion region and the second floating diffusion region.

3. 2. The image sensor of claim 1, wherein the level of an upper surface of the first buried wiring is lower than the level of an upper surface of the source follower gate electrode.

4. The image sensor of claim 1 , wherein the first buried wiring includes the same material as the first floating diffusion region.

5. a pixel group including a plurality of the pixel regions; the first floating diffusion region is disposed at the center of the pixel region; The image sensor of claim 1 , wherein the pixel regions share the first floating diffusion region.

6. a first source follower contact on the source follower gate electrode; 2. The image sensor of claim 1, wherein the first source follower contact contacts the source follower gate electrode and the first buried interconnection.

7. The image sensor of claim 6 , wherein the first floating diffusion region is electrically connected to the first source follower contact through the first buried interconnection.

8. the first source follower contact includes a first portion and a second portion on the first portion; the first portion of the first source follower contact directly contacts the first buried wiring; the second portion of the first source follower contact directly contacts the source follower gate electrode; 7. The image sensor of claim 6, wherein a maximum width of the first portion of the first source follower contact is smaller than a minimum width of the second portion of the first source follower contact.

9. the first portion of the first source follower contact includes a first sidewall adjacent the source follower gate electrode; the second portion of the first source follower contact includes a second sidewall adjacent the source follower gate electrode; the first sidewall is offset from the second sidewall in the second direction; 9. The image sensor of claim 8, wherein the first sidewall is spaced apart from the source follower gate electrode in the second direction.

10. a first ground region in the first buried wiring; 2. The image sensor of claim 1, wherein the first ground region is doped with impurities of a different conductivity type from that of the first floating diffusion region.

11. A substrate; a pixel region defined by a pixel separating portion within the substrate; a first floating diffusion region on the pixel region; a source follower gate electrode overlying the substrate; a first embedded wiring on the pixel separating portion; a first source follower contact on the source follower gate electrode; the first buried wiring electrically connects the first floating diffusion region and the source follower gate electrode to each other; The image sensor, wherein the first source follower contact is in contact with the source follower gate electrode and the first buried wiring.

12. 12. The image sensor of claim 11, wherein the first floating diffusion region is electrically connected to the first source follower contact through the first buried interconnection.

13. the first source follower contact includes a first portion and a second portion on the first portion; the first portion of the first source follower contact directly contacts the first buried wiring; the second portion of the first source follower contact directly contacts the source follower gate electrode; 12. The image sensor of claim 11, wherein a maximum width of the first portion of the first source follower contact is less than a minimum width of the second portion of the first source follower contact.

14. the first portion of the first source follower contact includes a first sidewall adjacent the source follower gate electrode; the second portion of the first source follower contact includes a second sidewall adjacent the source follower gate electrode; the first sidewall is offset from the second sidewall in a direction parallel to the top surface of the substrate; The image sensor of claim 13 , wherein the first sidewall is spaced apart from the source follower gate electrode.

15. the second portion of the first source follower contact further includes a connecting outer wall connecting the first side wall and the second side wall; The connecting outer wall extends in a second direction, The image sensor of claim 14 , wherein at least a portion of the connecting outer wall contacts the source follower gate electrode.

16. forming a pixel region defined by a pixel separator on a substrate; forming a first floating diffusion region and a first buried interconnect in the substrate; forming a source follower gate electrode on the pixel region; wherein the first buried wiring electrically connects the first floating diffusion region and the source follower gate electrode to each other; forming a first source follower contact on the source follower gate electrode; The step of forming the first floating diffusion region and the first buried wiring includes: forming a first etching portion by etching an upper portion of the substrate and an upper portion of the pixel separating portion; and filling the first etching portion with a semiconductor material.

17. The step of forming the first source follower contact comprises: forming a first interlayer insulating film covering the source follower gate electrode and the first buried wiring; performing a patterning process to form a first contact hole in the first interlayer insulating film; 17. The method of claim 16, wherein the first contact hole exposes at least a portion of the source follower gate electrode and at least a portion of the first buried wiring.

18. 18. The method of claim 17, wherein the exposed top surface of the source follower gate electrode is higher than the bottom surface of the first contact hole.

19. the first etching portion includes a first recess exposing the substrate and a second recess exposing the pixel separating portion; The second recess includes: a first portion extending from the first recess in a first direction; a second portion extending from the first portion in a second direction, The method of claim 16 , wherein the first direction and the second direction are perpendicular to each other.

20. The method further includes forming a second floating diffusion region spaced apart from the first floating diffusion region; 17. The method of claim 16, wherein the first buried wiring electrically connects the first floating diffusion region and the second floating diffusion region to each other.

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