Semiconductor device

Abstract

To provide a semiconductor device that can be miniaturized.SOLUTION: A semiconductor device has a source region and a drain region provided on a main surface of a semiconductor substrate, a gate insulating film provided on the main surface between the source region and the drain region, a gate electrode provided on the gate insulating film, and a drain wiring electrically connected to the drain region, the drain wiring includes a first wiring portion electrically connected to the drain region, a second wiring portion, and a polycrystalline silicon film electrically connected between the first wiring portion and the second wiring portion.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] 2. Description of the Related Art In a conventional semiconductor device including a transistor, a resistive element is connected between a pad connected to the drain of the transistor and a power supply pad to which an AC power supply is connected. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 62-165363 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-153636 [Patent Document 3] Japanese Patent Application Laid-Open No. 2014-075595 [Patent Document 4] Japanese Patent Publication No. 2023-124206 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been an increasing demand for miniaturization of semiconductor devices.

[0005] An object of the present disclosure is to provide a semiconductor device that can be miniaturized. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present disclosure includes a source region and a drain region provided on a main surface of a semiconductor substrate, a gate insulating film provided on the main surface between the source region and the drain region, a gate electrode provided on the gate insulating film, and a drain wiring electrically connected to the drain region, the drain wiring having a first wiring portion electrically connected to the drain region, a second wiring portion, and a polycrystalline silicon film electrically connected between the first wiring portion and the second wiring portion. [Effects of the Invention]

[0007] According to the present disclosure, miniaturization is possible. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view (part 1) illustrating the configuration of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view (part 2) illustrating the configuration of the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 3) illustrating the configuration of the semiconductor device according to the embodiment. [Figure 4] 1 is a plan view (part 1) showing the layout of a wiring layer and a polycrystalline silicon film in a semiconductor device according to an embodiment. [Figure 5] 10 is a plan view (part 2) showing the layout of the wiring layer and the polycrystalline silicon film in the semiconductor device according to the embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description may be omitted.

[0010] The embodiments relate to a semiconductor device including a transistor. FIGS. 1 to 3 are cross-sectional views showing the configuration of a semiconductor device according to the embodiments. FIG. 4 is a plan view showing the layout of a wiring layer 40 and a polycrystalline silicon film 61 in a semiconductor device according to the embodiments. FIG. 5 is a plan view showing the layout of a wiring layer 50 and a polycrystalline silicon film 61 in a semiconductor device according to the embodiments. FIG. 1 corresponds to a cross-sectional view taken along line II in FIGS. 4 and 5. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIGS. 4 and 5. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIGS. 4 and 5.

[0011] The semiconductor device 100 according to the embodiment has a p-type semiconductor substrate 10. The semiconductor substrate 10 has a main surface 10A. An n-type well 11 is provided in the main surface 10A, and a p-type well 12 is provided in the main surface 10A within the well 11. An n-type source region 13 is provided in the main surface 10A within the well 12. Furthermore, an n-type high-concentration well 14 having a high impurity concentration is provided in the main surface 10A within the well 11, away from the well 12. The well 11 and the high-concentration well 14 function as a drain region.

[0012] An insulating film 20 is provided on the main surface 10A, and openings 21 and 22 are formed in the insulating film 20. The source region 13, the well 12, and a portion of the well 11 are connected to each other and exposed through the opening 21, and the high-concentration well 14 is exposed through the opening 22. Inside the opening 21, a gate insulating film 31 is provided on the main surface 10A in contact with the wells 11 and 12. A gate electrode 32 is provided on the gate insulating film 31. A portion of the gate electrode 32 is on the insulating film 20. The gate electrode 32 is made of, for example, polycrystalline silicon.

[0013] An insulating film 91 is provided on the insulating film 20, the source region 13, the heavily doped well 14, and the gate electrode 32. The insulating film 91 is composed of a plurality of interlayer insulating films. The semiconductor device 100 has, within the insulating film 91, a polycrystalline silicon film 61, conductive vias 64 and 65, conductive vias 71, 72, and 73, a wiring layer 40, conductive vias 81 and 83, and a wiring layer 50.

[0014] The wiring layer 40 is composed of a conductive film such as an aluminum (Al)-silicon (Si) alloy film. The wiring layer 40 includes regions 41, 42, 43, 44, and 45. As shown in FIGS. 4 and 5 , the region 43 is formed in a disk shape. The region 44 is formed in an arc shape at four locations around the region 43, and the region 45 is formed in an arc shape at four locations around the region 43. In a plan view, the regions 44 and 45 are alternately arranged around the region 43. The region 44 is longer than the region 45 in the circumferential direction of the region 43. The regions 44 and 45 are both arranged in a four-fold rotational symmetry around the center of the region 43. The region 44 is connected to the region 43, and the region 45 is separated from the region 43. The region 42 is formed in a ring shape around the regions 43, 44, and 45, and the region 41 is formed in a ring shape around the region 42. A portion of region 41 is provided above source region 13, and region 41 is electrically connected to source region 13 by conductive via 71. A portion of region 42 is provided above gate electrode 32, and region 42 is electrically connected to gate electrode 32 by conductive via 72. A portion of region 43 is provided above heavily doped well 14, and region 43 is electrically connected to heavily doped well 14 by conductive via 73. Wiring layer 40 is an example of a first wiring layer. Regions 43 and 44 are examples of a first region, and region 45 is an example of a second region.

[0015] The wiring layer 50 is composed of a conductive film such as an aluminum (Al)-silicon (Si) alloy film. The wiring layer 50 is on an interlayer insulating film on the wiring layer 40. The wiring layer 50 includes regions 51, 53, and 54. As shown in FIGS. 4 and 5 , the region 53 is provided in a disk shape. The region 53 is provided in a disk shape above the region 43. The region 54 is provided in an arc shape at four locations around the region 53. The region 54 is arranged with four-fold rotational symmetry around the center of the region 53. The region 54 is connected to the region 53. A portion of the region 54 overlaps with the region 45 in a planar view. The region 54 is electrically connected to the region 45 by a conductive via 83. The region 51 is provided in a ring shape around the regions 53 and 54. The region 51 is provided above the region 41 and is electrically connected to the region 41 by a conductive via 81. The wiring layer 50 is an example of a second wiring layer. The regions 53 and 54 are examples of a third region.

[0016] The polycrystalline silicon film 61 is located between the insulating film 20 and the wiring layer 40. As shown in FIGS. 4 and 5 , the polycrystalline silicon film 61 is provided in four arc-shaped locations so as to overlap a pair of regions 44 and 45 in a plan view. The polycrystalline silicon film 61 is electrically connected to the region 44 by a conductive via 64 and to the region 45 by a conductive via 65. For example, the width of the polycrystalline silicon film 61 is 6 μm to 7 μm, and the length is 10 μm to 35 μm. For example, the material of the polycrystalline silicon film 61 is different from the material of the gate electrode 32, and the resistivity of the polycrystalline silicon film 61 is higher than the resistivity of the gate electrode 32. The polycrystalline silicon film 61 may be formed from the same material as the gate electrode 32, and the resistivity of the polycrystalline silicon film 61 may be equal to the resistivity of the gate electrode 32.

[0017] The conductive via 71, region 41, conductive via 81, and region 51 are electrically connected to the source region 13 and are included in the source wiring 101. The conductive via 72 and region 42 are electrically connected to the gate electrode 32 and are included in the gate wiring 102. The conductive via 73, region 43, region 44, conductive via 64, polycrystalline silicon film 61, conductive via 65, region 45, conductive via 83, region 54, and region 53 are electrically connected to the high-concentration well 14 and are included in the drain wiring 103. The conductive via 73, region 43, region 44, and conductive via 64 are an example of a first wiring portion. The conductive via 65, region 45, conductive via 83, region 54, and region 53 are an example of a second wiring portion. The resistivity of the polycrystalline silicon film 61 is higher than the resistivity of the first wiring portion and the resistivity of the second wiring portion.

[0018] As described above, in the semiconductor device 100, four polycrystalline silicon films 61 are connected in parallel between the first wiring portion (conductive via 73, region 43, region 44, and conductive via 64) and the second wiring portion (conductive via 65, region 45, conductive via 83, region 54, and region 53). When a voltage of 200 V is applied between region 53 and region 51, for example, the resistance between the first wiring portion and the second wiring portion, i.e., the combined resistance of the four polycrystalline silicon films 61, is 150 Ω or more and 250 Ω or less.

[0019] A protective film 92 is provided on an insulating film 91. The protective film 92 is, for example, a nitride film. The protective film 92 may have a nitride film and a polyimide film thereon. An opening 93 is formed in the protective film 92 and the insulating film 91, exposing a part of the region 53. The protective film 92 and the insulating film 91 are examples of insulating films.

[0020] In the semiconductor device 100, the polycrystalline silicon film 61 is electrically connected between the region 53 and the heavily doped well 14, and the portion of the region 53 exposed through the opening 93 is used as a pad and functions as a resistive element. This makes it possible to omit a resistive element between the transistor pad and the power supply pad to which an AC power supply is connected. Therefore, the semiconductor device 100 can be made smaller.

[0021] The number of polycrystalline silicon films 61 connected between the first wiring portion and the second wiring portion is not limited to four. One polycrystalline silicon film 61 may be connected between the first wiring portion and the second wiring portion, or two, three, or five or more polycrystalline silicon films 61 may be connected in parallel. When multiple polycrystalline silicon films 61 are connected in parallel, even if one of the polycrystalline silicon films 61 is disconnected due to an overcurrent or the like, the power supply voltage can be supplied to the transistor through the remaining polycrystalline silicon films 61. Furthermore, when the number of polycrystalline silicon films 61 is four, the planar configuration of the transistor can be made four-fold rotationally symmetric, so that the entire configuration can be obtained by designing only one-quarter of the configuration, which makes it easy to reduce the time and effort required for design.

[0022] Furthermore, the voltage applied to the transistor is not limited to 200 V, but may be 700 V, etc. The resistivity and size of the polycrystalline silicon film 61 may be adjusted according to the voltage applied to the transistor.

[0023] Although the preferred embodiments have been described above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0024] 10. Semiconductor substrate 10A main surface 13 Source Region 14 High concentration wells 31 Gate insulating film 32 gate electrode 40, 50 wiring layers 41, 42, 43, 44, 45, 51, 53, 54 area 61 Polycrystalline silicon film 100 Semiconductor device 101 Source wiring 102 Gate wiring 103 Drain wiring

Claims

1. a source region and a drain region provided on a main surface of a semiconductor substrate; a gate insulating film provided on the main surface between the source region and the drain region; a gate electrode provided on the gate insulating film; a drain wiring electrically connected to the drain region; and The drain wiring is a first wiring portion electrically connected to the drain region; A second wiring portion; a polycrystalline silicon film electrically connected between the first wiring portion and the second wiring portion; A semiconductor device having:

2. an insulating film covering the drain wiring; The semiconductor device according to claim 1 , wherein the insulating film has an opening through which a part of the second wiring portion is exposed.

3. a first wiring layer provided above the main surface; a second wiring layer provided above the first wiring layer; and the first wiring portion has a first region included in the first wiring layer, The second wiring portion is a second region included in the first wiring layer; a third region included in the second wiring layer; 3. The semiconductor device according to claim 1, further comprising:

4. 3. The semiconductor device according to claim 1, wherein a plurality of the polycrystalline silicon films are connected in parallel between the first wiring portion and the second wiring portion.

5. 3. The semiconductor device according to claim 1, wherein four of the polycrystalline silicon films are connected in parallel between the first wiring portion and the second wiring portion.

6. 3. The semiconductor device according to claim 1, wherein the resistivity of the polycrystalline silicon film is higher than the resistivity of the first wiring portion and the resistivity of the second wiring portion.

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