Enabling static program code memory access patterns

Abstract

A computer system configured to perform operations for validating a memory access pattern of a static variant of a program instruction stream, the operations including randomizing a first set of input arguments, generating an address translation list for virtual addresses based on the memory access pattern, storing the memory accesses in a first table, and executing the static variant of the program instruction stream on an accelerator processing unit. During execution, virtual addresses may be discarded and replaced by addresses provided in the address translation list. The operations may include recording and storing each memory access of the execution of the static variant of the program instruction stream in a second table, and comparing the memory access pattern stored in the second table with the memory access pattern stored in the first table. The memory access pattern may be validated or discarded.

Description

[Technical field]

[0001] The present disclosure relates generally to data processing systems, and more particularly to a method, computer system, computer program, and data processing system for validating memory access patterns of static variants of a program instruction stream. [Background technology]

[0002] When working with embedded programmable accelerator processing units in business-critical systems, it is crucial to preserve the validity and integrity of the code that runs on the processing unit. One way to achieve this is to only allow pre-validated static program code templates to execute.

[0003] However, when implementing deep learning algorithms, many input arguments and variables need to be provided to the algorithm to fit the specific problem. These need to be passed in the form of variables or arguments to the static program code. The program code can interpret those variables and alter the control flow of the program without changing the actual static program instruction stream.

[0004] To provide data to deep learning algorithms, data must be read from memory and written back to memory during execution and after the program code has finished. On accelerator processing units that lack a dedicated memory management unit to handle the translation, memory accesses performed by the program code target a linear virtual address space. Such systems presuppose the availability of an external memory translation mechanism capable of mapping the virtual addresses provided by the accelerator processing unit to actual system memory addresses.

[0005] To simplify this mapping mechanism, the memory access patterns imposed by the code executed on the accelerator processing units need to be calculated before the program execution: the access patterns depend on the arguments passed to the algorithm implemented by the program.

[0006] The main challenge in such systems is to extract and specify the address access patterns imposed by the program code. This must be done for many or all combinations of the input arguments. Furthermore, one must use static or templated program code that depends only on the input variables mentioned above. Summary of the Invention

[0007] Embodiments of the present disclosure include computer systems, computer program products, data processing systems, and computer-implemented methods for validating memory access patterns of static variants of a program instruction stream.

[0008] A computer system according to the present disclosure may include a randomization unit, a program code generator, an accelerator processing unit, an access recording unit, and a memory. The computer system may be configured to perform operations including randomizing a first set of input arguments and generating, for a flat memory space of the memory, an address translation list of virtual addresses based on the primary memory access pattern. The operations may include storing the primary memory access pattern in a first table in the flat memory space and generating, with the code generator, a static variant of the program instruction stream independent of the input arguments. The operations may include passing the first set of input arguments to the code generator and executing, on the accelerator processing unit, the static variant of the program instruction stream, where the virtual addresses may be replaced by the address translations provided in the address translation list. The operations may include recording and storing, in a second table in the flat memory space, a secondary memory access pattern of the execution of the static variant of the program instruction stream and comparing the secondary memory access pattern stored in the second table to the primary memory access pattern stored in the first table. The operations may include enabling a primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

[0009] A flat memory model may refer to a memory addressing paradigm in which memory appears to a program as a single, contiguous address space. A processing unit can directly and linearly address all of the available memory locations, without having to resort to any kind of memory segmentation or paging scheme.

[0010] In some embodiments of the present disclosure, memory address substitution may be performed based on a pre-recorded address translation list.

[0011] Randomized input arguments to the deep learning algorithm implemented by the program code are selected. A static variant of the program instruction stream, which may correspond to the generation-level program code used with the deep learning algorithm, is executed with these arguments. The accelerator unit on which the static program code is executed does not support any means of address translation. Therefore, a pre-recorded address translation list may be used. For each memory access, the virtual address may be ignored and replaced by an address from the address translation list.

[0012] If the access pattern imposed by the static program code matches the access pattern of an already validated pre-recorded address list, then the static program code and access pattern may be considered correct for a given set of input arguments, and thus that memory access pattern may be validated.

[0013] The present disclosure provides several advantages and enables efficient testing of static program code templates within the field of artificial intelligence acceleration.

[0014] The present disclosure removes the need to know or simulate memory access patterns within a test environment. It facilitates left shifting for testing, especially during the development phase of accelerator program code, because memory access patterns have been recorded during initial operation. The effort of the test environment is significantly reduced. The method significantly simplifies the test environment by eliminating the need for a memory translation unit or software.

[0015] This disclosure may be primarily of value to developers of embedded accelerators that require enhanced security, and may also be of value to vendors of validation tools.

[0016] In some embodiments of the present disclosure, the address translation list may be generated by passing the first set of input arguments to a program code generator and executing the dynamic variant of the program instruction stream on the accelerator processing unit to generate a dynamic variant of the program instruction stream that is tailored to the first set of arguments, and during execution, all memory translation mechanisms may be deactivated to provide a flat memory space. This embodiment may further include recording and storing memory accesses of the execution of the dynamic variant of the program instruction stream in a first table in the flat memory space.

[0017] Randomized input arguments may be passed to a program code generator to generate a dynamic variant of the program instruction stream that is custom tailored to the input arguments. The custom tailored version is not static and should not be used as final production code and may present security concerns. This can be used as a means to advance a step in the process and facilitate the use of more simplified program code.

[0018] The generated dynamic code may be executed on an accelerator processing unit. During execution, all memory translation mechanisms in the system may be deactivated to provide a flat memory space. All memory accesses, directions, and addresses may be recorded using an appropriate hardware mechanism, such as an access recorder unit, and stored for later use.

[0019] In some embodiments of the present disclosure, additionally or alternatively, the address translation list may be generated by pre-calculating an address access pattern based on the first set of input arguments.

[0020] In some embodiments of the present disclosure, memory address substitutions may be used based on deterministic predictions. In the case of production code, when static program code is enabled, the memory access pattern for its set of input arguments is predictable, and a list of memory accesses may be preloaded into the access recorder unit. In some embodiments, the address pattern may be precomputed based on the input arguments and an address translation list loaded into the access recorder unit for populating memory addresses.

[0021] In some embodiments of the present disclosure, a memory access may additionally or alternatively include an address and data to fully describe the memory access.

[0022] In some embodiments of the present disclosure, additionally or alternatively, an address translation list may be stored in an access recorder unit from which it may be used for address translation, for example, in additional portions of the processing or by further variants of the program instruction stream.

[0023] In some embodiments of the present disclosure, additionally or alternatively, permuting addresses for memory accesses may be based on an order of memory requests in a program instruction stream, hi some embodiments, permuting memory addresses may be based strictly on an order of memory requests for efficient execution of the program code.

[0024] In some embodiments of the present disclosure, additionally or alternatively, prior to executing the program instruction stream, an address translation list may be preloaded into the access recorder unit, from which the address translation list may be used for further address translations in further steps of processing or by further variants of the program instruction stream.

[0025] In some embodiments of the present disclosure, the access recorder unit may additionally or alternatively be configured to record memory accesses as well as inject the memory accesses into the memory, and thus the access recorder unit may store memory accesses of a previous operation (e.g., of a dynamic variant of the program instruction stream) and provide the stored memory accesses in a subsequent operation (e.g., of a static variant of the program instruction stream).

[0026] In some embodiments of the present disclosure, the access recorder unit may additionally or alternatively be configured with a selection element for recording memory accesses or for injecting memory accesses into the memory. Such a configuration may facilitate handling of the access recorder unit for use at different stages of a memory access pattern validation process.

[0027] In some embodiments of the present disclosure, additionally or alternatively, execution of a static variant of the program instruction stream may be repeated with different sets of input arguments to validate memory access patterns, and repeated execution may ensure the validity of the static program code and the predefined access patterns across many input arguments.

[0028] In some embodiments of the present disclosure, an automated regression system may additionally or alternatively be used to iterate the validation of memory access patterns with different sets of input arguments. In this manner, various combinations of input arguments may be used to ensure the validity of the static program code and the predefined access patterns across the input arguments.

[0029] According to some embodiments of the present disclosure, a computer-implemented method is proposed for validating a memory access pattern of a static variant of a program instruction stream on a computer system, the computer system being at least comprised of a randomizer unit, a program code generator, an accelerator processing unit, an access recorder unit, and a memory. The method may include storing a primary memory access pattern in a first table in a flat memory space, and generating, with the code generator, a static variant of the program instruction stream that is independent of input arguments. The method may include passing a first set of input arguments to the code generator, and executing, on the accelerator processing unit, the static variant of the program instruction stream, where the virtual addresses may be replaced by address translations provided in the address translation list. The method may include recording and storing, in a second table in the flat memory space, a secondary memory access pattern of the execution of the static variant of the program instruction stream, and comparing the secondary memory access pattern stored in the second table with the primary memory access pattern stored in the first table. The method may include enabling a primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

[0030] In some embodiments, memory address substitution may be performed based on a pre-recorded address translation list.

[0031] Randomized input arguments to the deep learning algorithm implemented by the program code may be selected. A static variant of the program instruction stream, which may correspond to the generation-level program code used with the deep learning algorithm, may be executed with these arguments. The accelerator unit on which the static program code is executed does not support any means of address translation. Therefore, a pre-recorded address translation list may be used. For each memory access, the virtual address may be ignored and replaced by an address from the address translation list.

[0032] If the access pattern imposed by the static program code matches the access pattern of an already validated pre-recorded address list, then the static program code and access pattern can be considered correct for a given set of input arguments. In this way, the memory access pattern is validated.

[0033] The use of the proposed disclosure offers several advantages and allows for efficient testing of static program code templates within the field of artificial intelligence acceleration.

[0034] In some embodiments of the present disclosure, the computer system may be configured to generate an address translation list by passing the first set of input arguments to a program code generator to generate a dynamic variant of the program instruction stream that is tailored to the first set of input arguments and executing the dynamic variant of the program instruction stream on an accelerator processing unit, wherein during execution, all memory translation mechanisms are deactivated to provide a flat memory space. In some embodiments, the computer system may include recording and storing memory accesses of the execution of the dynamic variant of the program instruction stream in a first table in the flat memory space.

[0035] In some embodiments of the present disclosure, the selected randomized input arguments may be passed to a program code generator to generate a dynamic variant of the program instruction stream that is custom tailored to the input arguments. This custom tailored version should not be used as final production code because it is not static and therefore may represent a security concern. It may facilitate further processing and the use of simpler program code.

[0036] In some embodiments of the present disclosure, the generated dynamic code may be executed on an accelerator processing unit. During execution, all memory translation mechanisms in the system may be deactivated to provide a flat memory space. Memory accesses, directions, and addresses may be recorded using an appropriate hardware mechanism, such as an access recorder unit, and stored for later use.

[0037] In some embodiments of the present disclosure, the computer system may be configured to generate the address translation list by pre-calculating an address access pattern based on a first set of input arguments.

[0038] In some embodiments of the present disclosure, memory address substitutions may be used based on deterministic predictions. In the case of production code, when the static program code is enabled, the memory access pattern for a set of input arguments is predictable, and a list of memory accesses may be preloaded into the access recorder unit. The address pattern may be precomputed based on the input arguments and the address translation list loaded into the access recorder unit for the input of memory addresses.

[0039] In some embodiments of the present disclosure, a memory access may include an address and data, hi some embodiments, a memory access may be fully described in this manner.

[0040] In some embodiments of the present disclosure, the computer system may be configured to store the address translation list in an access recorder unit, from which the address translation list may be used for further address translations in further steps of processing or by further variants of the program instruction stream.

[0041] In some embodiments of the present disclosure, the method may include permuting addresses for memory accesses based on an order of memory requests in a program instruction stream, in some embodiments, the permutation of memory addresses may be based strictly on an order of memory requests for efficient execution of the program code.

[0042] In some embodiments of the present disclosure, the method may include pre-loading the address translation list into an access recorder unit prior to execution of the program instruction stream, from which the address translation list may be used for further address translations in further steps of processing or by further variants of the program instruction stream.

[0043] In some embodiments of the present disclosure, the access recorder unit may be configured to record memory accesses as well as inject memory accesses into the memory. The access recorder unit may store memory accesses of a previous operation (e.g., of a dynamic variant of the program instruction stream) and may provide the stored memory accesses in a subsequent operation (e.g., of a static variant of the program instruction stream).

[0044] In some embodiments of the present disclosure, the access recorder unit may additionally or alternatively be configured with a selection element for recording memory accesses or for injecting memory accesses into the memory. Such a configuration may facilitate handling of the access recorder unit for use at different stages of a memory access pattern validation process.

[0045] In some embodiments of the present disclosure, the computer system may additionally or alternatively be configured to repeat execution of a static variant of the program instruction stream with different sets of input arguments to validate memory access patterns, whereby the repeated execution can ensure the validity of the static program code and the predefined access patterns across many input arguments.

[0046] In some embodiments of the present disclosure, the computer system may additionally or alternatively be configured to use an automated regression system to repeatedly validate memory access patterns with different sets of input arguments. Multiple combinations of input arguments may be used to ensure the validity of static program code and a given access pattern across the input arguments.

[0047] According to some embodiments of the present disclosure, a computer program product may enable a memory access pattern of a static variant of a program instruction stream on a computer system. The computer system may be comprised of a randomizer unit, a program code generator, an accelerator processing unit, an access recorder unit, and a memory. In some embodiments of the present disclosure, the computer program product includes a computer readable medium having program instructions embodied therein. The program instructions may be executable by the computer system to cause the computer system to execute a method. The method may include storing the primary memory access pattern in a first table in a flat memory space and generating, with a code generator, a static variant of the program instruction stream that is independent of the input arguments. The method may include passing a first set of input arguments to the code generator and executing, on the accelerator processing unit, the static variant of the program instruction stream, where the virtual address may be replaced by an address translation provided in the address translation list. The method may include recording and storing a secondary memory access pattern of the execution of the static variant of the program instruction stream in a second table in the flat memory space and comparing the secondary memory access pattern stored in the second table with the primary memory access pattern stored in the first table. The method may include enabling the primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

[0048] In some embodiments of the present disclosure, a mismatched memory access pattern may be an indication that the memory access pattern is incorrect and / or that a static variant of the code cannot produce the same results as a dynamic variant (e.g., one or more of the variants of the code may be defective).

[0049] In some embodiments of the present disclosure, a data processing system for execution of a data processing program is proposed, comprising computer readable program instructions for performing a method. The method may include storing a primary memory access pattern in a first table in a flat memory space, and generating, with a code generator, a static variant of the program instruction stream that is independent of input arguments. The method may include passing a first set of input arguments to the code generator, and executing the static variant of the program instruction stream on an accelerator processing unit, where the virtual addresses may be replaced by address translations provided in the address translation list. The method may include recording and storing, in a second table in the flat memory space, a secondary memory access pattern of the execution of the static variant of the program instruction stream, and comparing the secondary memory access pattern stored in the second table with the primary memory access pattern stored in the first table. The method may include enabling a primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

[0050] In some embodiments of the present disclosure, the address translation list may be generated by passing the first set of input arguments to a program code generator and executing the dynamic variant of the program instruction stream on the accelerator processing unit to generate a dynamic variant of the program instruction stream that is tailored to the first set of input arguments, and during execution, all memory translation mechanisms may be deactivated to provide a flat memory space. This embodiment may further include recording and storing memory accesses of the execution of the dynamic variant of the program instruction stream in a first table in the flat memory space.

[0051] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

[0052] The drawings contained in this application are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The drawings are merely illustrative of particular embodiments and are not intended to limit the disclosure. [Brief description of the drawings]

[0053] [Figure 1] FIG. 1 illustrates a computer system for validating memory access patterns of static variants of a program instruction stream that execute dynamic variants of the program instruction stream to create an address translation list, in accordance with some embodiments of the present disclosure. [Diagram 2] FIG. 1 illustrates a computer system that executes static variants of a program instruction stream to enable memory access patterns in accordance with some embodiments of the present disclosure. [Diagram 3] FIG. 1 illustrates a computer system for validating memory access patterns of static variants of a program instruction stream by pre-calculating address access patterns, in accordance with some embodiments of the present disclosure. [Figure 4] FIG. 1 illustrates an exemplary embodiment of a data processing system for performing methods according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] The present disclosure relates generally to data processing systems, and more particularly to computer systems, computer program products, data processing systems, and computer-implemented methods for validating memory access patterns of static variants of a program instruction stream.

[0055] In the drawings, like elements may be referred to by the same reference numerals. The drawings are not schematic representations intended to portray specific parameters of the present disclosure. Moreover, the drawings are merely illustrative of certain embodiments and are not intended to limit the present disclosure.

[0056] Exemplary embodiments described herein provide a computer system for validating memory access patterns of static variants of a program instruction stream, the computer system may include a randomization unit, a program code generator, an accelerator processing unit, an access recorder unit, and a memory.

[0057] Exemplary embodiments may further be used to randomize the first set of input arguments, generate an address translation list for the virtual addresses based on the memory access pattern into a flat memory space of the memory, and store the memory accesses in a first table in the flat memory space. Exemplary embodiments may be used to pass the first set of input arguments to a program code generator for generating a static variant of the program instruction stream that is independent of the input arguments to execute the static variant of the program instruction stream on an accelerator processing unit, where during execution, for every memory access, the address may be discarded and replaced by an address provided in the address translation list. Exemplary embodiments may be used to record and store each memory access of the execution of the static variant of the program instruction stream in a second table in the flat memory space, and compare the memory access pattern stored in the second table with the memory access pattern stored in the first table. Exemplary embodiments may be used to enable a primary memory access pattern for a set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or to discard the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

[0058] 1 illustrates a computer system 212 for validating memory access patterns of a static variant of a program instruction stream in accordance with some embodiments of the present disclosure. The system 212 is shown in a first operation of executing a dynamic variant of the program instruction stream to generate an address translation list 12.

[0059] The computer system 212 includes the randomizer unit 100, the program code generator 102, the accelerator processing unit 104, the access recorder unit 106, and the memory 108. The computer system 212 is configured to execute the proposed computer-implemented method for validating memory access patterns of static variants of a program instruction stream.

[0060] The input arguments 10 may be submitted to a deep learning algorithm implemented by a program instruction stream. The input arguments 10 may be selected by randomizing a first set of input arguments 10 with a randomization unit 100.

[0061] The input arguments 10 can be passed to a program code generator 102 to generate a dynamic variant of the program instruction stream that is custom tailored to the first set of input arguments 10. The custom tailored version should not be used as final production code because it is not static and therefore may represent a security concern, but may be used for further processing and to facilitate simpler code usage.

[0062] The generated dynamic code 20 may be executed on the accelerator processing unit 104. During execution, all memory translation mechanisms of the computer system 212 may be deactivated. A flat memory space may be provided. Memory accesses, directions, and addresses may be recorded using the access recorder unit 106 or other suitable hardware mechanisms and stored in an address translation list 12 for later use. The address translation list 12 may be stored in the access recorder unit 106.

[0063] Memory accesses, including addresses and data, for executing the dynamic variant of the program instruction stream may be stored in a flat memory space in a first table 14. In some embodiments, each memory access for executing the dynamic variant of the program instruction stream may be stored in the first table 14.

[0064] Memory access in the embodiment shown in Figure 1 may be performed by memory interfaces 112, 114. For example, store command 24 (ST400 = store at address 400) in Figure 1 is performed by memory interfaces 112, 114. Store command 24 is shown as ST400, which means store at address 400. Data may be stored below address 400 in memory 108.

[0065] The access recorder unit 106 may be configured to record memory accesses as well as to inject memory accesses to the memory 108. Thus, the access recorder unit 106 may include a selection element 110 for recording memory accesses or injecting memory accesses to the memory 108. During execution of a dynamic variant of the program instruction stream, as shown in FIG. 1, the selection element 110 may be switched to recording.

[0066] 2 illustrates a computer system 212 in a second operation of executing static variants of a program instruction stream to validate memory access patterns, in which memory address substitutions may be performed based on a pre-recorded address translation list 12.

[0067] The algorithm embodied in the program instruction stream may be executed using the same input arguments 10 selected in Figure 1. Static or generated level program code may be used. The memory accesses observed during such a call may differ from those of the first operation, since the accelerator processing unit 104 on which the program code is executing may not support a means of address translation.

[0068] To ensure that the memory access pattern (but not the actual memory addresses) of the second operation matches that of the first operation, the address translation list 12 may be pre-loaded with memory accesses recorded during the first operation. For each memory access observed during the second operation, the virtual address may be ignored, such as by marking the respective store command 26 with a cross, and replaced by the address recorded during the first operation and stored in the address translation list 12. This replacement may be strictly based on the order of the memory requests.

[0069] Memory accesses of the execution of the static variant of the program instruction stream may be recorded and stored in a second table 16 in a flat memory space of the memory 108. In some embodiments, each memory access may be recorded in the second table 16.

[0070] If the access patterns recorded during the first operation match the access patterns imposed by the code of the static program 22, the final program output may need to match that of the first operation. The combination of program code and access patterns may then be considered correct for a given set of input arguments 10. Thus, the memory access patterns stored in the second table 16 may be compared with the memory access patterns stored in the first table 14 during the first operation with the dynamic variant of the program instruction stream.

[0071] If a memory access pattern in the second table 16 matches a memory access pattern in the first table 14, then the memory access pattern is valid for that set of input arguments 10. Validating the memory access pattern may prove functional equivalence of static and dynamic program code.

[0072] If a memory access pattern in the second table 16 does not match a memory access pattern in the first table 14, then this memory access pattern may be discarded.

[0073] To ensure the validity of the code in static program 22, a given access pattern across many of the input arguments for both operations illustrated in Figures 1 and 2 may be repeated for other combinations of input arguments. In some embodiments, an automated regression system may be used to select one or more of the combinations of input arguments.

[0074] 3 illustrates a computer system 212 for validating memory access patterns of static variants of a program instruction stream according to some embodiments of the present disclosure. The system 212 may include pre-calculating the address access patterns. Memory address substitutions may be performed based on a deterministic prediction of the memory access patterns.

[0075] In the case of production code, when the static program code is enabled, a memory access pattern for a first set of input arguments 10 may be predicted and a list of memory accesses may be pre-loaded into the access recorder unit. Thereby, the address pattern may be pre-calculated in a pre-calculation S100 based on the first set of input arguments 10. This pre-calculation may be loaded as an address translation list 12, and in some embodiments, this pre-calculation may be directly loaded into the access recorder unit 106 in the injection mode such that the selection element 110 is switched to injection, as shown in FIG.

[0076] 4 illustrates a schematic diagram of an example of a data processing system 210. Although a data processing system 210 is illustrated, in some embodiments, one or more other suitable data processing systems may be used. The data processing system 210 may be capable of implementing and / or performing any of the functions described herein.

[0077] The data processing system 210 includes a computer system / server 212, which may be operational with many other general purpose or special purpose computer system environments or configurations. Examples of well-known computer systems, environments, or configurations, or combinations thereof, that may be suitable for use with the computer system / server 212 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or notebook PCs, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0078] The computer system / server 212 may be described in the general context of computer system executable instructions (e.g., program modules) executed by a computer system. Program modules may include, for example, routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular data types (e.g., abstract data types). The computer system / server 212 may be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0079] The computer system / server 212 of the data processing system 210 is shown in the form of a general purpose computing device. Components of the computer system / server 212 may include, but are not limited to, one or more processors or processing units 216, a system memory 228, and a bus 218 that couples various system components including the system memory 228 to the processor 216.

[0080] Bus 218 represents one or more of any of several types of bus structures, which may include a memory bus, a memory controller, a peripheral bus, an accelerated graphics port, and / or a processor or local bus using any of a variety of bus architectures, such as, for example, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and / or a Peripheral Component Interconnect (PCI) bus.

[0081] Computer system / server 212 may include a variety of computer system readable media. Such media may be any available media that can be accessed by computer system / server 212 and includes both volatile and nonvolatile media, removable and non-removable media.

[0082] The system memory 228 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 230 and / or cache memory 232. The computer system / server 212 may further include other removable / non-removable, volatile / non-volatile computer system storage media. For example, a storage system 234 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (e.g., a hard disk, not shown). In some embodiments, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a floppy disk) and an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical media may be provided. In such embodiments, each storage mechanism may be connected to the bus 218 by one or more data media interfaces. In some embodiments, the memory 228 may include at least one program product having a set (e.g., at least one) of program modules configured to implement the functionality of embodiments of the present disclosure.

[0083] The memory 228 may store a program / utility 240 having a set (e.g., at least one) of program modules 242. The memory 228 may also store an operating system, one or more application programs, other program modules, and / or program data. Each of the operating system, one or more application programs, other program modules, and program data, or combinations thereof, may include one or more implementations of a networking environment. The program modules 242 may perform the functions and / or methodologies of the embodiments of the present disclosure described herein.

[0084] The computer system / server 212 may communicate with one or more external devices 214, such as a keyboard, pointing device, display 224, and the like. The computer system / server 212 may communicate with one or more devices that allow a user to interact with the computer system / server 212 or any device that allows the computer system / server 212 to communicate with one or more other computing devices (e.g., network cards, modems, etc.). Such communication may occur through an input / output (I / O) interface 222 or other interfaces, or both. The computer system / server 212 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet) or combinations thereof, via a network adapter 220. As shown, the network adapter 220 communicates with other components of the computer system / server 212 via a bus 218. Although not shown, it is understood that other hardware and / or software components may be used in conjunction with computer system / server 212. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data archive storage systems, etc.

[0085] The present disclosure may be a system, method, and / or computer program product, which may include a computer-readable storage medium having computer-readable program instructions for causing a processor to implement aspects of the present disclosure.

[0086] A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. For example, a computer-readable storage medium may be, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or ridge structures in a groove having instructions recorded thereon, and any suitable combination of the above. As used herein, computer-readable storage media is not intended to be understood as transitory signals per se, such as electric waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted through wires.

[0087] The computer readable program instructions described herein may be downloaded to the respective computing and / or processing devices from a computer readable storage medium or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions for storage in the computer readable storage medium within the respective computing and / or processing device.

[0088] The computer readable program instructions for carrying out the operations of the present disclosure may include either source or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk, C++, or the like, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or a connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic circuit (PLA), may execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to perform aspects of the present disclosure.

[0089] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0090] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in the flowchart or block diagram blocks. These computer readable program instructions may be stored in a computer readable storage medium to cause the computer, programmable data processing apparatus, or other apparatus, or combination thereof, to function in a particular manner such that the computer readable storage medium on which the instructions are stored comprises an article of manufacture including instructions implementing aspects of the functions / acts specified in the flowchart or block diagram blocks.

[0091] The computer readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device, such that the instructions, which execute on a computer, other programmable apparatus, or other device, perform the functions / acts specified in the blocks of the flowcharts and / or block diagrams.

[0092] According to some embodiments of the present disclosure, a computer system may include a randomization unit, a program code generator, an accelerator processing unit, an access recorder unit, and a memory. The computer system may be configured to perform operations including randomizing a first set of input arguments and generating, for a flat memory space of the memory, an address translation list of virtual addresses based on a primary memory access pattern. The operations may include storing the primary memory access pattern in a first table in the flat memory space and generating, with the code generator, a static variant of the program instruction stream that is independent of the input arguments. The operations may include passing the first set of input arguments to the code generator and executing, on the accelerator processing unit, the static variant of the program instruction stream, where the virtual addresses may be replaced by the address translations provided in the address translation list. The operations may include recording and storing a secondary memory access pattern of the execution of the static variant of the program instruction stream in a second table in the flat memory space and comparing the secondary memory access pattern stored in the second table with the primary memory access pattern stored in the first table. The operations may include enabling the primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

[0093] A flat memory model may refer to a memory addressing paradigm in which memory appears to a program as a single, contiguous address space. A processing unit can directly and linearly address all of the available memory locations, without having to resort to any kind of memory segmentation or paging scheme.

[0094] In some embodiments of the present disclosure, memory address substitution may be performed based on a pre-recorded address translation list.

[0095] Randomized input arguments to the deep learning algorithm implemented by the program code are selected. A static variant of the program instruction stream, which may correspond to the generation-level program code used with the deep learning algorithm, is executed with these arguments. The accelerator unit on which the static program code is executed does not support any means of address translation. Therefore, a pre-recorded address translation list may be used. For each memory access, the virtual address may be ignored and replaced by an address from the address translation list.

[0096] If the access pattern imposed by the static program code matches the access pattern of an already validated pre-recorded address list, then the static program code and access pattern may be considered correct for a given set of input arguments, and thus that memory access pattern may be validated.

[0097] The present disclosure provides several advantages and enables efficient testing of static program code templates within the field of artificial intelligence acceleration.

[0098] The present disclosure removes the need to know or simulate memory access patterns within a test environment. It facilitates left shifting for testing, especially during the development phase of accelerator program code, because memory access patterns have been recorded during initial operation. The effort of the test environment is significantly reduced. The method significantly simplifies the test environment by eliminating the need for a memory translation unit or software.

[0099] This disclosure may be primarily of value to developers of embedded accelerators that require enhanced security, and may also be of value to vendors of validation tools.

[0100] In some embodiments of the present disclosure, the address translation list may be generated by passing the first set of input arguments to a program code generator and executing the dynamic variant of the program instruction stream on the accelerator processing unit to generate a dynamic variant of the program instruction stream that is tailored to the first set of input arguments, and during execution, all memory translation mechanisms may be deactivated to provide a flat memory space. This embodiment may further include recording and storing memory accesses of the execution of the dynamic variant of the program instruction stream in a first table in the flat memory space.

[0101] Randomized input arguments may be passed to a program code generator to generate a dynamic variant of the program instruction stream that is custom tailored to the input arguments. This custom tailored version should not be used as final production code because it is not static and may present security concerns. This can be used as a means to advance a step in the process and facilitate the use of more simplified program code.

[0102] The generated dynamic code may be executed on an accelerator processing unit. During execution, all memory translation mechanisms in the system may be deactivated to provide a flat memory space. All memory accesses, directions, and addresses may be recorded using an appropriate hardware mechanism, such as an access recorder unit, and stored for later use.

[0103] In some embodiments of the present disclosure, additionally or alternatively, the address translation list may be generated by pre-calculating an address access pattern based on the first set of input arguments.

[0104] In some embodiments of the present disclosure, memory address substitutions may be used based on deterministic predictions. In the case of production code, when static program code is enabled, the memory access pattern for its set of input arguments is predictable, and a list of memory accesses may be preloaded into the access recorder unit. In some embodiments, the address pattern may be precomputed based on the input arguments and an address translation list loaded into the access recorder unit for populating memory addresses.

[0105] In some embodiments of the present disclosure, a memory access may additionally or alternatively include an address and data to fully describe the memory access.

[0106] In some embodiments of the present disclosure, additionally or alternatively, an address translation list may be stored in an access recorder unit from which it may be used for address translation, for example, in additional portions of the processing or by further variants of the program instruction stream.

[0107] In some embodiments of the present disclosure, additionally or alternatively, permuting addresses for memory accesses may be based on an order of memory requests in a program instruction stream, hi some embodiments, permuting memory addresses may be based strictly on an order of memory requests for efficient execution of the program code.

[0108] In some embodiments of the present disclosure, additionally or alternatively, prior to executing the program instruction stream, an address translation list may be preloaded into the access recorder unit, from which the address translation list may be used for further address translations in further steps of processing or by further variants of the program instruction stream.

[0109] In some embodiments of the present disclosure, the access recorder unit may additionally or alternatively be configured to record memory accesses as well as inject the memory accesses into the memory, and thus the access recorder unit may store memory accesses of a previous operation (e.g., of a dynamic variant of the program instruction stream) and provide the stored memory accesses in a subsequent operation (e.g., of a static variant of the program instruction stream).

[0110] In some embodiments of the present disclosure, the access recorder unit may additionally or alternatively be configured with a selection element for recording memory accesses or for injecting memory accesses into the memory. Such a configuration may facilitate handling of the access recorder unit for use at different stages of a memory access pattern validation process.

[0111] In some embodiments of the present disclosure, additionally or alternatively, execution of a static variant of the program instruction stream may be repeated with different sets of input arguments to validate memory access patterns, and repeated execution may ensure the validity of the static program code and the predefined access patterns across many input arguments.

[0112] In some embodiments of the present disclosure, an automated regression system may additionally or alternatively be used to iterate the validation of memory access patterns with different sets of input arguments. In this manner, various combinations of input arguments may be used to ensure the validity of the static program code and the predefined access patterns across the input arguments.

[0113] According to some embodiments of the present disclosure, a computer-implemented method is proposed for validating a memory access pattern of a static variant of a program instruction stream on a computer system, the computer system being at least comprised of a randomizer unit, a program code generator, an accelerator processing unit, an access recorder unit, and a memory. The method may include storing a primary memory access pattern in a first table in a flat memory space, and generating, with the code generator, a static variant of the program instruction stream that is independent of input arguments. The method may include passing a first set of input arguments to the code generator, and executing, on the accelerator processing unit, the static variant of the program instruction stream, where the virtual addresses may be replaced by address translations provided in the address translation list. The method may include recording and storing, in a second table in the flat memory space, a secondary memory access pattern of the execution of the static variant of the program instruction stream, and comparing the secondary memory access pattern stored in the second table with the primary memory access pattern stored in the first table. The method may include enabling a primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

[0114] In some embodiments, memory address substitution may be performed based on a pre-recorded address translation list.

[0115] Randomized input arguments to the deep learning algorithm implemented by the program code may be selected. A static variant of the program instruction stream, which may correspond to the generation-level program code used with the deep learning algorithm, may be executed with these arguments. The accelerator unit on which the static program code is executed does not support any means of address translation. Therefore, a pre-recorded address translation list may be used. For each memory access, the virtual address may be ignored and replaced by an address from the address translation list.

[0116] If the access pattern imposed by the static program code matches the access pattern of an already validated pre-recorded address list, then the static program code and access pattern can be considered correct for a given set of input arguments. In this way, the memory access pattern is validated.

[0117] The use of the proposed disclosure offers several advantages and allows for efficient testing of static program code templates within the field of artificial intelligence acceleration.

[0118] In some embodiments of the present disclosure, the computer system may be configured to generate an address translation list by passing the first set of input arguments to a program code generator to generate a dynamic variant of the program instruction stream that is tailored to the first set of input arguments and executing the dynamic variant of the program instruction stream on an accelerator processing unit, wherein during execution, all memory translation mechanisms are deactivated to provide a flat memory space. In some embodiments, the computer system may include recording and storing memory accesses of the execution of the dynamic variant of the program instruction stream in a first table in the flat memory space.

[0119] In some embodiments of the present disclosure, the selected randomized input arguments may be passed to a program code generator to generate a dynamic variant of the program instruction stream that is custom tailored to the input arguments. The custom tailored version should not be used as final production code because it is not static and therefore may represent a security concern. It may facilitate further processing and the use of simpler program code.

[0120] In some embodiments of the present disclosure, the generated dynamic code may be executed on an accelerator processing unit. During execution, all memory translation mechanisms in the system may be deactivated to provide a flat memory space. Memory accesses, directions, and addresses may be recorded using an appropriate hardware mechanism, such as an access recorder unit, and stored for later use.

[0121] In some embodiments of the present disclosure, the computer system may be configured to generate the address translation list by pre-calculating an address access pattern based on a first set of input arguments.

[0122] In some embodiments of the present disclosure, memory address substitutions may be used based on deterministic predictions. In the case of production code, when the static program code is enabled, the memory access pattern for a set of input arguments is predictable, and a list of memory accesses may be preloaded into the access recorder unit. The address pattern may be precomputed based on the input arguments and the address translation list loaded into the access recorder unit for the input of memory addresses.

[0123] In some embodiments of the present disclosure, a memory access may include an address and data, hi some embodiments, a memory access may be fully described in this manner.

[0124] In some embodiments of the present disclosure, the computer system may be configured to store the address translation list in an access recorder unit, from which the address translation list may be used for further address translations in further steps of processing or by further variants of the program instruction stream.

[0125] In some embodiments of the present disclosure, the method may include permuting addresses for memory accesses based on an order of memory requests in a program instruction stream, in some embodiments, the permutation of memory addresses may be based strictly on an order of memory requests for efficient execution of the program code.

[0126] In some embodiments of the present disclosure, the method may include pre-loading the address translation list into an access recorder unit prior to execution of the program instruction stream, from which the address translation list may be used for further address translations in further steps of processing or by further variants of the program instruction stream.

[0127] In some embodiments of the present disclosure, the access recorder unit may be configured to record memory accesses as well as inject memory accesses into the memory. The access recorder unit may store memory accesses of a previous operation (e.g., of a dynamic variant of the program instruction stream) and may provide the stored memory accesses in a subsequent operation (e.g., of a static variant of the program instruction stream).

[0128] In some embodiments of the present disclosure, the access recorder unit may additionally or alternatively be configured with a selection element for recording memory accesses or for injecting memory accesses into the memory. Such a configuration may facilitate handling of the access recorder unit for use at different stages of a memory access pattern validation process.

[0129] In some embodiments of the present disclosure, the computer system may additionally or alternatively be configured to repeat execution of a static variant of the program instruction stream with different sets of input arguments to validate memory access patterns, whereby the repeated execution can ensure the validity of the static program code and the predefined access patterns across many input arguments.

[0130] In some embodiments of the present disclosure, the computer system may additionally or alternatively be configured to use an automated regression system to repeatedly validate memory access patterns with different sets of input arguments. Multiple combinations of input arguments may be used to ensure the validity of static program code and a given access pattern across the input arguments.

[0131] According to some embodiments of the present disclosure, a computer program product may enable a memory access pattern of a static variant of a program instruction stream on a computer system. The computer system may be comprised of a randomizer unit, a program code generator, an accelerator processing unit, an access recorder unit, and a memory. In some embodiments of the present disclosure, the computer program product includes a computer readable medium having program instructions embodied therein. The program instructions may be executable by the computer system to cause the computer system to execute a method. The method may include storing the primary memory access pattern in a first table in a flat memory space and generating, with a code generator, a static variant of the program instruction stream that is independent of the input arguments. The method may include passing a first set of input arguments to the code generator and executing, on the accelerator processing unit, the static variant of the program instruction stream, where the virtual address may be replaced by an address translation provided in the address translation list. The method may include recording and storing a secondary memory access pattern of the execution of the static variant of the program instruction stream in a second table in the flat memory space and comparing the secondary memory access pattern stored in the second table with the primary memory access pattern stored in the first table. The method may include enabling the primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

[0132] In some embodiments of the present disclosure, a mismatched memory access pattern may be an indication that the memory access pattern is incorrect and / or that a static variant of the code cannot produce the same results as a dynamic variant (e.g., one or more of the variants of the code may be defective).

[0133] In some embodiments of the present disclosure, a data processing system for execution of a data processing program is proposed, comprising computer readable program instructions for performing a method. The method may include storing a primary memory access pattern in a first table in a flat memory space, and generating, with a code generator, a static variant of the program instruction stream that is independent of input arguments. The method may include passing a first set of input arguments to the code generator, and executing the static variant of the program instruction stream on an accelerator processing unit, where the virtual addresses may be replaced by address translations provided in the address translation list. The method may include recording and storing, in a second table in the flat memory space, a secondary memory access pattern of the execution of the static variant of the program instruction stream, and comparing the secondary memory access pattern stored in the second table with the primary memory access pattern stored in the first table. The method may include enabling a primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

[0134] In some embodiments of the present disclosure, the address translation list may be generated by passing the first set of input arguments to a program code generator and executing the dynamic variant of the program instruction stream on the accelerator processing unit to generate a dynamic variant of the program instruction stream that is tailored to the first set of input arguments, and during execution, all memory translation mechanisms may be deactivated to provide a flat memory space. This embodiment may further include recording and storing memory accesses of the execution of the dynamic variant of the program instruction stream in a first table in the flat memory space.

[0135] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be accomplished as one step, may be executed simultaneously, substantially simultaneously, partially or fully overlapping in time, or the blocks may be executed in reverse order depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, are implemented by a dedicated hardware-based system that performs the specified functions or acts, or executes a combination of dedicated hardware and computer instructions.

[0136] Although the present disclosure has been described with respect to specific embodiments, it is expected that modifications and alterations thereto will become apparent to those skilled in the art. The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification have been selected to best explain the principles, practical applications, or technical improvements over the technology found in the marketplace of the embodiments, or to allow others of ordinary skill in the art to understand the embodiments disclosed herein. Therefore, it is intended that the following claims be interpreted as covering modifications and alterations that are within the spirit and scope of the present disclosure.

Claims

1. A computer system for validating memory access patterns, the computer system comprising a randomizer unit, a program code generator, an accelerator processing unit, an access recorder unit, and a memory, the computer system configured to perform operations, the operations comprising: Randomizing a first set of input arguments; generating an address translation list of virtual addresses based on a primary memory access pattern for a flat memory space of the memory; storing said primary memory access pattern in a first table in said flat memory space; generating, with a code generator, a static variant of the program instruction stream that is independent of the input arguments; passing the first set of input arguments to the code generator; executing the static variant of the program instruction stream on the accelerator processing unit, wherein the virtual addresses are replaced by address translations provided in the address translation list; recording and storing in a second table in the flat memory space a secondary memory access pattern of execution of the static variant of the program instruction stream; comparing the secondary memory access patterns stored in the second table with the primary memory access patterns stored in the first table; enabling the primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

1. A computer system comprising:

2. generating the address translation list, passing said first set of input arguments to said program code generator to generate a dynamic variant of said program instruction stream that is tailored to said first set of input arguments; executing the dynamic variant of the program instruction stream on the accelerator processing unit, wherein a memory translation mechanism is deactivated during execution to provide the flat memory space; recording and storing memory accesses of said execution of said dynamic variant of said program instruction stream in said first table in said flat memory space; 2. The computer system of claim 1, comprising:

3. 3. The computer system of claim 1, wherein the operations further comprise generating the address translation list by pre-calculating an address access pattern based on the first set of input arguments.

4. 4. The computer system of claim 1, wherein the memory access includes an address and data.

5. 5. The computer system of claim 1, wherein said operations further comprise storing said address translation list in said access recorder unit.

6. 6. The computer system of claim 1, wherein the operations further comprise: permuting the addresses for the memory accesses based on an order of memory requests in the program instruction stream.

7. 7. The computer system of claim 1, wherein said operations further comprise preloading said address translation list into said access recorder unit prior to executing said program instruction stream.

8. 8. A computer system as claimed in claim 1, wherein the access recorder unit is arranged to record memory accesses and to inject memory accesses into the memory.

9. 9. The computer system of claim 8, wherein the access recorder unit comprises a selection element for recording memory accesses or for injecting memory accesses into the memory.

10. 10. The computer system of claim 1, wherein the operations further comprise repeating execution of the static variant of the program instruction stream with several different sets of input arguments to validate the memory access pattern.

11. 11. The computer system of claim 10, wherein the operations further comprise using an automated regression system to repeat the validation of the memory access pattern with several different sets of input arguments.

12. 1. A computer-implemented method for validating memory access patterns of static variants of a program instruction stream on a computer system, the computer system comprising at least a randomizer unit, a program code generator, an accelerator processing unit, an access recorder unit, and a memory, the method comprising at least: Randomizing a first set of input arguments; generating an address translation list of virtual addresses based on a primary memory access pattern for a flat memory space of the memory; storing said primary memory access pattern in a first table in said flat memory space; generating, with a code generator, a static variant of the program instruction stream that is independent of the input arguments; passing the first set of input arguments to the code generator; executing the static variant of the program instruction stream on the accelerator processing unit, wherein the virtual addresses are replaced by address translations provided in the address translation list; recording and storing in a second table in the flat memory space a secondary memory access pattern of execution of the static variant of the program instruction stream; comparing the secondary memory access patterns stored in the second table with the primary memory access patterns stored in the first table; enabling the primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

4. A computer-implemented method comprising:

13. generating the address translation list, passing said first set of input arguments to said program code generator to generate a dynamic variant of said program instruction stream that is tailored to said first set of input arguments; executing the dynamic variant of the program instruction stream on the accelerator processing unit, wherein during execution, all memory translation mechanisms are deactivated to provide a flat memory space; and recording and storing in the first table in the flat memory space each memory access of the execution of the dynamic variant of the program instruction stream; 13. The computer-implemented method of claim 12, comprising:

14. 14. The computer-implemented method of claim 12 or 13, wherein the operations further comprise generating the address translation list by pre-calculating an address access pattern based on the first set of input arguments.

15. 15. The computer-implemented method of claim 12, wherein the memory access includes an address and data.

16. 16. The computer-implemented method of claim 12, wherein the operations further comprise storing the address translation list in the access recorder unit.

17. 17. The computer-implemented method of claim 12, wherein the operations further comprise permuting the addresses for the memory accesses based on an order of memory requests in the program instruction stream.

18. 18. The computer-implemented method of claim 12, wherein said operations further comprise preloading said address translation list into said access recorder unit prior to executing said program instruction stream.

19. 19. A computer-implemented method according to any one of claims 12 to 18, wherein the access recorder unit is configured to record memory accesses and to inject memory accesses into the memory.

20. 20. The computer-implemented method of claim 19, wherein the access recorder unit comprises a selection element for recording memory accesses or for injecting memory accesses into the memory.

21. 21. The computer-implemented method of claim 12, further comprising repeating execution of a static variant of the program instruction stream with several different sets of input arguments to validate the memory access pattern.

22. 22. The computer-implemented method of claim 21, further comprising using an automated regression system to iterate the validation of the memory access patterns with several different sets of input arguments.

23. 1. A computer program product for validating memory access patterns using a system, the system comprising a randomizer unit, a program code generator, an accelerator processing unit, an access recorder unit, and a memory, the computer program product comprising a computer readable storage medium having program instructions embodied by the computer readable storage medium, the program instructions being executable by the computer system to cause the computer system to perform operations, the operations being: Randomizing a first set of input arguments; generating an address translation list of virtual addresses based on a primary memory access pattern for a flat memory space of the memory; storing said primary memory access pattern in a first table in said flat memory space; generating, with a code generator, a static variant of the program instruction stream that is independent of the input arguments; passing the first set of input arguments to the code generator; executing the static variant of the program instruction stream on the accelerator processing unit, wherein the virtual addresses are replaced by address translations provided in the address translation list; recording and storing in a second table in the flat memory space a secondary memory access pattern of execution of the static variant of the program instruction stream; comparing the secondary memory access patterns stored in the second table with the primary memory access patterns stored in the first table; enabling the primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

2. A computer program product comprising:

24. A data processing system for executing a data processing program with computer readable program instructions for performing functions, said functions comprising: Randomizing a first set of input arguments; generating an address translation list of virtual addresses based on a primary memory access pattern for a flat memory space of the memory; storing said primary memory access pattern in a first table in said flat memory space; generating, with a code generator, a static variant of the program instruction stream that is independent of the input arguments; passing the first set of input arguments to the code generator; executing the static variant of the program instruction stream on the accelerator processing unit, wherein the virtual addresses are replaced by address translations provided in the address translation list; recording and storing in a second table in the flat memory space a secondary memory access pattern of execution of the static variant of the program instruction stream; comparing the secondary memory access patterns stored in the second table with the primary memory access patterns stored in the first table; enabling the primary memory access pattern for the set of input arguments if the secondary memory access pattern in the second table matches the primary memory access pattern in the first table, or discarding the primary memory access pattern if the secondary memory access pattern in the second table does not match the primary memory access pattern in the first table.

23. A data processing system comprising:

25. generating the address translation list, passing said first set of input arguments to said program code generator to generate a dynamic variant of said program instruction stream that is tailored to said first set of input arguments; executing the dynamic variant of the program instruction stream on the accelerator processing unit, wherein during execution, all memory translation mechanisms are deactivated to provide a flat memory space; and 25. The data processing system of claim 24, further comprising: recording and storing in said first table in said flat memory space each memory access of execution of said dynamic variant of said program instruction stream.

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