Vertically pumped gate charge transfer for high conversion gain CMOS image sensor pixels

Abstract

The image sensor may include a plurality of pixels. At least some of the pixels may each include a photodiode having a charge storage region ("PD"), a floating diffusion region ("FD"), and a vertical gate transfer ("GT"). The GT may include one or more charge transfer regions formed vertically between the PD and the FD. The GT may also include a gate control region ("gate") formed in a vertical trench and may be located laterally adjacent to one or more charge transfer regions of the GT. By applying a control signal to the gate, the GT may selectively transfer at least a portion of the charge stored in the PD vertically to the FD through one or more charge transfer regions of the GT between the PD and the FD.

Description

[Technical field]

[0001] The present disclosure relates generally to image sensors, and more particularly to pixels of image sensors having vertical pump gate transfer. [Background technology]

[0002] Image capture devices such as cameras are widely used in various electronic devices such as mobile devices (e.g., smartphones, tablets, laptops, etc.), robotic equipment, or security surveillance devices, among others. The image capture device may include an image sensor having a number of light-gathering pixels. Each pixel may include a photodiode. The image capture device may capture light from the environment and pass the light to the image sensor. When exposed to light, the photodiode of the pixel may accumulate an electric charge. Upon readout, the charge of the photodiode may be read out from the photodiode using one or more transistors to generate an analog image signal. The analog image signal may be converted to a digital signal and further processed to generate an image. [Brief description of the drawings]

[0003] [Figure 1] 1 is a cross-sectional view of an exemplary pixel according to some embodiments.

[0004] [Diagram 2] 1 is a top view of an exemplary pixel according to some embodiments.

[0005] [Figure 3A] 4 illustrates an exemplary potential profile along a charge transfer channel according to some embodiments. [Figure 3B] 4 illustrates an exemplary potential profile along a charge transfer channel according to some embodiments. [Figure 3C]4 illustrates an exemplary potential profile along a charge transfer channel according to some embodiments.

[0006] [Figure 4] 4 is a cross-sectional view of another exemplary pixel according to some embodiments.

[0007] [Diagram 5] 1 is a block diagram of an exemplary image capture device, according to some embodiments.

[0008] [Figure 6] 5 is a flowchart illustrating an exemplary method for using gate transfer with vertical gates to control charge transfer of a pixel according to some embodiments.

[0009] [Figure 7] 7 shows a schematic diagram of an example device 700 that may include an image capture device (eg, a camera) having an image sensor that includes at least some pixels that use the disclosed vertical gate transfer, according to some embodiments.

[0010] [Figure 8] A schematic block diagram of an exemplary computing device, referred to as computer system 800, that may include or host an embodiment of an image capture device (e.g., a camera) having an image sensor that includes at least some pixels having the disclosed vertical gate transfer, in accordance with some embodiments.

[0011] This specification includes references to "one embodiment" or "an embodiment." The phrases "in one embodiment" or "in an embodiment" do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0012] "Comprising." This term is open-ended. As used in the following claims, this term does not exclude additional structures or steps. Consider a claim that reads "Apparatus comprising one or more processor units...." Such a claim does not exclude the apparatus from including additional components (e.g., a network interface unit, graphics circuitry, etc.).

[0013] "Configured to." Various units, circuits, or other components may be described or claimed as being "configured to" perform a task or tasks. In this context, "configured" is used to imply structure by indicating that the unit / circuit / component includes structure (e.g., circuitry) that performs those task or tasks during operation. As such, a unit / circuit / component can be said to be configured to perform a task even when the specified unit / circuit / component is not currently operational (e.g., not turned on). A unit / circuit / component used with the phrase "configured to" includes hardware, e.g., circuits, memory that stores executable program instructions to perform an operation, etc. A statement that a unit / circuit / component is "configured to" perform one or more tasks expressly intends that 35 U.S.C. 112(f) will not be invoked for that unit / circuit / component. Additionally, "configured to" can include general purpose structure (e.g., general purpose circuitry) that can be manipulated by software and / or firmware (e.g., an FPGA or a general purpose processor running software) to operate in a manner capable of performing the task(s) in question. "Configured to" can also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate a device (e.g., an integrated circuit) adapted to perform or execute one or more tasks.

[0014] "first," "second," etc. As used herein, these terms are used as markers for the nouns that follow and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, a buffer circuit may be described herein as performing write operations on "first" and "second" values. The terms "first" and "second" do not necessarily imply that the first value must be written before the second value.

[0015] "Based on." As used herein, this term is used to describe one or more factors that influence the determination. This term does not preclude additional factors that may influence the determination. That is, the determination may be based solely on those factors, or at least in part on those factors. Consider the phrase "determining A based on B." In this case, B is a factor that influences the determination of A, but such a phrase does not preclude the determination of A being based on C as well. In other examples, A may be determined solely on B.

[0016] In this specification, terms such as first, second, etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first contact may be called a second contact, and similarly, a second contact may be called a first contact, without departing from the intended scope. Although a first contact and a second contact are both contacts, they are not the same contact.

[0017] The terms used in the description herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used in the description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Also, as used herein, the term "and / or" is to be understood to refer to and include any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0018] As used herein, the term "if" can be interpreted to mean "when," "upon," "in response to determining," or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (a stated condition or event) is detected" can be interpreted to mean "upon determining," "in response to determining," "upon detecting (the stated condition or event)," or "in response to detecting (the stated condition or event)," depending on the context. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Various embodiments described herein relate to an image sensor having a plurality of pixels, at least some of which may each include a vertical pump gate transfer. In some embodiments, at least some of the pixels may each include at least one photodiode with a charge storage region (hereinafter "PD"), at least one floating diffusion region (hereinafter "FD"), and at least one gate transfer (hereinafter "GT"). In some embodiments, the image sensor may be part of an image capture device, such as a camera. The image capture device may include one or more lenses. The lenses may pass light captured by the image capture device through the image sensor. When exposed to light, the PD may accumulate charge, e.g., electrons or holes. At least some of the charge may be transferred from the PD to the FD, e.g., during readout, to generate an image signal, e.g., an analog voltage. In some embodiments, the image signal from the pixel may be further processed, e.g., analog-to-digital converted by analog-to-digital converter(s) and digitally processed by an image signal processor (ISP), to generate one or more images.

[0020] In some embodiments, the GT may include a vertical pump gate formed by a first charge transfer region (hereinafter, "P1"), a second charge transfer region (hereinafter, "P2"), and a gate control region (hereinafter, "gate"). In some embodiments, P1 may be formed above and at least partially overlapping the PD, while P2 may be (a) formed above and at least partially overlapping P1 and (2) formed below and at least partially overlapping the FD. As a result, P1 and P2 may collectively form a region vertically between the PD and the FD. In some embodiments, the gate of the GT may be a vertical gate disposed laterally adjacent to P1 and P2, and thus may create a channel through P1 and P2 under a field effect when a control signal, e.g., a voltage, is applied. In some embodiments, by controlling the voltage applied to the gate, the GT may selectively transfer some or all of the charge vertically from the PD to the FD via the channel through P1 and P2. In some embodiments, the transfer of charge may be performed in two phases. For example, in a first phase, the GT may be turned on to pump charge from PD to P1 and then to P2, and in a second phase, the GT may be turned off to pump charge from P2 to FD.

[0021] FIG. 1 is a cross-sectional view of an exemplary pixel according to some embodiments. The right-hand view is an expanded view of a portion (marked with a dashed line) of the left-hand pixel. As shown in FIG. 1, the pixel 100 may include at least one photodiode with a charge storage region ("PD") 102, a floating diffusion ("FD"), and a gate transfer ("GT") 106. In some embodiments, the GT 106 may include a first charge transfer region ("P1") 108, a second charge transfer region ("P2") 110, and a gate control region ("gate") 112. The gate 112 and the FD 122 may further be connected with respective metal contacts 120 and 122. As mentioned above, the PD 102 may accumulate charge (e.g., electrons) when exposed to light. The charge may be transferred from the PD 102 through the GT 106 to the FD 104. The transfer of charge may result in an image signal, e.g., an analog voltage, in the FD 104, which may be read out through the metal contact 122. In FIG. 1, in some embodiments, the pixel 100 may also include one or more pixel transistors 130 for implementing the readout of the image signal from the pixel 100. In some embodiments, the pixel 100 may be implemented based on a substrate 124. Also, as shown in FIG. 1, in this example, the pixel 100 may be configured to receive backside illumination. However, alternatively, in some embodiments, frontside illumination may be implemented.

[0022] As shown in FIG. 1, in some embodiments, P1 108 may be formed above and at least partially overlap PD 102. P2 110 may be formed above and at least partially overlap P1 108. In addition, P2 110 may be below and at least partially overlap FD 104. Thus, P1 and P2 may collectively form a region between PD 102 and FD 104 in a vertical direction. In this disclosure, "vertical" refers to a vertical direction in the cross-sectional view of FIG. 1, e.g., from bottom to top in the cross-sectional view, or from the back surface to the front surface of the substrate 124. Furthermore, as shown in FIG. 1, at least a portion of P2 110 may be disposed away from and separated from FD 104 by a physical gap 114. In some embodiments, the physical gap 114 may provide a potential barrier (e.g., an electrostatic potential barrier) between P2 110 and FD 104, thereby preventing the transfer of charge from PD 102 to FD 104. As shown in FIG. 1, in some embodiments, the gate 112 can be implemented as a vertical gate and disposed laterally adjacent to P1 108 and P2 110. Thus, the gate 112 can at least partially overlap P1 108 and P2 110 such that a channel 116 can be created through P1 108 and P2 110 for charge transfer under field effect. For example, when a positive voltage is applied to the gate 112, the positive voltage can repel holes in the layers of P1 108 and P2 110 that interface with the gate 112 away from the gate 112, thus creating the channel 116 as shown in FIG. 1. In other words, an n-type field effect transistor can be formed, and electrons can flow from the source (e.g., PD 102) to the drain (e.g., FD 104) via an n-type channel (e.g., the channel 116 formed through P1 108 and P2 110).In some embodiments, a physical gap 114 may be formed near a portion of P2 110, for example, around the intersection between the channel 116 (through P1 108 and PD 110) and the FD 104, such that the potential barrier created by the physical gap 114 may prevent the transfer of charge from the PD 102 to the FD 104 through the channel 116. In some embodiments, the gate 112 may not necessarily overlap the FD 104 in the vertical direction, as shown in FIG. 1. The lack of overlap may create a distance between the gate 112 and the FD 104, thus reducing the parasitic capacitance on the FD 104. In some embodiments, the reduction in the parasitic capacitance of the FD 104 may increase the conversion gain of the pixel 100, and thus the value of the image signal may be increased even when the pixel 100 is exposed to low intensity or dim light. In some embodiments, the gate 112 may be formed vertically in a shallow trench. For example, as shown in FIG. 1, the trench may extend vertically laterally adjacent to and at least partially overlap P1 108 and P2 110. In some embodiments, the trench may be filled with polycrystalline silicon (also referred to as polysilicon), for example, at or near the bottom of the trench, to form the gate 112. The gate 112 may be connected with a metal contact 120, and the remainder of the trench may be filled with, for example, silicon dioxide. Additionally, as shown in FIG. 1, in some embodiments, the pixel 100 may include a shallow trench isolation (STI), which may have a depth shorter than the trench of the vertical gate 112. Alternatively, in some embodiments, the pixel 100 may instead use a deep trench isolation, which has a trench deeper than the trench of the vertical gate 112. Also, in some embodiments, the PD 102 may be extended to the area directly under the pixel transistor 130 to increase the fill factor and quantum efficiency.

[0023] In some embodiments, the GT 106 may be controlled to selectively transfer at least a portion of the charge from the PD 102 to the FD 104 vertically through P1 108 and P2 110. For example, in some embodiments, a control signal, e.g., a voltage, may be applied to the gate 112 of the GT 106, which may create a vertical channel 116 through P1 108 and P2 110 under a field effect. As a result, the charge may be transferred from the PD 102 to the FD 104 through the channel 116, as shown by the arrow in FIG. 1. Conversely, the voltage may be removed from the gate 112, or a different voltage may be applied to remove the channel 116. As a result, the transfer of charge may be stopped. Note that in this example, the pixel 100 may have gates 112 on the left and right sides of the cross-sectional view. Thus, the gates may create two channels 116 on either side of P1 108 and P2 110. For purposes of illustration, in this example, PD 102 may be an n-type region formed with one or more n-type dopants, P1 108 and P2 110 may be p-type regions formed with one or more p-type dopants, and FD 104 may be an n-type region formed with one or more n-type dopants. In some embodiments, P1 108 and P2 110 may use the same dopant(s) and P1 108 may have a higher doping concentration than P2 110. In some embodiments, P1 108 and P2 110 may be formed as two separate regions, both using implants with uniformly distributed energy. Alternatively, in some embodiments, P1 108 and P2 110 may be formed as a single doped region with different doping concentrations. For example, implants (e.g., ion beams) can be added with intentionally skewed distribution energies to create a doping gradient so that the lower regions (e.g., P1 108) can have a higher doping concentration than the upper regions (e.g., P2 110). Note that the above is just one example provided for illustrative purposes.In some embodiments, the PD 102, FD 104, P1 108, and P2 110 of pixel 100 may be doped in other ways to form other types of regions and / or may be spatially arranged in other ways. For example, in some embodiments, the PD 102 and FD 104 may be formed in p-type regions and P1 108 and P2 110 may be formed in n-type regions, thus resulting in a p-type field effect transistor in pixel 100. Also, alternatively, in some embodiments, pixel 100 may have a different number of PD 102, FD 104, GT 106, P1 108, P2 110, and / or gate 112. For example, in some embodiments, the pixel 100 may include two PDs 102, two GTs 106 (each having one P1 108, one P2 110, and one or more gates 112), and one FD 104, where the two PDs 102 may share the same FD 104, and each GT 106 may control the transfer of charges from each PD 102 to the shared GT 106. Also, alternatively, in some embodiments, the GT 106 may not necessarily include the charge transfer regions P1 108 and P2 110. Instead, the gate 112 may be recessed to be formed above the PDs 102 and below the FDs 104, thus forming a charge transfer region directly between the PDs 102 and the FDs 104.

[0024] FIG. 2 is a top view of an exemplary pixel according to some embodiments. In FIG. 2, cut line A-A' indicates the viewing direction of the cross-sectional view of FIG. 1. As shown in FIG. 2, in some embodiments, the gate 112 of the GT 106 may be formed in a U-shape that at least partially surrounds the periphery of the FD 104. Alternatively, in some embodiments, the gate 112 may have a ring shape that completely surrounds the FD 104. Although the gate 112 laterally surrounds the FD 104, the gate 112 may not necessarily go directly under or vertically overlap the FD 104 as described above in FIG. 1.

[0025] As described above in FIG. 1, in some embodiments, the pixel 100 may include one or more pixel transistors 130 for implementing the readout of an image signal from the pixel 100. For example, as shown in FIG. 2, in some embodiments, the pixel 100 may include at least one reset transistor ("RG") 132, one or more source follower transistors ("SF") 134, and / or one or more readout select transistors ("RS") 136. Using the pixel transistors, the pixel 100 may form a circuit as shown by the schematic diagram of FIG. 2. As shown here, the PD 102 may be coupled to the FD 104 via the GT 106. Thus, by turning on the GD 104, charge may be transferred from the PD 102 to the FD 104. Given a capacitance C at the FD 104, the transfer of charge may cause a current to be integrated through the capacitance C, thus resulting in an analog voltage at the FD 104. Also, as shown in FIG. 2, FD104 may also be coupled to a reset voltage VDD via RG132, for example, using metal contact 140 shown in the top view. RG132 may be selectively turned on to reset the voltage of FD104 to VDD. Furthermore, as shown in FIG. 2, FD104 may also be coupled to one or more SF134 and one or more RS136. In some embodiments, SF134 and RS136 may be turned on to couple FD104 to a pixel output line, through which the voltage of FD104 may be accessed and read out. In some embodiments, SF134 may provide a voltage buffer for the voltage of FD104, and RS136 may be selectively turned on to couple FD104 to the pixel output line to read out the voltage of FD104. During readout, SF134 and RS136 may be turned on first to couple FD104 to the pixel output line. Next, RG 132 may be turned on, resetting the voltage of FD 104 to a reset voltage VDD. The voltage of FD 104 may be sampled using, for example, an analog-to-digital converter(s) as a first sample of the voltage of FD 104.Next, RG132 may be turned off and GT106 may be turned on. Turning off RG132 and turning on GT106 may or may not be performed simultaneously or nearly simultaneously. When GT106 is turned on, the charge of PD102 may be transferred to FD104 as described above to generate an analog voltage across the capacitance C of FD104. The voltage of FD104 may be further accessed and read out at the pixel output line via SF134 and RS136. The voltage of FD104 may be sampled again, for example, using an analog-to-digital converter(s), as a second sample of the voltage of FD104. The difference between the first sample and the second sample may be calculated to offset the reset voltage, and the difference voltage may be determined as the final image signal from pixel 100. This image signal, along with image signals from other pixels, may be provided to an image signal processor (ISP) where it is processed to generate an image. In some embodiments, pixel 100, including the various components described above, may be implemented as an integrated circuit on a substrate (eg, substrate 124).

[0026] 3A-3C show example potential profiles along a charge transfer channel, according to some embodiments. For illustration purposes, assume in this example that PD 102 may be an n-type region, P1 108 and P2 110 may be p-type regions, P1 108 may have a higher doping concentration than P2 110, and FD 104 may be an n-type region. In FIG. 3A, GT 106 is turned off, for example, when gate 112 is biased at zero or a negative voltage. Given the doping types of these regions in this example, the potential profiles of PD 102, P1 108, P2 110, and FD 104 may have a multi-step shape, as shown in the figure. For example, due to the different doping concentrations of P1 108 and P2 110, P1 108 may have a lower potential than P2 110, thus showing a two-step profile in FIG. 3A. Also, as discussed above, in some embodiments, at least a portion of P2 110 may be positioned away from and separated from FD 104 by a physical gap 114, which may create a potential barrier (e.g., an electrostatic potential barrier) between P2 110 and FD 104. However, because gate 106 is biased at zero or a negative voltage, the potential of P2 110 may be lower than the potential barrier created by physical gap 114. Given the potential profile of FIG. 3A, in this mode of operation, charge may be accumulated and retained in PD 102 when exposed to light.

[0027] In FIG. 3B, the GT 106 may be turned on, for example, when the gate 112 is biased with a positive voltage. In some embodiments, P1 108 and P2 110 may follow the voltage applied to the gate 112. As a result, a channel 116 may be formed through P1 108 and P2 110. Thus, at least a portion of the charge may be pumped from the PD 102 to P1 108. Also, as described above, P1 108 may have a lower potential than P2 110, so that the charge may further flow from P1 108 to P2 110, as indicated by the arrows in FIG. 3B. In addition, because the gate 106 is biased with a positive voltage, the potential of P2 110 may be higher than the potential barrier created by the physical gap 114. 3B mode, when charge is transferred to P2 110, the charge may be blocked by the potential barrier created by the physical gap 114 between P2 110 and FD 104, and therefore may not necessarily flow to FD 104. As a result, the charge may be temporarily held in P2 110.

[0028] In FIG. 3C, the GT 106 can be turned off, e.g., the positive voltage is removed from the gate 112 or the gate 112 is biased to zero or a negative voltage. The potential profile can be restored to the starting level of FIG. 3A. Thus, the potential of P2 110 can again be lower than the potential barrier created by the physical gap 114. As a result, the charge in the PD 112 can be pumped from the PD 112 to the FD 104 through the physical gap 114. Furthermore, as described above, the potential of P1 108 is lower than that of P2 110, so that the charge can be prevented from flowing back from P2 110 through P1 108 to PD 102. Combining FIGS. 3A-3C, it can be seen that the transfer of charge from PD 102 to FD 104 can be implemented in two phases. In the first phase, when the GT 106 is turned on, at least a portion of the charge can be transferred from PD 102 through P1 108 to P2 110. In a second phase, when GT 106 is turned off, at least a portion of the charge may be transferred from P2 110 to FD 104.

[0029] FIG. 4 is a cross-sectional view of another exemplary pixel according to some embodiments. As shown in FIG. 4, pixel 400 is similar to pixel 100 of FIG. 1, except that the gate transfer of pixel 400 may include one single vertical gate 412. As shown in FIG. 4, pixel 400 may include PD 402 and FD 404. In some embodiments, the gate transfer may also include P1 408 and P2 410 vertically disposed between FD 402 and FD 404. Also, at least a portion of PD 410 may be disposed away from and separated from FD 404 by a physical gap 414, which may provide a potential barrier (e.g., an electrostatic potential barrier) between P2 410 and FD 404, as shown in FIG. 4. In some embodiments, gate 412 may be formed vertically like P1 408 and P2 410 and disposed laterally adjacent to P1 408 and P2 410. In some embodiments, the gate transfer of pixel 400 may be operated similarly to the GT 106 of pixel 100 described above. For example, in a first operation of a two-phase operation, the gate transfer may be selectively turned on to transfer charge from PD 402 through P1 408 to P2 410. In a second phase of the two-phase operation, the gate transfer may be selectively turned off to transfer charge from P2 410 to FD 404. Furthermore, as shown in FIG. 4, in some embodiments, pixel 400 may include one or more pixel transistors 430 similar to pixel 100 to form a circuit for an image signal read out from the pixel. Compared to pixel 100 of FIG. 1, pixel 400 may be less complex since it includes only one single vertical gate. However, on the other side, there is only one gate 412 close to P1 408 and P2 410, so that a charge transfer channel may be formed only on the left side of P1 408 and P2 410. Thus, in some embodiments, the charge transfer rate of pixel 400 may be slower than that of pixel 100 .

[0030] FIG. 5 is a block diagram of an exemplary image capture device, according to some embodiments. As shown in FIG. 5, in some embodiments, the image capture device 500 may include one or more lenses 502 and an image sensor 504. In some embodiments, the image capture device 500 may capture light from the environment, which may pass through the lens 502 to reach the image sensor 504. In some embodiments, the image sensor 504 may include a plurality of pixels, at least some of which may each include a vertical gate pump transfer, similar to the pixels described above. Also, in some embodiments, the image capture device 500 may include an infrared cutoff filter (IRCF) 506 disposed between the lens 502 and the image sensor 504 to block infrared light from reaching the image sensor 504. As shown in FIG. 5, in this example, the image sensor 504 and the IRCF 506 may be mounted on a substrate 508, and the image sensor 504 may be disposed upside down to receive backside illumination. However, as described above, alternatively, in some embodiments, frontside illumination may be implemented on the image sensor 504 having the pixels described above. In some embodiments, the image sensor 504 may be a CMOS image sensor.

[0031] FIG. 6 is a flow chart illustrating an exemplary method for using gate transfer with vertical gate to control charge transfer of a pixel, according to some embodiments. As shown in FIG. 6, in some embodiments, a pixel (similar to the pixel described above) having at least one photodiode with a charge storage region ("PD") may be formed on a substrate, as shown in block 602. As described above, the PD may accumulate charge, e.g., electrons or holes, when exposed to light. In some embodiments, a floating diffusion region ("FD") may be formed as part of the pixel on the substrate, as shown in block 604. In some embodiments, a gate transfer ("GT") may be formed as part of the pixel structure, and may include (a) forming one or more charge transfer regions vertically between the PD and the FD, and (b) forming a gate control region ("gate") vertically disposed laterally adjacent to the one or more charge transfer regions, as shown in block 606. As described above, in some embodiments, the one or more charge transfer regions may include a first charge transfer region ("P1") and a second charge transfer region ("P2"). In some embodiments, P1 may be formed above and at least partially overlap the PD. In some embodiments, P2 may be (a) formed above and at least partially overlap the P1, and (b) formed below and at least partially overlap the FD. As a result, P1 and P2 may collectively form a region between the PD and the FD. Also, as described above, in some embodiments, at least a portion of P2 may be located away from and separated from the FD by a physical gap to provide a potential barrier. Further, in some embodiments, the gate of the GT may be located away from the FD and may not vertically overlap the FD. However, the gate of the GT may be U-shaped or ring-shaped to at least partially surround the FD laterally. In some embodiments, at least a portion of the charge may be transferred from the PD to the FD vertically through one or more charge transfer regions (e.g., P1 and P2) between the PD and the FD by controlling the GT, as shown in block 608.As mentioned above, in some embodiments, the charge transfer may be performed in two phases: in a first phase, the GT may be turned on, e.g., in response to a positive voltage applied to the gate, to pump at least some charge from the PD to P2 via P1; in a second phase, the GT may be turned off, e.g., in response to removal of the positive voltage from the gate or the negative voltage applied to the gate, to pump at least some charge from P2 to the FD.

[0032] 7 illustrates a schematic diagram of an example device 700 that may include an image capture device (e.g., a camera) having an image sensor that includes at least some pixels with the vertical gate transfer described above, according to some embodiments. In some embodiments, device 700 may be a mobile device and / or a multifunction device. In various embodiments, device 700 may be any of a variety of types of devices, including, but not limited to, a personal computer system, a desktop computer, a laptop, a notebook, a tablet, a slate, a pad, or a netbook computer, a mainframe computer system, a handheld computer, a workstation, a network computer, a camera, a set-top box, a mobile device, an augmented reality (AR) and / or virtual reality (VR) headset, a consumer device, a video game console, a handheld video game device, an application server, a storage device, a television, a video recording device, a peripheral device such as a switch, a modem, a router, or generally any type of computing or electronic device.

[0033] In some embodiments, device 700 may include a display system 702 (e.g., including a display and / or a touch-sensitive surface) and / or one or more cameras 704. In some non-limiting embodiments, display system 702 and / or one or more front-facing cameras 704a may be provided on the front side of device 700, for example, as shown in FIG. 7. Additionally or alternatively, one or more rear-facing cameras 704b may be provided on the rear side of device 700. In some embodiments with multiple cameras 704, some or all of the cameras may be the same or similar to one another. Additionally or alternatively, some or all of the cameras may be different from one another. In various embodiments, the location(s) and / or arrangement(s) of camera(s) 704 may differ from that shown in FIG. 7.

[0034] Among other things, device 700 may include memory 706 (e.g., comprising an operating system 708 and / or application(s) / program instructions 710), one or more processors and / or controllers 712 (e.g., comprising a CPU(s), memory controller(s), display controller(s), and / or camera controller(s), etc.), and / or one or more sensors 716 (e.g., orientation sensor(s), proximity sensor(s), and / or position sensor(s), etc.). In some embodiments, device 700 may communicate with one or more other devices and / or services, such as computing device(s) 718, cloud services 720, etc., via one or more network(s) 722. For example, device 700 may include a network interface (e.g., network interface 810) that enables device 700 to transmit data to and receive data from network(s) 722. Additionally or alternatively, device 700 may be capable of communicating with other devices via wireless communications using any of a variety of communication standards, protocols, and / or technologies.

[0035] 8 illustrates a schematic block diagram of an exemplary computing device, referred to as computer system 800, that may include or host an embodiment of an image capture device (e.g., a camera) having an image sensor that includes at least some pixels that use vertical gate transfer as described above, according to some embodiments. In addition, computer system 800 may implement methods for controlling the operation of the camera and / or for performing image processing of images captured with the camera. In some embodiments, device 700 (described herein with reference to FIG. 7) may additionally or alternatively include some or all of the functional components of computer system 800 described herein.

[0036] Computer system 800 may be configured to perform any or all of the above-described embodiments. In different embodiments, computer system 800 may be any of a variety of types of devices, including, but not limited to, a personal computer system, a desktop computer, a laptop, a notebook, a tablet, a slate, a pad, or a netbook computer, a mainframe computer system, a handheld computer, a workstation, a network computer, a camera, a set-top box, a mobile device, an augmented reality (AR) and / or virtual reality (VR) headset, a consumer device, a video game console, a handheld video game device, an application server, a storage device, a television, a video recording device, a peripheral device such as a switch, modem, router, or generally any type of computing or electronic device.

[0037] In the illustrated embodiment, computer system 800 includes one or more processors 802 coupled to a system memory 804 via an input / output (I / O) interface 806. Computer system 800 further includes one or more cameras 808 coupled to the I / O interface 806. Computer system 800 further includes a network interface 810 coupled to the I / O interface 806, and one or more input / output devices 812, such as a cursor control device 814, a keyboard 816, and a display(s) 818. While in some cases, an embodiment may be implemented using a single instance of computer system 800, it is contemplated that in other embodiments, multiple such systems, or multiple nodes comprising computer system 800, may be configured to host different portions or instances of the embodiments. For example, in one embodiment, some elements may be implemented via one or more nodes of computer system 800 that are different from the nodes implementing other elements.

[0038] In various embodiments, computer system 800 may be a uniprocessor system including one processor 802, or a multiprocessor system including multiple processors 802 (e.g., two, four, eight, or another suitable number). Processor 802 may be any suitable processor capable of executing instructions. For example, in various embodiments, processor 802 may be a general-purpose or embedded processor implementing any of a variety of instruction set architectures (ISAs), such as the x86, PowerPC, SPARC, or MIPS ISA, or any other suitable ISA. Also, in some embodiments, one or more of processors 802 may include additional types of processors, such as a graphics processing unit (GPU), an application specific integrated circuit (ASIC), or the like. In a multiprocessor system, each of processors 802 may generally, but not necessarily, implement the same ISA. In some embodiments, computer system 800 may be implemented as a system on a chip (SoC). For example, in some embodiments, the processor 802, memory 804, I / O interface 806 (e.g., fabric), etc. may be implemented in a single SoC with multiple components integrated on a single chip. For example, an SoC may include multiple CPU cores, a multi-core GPU, a multi-core neural engine, a cache, one or more memories, etc. integrated on a single chip. In some embodiments, an SoC embodiment may implement a reduced instruction set computing (RISC) architecture, or any other suitable architecture.

[0039] The system memory 804 may be configured to store program instructions 820 accessible by the processor 802. In various embodiments, the system memory 804 may be implemented using any suitable memory technology, such as static random access memory (SRAM), synchronous dynamic RAM (SDRAM), non-volatile / flash type memory, or any other type of memory. Additionally, the existing camera control data 822 in the memory 804 may include any of the information or data structures described above. In some embodiments, the program instructions 820 and / or data 822 may be received, transmitted, or stored on different types of computer-accessible media, or on similar media separate from the system memory 804 or computer system 800. In various embodiments, some or all of the functionality described herein may be implemented via such a computer system 800.

[0040] In one embodiment, the I / O interface 806 may be configured to coordinate I / O traffic between the processor 802, the system memory 804, and any peripheral devices within the device, including other peripheral interfaces such as the network interface 810 or input / output devices 812. In some embodiments, the I / O interface 806 may perform any necessary protocol, timing, or other data conversions to convert data signals from one component (e.g., the system memory 804) into a format suitable for use by another component (e.g., the processor 802). In some embodiments, the I / O interface 806 may include support for devices attached via various types of peripheral buses, such as, for example, variations on the Peripheral Component Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard. In some embodiments, the functionality of the I / O interface 806 may be split into two or more separate components, such as, for example, a northbridge and a southbridge. Also, in some embodiments, some or all of the functionality of the I / O interface 806, such as an interface to the system memory 804, may be incorporated directly into the processor 802.

[0041] Network interface 810 may be configured to allow data to be exchanged between computer system 800 and other devices (e.g., carrier or agent devices) attached to network 824, or between nodes of computer system 800. Network 824, in various embodiments, may include one or more networks, including, but not limited to, a local area network (LAN) (e.g., Ethernet or enterprise network), a wide area network (WAN) (e.g., the Internet), a wireless data network, some other electronic data network, or some combination thereof. In various embodiments, network interface 810 may support communication over a wired or wireless general-purpose data network, such as, for example, any suitable type of Ethernet network. It may support communication over a telecommunications / telephone network, such as an analog voice network or a digital fiber communications network, communication over a storage area network, such as a Fibre Channel SAN, or communication over any other suitable type of network and / or protocol.

[0042] The input / output devices 812, in some embodiments, may include one or more display terminals, keyboards, keypads, touch pads, scanning devices, voice or optical recognition devices, or any other devices suitable for inputting or accessing data by one or more computer systems 800. Multiple input / output devices 812 may be present within computer system 800 or distributed on various nodes of computer system 800. In some embodiments, similar input / output devices may be separate from computer system 800 and may interact with one or more nodes of computer system 800 through wired or wireless connections, such as via network interface 810.

[0043] Those skilled in the art will appreciate that computer system 800 is merely exemplary and is not intended to limit the scope of the embodiments. In particular, computer systems and devices may include any combination of hardware or software capable of performing the depicted functions, including computers, network devices, Internet appliances, PDAs, wireless telephones, pagers, and the like. Computer system 800 may also be connected to other devices not shown, or may alternatively operate as a stand-alone system. In addition, functionality provided by the illustrated components may be combined in fewer components or distributed in additional components in some embodiments. Similarly, in some embodiments, the functionality of some of the illustrated components may not be provided and / or other additional functionality may be available.

[0044] Those skilled in the art will also appreciate that while various items are shown as being stored in memory or on a storage device during use, these items or portions thereof may be transferred between memory and other storage devices for purposes of memory management and data integrity. Alternatively, in other embodiments, some or all of the software components may execute in memory on another device and communicate with the illustrated computer system via computer-to-computer communications. Some or all of the system components or data structures may also be stored (e.g., instructions or structured data) on a computer-accessible medium or portable article to be read by an appropriate drive, various examples of which are described above. In some embodiments, instructions stored on a computer-accessible medium separate from computer system 800 may be transmitted to computer system 800 via a transmission medium or signal, such as an electrical, electromagnetic, or digital signal, conveyed over a communications medium, such as a network and / or a wireless link. Various embodiments may further include receiving, sending, or storing instructions and / or data executed on a computer-accessible medium in accordance with the preceding description. Generally speaking, a computer-accessible medium may include non-transitory computer-readable storage media or memory media, such as magnetic or optical media, e.g., volatile or non-volatile media, such as disks or DVDs / CD-ROMs, RAM (e.g., SDRAM, DDR, RDRAM, SRAM, etc.), ROM, etc. In some embodiments, the computer-accessible medium may include a transmission medium or signal, such as an electrical, electromagnetic, or digital signal, conveyed over a communication medium, such as a network and / or a wireless link.

[0045] The methods described herein may be implemented in different embodiments in the form of software, hardware, or a combination thereof. In addition, the order of blocks of the methods may be changed, and various elements may be added, reordered, combined, omitted, modified, etc. Various modifications and changes may be made as would be apparent to a person skilled in the art having the benefit of this disclosure. The various embodiments described herein are illustrative and not limiting. Many variations, modifications, additions, and improvements are possible. Thus, multiple instances may be provided for components described herein as a single instance. Boundaries between various components, operations, and data stores are somewhat arbitrary, and certain operations are illustrated in the context of specific example configurations. Other allocations of functionality are contemplated and may be included within the scope of the following claims. Finally, structures and functions presented as separate components in example configurations may be implemented as combined structures or components. These and other variations, modifications, additions, and improvements may be included within the scope of the embodiments, as defined in the following claims.

Claims

1. 1. An image sensor comprising: a plurality of pixels, at least some of the pixels each comprising: a photodiode including a charge storage region configured to store charge when exposed to light; a floating diffusion region; a transfer gate, the transfer gate comprising: one or more charge transfer regions formed vertically between the charge storage region and the floating diffusion region; a gate control region formed vertically and laterally disposed adjacent the charge transfer region; the transfer gate is configured to selectively transfer at least a portion of the charge from the charge storage region to the floating diffusion region via the charge transfer region in a vertical direction between the charge storage region and the floating diffusion region.

2. The transfer gate is a first charge transfer region formed above and at least partially overlapping the charge storage region of the photodiode; 2. The image sensor of claim 1 , comprising: (a) a second charge transfer region formed above and at least partially overlapping the first charge transfer region; and (b) a second charge transfer region formed below and at least partially overlapping the floating diffusion region, wherein at least a portion of the second charge transfer region is separated from the floating diffusion region by a physical gap so as to provide a potential barrier between the second charge transfer region and the floating diffusion region.

3. The transfer gate is turned on to transfer the at least some of the charges from the charge storage region to the charge transfer region; The image sensor of claim 1 , configured to be turned off to transfer the at least some of the charges from the charge transfer region to the floating diffusion region.

4. 4. The image sensor of claim 3, wherein the transfer gate is configured to be turned on in response to a positive voltage applied to the gate control region and turned off in response to the positive voltage being removed from the gate control region or a negative voltage being applied to the gate control region.

5. 2. The image sensor of claim 1, wherein the first charge transfer region has the same doping type as the second charge transfer region, and the first charge transfer region has a higher dopant concentration than the second charge transfer region.

6. The image sensor of claim 1 , wherein the gate control region does not overlap the floating diffusion region.

7. The image sensor of claim 1 , wherein the gate control region is formed in a shape that includes a partial circle or a complete circle that surrounds a periphery of the floating diffusion region.

8. 2. The image sensor of claim 1 , wherein the charge storage region is an n-type region, the first charge transfer region is a first p-type region, the second charge transfer region is a second p-type region, and the floating diffusion region is an n-type region.

9. 2. The image sensor of claim 1, wherein the pixel further comprises at least one of a reset switch for resetting a voltage on the floating diffusion region to a reset voltage, a source follower switch for buffering the voltage on the floating diffusion region, or a pixel select switch for selectively coupling the floating diffusion region to a pixel output line to read out the voltage on the floating diffusion region.

10. 1. A system comprising: One or more lenses; an image sensor including a plurality of pixels configured to receive light through the lens; At least a portion of the plurality of pixels each include a photodiode having a charge storage region configured to store charge when exposed to the light passing through the lens; a floating diffusion region; a transfer gate, the transfer gate comprising: one or more charge transfer regions formed vertically between the charge storage region and the floating diffusion region; a gate control region formed vertically and laterally disposed adjacent the charge transfer region; the transfer gate is configured to selectively transfer at least a portion of the charge from the charge storage region to the floating diffusion region via the charge transfer region in a vertical direction between the charge storage region and the floating diffusion region.

11. The transfer gate is a first charge transfer region formed above and at least partially overlapping the charge storage region of the photodiode; 11. The system of claim 10, comprising: (a) a second charge transfer region formed above and at least partially overlapping the first charge transfer region; and (b) a second charge transfer region formed below and at least partially overlapping the floating diffusion region, wherein at least a portion of the second charge transfer region is separated from the floating diffusion region by a physical gap so as to provide a potential barrier between the second charge transfer region and the floating diffusion region.

12. The transfer gate is turned on to transfer the at least some of the charges from the charge storage region to the charge transfer region; The system of claim 10 , configured to be turned off to transfer the at least some of the charge from the charge transfer region to the floating diffusion region.

13. 11. The system of claim 10, wherein the first charge transfer region has the same doping type as the second charge transfer region, and the first charge transfer region has a higher dopant concentration than the second charge transfer region.

14. The system of claim 10 , wherein the gate control region does not overlap the floating diffusion region.

15. The system of claim 10 , wherein the gate control region is formed in a shape that includes a partial circle or a complete circle that surrounds a periphery of the floating diffusion region.

16. 10. The system of claim 9, wherein the charge storage region is an n-type region, the first charge transfer region is a first p-type region, the second charge transfer region is a second p-type region, and the floating diffusion region is an n-type region.

17. 10. The system of claim 9, wherein each of the at least some pixels further comprises at least one of a reset switch for resetting a voltage on the floating diffusion region to a reset voltage, a source follower switch for buffering the voltage on the floating diffusion region, or a pixel select switch for selectively coupling the floating diffusion region to a pixel output line to read out the voltage on the floating diffusion region.

18. A device, comprising:

1. An image capture device, comprising: One or more lenses; an image sensor comprising a plurality of pixels configured to receive light through the lens, at least some of the pixels each comprising: a photodiode having a charge storage region configured to store charge when exposed to the light passing through the lens; a floating diffusion region; a transfer gate, the transfer gate comprising: one or more charge transfer regions formed vertically between the charge storage region and the floating diffusion region; a gate control region formed vertically and laterally disposed adjacent the charge transfer region; an image sensor, the transfer gate configured to selectively transfer at least a portion of the charges from the charge storage region to the floating diffusion region through the charge transfer region in a vertical direction between the charge storage region and the floating diffusion region; one or more circuits configured to generate a voltage signal based on the charge transferred to the floating diffusion region of the at least some of the pixels; and an image signal processor configured to process the voltage signals to generate one or more images.

19. The transfer gate is a first charge transfer region formed above and at least partially overlapping the charge storage region of the photodiode; 20. The device of claim 18, comprising: (a) a second charge transfer region formed above and at least partially overlapping the first charge transfer region; and (b) a second charge transfer region formed below and at least partially overlapping the floating diffusion region, wherein at least a portion of the second charge transfer region is separated from the floating diffusion region by a physical gap so as to provide a potential barrier between the second charge transfer region and the floating diffusion region.

20. The transfer gate is turned on to transfer the at least some of the charges from the charge storage region to the charge transfer region; 20. The device of claim 18, configured to be turned off to transfer the at least some of the charge from the charge transfer region to the floating diffusion region.

Images