Command analysis method, device and electronic device

Abstract

This application discloses an instruction parsing method, an apparatus and an electronic device, which includes the steps of: receiving a target instruction and a parameter processor set, where the target instruction includes a target instruction parameter vector whose elements are target instruction parameters, and the parameter processor set includes at least one parameter processor, where the parameter processor is composed of an instruction parameter vector to be matched with a predetermined matching target and a first predetermined anonymous function; determining a target parameter processor matching the target instruction parameters in the target instruction parameter vector from the parameter processors, and using the target parameter processor to process the target instruction parameters to obtain a processing result; and determining a processing instruction corresponding to the target instruction based on the processing result, and executing the processing instruction.

Description

[Technical field]

[0001] The present application relates to the field of software drafting, and in particular to an instruction parsing method, device and electronic device. [Background technology]

[0002] The idea of ​​the drawing module of the general-purpose numerical calculation software is as follows: drawing commands and parameters are introduced by the general-purpose numerical calculation software, the drawing module performs parameter analysis, and the image is displayed as a four-stage tree of Canvas-Figure-Axis-Object, and the process of parameter analysis and processing is the conversion process for the four-stage tree. After the parameter analysis and processing is completed, the four-stage tree is traversed and converted into a gnuplot script, and finally, the gnuplot program is called and the script is converted into an image. In this process, parameter analysis and processing are the most complicated parts. Because there are many commands and parameters that need to be supported, performing parameter analysis in a hard-coded manner will greatly increase the difficulty of code maintenance and is disadvantageous to the continuous development of the module.

[0003] Currently, there is no effective solution to the above problems. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present application provide a command analysis method, device, and electronic device, which at least solves the technical problem that parameter analysis is performed in a hard-coding manner in the prior art, which greatly improves the difficulty of code maintenance and is disadvantageous to the continuous development of modules. [Means for solving the problem]

[0005] According to one aspect of an embodiment of the present application, a method for parsing an instruction is provided, comprising the steps of receiving a target instruction and a parameter processor set, where the target instruction includes a target instruction parameter vector whose components are target instruction parameters, and the parameter processor set includes at least one parameter processor, the parameter processor being composed of an instruction parameter vector to be matched with a predetermined matching target and a first predetermined anonymous function; determining from the parameter processors a target parameter processor that matches the target instruction parameters in the target instruction parameter vector, processing the target instruction parameters using the target parameter processor, and obtaining a processing result; and determining a processing instruction corresponding to the target instruction based on the processing result, and executing the processing instruction.

[0006] Preferably, the step of determining a target parameter processor matching the target instruction parameters in the target instruction parameter vector, processing the target instruction parameters using the parameter processor, and obtaining a processing result includes the steps of: traversing each parameter processor among the at least one parameter processor from a first target instruction parameter in the target instruction parameter vector, and determining a target parameter processor from the at least one parameter processor based on an instruction parameter vector to which each parameter processor is a predetermined matching target; and processing the target instruction parameters matching the target parameter processor using a first predetermined anonymous function in the target parameter processor.

[0007] Preferably, the step of traversing each of the at least one parameter processors from a first target instruction parameter in the target instruction parameter vector and determining a target parameter processor from the at least one parameter processor based on the instruction parameter vector to be a predetermined matching target of each parameter processor includes the steps of: determining the number of elements in the instruction parameter vector to be a predetermined matching target corresponding to each parameter processor; and determining from the first target instruction parameter whether the target instruction parameter of the previous number of elements matches an element at a corresponding position in the instruction parameter vector to be matched, and determining that all of the target instruction parameters of the previous number of elements match an element at a corresponding position in the instruction parameter vector to be matched. in the case where the target parameter vector is a first target instruction parameter, the target parameter processor is determined as a target parameter processor; and, starting from a first target instruction parameter in the target parameter vector for which the target parameter processor is not matched, re-determine whether the previous number of target instruction parameters match elements at corresponding positions in the instruction parameter vector to be matched, and when it is determined that all of the previous number of target instruction parameters match elements at corresponding positions in the instruction parameter vector to be matched, determine the parameter processor corresponding to the instruction parameter vector to be matched as the target parameter processor until it is determined that all of the target instruction parameters have been matched with a parameter processor.

[0008] Preferably, the step of determining whether the target instruction parameters of the previous number of elements match elements at corresponding positions in the instruction parameter vector to be matched, and determining a parameter processor corresponding to the instruction parameter vector to be matched as a target parameter processor when it is determined that all of the target instruction parameters of the previous number of elements match elements at corresponding positions in the instruction parameter vector to be matched includes a step of selecting, when a plurality of parameter processors are determined as target parameter processors, a parameter processor among the plurality of target parameter processors which has the largest number of matched target instruction parameters as the target parameter processor.

[0009] Preferably, the step of determining whether the target instruction parameters of the previous number of elements match the elements at the corresponding positions in the instruction parameter vector to be matched includes the steps of determining a second predetermined anonymous function corresponding to each element in the instruction parameter vector to be matched, inputting the target instruction parameters of the previous number of elements into the second predetermined anonymous function corresponding to the elements at the corresponding positions and obtaining a return value returned from the second predetermined anonymous function based on the input target instruction parameters, and determining whether the target instruction parameters of the previous number of elements match the elements at the corresponding positions based on the return value.

[0010] Preferably, the step of determining a second predetermined anonymous function corresponding to each element in the instruction parameter vector to be matched includes the steps of determining a plurality of third predetermined anonymous functions; and selecting a predetermined number of third predetermined anonymous functions from the plurality of third predetermined anonymous functions and performing a logical operation on the predetermined number of third predetermined anonymous functions to obtain the second predetermined anonymous function, wherein the logical operation includes at least one of a logic and operation, a logic or operation, and a logical negation operation.

[0011] Preferably, the step of determining whether the target instruction parameters of the previous number of elements match elements at corresponding positions in the instruction parameter vector to be matched, and determining the parameter processor corresponding to the instruction parameter vector to be the specified matching target as the target parameter processor when it is determined that all of the target instruction parameters of the previous number of elements match elements at corresponding positions in the instruction parameter vector to be matched, includes the steps of determining whether an abnormal instruction parameter exists in the target instruction parameters of the previous number of elements, the abnormal instruction parameter being an instruction parameter that does not match any of the parameter processors, and deleting the abnormal instruction parameter and reselecting the target instruction parameters of the previous number of elements when it is determined that an abnormal instruction parameter exists, and determining whether the target instruction parameters of the previous number of elements match elements at corresponding positions in the instruction parameter vector to be matched, and determining the parameter processor corresponding to the instruction parameter vector to be the specified matching target as the target parameter processor when it is determined that all of the target instruction parameters of the previous number of elements match elements at corresponding positions in the instruction parameter vector to be matched.

[0012] According to another aspect of an embodiment of the present application, an instruction analysis device is further provided, comprising: a receiving module arranged to receive a target instruction and a parameter processor set, where the target instruction includes a target instruction parameter vector whose elements are target instruction parameters, and the parameter processor set includes at least one parameter processor, where the parameter processor is composed of an instruction parameter vector to be a predetermined matching target and a first predetermined anonymous function; a processing module arranged to determine from the parameter processor a target parameter processor matching a target instruction parameter in the target instruction parameter vector, process the target instruction parameters using the target parameter processor, and obtain a processing result; and an execution module arranged to determine a processing instruction corresponding to the target instruction based on the processing result, and execute the processing instruction.

[0013] According to another aspect of an embodiment of the present application, a non-volatile storage medium is provided that includes a program stored thereon that, when executed, controls an apparatus on which it resides to perform a method of parsing instructions.

[0014] According to another aspect of an embodiment of the present application, there is provided an electronic device including a processor, the processor being adapted to execute a program, the program being executed to perform the instruction parsing method. Effect of the Invention

[0015] In an embodiment of the present application, a target instruction and a parameter processor set are received, the target instruction includes a target instruction parameter vector whose components are target instruction parameters, the parameter processor set includes at least one parameter processor, the parameter processor is composed of an instruction parameter vector to be matched and a first predetermined anonymous function, a target parameter processor matching the target instruction parameters in the target instruction parameter vector is determined from the parameter processor, the target parameter processor is used to process the target instruction parameters to obtain a processing result, a processing instruction corresponding to the target instruction is determined based on the processing result, the processing instruction is executed, the target instruction parameters are matched with the corresponding parameter processor, and the parameter processor is used to process the matched target instruction parameters, thereby achieving the objective of efficiently analyzing the target instruction, achieving the technical effects of efficient implementation and maintainability of complex situation parameter analysis, and solving the technical problem that the difficulty of code maintenance caused by parameter analysis being performed in the manner of hard coding in the prior art is disadvantageous to the sustained development of modules. [Brief description of the drawings]

[0016] The drawings described herein are intended to provide an understanding of the present application and constitute a part of the present application, and the schematic embodiments of the present application and the description thereof are intended to interpret the present application without undue limitations to the application. [Figure 1] 2 is a flow diagram of a command parsing method according to an embodiment of the present application; [Diagram 2] FIG. 2 is a flow diagram of the complete flow of instruction parsing according to an embodiment of the present application. [Diagram 3] 1 is a schematic diagram of a configuration of a command analysis device according to an embodiment of the present application. [Figure 4] FIG. 1 is a schematic diagram of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In order to allow those skilled in the art to better understand the solution of the present application, the following clearly and completely describes the technical solutions of the embodiments of the present application in combination with the drawings of the embodiments of the present application, obviously, the described embodiments are not all the embodiments, but only some of the embodiments of the present application, on the premise that those skilled in the art do not make inventive efforts based on the embodiments of the present application, all other embodiments obtained fall within the protection scope of the present application.

[0018] Here, the terms "first", "second", etc. in the specification, claims and the above drawings of the present application are not intended to describe a particular order or sequence, but merely to distinguish between similar objects. The data used in this manner may be interchanged, where appropriate, so that the embodiments of the present application described herein may be performed according to other orders than those illustrated or described herein. And, the terms "comprise", "comprise", or any other variants are intended to include a non-exclusive inclusion, e.g., a process, method, system, or apparatus comprising a series of steps or units not only includes those steps or units expressly recited, but also includes other steps or units inherent in such process, method, product, or apparatus that are not expressly recited.

[0019] According to an embodiment of the present application, a method embodiment of an instruction parsing method is provided, in which the steps illustrated in the flowcharts of the drawings may be performed, for example, on a computer system as a set of computer-executable instructions, and although the flowcharts show a logical order, in some cases the steps may be performed in an order that differs from that shown or described.

[0020] FIG. 1 is an instruction parsing method according to an embodiment of the present application. As shown in FIG. 1, the method includes the following steps: Step S102: receiving a target instruction and a parameter processor set, the target instruction including a target instruction parameter vector whose components are target instruction parameters, the parameter processor set including at least one parameter processor, the parameter processor including an instruction parameter vector to be matched with a predetermined matching target and a first predetermined anonymous function; In some embodiments of the present application, in addition to the target command parameter vector (args) and the parameter processor set (handlers), the target command may also include a command name (cmd) and a number of command parameters (argc).

[0021] In some embodiments of the present application, the first predetermined anonymous function in the parameter processor may be an anonymous function of type handle, and the predetermined matching instruction parameter vector is a pre-registered vector.

[0022] In some embodiments of the present application, the above pre-registration is carried out by adding the above-mentioned instruction parameter vector that is the specified matching target to an instruction processor at the program initialization stage, and then, when actually performing instruction processing, directly calling the instruction processor to which the instruction parameter vector that is the specified matching target has been added to process the instruction.

[0023] Step S104: from the parameter processors, determine a target parameter processor matching the target instruction parameters in the target instruction parameter vector, and use the target parameter processor to process the target instruction parameters and obtain a processing result; In some embodiments of the present application, a specific manner of determining the target parameter processor matching the target instruction parameters in the target instruction parameter vector, using the parameter processor to process the target instruction parameters, and obtaining a processing result is as follows: starting from a first target instruction parameter in the target instruction parameter vector, traverse each parameter processor among the at least one parameter processor, and determine the target parameter processor from the at least one parameter processor based on the instruction parameter vector to be matched by each parameter processor; and using a first predetermined anonymous function in the target parameter processor to process the target instruction parameters matching the target parameter processor.

[0024] In some embodiments of the present application, the above target command may be any target command set based on the needs of the user. Specifically, if the command is a "hold command", the hold command is introduced with one string parameter whose value is on or off. When processing the hold command, after the parameters are matched, the command processor actually processes hold('on') or hold('off'). Here, the processing is actually modifying a global variable in a program to change the processing method of the module for the subsequent drawing command. In the hold off state, before each drawing, the module needs to clear the currently drawn drawing, and in the hold on state, it is not necessary.

[0025] In some embodiments of the present application, the step of traversing each of the at least one parameter processors from a first target instruction parameter in the target instruction parameter vector and determining the target parameter processor from the at least one parameter processor based on the predetermined matching target instruction parameter vector of each parameter processor includes the steps of determining the number of elements in the predetermined matching target instruction parameter vector corresponding to each parameter processor, and determining from the first target instruction parameter whether the previous number of target instruction parameters match elements at corresponding positions in the matching target instruction parameter vector, and if all of the previous number of target instruction parameters match elements at corresponding positions in the matching target instruction parameter vector, determining, from a first target instruction parameter in the target parameter vector to which the target parameter processor is not matched, whether a previous target instruction parameter of the number of elements matches an element at a corresponding position in the instruction parameter vector to be matched, and determining, when it is determined that all of the previous target instruction parameters of the number of elements match an element at a corresponding position in the instruction parameter vector to be matched, the parameter processor corresponding to the instruction parameter vector to be matched is determined as the target parameter processor until it is determined that all of the target instruction parameters have been matched with a parameter processor.

[0026] In some embodiments of the present application, it is determined whether the previous number of target instruction parameters match elements at corresponding positions in the instruction parameter vector to be matched, and if it is determined that all of the previous number of target instruction parameters match elements at corresponding positions in the instruction parameter vector to be matched, when determining a parameter processor corresponding to the instruction parameter vector to be matched as the target parameter processor, if multiple parameter processors are determined as the target parameter processors, the parameter processor with the largest number of matched target instruction parameters is selected as the target parameter processor among the multiple target parameter processors.

[0027] Specifically, in some embodiments of the present application, the specific flow of the above matching process is as follows: from the 0th element of the instruction parameter vector args (the subscript of the C++ array starts from 0), before matching of all parameters is completed, traverse all instruction processor handles in handlers, and in the traversal process for each handle, traverse handle.params (i.e., the instruction parameter vector to be matched), and check whether the corresponding element in args satisfies the condition that the corresponding element in handle.params needs to satisfy (here, the condition is realized by an anonymous function whose function prototype is bool(void *)). After finding a handler that satisfies the condition (if not found, repeat the above process from the next element of args), assign it to matched_handler (i.e., select an anonymous function of the target parameter processor to process the parameters), and process the matched instruction parameters by matched_handler.handle, and repeat the above process from the unprocessed instruction parameters until processing of all parameters is completed.

[0028] In some embodiments of the present application, the step of determining whether the target instruction parameters of the previous number of elements match the elements at the corresponding positions in the instruction parameter vector to be matched includes the steps of determining a second predetermined anonymous function corresponding to each element in the instruction parameter vector to be matched, inputting the target instruction parameters of the previous number of elements into the second predetermined anonymous function corresponding to the elements at the corresponding positions, and obtaining a return value returned from the second predetermined anonymous function based on the input target instruction parameters, and determining whether the target instruction parameters of the previous number of elements match the elements at the corresponding positions based on the return value.

[0029] In some embodiments of the present application, the step of determining a second predetermined anonymous function corresponding to each element in the instruction parameter vector to be matched includes the steps of determining a plurality of third predetermined anonymous functions; and selecting a predetermined number of third predetermined anonymous functions from the plurality of third predetermined anonymous functions and performing a logical operation on the predetermined number of third predetermined anonymous functions to obtain the second predetermined anonymous function, wherein the logical operation includes at least one of a logic and operation, a logic or operation, and a logical negation operation.

[0030] In some embodiments of the present application, the step of determining whether the target instruction parameters of the previous number of elements match elements at corresponding positions in the instruction parameter vector to be matched, and determining a parameter processor corresponding to the instruction parameter vector to be the predetermined matching target as the target parameter processor when it is determined that all of the target instruction parameters of the previous number of elements match elements at corresponding positions in the instruction parameter vector to be matched includes the steps of determining whether an abnormal instruction parameter exists in the target instruction parameters of the previous number of elements, the abnormal instruction parameter being an instruction parameter that does not match any one of the parameter processors, and deleting the abnormal instruction parameter and reselecting the target instruction parameters of the previous number of elements when it is determined that the abnormal instruction parameter exists, determining whether the target instruction parameters of the previous number of elements match elements at corresponding positions in the instruction parameter vector to be matched, and determining a parameter processor corresponding to the instruction parameter vector to be the predetermined matching target as the target parameter processor when it is determined that all of the target instruction parameters of the previous number of elements match elements at corresponding positions in the instruction parameter vector to be matched.

[0031] Step S106: Based on the processing result, determine a processing instruction corresponding to the target instruction, and execute the processing instruction.

[0032] In some embodiments of the present application, the image processing method described in Fig. 1 is realized by a customized target function of a target object. Specifically, when the target object is a self-established target function using C++ language, the specific flow of the execution of the command parsing method of Fig. 1 by the target function is shown in Fig. 2, which includes the following steps: First, after receiving a parameter analysis command, the above target function first executes step S202 to receive input data from the target object, where the input data includes an instruction name, a parameter vector, a number of parameters and a parameter processor set, where the number of parameters determines the number of elements in the parameter vector, and the number of elements in the parameter vector is a different parameter.

[0033] Then, the target function executes step S204, and sets the value of the custom variable start_index to zero, where start_index indicates the subscript of the parameter currently being processed, and since in C++ language, counting starts from 0, the initial value of start_index is set to zero, where, if the target object adopts other types of languages, the initial value of start_index may be other values.

[0034] Then, the target function executes step S206 to determine whether start_index is smaller than argc (the number of parameters). If the determination result is that start_index is greater than or equal to argc, the parameter analysis is terminated and the device that operates the target function is controlled to execute the command corresponding to the input data. If the determination result is that start_index is smaller than argc, the target function continues to execute step S208 to determine a target parameter processor from the input parameter processor set. If a matching target parameter processor is not found, add 1 to start_index and re-execute step S206. If a matching target parameter processor is found, execute step S210, set an anonymous function in the target parameter processor as matched_handler, execute step S212, process the parameters args[a;b] by matched_handler, and after processing the parameters, add the number of elements in the instruction parameter vector to be matched corresponding to the target parameter processor based on the original start_index as a new value of start_index, and re-execute step S206, where a=start_index and b=start_index+matched_handler.params.size( ), that is, b=start_index+the number of elements in the instruction parameter vector to be matched corresponding to the target parameter processor.

[0035] A target instruction and a parameter processor set are received, the target instruction includes a target instruction parameter vector whose components are target instruction parameters, and the parameter processor set includes at least one parameter processor, the parameter processor being composed of an instruction parameter vector to be matched and a first predetermined anonymous function, a target parameter processor matching the target instruction parameter in the target instruction parameter vector is determined from the parameter processor, the target parameter processor is used to process the target instruction parameters and obtain a processing result, and a processing instruction corresponding to the target instruction is determined based on the processing result, and the processing instruction is executed. By adopting a table-driven approach + greedy method and making full use of the lambda (anonymous function) expression introduced in C++11, the implementation code of multiple parameters of the instruction is effectively separated and orthogonal between the parameters is provided, and the method realizes a unified parameter analysis framework, and when a developer realizes a new instruction, the developer can use the framework to effectively support complex parameter analysis, and improve development efficiency and code maintainability.

[0036] According to an embodiment of the present application, an apparatus embodiment of an instruction parsing device is provided. Figure 3 shows an instruction parsing device provided by an embodiment of the present application. As shown in Figure 3, the instruction parsing device includes: a receiving module 30 configured to receive a target instruction and a parameter processor set, where the target instruction includes a target instruction parameter vector whose components are target instruction parameters, and the parameter processor set includes at least one parameter processor, where the parameter processor is composed of an instruction parameter vector to be a predetermined matching target and a first predetermined anonymous function; a processing module 32 configured to determine a target parameter processor matching the target instruction parameters in the target instruction parameter vector from the parameter processor, process the target instruction parameters using the target parameter processor, and obtain a processing result; and an execution module 34 configured to determine a processing instruction corresponding to the target instruction based on the processing result, and execute the processing instruction.

[0037] Here, since the command parsing device of FIG. 3 can execute the command parsing method of FIG. 1, the relevant explanation of the command parsing method of FIG. 1 can also be applied to the command parsing device of FIG. 3 and will not be repeated here.

[0038] According to an embodiment of the present application, a storage medium embodiment of a non-volatile storage medium is provided, the non-volatile storage medium includes a program stored therein, and when the program is executed, controls a device in which the non-volatile storage medium is located to perform the steps of: receiving a target instruction and a set of parameter processors, the target instruction including a target instruction parameter vector whose components are target instruction parameters, the set of parameter processors including at least one parameter processor, the parameter processor being composed of an instruction parameter vector to be a predetermined matching target and a first predetermined anonymous function, determining from the parameter processors a target parameter processor matching a target instruction parameter in the target instruction parameter vector, processing the target instruction parameters using the target parameter processor to obtain a processing result, and determining a processing instruction corresponding to the target instruction based on the processing result, and executing the processing instruction.

[0039] According to an embodiment of the present application, an embodiment of an electronic device is provided, the electronic device includes a processor, the processor executes a program, and when the program is executed, the electronic device executes the steps of: receiving a target instruction and a parameter processor set, the target instruction including a target instruction parameter vector whose components are target instruction parameters, the parameter processor set including at least one parameter processor, the parameter processor being composed of an instruction parameter vector to be a predetermined matching target and a first predetermined anonymous function, determining a target parameter processor matching a target instruction parameter in the target instruction parameter vector from the parameter processors, processing the target instruction parameters using the target parameter processor to obtain a processing result, and determining a processing instruction corresponding to the target instruction based on the processing result, and executing the processing instruction.

[0040] According to an embodiment of the present application, an embodiment of a computer terminal is further provided. Figure 4 is a schematic diagram of a computer device 400 according to an embodiment of the present application.

[0041] In an exemplary embodiment, a computer-readable storage medium containing instructions, such as a memory 404 containing instructions, is further provided, and the instructions are executed by the processor 402 of the device 400 to complete the steps of receiving a target instruction and a parameter processor set, where the target instruction includes a target instruction parameter vector whose elements are target instruction parameters, and the parameter processor set includes at least one parameter processor, where the parameter processor is composed of an instruction parameter vector to be matched and a first predetermined anonymous function; determining from the parameter processors a target parameter processor that matches the target instruction parameters in the target instruction parameter vector, and using the target parameter processor to process the target instruction parameters to obtain a processing result; and determining a processing instruction corresponding to the target instruction based on the processing result, and executing the processing instruction.

[0042] The numbers of the examples in the present application above do not represent the superiority or inferiority of the examples, but are for description purposes only.

[0043] In the above embodiments of the present application, the description of each embodiment has its own emphasis, and for the parts not described in detail in an embodiment, reference may be made to the relevant descriptions of other embodiments.

[0044] Here, in some embodiments provided by this application, the disclosed technical contents may be realized in other ways. The above-described device embodiments are merely schematic, and for example, the division of the units may be a division of logical functions, and in actual implementation, other division methods may be adopted, for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented. In addition, the coupling or direct coupling or communication connection between the shown or discussed mutually may be an indirect coupling or communication connection by some interfaces, units or modules, or may be an electrical or other form.

[0045] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., located in one place or distributed among multiple units, among which some or all of the units may be selected to achieve the objective of the solution of the present embodiment according to the actual needs.

[0046] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist physically alone, and two or more units may be integrated into one unit. The above-mentioned integrated units may be realized in the form of hardware or software functional units.

[0047] The integrated unit may be realized in the form of a software functional unit and stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the essence of the technical solution of the present application, or a part having a contribution to the prior art, or all or a part of the technical solution, may be embodied in the form of a software product, and the computer software product is stored in a storage medium and includes some instructions that cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or a part of the steps of the method described in each embodiment of the present application. The above storage medium includes various media that can store program code, such as a U disk, a read-only memory (ROM), a random access memory (RAM), a portable hard disk, a magnetic disk, or an optical disk, etc.

[0048] The above are only preferred embodiments of the present application, and those skilled in the art may make some improvements and modifications without departing from the principles of the present application, and these improvements and modifications should also be considered as the protection scope of the present application. [Industrial Applicability]

[0049] The solution provided in the embodiments of the present application is applied to the field of software drafting. In the embodiments of the present application, the target command parameters are matched with corresponding parameter processors, and the parameter processors are used to process the matched target command parameters, thereby achieving the purpose of efficiently analyzing the target command, and achieving the technical effects of efficient implementation and maintainability of complex situation parameter analysis. The technical problem of performing parameter analysis in the hard-coding manner in the prior art, which greatly improves the difficulty of code maintenance and is disadvantageous to the continuous development of modules, is solved.

Claims

1. 1. A command parsing method, comprising: receiving a target instruction and a set of parameter processors, the target instruction including a target instruction parameter vector whose members are target instruction parameters, the set of parameter processors including at least one parameter processor, the parameter processor comprising an instruction parameter vector subject to a predetermined matching and a first predetermined anonymous function; determining a target parameter processor from the parameter processors that matches the target instruction parameters in the target instruction parameter vector, and using the target parameter processor to process the target instruction parameters and obtain a processing result; determining a processing instruction corresponding to the target instruction based on the processing result, and executing the processing instruction.

2. determining the target parameter processor that matches the target instruction parameters in the target instruction parameter vector, and processing the target instruction parameters using the parameter processor to obtain a processing result, traversing each of the at least one parameter processors from a first target instruction parameter in the target instruction parameter vector to determine the target parameter processor from the at least one parameter processor based on the predetermined matching instruction parameter vector of each of the parameter processors; 2. The method of claim 1, further comprising: processing the target instruction parameters that match the target parameter processor using a first predetermined anonymous function in the target parameter processor.

3. traversing each of the at least one parameter processors from a first target instruction parameter in the target instruction parameter vector to determine the target parameter processor from the at least one parameter processor based on the predetermined matching target instruction parameter vector of each of the parameter processors; determining a number of elements in the instruction parameter vector to be matched that corresponds to each of the parameter processors; determining whether the previous target instruction parameters of the number of elements match the elements at the corresponding positions in the instruction parameter vector to be matched from the first target instruction parameter, and if it is determined that the previous target instruction parameters of the number of elements match the elements at the corresponding positions in the instruction parameter vector to be matched, determining a parameter processor corresponding to the instruction parameter vector to be matched as the target parameter processor; 3. The method of claim 2, further comprising the step of: re-determining, from a first target instruction parameter in the target parameter vector for which the target parameter processor is not matched, whether a previous target instruction parameter of the number of elements matches an element at a corresponding position in the instruction parameter vector to be matched; and, if it is determined that all of the target instruction parameters of the number of elements match an element at a corresponding position in the instruction parameter vector to be matched, determining a parameter processor corresponding to the instruction parameter vector to be matched as the target parameter processor until it is determined that all of the target instruction parameters have been matched with a parameter processor.

4. determining whether the previous number of target instruction parameters match elements at corresponding positions in the instruction parameter vector to be matched; and when it is determined that the previous number of target instruction parameters match elements at corresponding positions in the instruction parameter vector to be matched, determining a parameter processor corresponding to the predetermined matching target instruction parameter vector as the target parameter processor; 4. The command analysis method according to claim 3, further comprising the step of: when a plurality of parameter processors are determined as the target parameter processor, selecting, from among the plurality of target parameter processors, a parameter processor having the largest number of matched target instruction parameters as the target parameter processor.

5. The step of determining whether the previous number of target instruction parameters match an element at a corresponding position in the matching instruction parameter vector comprises: determining a second predetermined anonymous function corresponding to each element in the instruction parameter vector to be matched; inputting target instruction parameters of the previous number of elements into the second predetermined anonymous function corresponding to the element at the corresponding position, and obtaining a return value returned from the second predetermined anonymous function based on the input target instruction parameters; and determining whether a target instruction parameter of the previous number of elements matches an element at a corresponding position based on the returned value.

6. The step of determining a second predetermined anonymous function corresponding to each element in the instruction parameter vector to be matched includes: determining a third plurality of predetermined anonymous functions; 6. The method of claim 5, further comprising: selecting a predetermined number of third predetermined anonymous functions from the plurality of third predetermined anonymous functions; and performing a logical operation on the predetermined number of third predetermined anonymous functions to obtain the second predetermined anonymous function, wherein the logical operation includes at least one of a logic and operation, a logic or operation, and a logical negation operation.

7. determining whether the previous number of target instruction parameters match elements at corresponding positions in the instruction parameter vector to be matched; and when it is determined that the previous number of target instruction parameters match elements at corresponding positions in the instruction parameter vector to be matched, determining a parameter processor corresponding to the predetermined matching target instruction parameter vector as the target parameter processor; determining whether there is an abnormal command parameter in the target command parameters of the previous number of elements, the abnormal command parameter being a command parameter that does not match any one of the parameter processors; 4. The command analysis method according to claim 3, further comprising the steps of: if it is determined that the abnormal command parameter exists, deleting the abnormal command parameter and reselecting a previous number of target command parameters; determining whether the previous number of target command parameters matches elements at corresponding positions in the command parameter vector to be matched; and if it is determined that all of the previous number of target command parameters match elements at corresponding positions in the command parameter vector to be matched, determining a parameter processor corresponding to the command parameter vector to be matched as the target parameter processor.

8. A command parser comprising: a receiving module arranged to receive a target instruction and a set of parameter processors, the target instruction including a target instruction parameter vector whose members are target instruction parameters, the set of parameter processors including at least one parameter processor, the parameter processor comprising an instruction parameter vector subject to a predetermined matching and a first predetermined anonymous function; a processing module configured to determine, from the parameter processors, a target parameter processor matching the target instruction parameters in the target instruction parameter vector, and to process the target instruction parameters using the target parameter processor to obtain a processing result; an execution module arranged to determine a processing instruction corresponding to the target instruction based on the processing result, and to execute the processing instruction.

9. A non-volatile storage medium including a stored program, which, when executed, controls an apparatus in which the program is located to execute the command analysis method according to any one of claims 1 to 7.

10. 8. An electronic device comprising a processor, the processor being adapted to execute a program, the electronic device executing the command analysis method according to any one of claims 1 to 7 when the program is executed.

Images