DRAM-specific interface calibration via programmable training sequences

Abstract

A method and system are disclosed for a sequencer of a memory interface system to train an interface with a DRAM. The disclosed technique includes scheduling a command sequence including DRAM commands interleaved with one or more CSR commands, executing the scheduled command sequence, where the DRAM commands are sent to the DRAM via an internal data path of the system and the CSR commands are sent to the internal data path, and training the interface based on the exchange of data effected by the DRAM commands, where the training includes adjusting operational parameters associated with the interface.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 17 / 564,327, filed December 29, 2021, the contents of which are incorporated herein by reference. [Background technology]

[0002] Processing units rely on memory devices to store data and instructions used during operation. Access to memory devices, e.g., dynamic random-access memory (DRAM), is controlled by a memory physical layer, i.e., memory interface (or PHY). Due to variations in the computing environment and during manufacturing (associated with the DRAM, the processing units accessing the DRAM, and the communication links between them), the operating parameters that control the circuits in the data paths to and from the DRAM need to be calibrated periodically. Such calibration is performed through training of the memory interface to the DRAM.

[0003] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of an example device capable of implementing one or more features of the present disclosure. [Diagram 2] 2 is a block diagram of an example memory interface system that can be used by the device of FIG. 1, capable of implementing one or more features of the present disclosure. [Diagram 3] FIG. 1 is a block diagram of an example sequencer capable of implementing one or more features of the present disclosure. [Figure 4]FIG. 1 is a diagram of example operation codes (opcodes) for encoding DRAM commands, control and status register (CSR) commands, and miscellaneous (MISC) commands, in which one or more features of the present disclosure can be implemented. [Diagram 5] 1 is a flowchart of an example method for training a memory interface that can implement one or more features of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] The use of DRAM involves transmitting signals between the DRAM and a memory interface at specified timings and voltage levels. To reliably interface with the DRAM, it is necessary to adjust the voltage offset and relative arrival time of the signals for each pin on the DRAM. Such adjustments are made to compensate for differences in trace length between the pins on the access processing unit and the pins on the DRAM, and to compensate for manufacturing variations in the DRAM and the access processing unit. Thus, the searching space of the correct values ​​of the voltage offset and timing delay for each pin of the DRAM is large considering the number of pins (e.g., 144) and the number of possible values ​​for the voltage offset and timing delay (e.g., 256). Assumptions about manufacturing ranges and tolerances may limit the search space so that a simpler training algorithm can be implemented with fewer hardware components.

[0006] However, modern DRAM technologies and the diverse computing environments in which these DRAMs operate do not allow simplifying assumptions, and therefore thorough training should be performed to ensure high performance. Furthermore, there is a user expectation that a device (e.g., a laptop or any other mobile device) is booted or initialized almost instantly. Furthermore, training often needs to be performed periodically as the computing environment changes. Thus, training operations are limited by time budgets. Therefore, considering the diversity in DRAM technologies and computing environments, and considering the constraints on training time, a flexible, robust, and efficient training algorithm should be designed.

[0007] A system and method are provided for programmable accelerated training of data paths present in a memory interface system and DRAMs connected thereto. The system includes a sequencer implemented in programmable firmware to orchestrate training operations. The sequencer is configured to schedule DRAM commands in-line with other system commands, such as CSR and MISC commands. The DRAM commands are sent to the DRAM via the system data path. During and in coordination with the training operations, the system commands are sent to various registers of the memory interface system. The DRAM commands may include optional bits (which may or may not match valid DRAM commands) that are used to perform training under different levels of stress. The sequencer may be integrated with an acceleration unit that generates DRAM-specific commands to support DRAM technologies such as DDR1-DDR6 LPDDR4-LPDDR6, GDDR7, and HBM3.

[0008] Aspects disclosed herein describe a method for training an interface with a DRAM by a sequencer of a memory interface system. The method includes scheduling a command sequence including a DRAM command and a CSR command. The scheduled command sequence is then executed, with the DRAM command being sent to the DRAM via an internal data path of the system and the CSR command being sent to the internal data path. The method further includes training the interface based on the exchange of data performed by the DRAM command. The training includes adjustments to operational parameters associated with the interface.

[0009] Aspects disclosed herein also describe a sequencer of a memory interface system for training an interface with a DRAM. The system includes at least one processor and a memory that stores instructions. When executed by the at least one processor, the instructions cause the processor to schedule a command sequence including a DRAM command and a CSR command, execute the scheduled command sequence, where the DRAM command is sent to the DRAM via an internal data path of the system and the CSR command is sent to the internal data path, and train the interface based on the exchange of data performed by the DRAM command. The training includes adjustments to operating parameters associated with the interface.

[0010] Further disclosed aspects of the present disclosure describe a non-transitory computer-readable storage medium including instructions executable by at least one processor to execute a method for training an interface with a DRAM by a sequencer of a memory interface system. The method includes scheduling a command sequence including a DRAM command and a CSR command. The scheduled command sequence is then executed, the DRAM command being sent to the DRAM via an internal data path of the system and the CSR command being sent to the internal data path. The method further includes training the interface based on an exchange of data performed by the DRAM command. The training includes adjustments to operating parameters associated with the interface.

[0011] FIG. 1 is a block diagram of an example device 100 that can implement one or more features of the present disclosure. The device 100 can be, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. The device 100 can include a processor 110, an accelerated processing unit (APU) 120, storage 130, an input device 140, a memory 150, and an output device 160. The device 100 can also include an input driver 145 and an output driver 165. The processor 110 and the APU 120 can each represent one or more cores of a central processing unit (CPU) and one or more cores of an APU. The processor 110, the APU 120, and the memory 150, or a subset thereof, can be located on the same die or on separate dies. In an aspect, the device 100 can include additional components not shown in FIG. 1.

[0012] APU 120 may represent a graphics processing unit (GPU), i.e., a shader system comprising one or more parallel processing units configured to perform computations according to, for example, the single instruction multiple data (SIMD) paradigm. APU 120 may be configured to accept computation and graphics rendering commands from processor 110 for processing these computation and graphics rendering commands and / or providing output to a display (output device 160).

[0013] Storage 130 may include fixed or removable storage (e.g., hard disk drive, solid state drive, optical disk, flash drive). Input device 140 may represent, for example, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for reception of wireless IEEE 802 signals). Output device 160 may represent, for example, a display, a speaker, a printer, a haptic feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless local area network card for transmission of wireless IEEE 802 signals). In one aspect, input driver 145 communicates with processor 110 (or APU 120) and input device 140 to facilitate receipt of input from input device 140 to processor 110 (or APU 120). In another aspect, the output driver 165 communicates with the processor 110 (or APU 120 ) and the output device 160 and facilitates transmission of output from the processor 110 (or APU 120 ) to the output device 160 .

[0014] Memory 150 may represent volatile or non-volatile memory including random access memory (RAM), static random-access memory (SRAM), dynamic random access (DRAM), cache, or a combination thereof. Memory 150 includes a memory interface 152 that can facilitate access to DRAM 154 by a system component (e.g., processor 110 or APU 120). Memory interface 152 performs operations such as read, write, refresh, and configuration on DRAM 154. Memory interface 152 also performs training based on which internal and external data path operating parameters are set, as described herein.

[0015] FIG. 2 is a block diagram of an example memory system 200 that can be used by the device of FIG. 1, which can implement one or more features of the present disclosure. The system 200 includes a memory interface system 210 (e.g., memory interface 152 shown in FIG. 1) configured to access a DRAM 260 (e.g., DRAM 154 shown in FIG. 1). The DRAM 260 can represent various DRAM technologies, such as DDR1-DDR6, LPDDR4-LPDDR6, GDDR7, or HBM3. The memory interface system 210 includes a microcontroller 220, a training engine 230, and an internal data path 240. The microcontroller 220, the training engine 230, and the internal data path 240 are communicatively coupled directly and / or via an internal bus 250 of the system 210. The functionality of the system 210 can be implemented by components such as the microcontroller 220, the training engine 230, and the internal data path 240 in hardware, firmware, software, or a combination thereof, as described herein.

[0016] The microcontroller 220 is configured to initiate training operations performed by the training engine 230. The microcontroller 220 can initiate training operations and / or set status registers of the system 210 in response to events such as a signal sent by the host 100 (e.g., the processor 110 or the APU 120), power-on, a change in clock frequency, a power state transition (e.g., between an idle state and an active state), or periodically at a predetermined frequency.

[0017] The internal data path 240 includes a calibrator 241, an inbound first-in-first-out (FIFO) stack 242 coupled to a receiver 246, and an outbound FIFO stack 244 coupled to a transmitter 248. The receiver 246 converts analog signals measured from the pins of the DRAM 260 into discrete data that is then pushed onto the inbound FIFO stack 242. The transmitter 248 converts the discrete data popped out of the outbound FIFO 244 into an analog signal that is provided to the pins of the DRAM 260. The operation of the internal data path 240, including the receiver 246 circuitry (using analog-to-digital conversion) and the transmitter 248 circuitry (using digital-to-analog conversion), may be controlled and adjusted by various configuration registers (i.e., CSRs). Similarly, the DRAM includes a corresponding data path (referred to herein as the external data path) 270, which may include, for example, a receiver that receives signals from transmitter 248 and a transmitter that transmits signals to receiver 246, and which may be controlled and regulated by various configuration registers in the DRAM. During training operations performed by training engine 230, the configuration registers of both internal data path 240 and external data path 270 are set (or calibrated) as disclosed herein.

[0018] Training engine 230 comprises components that perform training for internal data path 240 and external data path 270, including sequencer 238, pattern generator 236, SRAM 234, and correlator 232. Training engine 230 can perform various programmable functions as disclosed herein.

[0019] The sequencer 238 can be programmed to generate sequences of commands used in training an interface with DRAM 260 of various technologies (e.g., having different interface protocols). As disclosed herein, training a memory interface involves adjustments made to operating parameters that control circuits in the datapaths 240, 270, i.e., calibration of configuration registers. Calibration of the configuration registers of the internal datapath 240 is performed by CSR commands, and calibration of the configuration registers of the external datapath 270 is performed by DRAM commands. Calibration of these configuration registers is performed, for example, in an iterative process (i.e., training) in which differences between data patterns read from the DRAM and reference data patterns are minimized. To perform training operations, the sequencer 238 generates training command sequences that include DRAM commands interleaved with system commands, such as CSR and MISC commands, as further described with reference to FIGS. 3 and 4. The sequencer 238 then executes the training command sequences, coordinates the training operations, and sends signals to other system components, such as the correlator 232 and the pattern generator 236, to perform their respective functions. In one embodiment, sequencer 238 contains many independent sequences for different training phases and can be dynamically reprogrammed.

[0020] The pattern generator 236 is configured to generate a data pattern to be used as a reference data pattern by a training operation. For example, a training operation may be used to calibrate configuration registers that control writing to the DRAM 260. In this case, the command sequence generated by the sequencer 238 may include commands to write the data pattern generated by the pattern generator 236 to a specified location in the DRAM 260 and to read back the written data pattern from the specified location in the DRAM 260. The read data pattern may then be compared to the written data pattern, and based on this comparison, an error statistic may be determined. The determined error statistic may then be used to calibrate the configuration registers, i.e., to adjust control variables of the internal data path 240 and the external data path 270 through which the written data pattern is transmitted, as described in more detail below.

[0021] SRAM 234 may be used, for example, to store training sequences or data patterns previously generated by sequencer 238 or pattern generator 236, respectively. The stored training sequences and data patterns may be used when system 100 is booting up or for periodic training. Having such training sequences and data patterns already in SRAM 234 allows for faster (boot or periodic) training times.

[0022] The correlator 232 is configured to access reference data patterns (e.g., generated by the pattern generator 236 and / or stored in the SRAM 234) and compare these reference data patterns to corresponding data patterns read from the DRAM 260. For example, if the training is for a write operation, the reference data pattern may be a data pattern written to a location in the DRAM 260 and then read back from that location. In such a case, for example, the sequencer 238 may signal the pattern generator 236 to generate a reference data pattern (or to load a reference data pattern already generated and / or stored in the SRAM 234). The sequencer 238 may then encode commands that facilitate writing the reference data pattern to a location in the DRAM 260. The sequencer 238 may also encode commands that facilitate reading back the written data pattern from the DRAM 260. These DRAM commands and the written data are transmitted to the DRAM 260 via the outbound FIFO stack 244 and the transmitter 248. The read data is received via the receiver 246 and the inbound FIFO stack 242. Following the read operation, the sequencer 238 can signal the correlator 232 to perform a comparison between a reference data pattern and the corresponding read data pattern. Based on the comparison, the correlator 232 can determine error statistics. The error statistics can be used to adjust operating parameters stored in configuration registers for each of the data paths 240, 270.

[0023] During training, sequencer 238 may iterate through a command sequence (e.g., including write and / or read operations), with each iteration resulting in further adjustment of the operational parameters and convergence to an optimal result (having favorable error statistics). However, if convergence is not achieved, error statistics across iterations may be collected and further analysis may be performed to arrive at an optimal result for the operational parameters. In one aspect, to calibrate the operational parameters stored in the control registers of internal datapath 240, correlator 232 may provide data associated with error statistics derived from one or more iterations through the command sequence to calibrator 241. Based on that data, calibrator 241 may adjust the operational parameters. However, to calibrate the operational parameters stored in the control registers of external datapath 270, the calibrator may signal an adjustment value to sequencer 238. In response, sequencer 238 may send a DRAM command (e.g., a mode register write command or a mode register read command) that adjusts the respective control registers in the DRAM accordingly. In another aspect, calibrator 241 may determine the quality of signals measured from the DRAM pins during each iteration and use these measurements to adjust operational parameters of either internal data path 240 or external data path 270. As mentioned above, data associated with error statistics and / or signal quality may be collected over several training iterations and used by system 210 for further analysis based on which optimal results for the operational parameters may be calculated if iterative adjustments of the operational parameters do not converge.

[0024] A training sequence unit for a write operation that calibrates an operating parameter is demonstrated herein. The operating parameter may be a voltage offset stored in a write register used by a receiver in the external data path 270. The training sequence unit may include the following commands: The first command in the sequence unit sets an initial voltage offset in the write register (a mode register write command). This first command is followed by several commands that activate the memory area in the DRAM 260 to be accessed (e.g., four activate commands that specify the bank group, bank, row, and column in the DRAM 260). Next in the sequence unit are several write commands (e.g., 4000 write commands) that write a reference data pattern to the activated area, followed by several read commands (e.g., 4000 read commands) that read back from the activated area. The end of this sequence unit is a precharge command (required after a read from a raw state to restore the value read from the capacitor of each DRAM). This sequence unit may be executed in several iterations. At each iteration, an error statistic may be derived based on a comparison between the written data and the read back data. Based on the error statistic, a new (adjusted) value is calculated for the reference voltage to be used in the next iteration of the sequence unit. Alternatively, the sequence unit may be repeated in a loop for a range of reference voltages. Error data for each loop may be collected based on a comparison between the reference data and the read data, and an optimal reference voltage may be calculated based on statistics derived from the collected error data.

[0025] The above training on write operations depends on read operations functioning properly. Therefore, training on read operations should be performed before training on write operations. This can be done by first setting up the DRAM with a reference data pattern. This can be done by writing a reference pattern to the DRAM at a very slow speed or by using a reference data pattern that is already pre-programmed into the DRAM. For example, when using DDR5, there is a mode register command that allows all read values ​​from the DRAM to be read from a LFSR (Linear Feedback Shift Register) that can be set with a known value.

[0026] A training sequence unit for a read operation that calibrates an operating parameter is demonstrated herein. The operating parameter may be a voltage offset stored in a read register used by a transmitter in the external data path 270. The training sequence unit may include the following commands: The first command in the sequence unit sets an initial voltage offset in the read register (mode register read command). This first command is followed by several commands that activate the memory area in the DRAM 260 to be accessed (e.g., four activate commands that specify the bank group, bank, row, and column in the DRAM 260). Next in the sequence unit are several read commands that read, e.g., at a slow rate, from the activated area a reference data pattern that was previously written to the activated area (e.g., 4000 read commands). As before, the end of this sequence unit is a precharge command. This sequence unit may be executed in several iterations. In each iteration, error statistics may be derived based on a comparison of the reference data and the read data. Based on the error statistics, a new (adjusted) value is calculated for the reference voltage to be used in the next iteration of the sequence unit. Alternatively, the sequence unit may be repeated in a loop for a range of reference voltages, and error data for each loop may be collected based on a comparison of the reference data to the read data, and an optimal reference voltage may be calculated based on statistics derived from the collected error data.

[0027] 3 is a block diagram of an example sequencer 300 capable of implementing one or more features of the present disclosure. The sequencer 300 (e.g., sequencer 238 of FIG. 2) includes an opcode encoder 310, a controller 330, and an address generator 370. The opcode encoder 310 is configured to generate a sequence of opcodes 320 that are provided as input to the controller 330. Based on the sequence of opcodes 320, the controller 330 orchestrates a training operation.

[0028] The opcode encoder 310 can interleave different opcode types when encoding the opcodes 320. That is, opcodes encoding DRAM commands can be interleaved with opcodes encoding system commands, such as CSR and / or MISC commands. This feature allows the controller to continuously launch training operations, for example, without pausing for the microcontroller 220 to reconfigure control registers in the internal datapath 240 or to reconfigure state (or mode) registers of other system components. Based on the encoding 310 of the opcodes 320, a training sequence can be generated and the training operations can be performed by the controller 330, which will be described in more detail with reference to FIG. 4.

[0029] Thus, the controller 330 receives from the opcode encoder 310 an opcode 320 that includes interleaved commands including DRAM commands, CSR commands, and MISC commands. The controller 330 orchestrates training operations using the received interleaved opcode 320. Thus, based on the opcode encoding a DRAM command, the controller generates a training sequence for the raw DRAM commands 340, enables reads / writes via the internal datapath 240, and sends control signals to other system components (such as the pattern generator 236, the correlator 232, or the calibrator 241). Based on the opcode encoding a CSR command, the controller generates a CSR write message 370 and sends these messages (via the bus 250) to the respective configuration registers in the internal datapath 240. Based on the opcode encoding a MISC command, the controller can set the status registers of other system components (such as the pattern generator 236, the correlator 232, or the calibrator 241). Address generator 370 converts (or reformats) raw DRAM commands into DRAM-specific commands 360 .

[0030] FIG. 4 is a diagram of an example operation code 400 for encoding a DRAM command 410, a CSR command 420, and a MISC command 430 that can implement one or more features of the present disclosure. The OType field (bits 0:1) indicates the type of command encoded by the opcode 400 (e.g., "0" for DRAM command 410, "1" for CSR command 420, or "2" for MISC command 430). The command can be encoded by the opcode encoder 310 to be applied iteratively in a loop using the LT, RptCnt, and Dly fields of the opcode 400. Each of the LT field (bits 2:3), RptCnt (bits 4:11), and Dly (bits 12-19) can be used to determine the loop type, the number of times the loop is executed, and the number of clock cycles in the interval between execution of successive commands. The CU flag (bit 20), when on, triggers an update of the circuitry in the internal data path (e.g., DLL / DAC) 240 with the value in the corresponding CSR. The TER flag (bit 21), when on, triggers the termination of the execution of a sequence of commands, terminating with the execution of the command encoded by this operation code. The MBZ (i.e., must be zero) fields in opcodes 410, 420, and 430 must be set to 0 (these fields are reserved for future use). The other fields in the operation codes are defined as functions of the OType.

[0031] When the encoder 310 encodes a DRAM command (i.e., OType=0) 410, a generic version of the command is stored in the Raw DRAM Cmd (bits 36:63). The Raw DRAM Cmd may contain values ​​of raw address components. In general, the DRAM 260 is organized by groups of banks. Each bank in a bank group is further organized by rows, and each row is organized by columns. The bank group, bank, row, and column make up the memory address components. However, the format in which these address components are packed into the DRAM command depends on the DRAM technology. Therefore, to generate an address in the required format, the raw address components may need to be reformatted (as will be further described with reference to the address generator 370 of FIG. 3). To that end, the flags indicated by BGG, BG, and AG (bits 22:24), when on, indicate that the raw addresses of the bank group, bank, and row and column, respectively, must be reformatted. The Read pipe enable flag, RPE (bit 25), when on indicates that the DRAM read pipeline should be enabled for one burst. The Write pipe enable flag, WPE (bit 26), when on indicates that the DRAM write pipeline should be enabled for one burst. The Max read latency (MRL) pipeline enable flag, MPE (bit 27), when on indicates that the MRL pipeline should be triggered to pop one burst of data from the inbound FIFO 242. The length of each burst is configurable via the CSR command. The CSReg field (bits 28-30 and 33-35) is a multi-purpose register; for example, the CSReg field can be used to activate chip select pins in the DRAM.

[0032] When opcode encoder 310 encodes a CSR command (i.e., OType=1) 420, the CSR command may be scheduled in-line with other DRAM commands. Such scheduling allows controller 330 to generate a CSR write message anywhere within the training sequence of the DRAM command to adjust the value of any of the configuration registers in internal datapath 240. Thus, when encoding a CSR command 420, the CSRAddr field (bits 22-45) of opcode 400 may be used to specify the address of the configuration register, and the WrDat field (bits 46-61) of opcode 400 may specify the data to be written to that configuration register.

[0033] When the opcode encoder 310 encodes a MISC command (i.e., OType=2) 430, the MISC command may be scheduled in-line with other DRAM commands. Such scheduling allows the controller 330 to respond to the MISC command anywhere in the training sequence of DRAM commands. The controller 330 may generate control signals 380 to other system components (such as the pattern generator 236, the correlator 232, or the calibrator 241) to set their status registers and coordinate training operations in response to the MISC command 430. When encoding the MISC command 430, the function field (bits 22-29) may be used to define the function to be performed, and the payload field (bits 32-63) may be used to store data used by the function to be performed. For example, the function may be to write the contents of the payload field to a status register accessible by one of the other system components. Alternatively, the function may be to use the contents of the payload to set the operating mode of the sequencer 238, 300. The latter allows the sequencer to change its operating mode during the execution of a training sequence.

[0034] As described above, interleaving DRAM commands with system commands such as CSR and / or MISC commands allows for strict scheduling of training operations. For example, within each iteration of a training sequence unit, a DRAM command in which a write operation and / or a read operation is performed can be immediately followed by a CSR command to adjust the operating parameters based on the write operation and / or read operation before the subsequent iteration of the sequence unit is performed. Similarly, dynamically changing the operating mode of the sequencer or the status registers of other system components via MISC commands allows for faster and uninterrupted training operations. As a result, more training can be performed in the same amount of time (e.g., 100 milliseconds), leading to more robust performance. Traditionally, the microcontroller 220 controls the modification of configuration registers and the change of the operating mode of the sequencer 238. However, in order for the microcontroller 220 to perform these functions, the sequencer must be paused. This places constraints on the training operations, which must be performed in small chunks between pauses, and slows down the training operations.

[0035] In addition to encoding valid DRAM commands, the opcode encoder 310 can encode DRAM commands that contain arbitrary bit patterns. For example, when training the address pins of the DRAM 260, these pins can be tested under high and low stress conditions. To this end, a chip select pin in the DRAM can be utilized, which when deactivated puts the DRAM into a mode where it ignores signals sent to its command and address bus. The system 210 allows for driving different data on the address pins during sequences where the DRAM chip transitions from an inactive state to an active state and back to the inactive state. Thus, sending the same signal when the chip select is deactivated, activated, and deactivated again provides an opportunity for testing when the signal is at a steady state (during the time that the chip select is activated), i.e., testing under low stress conditions. On the other hand, sending a different signal when the chip select is deactivated, activated, and deactivated again provides an opportunity for testing when the signal is not at a steady state (during the time that the chip select is activated), i.e., testing under high stress conditions.

[0036] The controller 330 receives the opcodes 320 encoded by the opcode encoder 310 and coordinates training operations based on these opcodes. Upon encountering an opcode encoding a DRAM command 410, the controller extracts the raw DRAM Cmd (bits 36:63) and sends the raw DRAM command 340 to the address generator 350 for reformatting into a DRAM specific command 360. The controller can repeat the command according to the information encoded in the LT and RptCnt fields and send the command repeatedly at a time interval specified by the Dly field. The controller can repeat the command in a nested loop as follows: INSTRUCTION1(RptCnt=1) LOOP_1(loop1 count=5) INSTRUCTION2(RptCnt=1) LOOP_2(loop2 count=2) INSTRUCTION3(RptCnt=1) INSTRUCTION4(RptCnt=4) END_LOOP_2 END_LOOP_1 Therefore, INSTRUCTION1 will be executed 1 time, INSTRUCTION2 will be executed 5 times, INSTRUCTION3 will be executed 10 times, and INSTRUCTION4 will be executed 40 times.

[0037] If the opcode encodes a read DRAM command or a write DRAM command based on the RPE or WPE flag, the controller enables the read data path 242, 246 or the write data path 244, 248, respectively. When an opcode encoding a CSR command 420 is encountered, the controller generates a CSR write message 370 that uses the CSRaddr field to specify the destination address of a configuration register and the WrDat field to specify the contents to be written to that configuration register. The controller transmits the generated CSR write message 370 over the bus 250 in-line with other commands in the training sequence (e.g., in the immediate time cycle after the previous DRAM command is transmitted). When an opcode encoding a MISC command 430 is encountered, the controller performs the function indicated by the function field. For example, the function may specify that the contents of the payload field are to be written to a status register of another system component (such as the pattern generator 236, the correlator 232, or the calibrator 241).

[0038] The address generator 350 is configured to convert the raw DRAM commands 340 into DRAM specific commands 360. The address generator 350 comprises an acceleration unit capable of generating addresses according to a protocol specific to the DRAM technology supporting the DRAM technology, such as DDR1-DDR7, LPDDR5, GDDR7 or HBM3, respectively. When manufactured according to different technologies, the memory regions in the DRAM are organized differently; that is, the size and number of groups of banks, banks within a bank group, rows and columns are different. Therefore, to access the same memory region, different values ​​need to be specified for each bank group, bank, row and column according to the DRAM specification (or standard). Furthermore, each DRAM technology dedicates a different number of pins to commands and dedicates different pin locations where the bank group, bank, row and column data are supplied. For example, in DDR5, the command length is 14 bits. Therefore, 28 bits of raw DRAM Cmd should be sent to the DRAM in two DRAM clock cycles. In another example, in LPDDR5, the command length is 7 bits. Therefore, the 28 bits of the raw DRAM Cmd should be sent to the DRAM in four DRAM clock cycles. Therefore, the address generator 350 must map the 28 bits of the raw DRAM command 340 into a DRAM-specific command format according to the specific DRAM standard. That is, the raw values ​​of bank group, bank, row and column should be converted and mapped to pin numbers and sent in the command cycles specified by the standard.

[0039] FIG. 5 is a flow chart of an example method 500 for training a memory interface that can implement one or more features of the present disclosure. The method 500 can use the sequencer 238, 300 of the memory interface system 210 to perform the following steps: In step 510, a command sequence is scheduled that includes DRAM commands interleaved with CSR commands. Then, in step 520, the scheduled command sequence is executed. During execution, the DRAM commands are sent to the DRAM via the system 210's internal data path, and the CSR commands are sent to the internal data path. In step 530, the interface is trained based on the exchange of data made by the DRAM commands. The training includes adjustments to operational parameters associated with the interface. The adjusted operational parameters may be associated with configuration registers of the internal data path, in which case the adjustments are made by the CSR commands. The adjusted operational parameters may also be associated with configuration registers of the external data path in the DRAM, in which case the adjustments are made by one or more of the DRAM commands. In one aspect, scheduling the command sequence in step 510 may include interleaving one or more MISC commands with the DRAM commands and the CSR commands, and executing the scheduled command sequence in step 520 may include setting a status register of the memory interface system 210 in response to one of the MISC commands.

[0040] It should be understood that many variations are possible based on the disclosure herein, and although features and elements have been described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0041] The provided methods may be implemented in a general purpose computer, processor, or processor core. Suitable processors include, by way of example, general purpose processors, special purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data including netlists (such as instructions that may be stored on a computer readable medium). The results of such processing may be a mask work, which is then used in a semiconductor manufacturing process to manufacture a processor implementing aspects of the embodiments.

[0042] The methods or flow charts provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, internal hard drives and disks, magnetic media such as removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A method for a sequencer of a memory interface system to train an interface with a dynamic random access memory (DRAM), comprising: Scheduling a command sequence including DRAM commands and control and status register (CSR) commands; executing the scheduled command sequence, the DRAM commands being sent to the DRAM via an internal data path of the memory interface system and the CSR commands being sent to the internal data path; training the interface based on the exchange of data performed by the DRAM commands; the training includes adjusting operational parameters associated with the interface; method.

2. the DRAM commands and the CSR commands are interleaved; 2. The method of claim 1.

3. the operational parameters are associated with configuration registers of the internal datapath, and the adjustments are made by the CSR commands; 2. The method of claim 1.

4. the operational parameters are associated with configuration registers of an external data path in the DRAM, and the adjustment is effected by one or more of the DRAM commands; 2. The method of claim 1.

5. the exchange of data includes a data pattern read from the DRAM; The training of the interface includes: calculating an error statistic based on a comparison between the read data pattern and a reference data pattern; and adjusting the operating parameters based on the error statistics.

2. The method of claim 1.

6. the exchange of data includes a reference data pattern written to the DRAM and a data pattern read back from the DRAM; The training of the interface includes: calculating an error statistic based on a comparison between the read data pattern and the reference data pattern; and adjusting the operating parameters based on the error statistics.

2. The method of claim 1.

7. the scheduling of the command sequence includes interleaving one or more miscellaneous (MISC) commands with the DRAM commands and the CSR commands; executing the scheduled command sequence includes setting a status register of the memory interface system in response to any of the MISC commands; 2. The method of claim 1.

8. one or more of the DRAM commands includes an arbitrary bit pattern; 2. The method of claim 1.

9. generating said DRAM commands; generating the DRAM commands includes encoding raw DRAM commands and reformatting the raw DRAM commands into DRAM-specific commands according to an interface protocol specific to the DRAM; 2. The method of claim 1.

10. 1. A sequencer for a memory interface system for training an interface with a dynamic random access memory (DRAM), comprising: At least one processor; A memory for storing instructions, The instructions, when executed by the at least one processor, Scheduling a command sequence including DRAM commands and control and status register (CSR) commands; executing the scheduled command sequence, the DRAM commands being sent to the DRAM via an internal data path of the memory interface system and the CSR commands being sent to the internal data path; training the interface based on the exchange of data performed by the DRAM commands; causing said processor to perform the training includes adjusting operational parameters associated with the interface; Sequencer.

11. the DRAM commands and the CSR commands are interleaved; The sequencer of claim 10.

12. the operational parameters are associated with configuration registers of the internal datapath, and the adjustments are made by the CSR commands; The sequencer of claim 10.

13. the operational parameters are associated with configuration registers of an external data path in the DRAM, and the adjustment is effected by one or more of the DRAM commands; The sequencer of claim 10.

14. the exchange of data includes a data pattern read from the DRAM; The training of the interface includes: calculating an error statistic based on a comparison between the read data pattern and a reference data pattern; and adjusting the operating parameters based on the error statistics. The sequencer of claim 10.

15. the exchange of data includes a reference data pattern written to the DRAM and a data pattern read back from the DRAM; The training of the interface includes: calculating an error statistic based on a comparison between the read data pattern and the reference data pattern; and adjusting the operating parameters based on the error statistics. The sequencer of claim 10.

16. the scheduling of the command sequence includes interleaving one or more miscellaneous (MISC) commands with the DRAM commands and the CSR commands; executing the scheduled command sequence includes setting a status register of the memory interface system in response to any of the MISC commands; The sequencer of claim 10.

17. one or more of the DRAM commands includes an arbitrary bit pattern; The sequencer of claim 10.

18. The instruction: causing the processor to generate the DRAM commands; generating the DRAM commands includes encoding raw DRAM commands and reformatting the raw DRAM commands into DRAM-specific commands according to an interface protocol specific to the DRAM; The sequencer of claim 10.

19. 1. A computer-readable storage medium comprising instructions executable by at least one processor to implement a method for a sequencer of a memory interface system for training an interface with a dynamic random access memory (DRAM), the method comprising: The method comprises: Scheduling a command sequence including DRAM commands interleaved with control and status register (CSR) commands; executing the scheduled command sequence, the DRAM commands being sent to the DRAM via an internal data path of the memory interface system and the CSR commands being sent to the internal data path; training the interface based on the exchange of data performed by the DRAM commands; the training includes adjusting operational parameters associated with the interface; A computer-readable storage medium.

20. the operational parameters are associated with configuration registers of the internal datapath, and the adjustments are made by the CSR commands; 20. The computer readable storage medium of claim 19.

Images