USING CHIPLET LEVEL PERFORMANCE INFORMATION TO CONFIGURE CHIPLETS IN A PROCESSOR - Patent application

Abstract

The processor comprises a controller and a plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for each chiplet identifying the performance of each chiplet at each of a plurality of performance levels of a designated set of processor cores on the chiplet. The controller receives identification information of one or more selected chiplets of the plurality of chiplets for which a designated number of processor cores are configured at a predetermined performance level, the one or more selected chiplets being selected based on the chiplet-level performance information and the performance requirements. The controller configures the designated number of processor cores of the one or more selected chiplets at the predetermined performance level. A task is then executed on the designated number of processor cores of the one or more selected chiplets at the predetermined performance level.

Description

[Background technology]

[0001] (Related Technology) Some electronic devices include a processor that executes tasks to perform various operations, such as executing program code for an application or performing control or configuration operations. In some cases, a processor includes several processor cores (e.g., a central processing unit core, a graphics processing unit core, etc.), where each processor core can be used to perform a task or a portion thereof. For example, some processors are manufactured with multiple processor cores that are fabricated on a single semiconductor die, or "chiplet," and then enclosed / contained within a package (e.g., a pin grid array (PGA) package, etc.). As another example, some processors are manufactured with two or more chiplets, each chiplet having multiple processor cores fabricated thereon, and the chiplets are enclosed / contained within the same package. For example, a 16-core processor may be manufactured with two chiplets with eight processor cores each, a 64-core processor may be manufactured with eight chiplets with eight processor cores each, etc.

[0002] Many electronic devices and the processors therein operate under various operational constraints, such as performance constraints, power consumption constraints, and / or thermal operational constraints. For example, a processor in an electronic device may be required to operate at a specified performance level (e.g., clock frequency and voltage pairs, throughput levels, control which parts of the chip are powered on / off, etc.) while remaining below a thermal threshold. In some electronic devices, the Advanced Configuration and Power Interface (ACPI) standard is used to allow an operating system (and other entities) to manage the power consumption by the processor while meeting other operational constraints. The ACPI standard allows an operating system (or other entity) to put processor cores (and other functional blocks) into specified power states, receive performance monitoring information for the processor cores, etc. One aspect of the ACPI standard is Collaborative Processor Performance Control (CPPC), which is a mechanism for an operating system (or another entity) to manage the power consumption of individual processor cores by setting operating parameters such as the voltage and frequency of the individual processor cores. With CPPC, the operating system is provided with performance information about individual processor cores (e.g., identifying their execution capabilities), and this information is used to set the operating parameters (and therefore performance levels) of the processor cores while keeping them below thermal thresholds.

[0003] While CPPC has proven useful for controlling the operation of individual processor cores, controlling processor cores individually may not result in optimal operation of the entire processor and / or chiplets therein. For example, CPPC may allow an operating system to transfer / rotate tasks between processors in an attempt to keep each processor core below a thermal threshold. In a processor with multiple chiplets, this may include transferring tasks between processor cores on different chiplets. Transferring tasks between processor cores, especially between processor cores on different chiplets, may incur significant overhead including delays in task transfer, consumption of communication system bandwidth, etc., and may cause transfer of other unrelated tasks. The overhead associated with transferring tasks reduces the overall performance of the processor.

[0004] In some processors, chiplets and the processor cores thereon are tested during manufacturing to find chiplets with uniform, higher processor core performance. In other words, the chiplets are tested to find chiplets whose processor cores all have a similar high performance level, despite the virtually unavoidable manufacturing variations in the circuits within the processor cores. The chiplets are then packaged and grouped, or "binned," for sale with other chiplets whose processor cores all have relatively similar high performance levels. Other chiplets, i.e., chiplets with processor cores with various performances, may be binned into lower performance bins according to their lower performance processor cores or discarded, thus reducing manufacturing yields. Since many chiplets have the same higher processor core performance, transferring tasks between processor cores using CPPC as described above means that tasks are moved between processors with similar performance levels. Tasks that are lower performance and therefore do not necessarily need to be executed on the higher performance processor cores are therefore executed on the processor cores with higher performance, which makes it more difficult to operate within the operational constraints. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram illustrating an electronic device according to some embodiments. [Diagram 2] FIG. 2 is a block diagram illustrating a processor according to some embodiments. [Diagram 3] FIG. 2 is a block diagram illustrating a controller according to some embodiments. [Figure 4] 1 is a block diagram illustrating a lookup table containing chiplet-level performance information, according to some embodiments. [Diagram 5] FIG. 2 is a block diagram illustrating operations for configuring processor cores in a chiplet to perform tasks at several performance levels, according to some embodiments. [Figure 6] FIG. 2 is a flow diagram illustrating a process for configuring processor cores on a chiplet in accordance with some embodiments. [Figure 7] FIG. 2 is a flow diagram illustrating a process for determining performance of a chiplet, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Throughout the drawings and description, like numbers refer to the same drawing elements.

[0007] The following description is presented to enable any person skilled in the art to make and use the described embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the described embodiments will be readily apparent to those skilled in the art, and the generic principles described herein may be applied to other embodiments and applications. Thus, the described embodiments are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features described herein.

[0008] (term) In the following description, various terms are used to describe the embodiments. Below are simplified general descriptions of some of the terms. Please note that these terms may have important additional aspects that are not listed here for clarity and conciseness, and therefore the following description is not intended to limit these terms.

[0009] Functional Block: A functional block refers to a set of interrelated circuitry, such as integrated circuitry, discrete circuitry, etc. The circuitry is "interrelated" in that the circuit elements in the circuitry share at least one characteristic. For example, the circuits may be contained in, fabricated on, or otherwise coupled to a particular integrated circuit chip, substrate, circuit board, or portion thereof, may be involved in performing particular operations (e.g., computational operations, control operations, storage operations, etc.), may be controlled by a common control element and / or a common clock, etc. The circuitry of a functional block may have any number of circuit elements, from a single circuit element (e.g., a single integrated circuit logic gate or discrete circuit element) to millions or billions of circuit elements (e.g., integrated circuit memory). In some embodiments, the functional block performs operations "in hardware" using circuitry that performs the operations without executing program code.

[0010] Data: Data is a generic term referring to information that can be stored in memory and / or used in a calculation, control and / or other operation. Data includes information such as actual data (e.g., results of a calculation or control operation, outputs of processing circuitry, inputs for a calculation or control operation, variable values, sensor values, etc.), files, program code instructions, control values, variables, and / or other information.

[0011] Memory Access: Memory access, or more simply, access, includes interactions that may be performed for, on, using, and / or with data stored in memory. For example, access may include writing or storing data to memory, reading data in memory, invalidating or deleting data in memory, moving data in memory, writing or storing metadata associated with data in memory, etc. In some cases, a copy of the data is accessed in a cache, and access to a copy of the data may include interactions that may be performed for, on, using, and / or with the copy of the data stored in the cache (such as those described above), along with cache-specific interactions such as updating coherence or access permission information.

[0012] (overview) In a described embodiment, an electronic device includes a processor having a plurality of chiplets, each of the plurality of chiplets including two or more processor cores (e.g., a central processing unit core, a graphics processing unit core, etc.). For example, the processor may be a 16-core processor having four chiplets, each having four processor cores. The processor also includes a controller that performs operations to configure the processor cores on the chiplets. In operation, an operating system (or other entity) uses chiplet-level performance information provided by the controller that identifies the performance capabilities of a designated set / group of processor cores in a chiplet to select a processor core on the chiplet on which a task is to be executed. The operating system then causes the controller to configure the selected processor cores on the chiplet at a predetermined performance level in preparation for execution of the task on the selected processor cores. The operating system then executes the task on the selected processor cores. In this manner, the operating system uses the chiplet-level performance information to distribute tasks among the processor cores on the chiplet.

[0013] In some embodiments, the controller generates the chiplet-level performance information described above and provides the chiplet-level performance information to the operating system. For these operations, the controller first obtains from each chiplet of multiple chiplets in the processor (e.g., from a performance information register or storage element on the chiplet) chiplet-level information identifying the performance of the chiplet for a designated set of processor cores on the chiplet. For example, assuming a chiplet has four processor cores, the performance information may identify the maximum performance of the chiplet given the use of a single processor core, two processor cores, three processor cores, and four processor cores. The controller then aggregates the chiplet-level performance information of all chiplets into a lookup table (or other data structure) that indicates the performance of each chiplet at each of the performance level sets for each designated set of processor cores on the chiplet. The controller then provides the chiplet-level performance information for each chiplet to the operating system, identifying the performance of each of the chiplets for a designated set of processor cores on the chiplet. For example, the controller may store the lookup table in memory within the electronic device or in a dedicated storage element for the lookup table (e.g., a register set, etc.) that allows the operating system itself to access the lookup table. As another example, the controller may respond to requests from the operating system using information obtained from the lookup table.

[0014] In some embodiments, to use the chiplet-level performance information to select a processor core within a chiplet on which a task (or a portion thereof) is to be executed, the operating system first selects one or more selected chiplets and a number of processor cores thereon based on the chiplet-level performance information based on the performance requirements of the task. For example, the operating system may search the look-up table described above to determine one or more chiplets having two processor core performances that most closely match a high performance threshold, etc. Next, the operating system communicates to the controller an identification of the one or more selected chiplets along with a number of processor cores and a performance level at which the number of processor cores are configured. The controller configures the processor cores within the one or more selected chiplets at a performance level specified by the operating system based on the identification. For example, the controller may configure the processor cores by setting operating parameters (e.g., voltage, current, clock frequency, etc.) of the processor cores to operate at the performance level. The controller may also idle or otherwise process processor cores not used to execute a task in the one or more selected chiplets and non-selected chiplets. The operating system then executes tasks (or portions thereof) on processor cores in one or more selected chiplets.

[0015] In some embodiments, the above-mentioned performance levels for each designated set of processor cores include a higher performance level, which is generally an upper (and possibly maximum) performance level, taking into account thermal and other constraints, a lower performance level, which is a lower (and possibly minimum) performance level below which the processor cores may operate inefficiently, and one or more intermediate performance levels. Thus, in these embodiments, the chiplet-level performance information includes information identifying the performance of each chiplet at each of these (or other) performance levels for each designated set of processor cores on that chiplet.

[0016] In some embodiments, the controller monitors the operational performance of the chiplet while configuring the processor cores on the chiplet. In these embodiments, the controller first obtains a provided performance counter value and a reference performance counter value from or for a given chiplet. The provided performance counter value identifies the actual performance of the given chiplet during a measurement period (e.g., including the number of operations performed). The reference performance counter value identifies a baseline performance of the given chiplet during a similar measurement period, and may be estimated for an ideal chiplet, measured based on testing of other chiplets, etc. The controller then calculates the operational performance of the given chiplet based on the provided performance counter value and the reference performance counter value. That is, a mathematical formula is used to calculate the performance as a function of the provided performance counter value and the reference performance counter value.

[0017] By using chiplet-level performance information to distribute tasks among processor cores on a chiplet, the described embodiments consider the performance of a set of two or more processor cores on a chiplet to configure the processor cores to perform tasks (versus existing systems that use the performance of individual processor cores). This allows for more efficient use of heterogeneous processor cores, i.e., chiplets with processor cores having processor cores of varying performance (as opposed to existing systems in which the processor cores have uniform performance). In other words, tasks can be more effectively matched to processor cores within a chiplet having processor cores of varying performance. Chilets with larger performance differences between processor cores can then be used, which may help avoid down-binning (i.e., selling a processor based on the performance of its lowest performing processor core) or, worse, scrapping or partial disabling of such chiplets. Using chiplets with larger performance variation can save chiplet manufacturers money and effort. Additionally, by being able to more precisely configure the processor cores to meet desired performance levels, the described embodiments can improve the performance of an electronic device when performing tasks. Improving the overall performance of an electronic device increases user satisfaction with the electronic device.

[0018] (Electronic Devices) FIG. 1 illustrates a block diagram of an electronic device 100, according to some embodiments. As shown in FIG. 1, the electronic device 100 includes a processor 102, a memory 104, and a communication (COMM) fabric 106. Generally, the processor 102, the memory 104, and the communication fabric 106 are implemented in hardware, i.e., using corresponding integrated circuits, discrete circuits, and / or devices. For example, in some embodiments, the processor 102, the memory 104, and the communication fabric 106 are implemented in an integrated circuit on one or more semiconductor chips, a combination of integrated circuits on one or more semiconductor chips in combination with discrete circuits and / or devices, or implemented in discrete circuits and / or devices. In some embodiments, the processor 102, the memory 104, and / or the communication fabric 106 perform operations for or related to using chiplet-level performance information to distribute tasks among processor cores on the chiplets, as described herein.

[0019] Processor 102 is a functional block that performs operations to perform tasks (e.g., executing program code such as a software application, an operating system, performing control or configuration operations, etc.), access data in memory 104, and other operations. Processor 102 may be or include a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a system on a chip (SOC), a field programmable gate array (FPGA), etc. Processor 102 is described in more detail below.

[0020] The memory 104 is a functional block that performs operations to store data for access by the processor 102. The memory 104 includes volatile and / or non-volatile memory circuits (e.g., fifth generation double data rate synchronous DRAM (DDR5 SDRAM)) for storing data, as well as control circuitry for handling access of data stored in the memory circuits, performing control or configuration operations, etc.

[0021] Communications fabric 106 is a functional block that performs operations to communicate data between other functional blocks in electronic device 100 over one or more communications channels. Communications fabric 108 includes wires / traces, transceivers, control circuits, etc. used to communicate data according to a protocol or standard used on communications fabric 106. For example, in some embodiments communications fabric 106 is or includes a communications fabric such as Infinity Fabric from Advanced Micro Devices Inc. (Santa Clara, Calif.).

[0022] Although electronic device 100 is illustrated in FIG. 1 with a particular number and arrangement of elements, in some embodiments, electronic device 100 includes a different number and / or arrangement of elements. For example, in some embodiments, electronic device 100 includes a different number of processors 102. Also, electronic device 100 is simplified for illustrative purposes. However, in some embodiments, electronic device 100 includes additional or different elements. For example, electronic device 100 may include a human interface subsystem (e.g., a display, a speaker, a keyboard, etc.), a power subsystem, an input / output (I / O) subsystem, etc. Generally, in the described embodiments, electronic device 100 includes a number and / or arrangement of elements sufficient to perform the operations described herein.

[0023] Electronic device 100 may be or be included in any device that performs operations related to or for using chiplet-level performance information to distribute tasks among processor cores on a chiplet, as described herein. For example, electronic device 100 may be or be included in a desktop computer, a laptop computer, a wearable computing device, a tablet computer, a virtual or augmented reality device, a smartphone, an artificial intelligence (AI) or machine learning device, a server, a networking device, a toy, an audiovisual device, a home appliance, a vehicle, and / or combinations thereof. In some embodiments, electronic device 100 is included on one or more semiconductor chips. For example, in some embodiments, electronic device 100 is included entirely on a single "system-on-chip" (SOC) semiconductor chip, included on one or more ASICs, etc.

[0024] (Processor) In the described embodiment, the processor performs operations for or related to using chiplet-level performance information to distribute tasks among processor cores on the chiplet. FIG. 2 illustrates a block diagram illustrating a processor 102, according to some embodiments. As shown in FIG. 2, the processor 102 includes chiplets 200-202 and a controller 204. Generally, the processor 102, and thus the chiplets 200-202, and the controller 204 are implemented in hardware, i.e., using corresponding integrated circuits, discrete circuits, and / or devices. For example, in some embodiments, the processor 102 is implemented in integrated circuits (i.e., transistors, signal paths, etc.) on multiple semiconductor chips / dies, and each of the chiplets 200-202 is implemented on their own semiconductor die, etc.

[0025] Each of the chiplets 200-204 is or includes an integrated circuit semiconductor die having integrated circuits fabricated thereon using integrated circuit fabrication processes such as doping or ion implantation, etching, deposition of various materials, photolithographic patterning through one or more masks, etc. Among the integrated circuits on the chiplets 200-202 are processor cores (COREs) 206-212 on the chiplet 200 and processor cores (COREs) 214-220 on the chiplet 202. Each of the processor cores 206-220 is a functional block that performs operations to perform tasks (e.g., executing program code such as a software application, an operating system, performing control or configuration operations, etc.), access data in the memory 104, and other operations. Each of the processor cores 206-220 is or includes a processor core, such as a CPU core, a GPU core, an embedded processor, an ASIC, an FPGA, etc. For example, in some embodiments, all of the processor cores 206-220 are CPU cores or GPU cores.

[0026] In addition to the processor cores 206-220, chiplet level information (CHIPLET INFO) 222 and 224 are included within the integrated circuits on the chiplets 200-202, respectively. The chiplet level information 222-224 are functional blocks including storage element circuits (e.g., flip-flops / latches, SRAM memory circuits, etc.) used to store chiplet level information identifying the performance of each chiplet at each of several different performance levels for a designated set of processor cores on each chiplet. For example, in some embodiments, the chiplet level information 222 includes performance information for the chiplet 200 at each of three performance levels (lowest performance, nominal performance, and highest performance) for each set of one or more processor cores among the processor cores 206-212. Thus, in these embodiments, the chiplet-level information 222 includes an identification of the minimum performance (i.e., performance level for executing a task below which a performance penalty occurs) of one processor core among 206-212, or of any combination of two of processor cores 206-212, three of processor cores 206-212, or all four of processor cores 206-212. In other words, the chiplet-level information 222 includes information regarding the performance of the chiplet 200 of the lowest performing two processor core pair among all possible two processor core combinations (i.e., processor cores 206-208, 206-210, 206-212, 208-210, 208-212, and 210-212), and the like. The chiplet-level information 222 also includes similar information regarding the maximum performance levels and nominal performance levels of the processor cores 206-212. In some embodiments, chiplet-level information 222 and 224 are initially set at the time of manufacture of each chiplet and remain unchanged, e.g., based on testing performed by a manufacturer. However, in some embodiments, chiplet-level information 222 and 224 can be updated, such as after running each chiplet for a predetermined amount of time, based on monitoring chiplet operation, etc.

[0027] The controller 204 is a functional block that performs operations to control the operational state of the processor cores 206-220 on the chiplets 200-202. For example, in some embodiments, the controller 204 monitors the operation of the chiplets 200-202 and / or the processor cores 206-220, generates and provides chiplet-level performance information of the chiplets 200-202 and / or the processor cores 206-220 to other entities (e.g., an operating system, etc.), controls the operational state of the chiplets 200-202 and / or the processor cores 206-220, etc. In some embodiments, the controller 204 is or includes a system management unit (SMU), a power controller, a CPU core, a microcontroller, and / or another functional block. FIG. 3 illustrates a block diagram of the controller 204, according to some embodiments. As illustrated in FIG. 3, the controller 204 includes a processing circuit 300, chiplet-level performance information 302, and a performance requirement 304. The processing circuitry 300 is a functional block that performs the operations of the controller 204 described herein, such as monitoring the operation of the chiplets 200-202 and / or processor cores 206-220, generating chiplet-level performance information 302, etc.

[0028] Chiplet level performance information 302 is a functional block that stores information identifying the performance of each of chiplets 200-202 for a designated set of processor cores on that chiplet. Chiplet level performance information 302 includes storage elements (e.g., registers, memory circuits, etc.) used to store information identifying the performance of each chiplet. In some of these embodiments, chiplet level performance information 302 stores information based on some or all of chiplet level information 222 and 224 of chiplets 200-202. In these embodiments, processing circuitry 300 obtains (e.g., reads from storage elements within each chiplet 200-202) chiplet level information 222-224 and uses chiplet level information 222-224 to generate chiplet level performance information 302. For example, processing circuitry 300 may store copies of chiplet level information 222-224, or values ​​calculated or generated therefrom, in chiplet level performance information 302. As described below, in some embodiments, the chiplet-level performance information 302 is organized as a look-up table.

[0029] Performance requirements 304 is a functional block that stores performance requirement information used by processing circuitry 300 to determine how processor cores 206-220 on chiplets 200-202 are configured (e.g., for performing tasks, conserving power, etc.). Performance requirements 304 includes storage elements (e.g., registers, memory circuits, etc.) used to store the performance requirement information. During operation, an operating system (or another entity) writes information to some or all of the storage elements in performance requirements 304 that identifies the configuration / performance level at which some or all of processor cores 206-220 are configured by processing circuitry 300. For example, in some embodiments, performance requirements 304 includes information regarding the number of processor cores of a given chiplet and the specified performance level at which the processor cores are configured. Processing circuitry 300 reads the information from the storage elements in performance requirements 304 and configures some or all of processor cores 206-220 on chiplets 200-202 accordingly. For example, in some embodiments, performance requirements 304 includes maximum and / or minimum chiplet performance registers for each chiplet. In these embodiments, the operating system (or other entity) writes information regarding maximum and / or minimum performance to corresponding chiplet performance registers, which is used by processing circuitry 300 to configure the processor cores within the chiplets. For example, processing circuitry 300 may set the processor core's voltage, current, clock frequency, queue depth, network interface speed, etc. to configure the processor cores.

[0030] 3, in some embodiments a different number and / or arrangement of elements are present in the controller 204. For example, in some embodiments, one or both of the chiplet-level performance information 302 and the performance requirements 304 are stored in the memory 104 and accessed therefrom for the operations described above. Generally, in the described embodiments, the controller 204 includes sufficient elements to perform the operations described herein.

[0031] Returning to FIG. 2, while processor 102 is shown having a particular arrangement and number of chiplets and processor cores, in some embodiments processor 102 includes a different number and / or arrangement of chiplets and / or processor cores. For example, in some embodiments, each chiplet includes eight processor cores. In general, the described embodiments are operable with various numbers and / or arrangements of chiplets and / or processor cores. Additionally, while only one controller 204 is shown in the example of FIG. 2, in some embodiments there are multiple controllers, such as a separate controller for each chiplet. In these embodiments, the multiple controllers are configured to interact with each other to coordinate their operation, such as a master controller (which may be either controller or another controller) coordinating the operation of the multiple controllers.

[0032] While some embodiments are described in which the controller maintains only chiplet-level performance information 302, in some embodiments, the controller maintains core-level performance information. In other words, the controller maintains information identifying the performance of individual cores at various performance levels (e.g., minimum performance, nominal performance, maximum performance, etc.). In these embodiments, the core-level performance information may be provided by the chip, etc., as well as the chiplet-level performance information as described herein. In some embodiments, the chiplet-level performance information and the core-level performance information may be used in combination (e.g., in a hierarchical arrangement) to determine processor cores configured at several performance levels to perform a task.

[0033] While embodiments are described in which the controller 204 is within the processor 102 (e.g., fabricated on an integrated circuit chip / die along with the chiplets 200-202), in some embodiments the controller 204 is located remotely from the processor 200. For example, in some embodiments the controller is located within a chip / die within a chipset (not shown) within the electronic device 100. Generally, the chipset includes various integrated circuit chips / dies for managing data flow within the communications fabric 106, among the processor 200, the memory 104, and peripherals (not shown) and elsewhere, as well as for performing other operations. In some of these embodiments, the processor 102, the memory 104, and / or the chipset chips / dies are mounted on a circuit board, an interposer, and / or another mounting device or element.

[0034] (Lookup table) In some embodiments, the chiplet-level performance information (e.g., chiplet-level performance information 302) is organized in the form of a lookup table. FIG. 4 illustrates a block diagram of a lookup table 400 for chiplet-level performance information, according to some embodiments. Generally, lookup table 400 includes indicators of chiplet performance (i.e., values ​​indicative / identifying chiplet performance) that enable a processing circuit (e.g., processing circuit 300) (and possibly other entities) to determine how a given chiplet will perform given different numbers of processor cores and performance levels. In some embodiments, as shown along the top row of sub-table 402, the performance levels in lookup table 400 include a minimum performance (a performance level for performing a task below which a specified circuit in a processor core will incur a performance penalty (e.g., leakage current, state fidelity reductions, etc.)). The performance levels also include a minimum nonlinear performance (the minimum nonlinear performance is the lowest performance level above which nonlinear power savings are achieved, i.e., levels slightly higher than this performance level are much more power efficient compared to higher values ​​above this threshold). The performance levels also include a nominal performance (nominal performance is the highest sustainable performance level for performing a task under specified nominal operating conditions). The performance levels further include a maximum performance (maximum performance is the highest performance level for performing a task under high performance operating conditions, e.g., thermal constraints, throughput requirements, etc.).

[0035] In the example of FIG. 4, it is assumed that the lookup table 400 stores chiplet level performance information of the chiplets 200-202 as shown in FIG. 2. Thus, as shown in FIG. 4, the lookup table 400 includes two sub-tables 402-404, each of which stores a respective chiplet 200-202 and information related thereto. Thus, information related to the chiplet 200 can be obtained by performing a lookup in the lookup table 402. In other words, given a given number of processor cores and a requirement for chiplet level performance information of a specified performance level, the processing circuit 300 can perform a lookup in each sub-table 402-404 to obtain the chiplet level performance information of each chiplet 200-202.

[0036] In some embodiments, the value of the indicator in lookup table 400 is relative and set based on the respective performance of one or more other processor cores in the respective chiplet. For example, the indicator may be expressed as a function of a performance threshold of a designated processor core on the chiplet. For example, the designated processor core may be the highest or lowest performing processor core in the chiplet, taking into account the performance of all processor cores on the chiplet (e.g., as tested by the manufacturer, etc.). Thus, in some embodiments, using sub-table 402 as an example, for a performance level of the lowest performance, the lookup table may store a value such as 0.95 for a two-core processor core set (i.e., where the performance level is for a combination of two processor cores in a chiplet). In this case, the minimum performance when executing a task on two processor cores in a chiplet is 2×the minimum performance of the best lowest performing processor core in the chiplet×0.95. This means that 2 * LowestPerformanceBestCore *0.95 Example relative values ​​of the four performance levels for combinations of two, three and four processor cores are shown in sub-table 402 of Figure 4 (values ​​of a similar nature are shown in sub-table 404, if displayed).

[0037] In some embodiments, the values ​​in lookup table 400 are associated with a particular combination of processor cores for a given chiplet, and thus reflect the chiplet's performance for executing a task, assuming the use of the particular processor cores. For example, using processor cores 206-212, the minimum performance value of 0.95 for two processor cores in sub-table 402 is associated with the particular two processor cores (e.g., processor cores 208 and 212) that most closely (and possibly best) meet the "minimum performance" standard as a pair. In other words, among all of the possible two processor core combinations for a given chiplet (i.e., processor cores 206-208, 206-210, 206-212, 208-210, 208-212, 210-212), the particular combination of two processors best meets the thresholds, guidelines, rules, etc. associated with a minimum performance level (e.g., operate at one or more low frequencies without incurring a performance penalty, such as a specified amount of leakage current, state decay, etc.). In some embodiments, as described elsewhere herein, when configuring one or more selected chiplets to perform tasks at a certain performance level, the controller, processor, and / or one or more selected chiplets use the particular processor cores for which lookup table 400 stores information. For example, when configuring chiplet 200 to operate at a minimum performance level for two processor cores, the two particular processor cores (e.g., processor cores 208 and 212, as described above) will be used and the other processor cores may be disabled or used to perform other tasks.

[0038] 4 shows sub-tables 402-404, in some embodiments there are no sub-tables and all chiplet level performance information is listed in a single table. Additionally, while FIG. 4 uses two four-processor core chiplets as an example, and thus two sub-tables with three rows, in some embodiments a different number of chiplets and / or processor cores may be used, and a corresponding number of sub-tables and / or rows would be present in lookup table 400. Generally, in the described embodiment, lookup table 400 includes sufficient information to allow processing circuit 300 (and possibly other entities) to look up chiplet level performance information based on the number and performance level of processor cores.

[0039] (Chiplet configuration) In the described embodiment, a controller in the processor configures processor cores in selected chiplets in the processor at specified performance levels as requested by the operating system (or another entity). FIG. 5 illustrates a block diagram illustrating operations for configuring processor cores in a chiplet to perform tasks at certain performance levels, according to some embodiments. FIG. 5 is presented as a general example of operations that may be performed in some embodiments. However, in other embodiments, different operations are performed and / or operations are performed in a different order. Additionally, although certain elements (e.g., controllers, etc.) are used in describing a process, in some embodiments, other elements perform the operations.

[0040] In the example of FIG. 5, an embodiment having two chiplets, namely chiplets 200-202, is described. However, some elements within chiplets 200-202 (i.e., processor cores 206-220 and chiplet-level information 222-224) are not labeled in FIG. 5 itself for clarity. In addition, in the example of FIG. 5, it is assumed that controller 204 has previously generated chiplet-level performance information 302 in the form of lookup table 400. In other words, controller 204 obtained chiplet-level information 222 and 224 (shown as chiplet-level information 506 in FIG. 5) from chiplets 200 and 202 and generated lookup table 400 therefrom. In the example of FIG. 5, it is also assumed that controller 204 performs a lookup in a lookup table (e.g., lookup table 400) and returns a performance indicator to the requesting entity (i.e., instead of providing lookup table 400 itself to another entity). Further assume that an operating system 500, for example the Windows operating system from Microsoft (Redmond, WA), is being executed by the processor.

[0041] The operations of FIG. 5 begin when controller 204 provides chiplet level performance information 502 to operating system 500. For this operation, in some embodiments, operating system 500 requests chiplet level performance information from controller 204 for a predetermined number of processor cores (e.g., 2, 3, etc.) and a specified performance level (e.g., minimum performance, nominal performance, etc.). For example, in some embodiments, the operating system interacts with the controller to make the request and receive a corresponding response using an application programming interface (API) provided / supported by the controller. Upon receiving the request from operating system 500, controller 204 retrieves the appropriate chiplet level performance information and returns chiplet level performance information 502 to operating system 500. Continuing with the example of lookup table 400, operating system 500 performs a lookup in lookup table 400 (e.g., in sub-tables 402-404) for each processor core using the predetermined number of processor cores and the specified performance level, and then returns chiplet level performance information 502 from lookup table 400 to operating system 500. For example, the controller 204 may obtain an indicator, such as 0.95, for the minimum performance of two processor cores from the sub-table 402 and return the indicator to the operating system 500 .

[0042] The operating system 500 then sends a request to the controller 204 identifying the number of processor cores on the selected chiplet and the performance level 504 at which the operating system 500 wants the controller 204 to configure the chiplet. For this operation, the operating system 500 analyzes the chiplet level performance information 502 to determine the suitable chiplets to perform the task. For example, the operating system 500 can determine one or more chiplets having performance that best meets (i.e., is closest to) the performance level threshold based on the chiplet level performance information 502 and can select the best-fit one or more chiplets to perform the task. For example, for the highest performance level, the operating system 500 can determine the chiplet whose combination of two processor cores has an indicator that is closest to 1 (e.g., 0.92 in the sub-table 402). The operating system 500 then sends a request including the number of processor cores on the selected chiplet and the performance level 504 to the controller 204 to configure the chiplet. In some embodiments, for this action, the operating system 500 writes corresponding information to the performance request 304 to notify the controller 204 of the request.

[0043] Controller 204 then communicates configuration information (INFO) 508 to one or both of chiplets 200-202 to configure the requested number of processor cores on the selected chiplet at that performance level. For example, in some embodiments, controller 204 sets the voltage, current, clock frequency, queue depth, network interface speed, etc., for the number of processor cores in the selected chiplet based on the information in performance request 304. In other words, controller 204 adjusts adjustable circuitry, requests adjustments from control circuitry, etc. via switches or other configuration elements such that the voltage, current, clock frequency, etc. provided to the number of processor cores in the selected chiplet are set according to the requested performance level. In some embodiments, other processor cores in the selected chiplet are disabled, set to a low power operating state, and / or otherwise processed. In some embodiments, the performance levels of other processor cores on the selected chiplet (and possibly non-selected chiplets) are set based at least in part on the configuration of the selected chiplet and / or the processor cores therein (e.g., to keep a given chiplet within thermal limits, etc.).

[0044] (Process for Configuring Chiplets) In the described embodiment, a controller (e.g., controller 204) performs operations to configure processor cores on a chiplet (e.g., processor cores 206-220 on chiplets 200-202) at a specified performance level. FIG. 6 illustrates a flow diagram illustrating a process for configuring processor cores on a chiplet, according to some embodiments. FIG. 6 is presented as a general example of operations performed in some embodiments. However, in other embodiments, different operations are performed and / or operations are performed in a different order. For example, in some embodiments, the chiplet-level performance information (step 600) is prepared by the controller well before other operations of FIG. 6, and steps 602-608 may be performed multiple times (possibly multiple times) using the same chiplet-level performance information. Additionally, although certain elements (e.g., controllers, etc.) are used in describing the process, in some embodiments, other elements perform the operations.

[0045] A processor similar to processor 102 is used in describing the example of Figure 6. Thus, the processor is assumed to have two chiplets (e.g., chiplets 200-202), eight processor cores (e.g., processor cores 206-220) therebetween, and a controller (controller 204). In addition, a lookup table, e.g., lookup table 400, is used as the chiplet level performance information in the example of Figure 6.

[0046] 6 begins when a controller within a processor generates chiplet-level performance information (step 600). For this operation, the controller retrieves chiplet-level information from storage elements on each chiplet within the processor (e.g., chiplet-level information 222 and 224) and writes the chiplet-level information to corresponding locations in a lookup table. For example, in some embodiments, the controller writes relative numerical indicators to locations in the lookup table (as described above with respect to FIG. 4).

[0047] The controller then provides the chiplet-level performance information (step 602). For this operation, in some embodiments, the controller provides the chiplet-level performance information by making the entire lookup table available to the operating system (and possibly other entities). For example, the controller may store the lookup table in a shared / public memory circuit (e.g., in memory 104, in a dedicated register, etc.) where the lookup table is accessible to the operating system. In these embodiments, the operating system obtains the information from the lookup table by performing its own lookup in the lookup table for a particular number of processor cores and performance level. During such lookup, the operating system would retrieve an indicator from the lookup table (e.g., 2 processor cores, 0.95 for lowest performance, etc. in lookup table 400). However, in some embodiments, the controller provides the chiplet-level performance information by responding to a request from the operating system (and possibly other entities), but stores the lookup table locally (e.g., in a local storage element in the controller, etc.). In these embodiments, the controller retrieves and provides only the requested indicator from the lookup table in response to a request. Thus, in these embodiments, the operating system requests from the controller an indicator associated with a particular number of processor cores and a performance level, and upon receiving such a request, the controller retrieves the respective indicator from the lookup table and provides the indicator to the operating system in response.

[0048] Next, the controller receives identification information of one or more selected chiplets in which a designated number of processor cores are to be configured at the predetermined performance level (step 604). In response to this operation, the operating system uses the provided chiplet-level performance information to determine the chiplets in which a designated number of processor cores are to be configured at the predetermined performance level in order to prepare the designated number of processor cores to execute a task. For example, the operating system may compare indicators from the lookup table to one or more thresholds and / or each other to determine one or more chiplets that meet (or most closely meet, exceed, etc.) the performance level of the designated number of processor cores. Upon selecting the one or more selected chiplets for which the performance level is suitable, the operating system communicates a request to the controller to configure the designated number of processor cores in the one or more chiplets at the predetermined performance level. For example, the operating system may write information identifying the one or more selected chiplets and the designated number of processor cores to a chiplet performance register associated with the predetermined performance level in the controller. In these embodiments, the controller receives the identification information by reading the chiplet performance register associated with the predetermined performance level (e.g., in response to an interrupt from the operating system, to detect a write, etc.).

[0049] The controller then configures (step 606) the designated number of processor cores of the one or more chiplets at a predetermined performance level. For this operation, the controller sets one or more operating parameters for each of the designated number of processor cores based on the predetermined performance level. For example, the controller may set the operating parameters such as voltage, current, clock frequency, queue depth, network interface speed, etc. Recall that the indicators in the lookup table are associated with particular processor cores. Thus, in this operation, the controller configures the particular processor core associated with the indicator. For example, when a request is received to set two of four processor cores in the processor to a minimum performance level, the controller knowing which two processor cores the indicators in the lookup table apply to configures those two processor cores at the minimum performance level. Other processor cores not configured as described may be disabled, placed in a low power mode (e.g., operating parameters are set to a low power level, etc.), and / or used for other purposes (e.g., to perform other tasks).

[0050] The operating system then executes the task on the designated number of processor cores of the one or more selected chiplets (step 608). For this operation, the operating system executes the task, such as executing program code, performing control or configuration operations, on the designated number of processor cores of the one or more selected chiplets. Thus, in these embodiments, the operating system first configures (with the assistance of the controller) the designated number of processor cores of the one or more selected chiplets and then executes the task on the designated number of processor cores of the one or more selected chiplets.

[0051] (Process for determining the performance of chiplets) In some embodiments, in addition to other operations described herein, the controller performs operations to determine performance of chiplets in the processor. In these embodiments, the controller uses actual / measured performance information and baseline information to determine performance of the chiplets. FIG. 7 illustrates a flow diagram illustrating a process for determining performance of chiplets, according to some embodiments. FIG. 7 is presented as a general example of operations performed in some embodiments. However, in other embodiments, different operations are performed and / or operations are performed in a different order. Additionally, although certain elements (e.g., controllers, etc.) are used in describing the process, in some embodiments, other elements perform the operations.

[0052] The process of Figure 7 begins when the controller retrieves from a chiplet (e.g., chiplet 200) in a processor a provided performance counter value that identifies the chiplet's performance during a measurement period (step 700). For this operation, the controller retrieves the provided performance counter value from a storage element within the chiplet (or possibly elsewhere), such as a provided performance counter value register. The provided performance counter value is a value that represents, or is set proportional to, one or more indicators of the chiplet's performance during the measurement period (e.g., for N ms (N = 250, 500, or another number)). For example, in some embodiments the provided performance counter value is or includes a number of operations executed, a number of instructions executed, etc. during execution of a task.

[0053] The controller also retrieves a baseline performance counter value from the chiplet within the processor (or elsewhere) that identifies the chiplet's baseline performance during the measurement period (step 702). For this operation, the controller retrieves a baseline performance counter value from a storage element within the chiplet, such as a baseline performance counter value register. The baseline performance counter value is a value that represents, or is set proportionally to, one or more indicators of the expected or baseline performance of the chiplet during the measurement period. For example, in some embodiments the baseline performance counter value is or includes an expected or baseline number of operations performed during execution of a task, a number of instructions executed, etc.

[0054] The controller then calculates the performance provided by the chiplet during the reference period based on the provided performance counter values ​​and the reference performance counter values ​​(step 704). For this operation, the controller calculates the result of a mathematical formula as a function of the provided performance counter values ​​and the reference performance counter values, the result of which represents or is proportional to the delivered performance of the chiplet. For example, in some embodiments, the controller calculates the result of the following formula:

[0055]

number

[0056] In some embodiments, at least one electronic device (such as, for example, electronic device 100) or a portion thereof uses code and / or data stored in a non-transitory computer-readable storage medium to perform some or all of the operations described herein. More specifically, at least one electronic device reads the code and / or data from the computer-readable storage medium and executes the code and / or uses the data when performing the described operations. The computer-readable storage medium may be any device, medium, or combination thereof that stores code and / or data used by the electronic device. For example, the computer-readable storage medium may include, but is not limited to, volatile and / or non-volatile memory, such as flash memory, random access memory (e.g., DDR5 DRAM, SRAM, eDRAM, etc.), non-volatile RAM (e.g., phase change memory, ferroelectric random access memory, spin transfer torque random access memory, magnetoresistive random access memory, etc.), read-only memory (ROM), and / or magnetic or optical storage media (e.g., disk drives, magnetic tapes, CDs, DVDs, etc.).

[0057] In some embodiments, one or more hardware modules perform the operations described herein. For example, a hardware module may include, but is not limited to, one or more central processing units (CPUs) / CPU cores, graphics processing units (GPUs) / GPU cores, application-specific integrated circuit (ASIC) chips, field programmable gate arrays (FPGAs), compressors or encoders, computational units, embedded processors, accelerated processing units (APUs), controllers, requesters, completers, network communication links, and / or other functional blocks. When circuitry (e.g., integrated circuit elements, discrete circuit elements, etc.) within such a hardware module is activated, the circuitry performs some or all of the operations. In some embodiments, a hardware module includes general-purpose circuits, such as execution pipelines, computational or processing units, that perform operations upon execution of instructions (e.g., program code, firmware, etc.). In some embodiments, a hardware module includes application-specific or dedicated circuits that perform operations "in hardware" without executing instructions.

[0058] In some embodiments, data structures representing some or all of the functional blocks and circuit elements described herein (e.g., electronic device 100 or some portion thereof) are stored in a non-transitory computer-readable storage medium including a database or other data structure that can be read by the electronic device and used directly or indirectly to fabricate hardware including the functional blocks and circuit elements. For example, the data structure can be a behavioral level description or a register-transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description can be read by a synthesis tool that can synthesize the description to generate a netlist including a list of transistors / circuit elements from a synthesis library that represents the functionality of the hardware including the functional blocks and circuit elements described above. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor processing steps to fabricate a semiconductor circuit or circuits (e.g., integrated circuits) corresponding to the functional blocks and circuit elements described above. Alternatively, the database on the computer accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0059] In this description, variables or unspecified values ​​(i.e., general descriptions of values ​​without specific examples of values) are represented by letters such as N, T, X, etc. As used herein, despite the possible use of similar letters in different places in this description, the variables and unspecified values ​​in each instance are not necessarily the same, i.e., there may be variables and values ​​intended for some or all of the general variables and unspecified values. In other words, the examples of specific values ​​of N, as well as any other letters used to represent variables and unspecified values ​​in this description, are not necessarily related to each other.

[0060] As used herein, the phrase "et al." or "etc." is intended to present one and / or instance, i.e., the equivalent of "at least one of" the elements in the list with which the others are associated. For example, in a statement that "the electronic device performs a first operation, a second operation, etc.", the electronic device performs at least one of the first operation, the second operation, and the other operation. In addition, the elements in the list with which the others are associated are merely examples from a set of examples, and at least some of the examples may not appear in some embodiments.

[0061] The foregoing descriptions of the embodiments have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Accordingly, many modifications and variations will be apparent to those skilled in the art. Further, the above disclosure is not intended to limit the embodiments. The scope of the embodiments is defined by the appended claims.

Claims

1. 1. A processor comprising: a plurality of chiplets, each chiplet including a plurality of processor cores; A controller, The controller: providing chiplet-level performance information for each chiplet, the chiplet identifying the performance of each chiplet at each of a plurality of performance levels for a designated set of processor cores on the chiplet; receiving identification information of one or more selected chiplets among the plurality of chiplets, wherein a designated number of processor cores are configured at a predetermined performance level, the one or more selected chiplets being selected based on the chiplet level performance information and performance requirements; configuring the designated number of processor cores of the one or more selected chiplets at the predetermined performance level; [0023] Processor.

2. the controller is configured to provide a lookup table indicating performance of each chiplet at each of a plurality of performance levels of a designated set of processor cores on the chiplet to provide the chiplet-level performance information; each of the designated sets of processor cores includes a different number of processor cores; The processor of claim 1 .

3. an indicator of performance of each chiplet at each of the plurality of performance levels for the designated set of processor cores is expressed as a value calculated as a function of performance capacity of one or more cores within the chiplet. The processor of claim 2.

4. The controller: For each chiplet, obtaining chiplet-level information from a storage element on the chiplet that identifies performance of the chiplet at each of the plurality of performance levels for a designated set of the processor cores on the chiplet; generating the lookup table by populating the lookup table with an indicator of performance of the chiplet at each of the plurality of performance levels for each designated set of the processor cores on the chiplet based on the chiplet level information; [0023] The processor of claim 2.

5. the plurality of performance levels including some or all of a minimum performance, a minimum nonlinear performance, a nominal performance, and a maximum performance; The processor of claim 2.

6. a chiplet performance register in the controller associated with each performance level; Upon receiving identification of the one or more selected chiplets, the controller: configured to receive information written to a chiplet performance register associated with the predetermined performance level; the information identifying the one or more selected chiplets and the specified number of processor cores. The processor of claim 1 .

7. the controller is configured to, when configuring the designated number of processor cores of the one or more selected chiplets at the predetermined performance level, set, for each of the designated number of processor cores, one or more operating parameters based on the predetermined performance level. The processor of claim 1 .

8. The controller: For each chiplet, obtaining provided performance counter values ​​from a chiplet, the provided performance counter values ​​identifying performance of the chiplet during a measurement period; obtaining a baseline performance counter value from the chiplet, the baseline performance counter value identifying a baseline performance of the chiplet during the measurement period; calculating performance provided by the chiplet based on the provided performance counter values ​​and the reference performance counter values; and configured to measure performance provided by any one of the plurality of chiplets by The processor of claim 1 .

9. some or all of the processor cores in each chiplet have different performance levels due to manufacturing variations in the circuitry within the processor cores; The processor of claim 1 .

10. executing a task on the designated number of processor cores of the one or more selected chiplets after the designated number of processor cores of the one or more selected chiplets are configured at the predetermined performance level. The processor of claim 1 .

11. the controller, when configuring the specified number of processor cores of the one or more selected chiplets at the predetermined performance level, configures other processor cores of the selected chiplets in a lower power state or disables the other processor cores. The processor of claim 1 .

12. 1. A method for configuring processor cores within a chiplet for a processor including a plurality of chiplets, comprising: Each chiplet contains multiple processor cores, The method comprises: providing chiplet-level performance information for each chiplet, the chiplet identifying the performance of each chiplet at each of a plurality of performance levels for a designated set of processor cores on the chiplet; receiving identification information of one or more selected chiplets among the plurality of chiplets, wherein a designated number of processor cores are configured at a predetermined performance level, the one or more selected chiplets being selected based on the chiplet level performance information and performance requirements; and configuring the designated number of processor cores of the one or more selected chiplets at the predetermined performance level. method.

13. Providing the chiplet level performance information includes: providing a lookup table indicating the performance of each chiplet at each of a plurality of performance levels of a designated set of processor cores on the chiplet; each of the designated sets of processor cores includes a different number of processor cores; 13. The method of claim 12.

14. an indicator of performance of each chiplet at each of the plurality of performance levels for the designated set of processor cores is expressed as a value calculated as a function of performance capacity of one or more cores within the chiplet.

14. The method of claim 13.

15. The method comprises: For each chiplet, obtaining chiplet-level information from a storage element on the chiplet that identifies performance of the chiplet at each of the plurality of performance levels for a designated set of the processor cores on the chiplet; and generating the lookup table by populating the lookup table with an indicator of performance of the chiplet at each of the plurality of performance levels for each designated set of the processor cores on the chiplet based on the chiplet level information.

14. The method of claim 13.

16. the plurality of performance levels including some or all of a minimum performance, a minimum nonlinear performance, a nominal performance, and a maximum performance; 14. The method of claim 13.

17. Receiving identification information of the one or more selected chiplets includes: receiving information written to a chiplet performance register associated with the predetermined performance level; the information identifying the one or more selected chiplets and the specified number of processor cores.

13. The method of claim 12.

18. Configuring the designated number of processor cores of the one or more selected chiplets at the predetermined performance level includes: setting one or more operating parameters for each of the specified number of processor cores based on the predetermined performance level.

13. The method of claim 12.

19. The method comprises: obtaining provided performance counter values ​​from a chiplet, the provided performance counter values ​​identifying performance of the chiplet during a measurement period; obtaining a baseline performance counter value from the chiplet, the baseline performance counter value identifying a baseline performance of the chiplet during the measurement period; calculating performance provided by the chiplet based on the provided performance counter values ​​and the reference performance counter values; measuring the performance provided by any one of the plurality of chiplets by 13. The method of claim 12.

20. some or all of the processor cores in each chiplet have different performance levels due to manufacturing variations in the circuitry within the processor cores; 13. The method of claim 12.

21. The method comprises: executing a task on the designated number of processor cores of the one or more selected chiplets after the designated number of processor cores of the one or more selected chiplets are configured at the predetermined performance level.

13. The method of claim 12.

22. Configuring the designated number of processor cores of the one or more selected chiplets at the predetermined performance level includes: configuring other processor cores of the selected chiplet in a lower power state or disabling the other processor cores.

13. The method of claim 12.

23. 1. An electronic device comprising: Memory, a processor, the processor including a plurality of chiplets, each chiplet including a plurality of processor cores; A controller, The controller: providing chiplet-level performance information for each chiplet, the chiplet identifying the performance of each chiplet at each of a plurality of performance levels for a designated set of processor cores on the chiplet; receiving identification information of one or more selected chiplets among the plurality of chiplets, wherein a designated number of processor cores are configured at a predetermined performance level, the one or more selected chiplets being selected based on the chiplet level performance information and performance requirements; configuring the designated number of processor cores of the one or more selected chiplets at the predetermined performance level; [0023] Electronic devices.

24. the controller is located remotely from the processor within a chipset; 24. The electronic device of claim 23.

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