High-speed tag deactivation circuit

Abstract

A system and method for efficiently resetting data stored in a memory array is described. In various embodiments, an integrated circuit includes a memory for storing data and a processing unit for generating access requests for the data stored in the memory. When an access circuit of the memory array initiates a reset operation, it reduces a power supply voltage level used by memory bit cells in a column of the array to a value below the threshold voltage of the transistor. Thus, the p-type transistors of the bit cells do not contend with the write driver during a write operation. The access circuit provides reset data on the write bit lines and asserts each of the write word lines of the memory array. To complete the write operation, the access circuit returns the power supply voltage level from below the threshold voltage level to the operating voltage level.

Description

[Background technology]

[0001] Description of Related Art Generally, various semiconductor chips use a memory for storing data and a processing unit for generating access requests to the data stored in the memory. The memory includes a memory array of many bit cells and access circuitry used to access the values ​​stored in the array. An example of a memory array is a tag array of a cache in any of the multiple levels of a cache memory subsystem. Semiconductor chips with multiple processing units increase the demand for memory. A larger amount of memory provides both sufficient storage for each processing unit and more sharing of information across multiple processing units. In some designs, the processing unit and memory are on the same die, such as a system-on-a-chip (SOC). In other designs, the processing unit and memory are on different dies in the same package, such as a system-on-a-package (SIP).

[0002] Static Random Access Memory (SRAM) is commonly used for memory arrays. To balance performance and power consumption, memory arrays are reset from time to time. Examples of resetting memory arrays are invalidating the cache between sleep-to-active transitions, invalidating the cache to push new content to clients, invalidating the cache to change cache size, etc. Resetting memory arrays quickly improves performance. However, updating a large number of entries simultaneously significantly increases the size of the write driver of the access circuitry. Thus, there is a cost associated with increased power consumption and increased on-die area.

[0003] In view of the above, what is desired is an efficient method and system for efficiently resetting data stored in a memory array. [Brief description of the drawings]

[0004] [Figure 1] FIG. 2 is a generalized diagram of a memory bitcell. [Diagram 2] FIG. 2 is a generalized diagram of a method for efficiently resetting data stored in a memory array. [Diagram 3] FIG. 2 is a generalized diagram of a memory array access circuit. [Figure 4] FIG. 2 is a generalized diagram of a method for efficiently resetting data stored in a memory array. [Diagram 5] FIG. 2 is a generalized diagram of a method for efficiently resetting data stored in a memory array. [Figure 6] FIG. 2 is a generalized diagram of a memory bank. [Figure 7] FIG. 2 is a generalized diagram of a method for efficiently resetting data stored in a memory array. [Figure 8] FIG. 1 is a generalized diagram of a computing system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the invention to the particular forms disclosed, but on the contrary, the invention is intended to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

[0006] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art should recognize that the present invention may be practiced without these specific details. In some instances, well-known circuits, structures and techniques have not been shown in detail in order to avoid obscuring the present invention. Furthermore, it will be understood that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements are exaggerated relative to other elements.

[0007] Systems and methods are contemplated for efficiently resetting data stored in a memory array. In various embodiments, an integrated circuit includes a memory for storing data and a processing unit for generating access requests to the data stored in the memory. The memory includes a memory array of many bit cells and access circuitry used to access values ​​stored in the array. In various embodiments, the memory array is implemented with SRAM. An example of a memory array is a tag array of a cache in any of the multiple levels of a cache memory subsystem. A memory array (or arrays) utilizes memory bit cells arranged in multiple rows and multiple columns.

[0008] Prior to a reset operation, the access circuitry of the memory array generates a power supply reference voltage level of the array on the power supply connections used by the memory bitcells of any of the multiple columns. In various embodiments, the p-type devices (transistors) of the back-to-back inverters of the SRAM bitcells receive the power supply reference voltage level. However, when the access circuitry receives an indication of a reset operation, the access circuitry generates a voltage level on the power supply connections that is less than the threshold voltage of the transistors used in the memory bitcells. Thus, the p-type devices are turned off and do not contend with the write drivers during a write operation. In some embodiments, the access circuitry generates a ground reference voltage level on the power connections.

[0009] The access circuit also generates a reset value on the write data lines. In one embodiment, the reset data value indicates an invalid cache line. Once the power connections are updated and write data is provided to the write bit lines, the access circuit asserts each of the write word lines of the memory array. Thus, for a particular column of the memory array, each of the multiple rows have simultaneously stored data updated to the reset value on the write data lines. In some embodiments, the access circuit simultaneously asserts each of the write word lines corresponding to each of the multiple rows of the memory array. In another embodiment, the access circuit asserts the multiple write word lines in a staggered manner to reduce voltage droop caused by simultaneous switching of the wide bus. Similarly, if the memory array uses multiple column select lines, in one embodiment the access circuit simultaneously asserts the multiple column select lines. In another embodiment, the access circuit asserts the multiple column select lines in a staggered manner.

[0010] When the write word line and any column select lines are asserted, a write operation is initiated by the pass gates and n-type devices in the SRAM bitcell. However, the write operation is not completed while the p-type devices remain disabled. The power supply voltage level of the bitcell returns from a reset value, which is below the device threshold voltage level, to an operating value above the device threshold voltage level. The write operation can be completed without the p-type devices having to contend with the write drivers of the access circuitry. Thus, both the latency and power consumption of the write operation during reset are reduced. Once the write operation is completed and the reset operation is finished, the access circuitry reverses the above steps to prepare the memory array for an access request generated from the processing unit.

[0011] Referring to FIG. 1, a generalized diagram of a memory bitcell 100 is shown. As shown, data storage is provided by the memory bitcell 100 using a variation of a six-transistor (6T) static random access memory (SRAM) cell. In other embodiments, other RAM cells of various types are used. In various embodiments, the memory bitcell 100 is copied multiple times and arranged in an array of rows and columns for memory. The memory also includes access circuitry that is not shown here for ease of explanation. However, further explanation of the access circuitry is provided in the discussion directed to the access circuitry 300 (of FIG. 3) and the memory bank 600 (of FIG. 6). The access circuitry uses several components to generate voltage levels on the word lines 114, the data lines 116 and 118, and the power supply voltage reference VDD 140. Examples of these components are row decoders, column decoders, sense amplifiers, and latches for storing read and write data.

[0012] The memory bitcell 100 utilizes both p-type and n-type MOSFETs (metal oxide semiconductor field effect transistors). As used herein, MOSFETs are also referred to as transistors and devices. The terms "transistor" and "device" are used interchangeably in the following description. An n-type transistor or device is an NMOSFET. Similarly, a p-type transistor or device is a PMOSFET. As used herein, a Boolean logic high level is also referred to as a logic high level. Similarly, a Boolean logic low level is also referred to as a logic low level. In various embodiments, a logic high level is equal to a power supply reference level and a logic low level is equal to a ground reference level. As used herein, a circuit node or line is "asserted" when the node or line stores a voltage level that enables a transistor to receive the voltage level or indicates that the operation is enabled. For example, an n-type transistor is enabled when the n-type transistor receives a positive non-zero voltage level on its gate terminal that is at least a threshold voltage above the voltage level on its source terminal.

[0013] As used herein, a circuit node or line is "negated" when the node or line stores a voltage level that disables a transistor that receives that voltage level. An n-type transistor is disabled when it receives a voltage level on its gate terminal that is a threshold voltage below the voltage level on its source terminal. Similarly, a p-type transistor is enabled when it receives a voltage level on its gate terminal that is at least a threshold voltage below the voltage level on its source terminal. A p-type transistor is negated when it receives a voltage level on its gate terminal that is at least a threshold voltage above the voltage level on its source terminal.

[0014] Memory bitcell 100 (or bitcell 100) uses a latch element implemented with p-type transistors 102-104 and n-type transistors 106-108. Bitcell 100 also uses pass gates implemented with n-type transistors 110 and 112. When pass gates 110 and 112 are enabled by word line input 114, the latch element accesses data bit lines 116 and 118. Transistors 102-108 of the latch element consume no power other than leakage current power when they resolve voltage levels (data values) on their drain terminals, output nodes 120 and 122.

[0015] Data stored by the transistors 102-108 of the latch element are gated from the bit lines 116 and 118 by n-type transistors 110 and 112. The n-type transistors 110 and 112 continue to block the stored data from the bit lines 116 and 118 until the word line input 114 is enabled by an external access circuit, which also precharges the bit lines 116 and 118. The transistors 102-108 of the latch element amplify any voltage difference detected between the differential voltages on the bit lines 116 and 118 and resolve these voltages into full swing voltage values. The bit lines 116 and 118 are routed throughout their respective columns of the array. In some embodiments, the bit lines 116 and 118 are also inputs to a sense amplifier (not shown) and a read latch (not shown). In other embodiments, the bit lines 116 and 118 are inputs to dynamic logic.

[0016] A word line 114 is used to enable n-type transistors 110 and 112 (pass gates 110 and 112). Word line 114 is also connected to other 6T RAM cells of other bit cells in a corresponding row of the array. Typically, a row decoder (not shown) asserts a single word line of the multiple word lines at a time. For example, the row decoder receives address information that is used to identify a single row of the multiple rows of the array. Once identified, the row decoder asserts the corresponding single word line of the multiple word lines. If the address information indicates that word line 114 is the selected word line to be asserted, then n-type transistors 110 and 112 of each 6T RAM cell in the row are enabled, providing access to bit lines 116 and 118 for transistors 102-108 of the latch elements. However, during a reset operation, multiple word lines are asserted simultaneously. Further details of the reset operation are provided briefly below.

[0017] For a read access operation, the external sense amplifier is enabled, the external read latch is enabled, and the external precharge transistor is disabled. Thus, the latch element transistors 102-108 can resolve the differential voltage on the bit lines 116 and 118 to a full voltage swing value. For a write access operation, the column decoder selects a column of the array and drives a voltage level on the bit lines 116 and 118 routed across the selected column in addition to disabling the external precharge signal. Although the memory bitcell 100 is shown as a single-port cell, in other embodiments, the memory bitcell 100 uses a multi-port design to provide parallel access operations for improved performance.

[0018] There are various reasons for resetting a memory array that uses bitcell 100. In some designs, the memory array is a tag array for any of the multiple levels of cache in a cache memory subsystem. Examples of reasons for performing a reset include invalidating the cache during a transition from a sleep state to an active state, invalidating the cache to push new content to a client, invalidating the cache to change the cache size, etc. Prior to the reset operation, the external access circuit generates a power supply reference voltage VDD 140 as a positive non-zero voltage level greater than a transistor threshold voltage level. In various embodiments, each bitcell in at least one of the multiple columns of the array shares VDD 140. Bitcell 100 is included in this column. However, when the access circuit receives an indication of a reset operation, the access circuit generates a voltage level on VDD 140 that is less than the transistor threshold voltage level. In some embodiments, the access circuit generates a ground reference voltage level, such as VSS 130, on VDD 140. Thus, p-type devices 102 and 104 are disabled. By being disabled, p-type devices 102 and 104 do not contend with external write drivers during subsequent write operations. In various embodiments, each bitcell in at least one of the multiple columns that includes bitcell 100 has a similar p-type device that is disabled.

[0019] When the access circuit provides a voltage level on VDD 140 that turns off p-type devices 102 and 104 and additionally provides write data on bit lines 116 and 118, the access circuit asserts word line 114 along with each of the other word lines of the multiple rows of the memory array. When each of the write word lines of the memory array, such as word line 114, is asserted, a write operation begins. For example, pass gates 110 and 112 of bit cell 10 are enabled. Although the write operation has begun, it will not complete while p-type devices 102 and 104 remain disabled. The access circuit later returns VDD 140 to a voltage level above the transistor threshold voltage from a voltage level below the transistor threshold voltage. The write operation can be completed without p-type devices 102 and 104 contending with the external write driver of the access circuit. In various embodiments, each bit cell of at least one of the multiple columns that includes bit cell 100 simultaneously completes the write operation without contention from the p-type devices. Thus, both the latency and power consumption of the write operation during reset are reduced. Once the write operation is completed and the reset operation is finished, the access circuitry reverses the steps above to prepare the memory array for access requests generated from the processing units.

[0020] Referring to Figure 2, a generalized diagram of a method 200 for efficiently resetting data stored in a memory array is shown. For purposes of explanation, the steps in this embodiment (as well as in Figures 4-5 and 7) are shown in order. However, in other embodiments, some steps may occur in a different order than that shown, some steps may be performed simultaneously, some steps may be combined with other steps, and some steps may not be present.

[0021] An array of memory bitcells stores data, with the array arranged as a number of rows and columns (block 202). In various embodiments, the value of the stored data is maintained by a data storage loop within the memory bitcell. Furthermore, the value of the stored data is updated by a write operation. In some embodiments, the memory bitcell includes pass gates and feedback inverters (and feedback tri-state inverters) to implement the data storage loop and enable updating of the stored value during a write operation. For example, each bitcell uses a variant of a six-transistor (6T) static random access memory (SRAM) cell. In some embodiments, the memory bitcell uses the pass gates and feedback inverters of memory bitcell 100 (of FIG. 1).

[0022] If the memory array access circuit (or access circuitry) determines that a reset request has not been received (conditional block 204: "NO"), control flow of method 200 returns to block 202 where the array continues to store data. However, if the access circuitry determines that a reset request has been received (conditional block 204: "YES"), the access circuitry generates a voltage level that is less than the threshold voltage of the transistor on the power supply connection used by the memory bitcells of a column of the array (block 206). By doing so, the p-type devices in the bitcells are disabled.

[0023] The access circuit generates reset data on the write data lines (block 208). In one embodiment, the reset data includes an invalid bit that is used to invalidate the cache line. The access circuit then asserts the write word lines of each row of the array (block 210). Typically, the access circuit asserts a single write word line during a write operation and continues to provide a voltage level greater than the transistor threshold voltage level on the power connections of the bitcells. However, for a reset operation, the access circuit asserts each write word line during the write operation and provides a voltage level less than the transistor threshold voltage level on the power connections of the bitcells.

[0024] A write operation begins when each of the write word lines of the memory array is asserted. For example, the pass gates of each bitcell in a particular column are enabled. Once the write operation is initiated, it will not complete while the p-type devices of the bitcells remain disabled. The access circuitry later changes the voltage levels on the power connections of the bitcells back from a voltage level below the transistor threshold voltage to a voltage level above the transistor threshold voltage (block 212). The write operation can be completed without the p-type devices of the bitcells having to contend with the external write drivers of the access circuitry. Thus, both the latency and power consumption of the write operation during reset are reduced. Once the write operation is completed and the reset operation is finished, the access circuitry reverses the above steps to prepare the memory array for an access request generated from the processing unit. For example, the access circuitry negates the write word lines of each row of the array (block 214).

[0025] 3, a generalized block diagram of a memory array access circuit 300 is shown. As shown, memory array access circuit 300 (or access circuit 300) includes a word line decoder 310 and a number of Boolean composite gates 320, 340, 360-362. In some embodiments, the entire external memory array uses the output signal of access circuit 300. In other embodiments, the memory is divided into multiple memory banks, and specific memory banks use the output signal of access circuit 300.

[0026] The access circuit receives an asserted value on a control signal collapse 330 when a reset operation is occurring. In one embodiment, the collapse signal 330 is used to generate a voltage level below the transistor threshold voltage used by the p-type devices of the memory bitcells. In some embodiments, this voltage level is a ground reference voltage level. For example, in one embodiment, when a reset operation begins, the collapse signal 330 is asserted at a Boolean high value and an inverter 380 generates a local VDD signal 382 as a Boolean low value. The local VDD signal 382 is communicated to the p-type devices of each memory bitcell in a particular column of the memory array.

[0027] The word line decoder 310 receives word line pre-decode signals 302-304. The number of signals 302-304 is equal to the number of rows in the memory array or memory bank using the access circuit 300. During a typical write operation, a write request address is used to determine which of the rows of the memory array (or memory bank) is selected. One of the word line pre-decode signals 302-304 is asserted based on the write request address. The word line decoder 310 also receives a word line (WL) clock signal 326 that is generated by a Boolean composite gate 320 (or gate 320).

[0028] Gate 320 receives a clock signal 322 and an enable signal. In some embodiments, enable signal 324 indicates that a particular memory bank is being written. Gate 320 also receives a collapse signal 330. Thus, based on gate 320 and its Boolean OR function, collapse signal 330 overrides clock signal 332 and enable signal 324 during a reset operation. In one embodiment, during a reset operation, an external pre-decoder asserts each of the wordline pre-decode signals 302-304. Thus, collapse signal 330 asserts WL clock signal 326, which causes each of the wordlines 312-314 to be asserted. In another embodiment, wordline decoder 310 receives collapse signal 330 directly, such that when collapse signal 330 is asserted, wordline decoder 310 asserts each of the wordlines 312-314.

[0029] Boolean composite gate 340 (or gate 340) and inverter 344 generate a BLPCX signal 350 that is used as a bitline precharge signal by the p-type devices of the memory array. These external p-type devices perform precharge operations on the bitlines of a particular column of the memory array. Gate 340 receives a bitline precharge signal 342 from a previous stage of control circuitry that determines when to enable and disable precharge for write operations. However, the Boolean logic of gate 340 allows collapse signal 330 to override this bitline precharge signal 342. When collapse signal 330 is asserted at a Boolean logic high level, inverter 344 generates the BLPCX 350 signal as a Boolean high level, which disables the p-type devices of the bitline precharge circuitry of the particular column of the memory array.

[0030] The Boolean composite gates 360-362 are copies of the same composite gate. The access circuit 300 includes as many Boolean composite gates 360-362 (or composite gates 360-362) as there are columns used for the same type of data stored in the memory array. For example, instead of using 1024 rows, the memory array uses 256 rows where the data is arranged horizontally such that 4 columns are used. Thus, 4 column select lines are used. Such an arrangement reduces the capacitive load on the bit lines. Furthermore, multiple columns of the memory array can share a single write driver and a single sense amplifier of the memory array.

[0031] In one embodiment, composite gate 360 ​​receives clock signal 322, enable signal 324, write enable signal 352, and write column decode signal 354, which is the output of a decoder that selects which of multiple columns are being updated. Gate 362 receives the same input signals. However, during a reset operation, an asserted collapse signal 330 causes each of gates 360-362 to bypass these other input signals and generate asserted values ​​for output signals WRCS 370-372. These output signals WRCS 370-372 are used as write column select lines by the external memory array.

[0032] Referring now to FIG. 4, a generalized diagram of a method 400 for efficiently resetting data stored in a memory array is shown. An access circuit initiates a reset of an array of memory bit cells arranged as a number of rows and a number of columns (block 402). The access circuit asserts the write word lines of each row of a first portion of the number of rows in a first clock cycle (block 404). In various embodiments, the access circuit has already performed the steps previously described directed to blocks 206 and 208 of method 200 (of FIG. 2). For example, the access circuit has already reduced the voltage level received by the p-type devices of the bit cells of a particular column of the memory array. For example, the access circuit has reduced this voltage level below a transistor threshold voltage level. Additionally, the access circuit has already generated reset data on the write bit lines.

[0033] The access circuit asserts the write word lines of each row of the second portion of the plurality of rows in a second clock cycle after the first clock cycle (block 406). Thus, the access circuit asserts the write word lines in a stepped manner to reduce voltage droop caused by simultaneous switching of the wide bus. The voltage droop is proportional to the equation L di / dt, where L is the parasitic inductance and di / dt is the time rate of change of current consumption. In one embodiment, the access circuit divides the memory array into two portions and asserts half of the total number of word lines in a first clock cycle and asserts the other half of the total number of word lines in a second clock cycle. In such an embodiment, the access circuit uses two clock cycles to assert each of the word lines of the memory array during a reset operation. The access circuit writes the reset data to each memory bit cell of the column (block 408). For example, the access circuit performs the previously described steps directed to blocks 210-214 of method 200 (of FIG. 2).

[0034] In another embodiment, the access circuit asserts one-quarter of the total number of word lines in a first clock cycle and another one-quarter of the total number of word lines in a second clock cycle. In such an embodiment, the access circuit uses four clock cycles to assert each of the word lines of the memory array during a reset operation. However, using a conventional mechanism for performing a reset operation, the access circuit updates a single row per clock cycle. For example, the conventional mechanism did not reduce the power supply voltage used by the p-type devices of the bit cells. Thus, the p-type devices compete with the write driver during a write operation during reset. Updating multiple rows simultaneously significantly increases the size of the write driver of the access circuit. Thus, there is a cost associated with increased power consumption and increased on-die area. Thus, the conventional mechanism updated one row per clock cycle. For a memory array with 1024 entries, the reset operation requires 1024 clock cycles. However, using at least the steps described in methods 200 and 400 (of FIGS. 200 and 400), the reset operation requires only 2, 4, or 8 clock cycles. The latency and on-die area of ​​components such as write drivers are reduced, respectively.

[0035] Referring now to FIG. 5, a generalized diagram of a method 500 for efficiently resetting data stored in a plurality of memory bitcells in a column of a memory array is shown. An access circuit initiates a reset of an array of memory bitcells arranged as a plurality of rows and a plurality of columns (block 502). The access circuit asserts two or more column select lines (block 504). As previously described, in some designs, instead of using 1024 rows, the memory array uses 256 rows in which the data is arranged horizontally such that four columns are used. Thus, four column select lines are used. Such an arrangement reduces the capacitive load on the bitlines. Additionally, multiple columns of the memory array can share a single write driver and a single sense amplifier of the memory array. In such designs, typically, a single column select line is asserted during a write operation. However, here, two or more select lines are asserted during a reset operation. In some embodiments, each of the multiple column select lines is asserted.

[0036] The access circuitry disables precharge of the write bitlines of two or more of the multiple columns (block 506). Additionally, the access circuitry disables precharge of the bitlines of two or more columns corresponding to the complements of the write bitlines of the two or more columns. Typically, a single bitline of a single column and its single corresponding complementary bitline have their precharge circuits disabled during a write operation to place write data on these two bitlines of the single column. However, here, the bitlines of the two or more columns have corresponding precharge circuits disabled during a reset operation to place write data on these bitlines of the two or more columns. In some embodiments, the two or more columns include each column of the multiple columns. The access circuitry writes reset data to each memory bitcell of the two or more columns with the corresponding column select asserted (block 508). In various embodiments, the access circuitry performs the steps described above directed to blocks 210-214 of method 200 (of FIG. 2) for two or more of the multiple columns.

[0037] Referring now to FIG. 6, a generalized block diagram of a memory bank 600 is shown. In various embodiments, the memory is organized as multiple memory banks, and a memory macroblock includes both a left bank and a right bank. In some embodiments, the bank 600 is either the left bank or the right bank of the memory macroblock. Although "left" and "right" are used to describe the memory banks, other notations such as "upper bank" and "lower bank" may be used. As shown, the memory bank 600 includes arrays 610A-610B, row decoders 620A-620B, sense amplifiers 630A-630B between the arrays 610A-610B, read and write timing control logic 640A-640B, and read and write latches in block 650. It should be noted that in some embodiments, multiple banks are accessed simultaneously in the same clock cycle or in the same pipeline stage. The access includes one of a read access and a write access. In such an embodiment, a bank address decoder selects the corresponding bank to be accessed.

[0038] In various embodiments, each of the blocks 610A-610B, 620A-620B, 630A-630B, 640A-640B, 650 in the memory bank 600 is communicatively coupled to another one of the blocks. For example, a direct connection is used where the routing is via another block. Alternatively, signal staging is performed in an intermediate block. In various embodiments, each of the arrays 610A-610B includes a number of memory bit cells 660 arranged in a tiled format. In various embodiments, the bit cells 660 include circuitry of the bit cells 100 (of FIG. 1), where the rows are aligned, such as vertically in the illustrated embodiment, with tracks used for routing the word lines of the array, and the columns are aligned, such as horizontally in the illustrated embodiment, with tracks used for routing the bit lines of the array.

[0039] The row decoders and word line drivers in blocks 620A-620B receive address information corresponding to an access request. For example, each of blocks 620A-620B receives information provided by access request address 670. Each of blocks 620A-620B selects a particular row or entry among multiple rows in an associated one of arrays 620A-620B. In some embodiments, blocks 620A-620B use an index portion of address 670 to select a given row or entry in an associated one of arrays 620A-620B. Each row or entry stores one or more memory lines.

[0040] In the illustrated embodiment, the rows or entries in arrays 620A-620B are arranged vertically. However, in other embodiments, a horizontal orientation is used for memory line storage. For a write access request, write latches are located in block 650. Write data is driven into arrays 610A-610B. Timing control circuits 640A-640B update the write latches with new data and set up write word line driver logic in block 650. The write data is written into the row of bit cells selected by the associated one of blocks 620A-620B. In some embodiments, precharge circuitry is included in block 650.

[0041] For a read access request, block 650 is used to precharge the read bit lines routed to arrays 610A-610B. Timing circuits in blocks 640A-640B are used to precharge and set up the sense amplifiers in blocks 630A-630B. Timing circuits 640A-640B set up the read word line driver logic. One of row decoders 620A-620B selects the row from which data is read, and this data is provided on the read bit lines to be sensed by the sense amplifiers. A read latch captures the read data.

[0042] In various embodiments, the row decoders and word line drivers 620A-620B and column select control circuits in any of blocks 630A-630B and 650 utilize the functionality of the access circuit 300 (of FIG. 3) and perform the steps described above with respect to the bit cell 100 (of FIG. 1) and the access circuit 300 (of FIG. 3). In other words, the access circuit shown surrounding the arrays 610A-610B utilizes a collapse control signal that is asserted during a reset operation. Thus, the access circuit shown surrounding the arrays 610A-610B can generate and send a power supply voltage level below the transistor threshold voltage to the power connection of each bit cell in a particular column. Additionally, the access circuit shown surrounding the arrays 610A-610B can assert each of the word lines during a reset operation. Furthermore, this access circuit of the memory bank 600 can assert multiple word lines in groups over multiple clock cycles. Therefore, this access circuitry of memory bank 600 completes the reset operation without the p-type devices of the bitcells having to contend with the write drivers, reducing power consumption and reducing the on-die area of ​​the word drivers.

[0043] 7, a generalized diagram of a method 700 for efficiently resetting data stored in a memory array is shown. An access circuit performs a reset of an array of memory bit cells arranged as a number of rows and a number of columns (block 702). If the access circuit determines that the requested write reset operation is not yet complete (conditional block 704: "NO"), control flow of the method 700 returns to block 702 where the reset operation continues. However, if the access circuit determines that the requested write reset operation is complete (conditional block 704: "YES"), the access circuit negates the write word lines of each row of a first portion of the number of rows in a first clock cycle (block 706).

[0044] The access circuit negates the write word lines of each row of a second portion of the plurality of rows in a second clock cycle after the first clock cycle (block 708). The access circuit negates the column select lines of two or more columns of the plurality of columns (block 710). The access circuit enables precharge of the write bit lines of two or more columns of the plurality of columns (block 712).

[0045] Referring to FIG. 8, one embodiment of a computing system 800 is shown. The computing system 800 includes a processor 810 and a memory 830. Interfaces such as a memory controller, a bus or communication fabric, one or more phased locked loops (PLLs) and other clock generation circuits, a power management unit, etc. are not shown for ease of illustration. It is understood that in other embodiments, the computing system 800 includes one or more of other processors of the same or different type as the processor 810, one or more peripheral devices, a network interface, one or more other memory devices, etc. In some embodiments, the functionality of the computing system 800 is integrated on a system on chip (SoC). In other embodiments, the functionality of the computing system 800 is integrated on a peripheral card inserted into a motherboard. The computing system 800 may be used in any of a variety of computing devices, such as a server computer, a desktop computer, a tablet computer, a laptop, a smartphone, a smartwatch, a game console, a personal assistant device, etc.

[0046] The processor 810 includes hardware such as circuits. For example, the processor 810 includes at least one integrated circuit 820 that utilizes a fast reset array 822. The integrated circuit 820 uses the fast reset array 822 for data storage of various types of data. In various embodiments, the fast reset array 822 uses memory bit cells arranged in multiple rows and columns. One or more of the processor 810 and the integrated circuit 820 use the fast reset array as a cache at a particular one of multiple levels of a cache memory subsystem. In some embodiments, the fast reset array 822 uses one or more of the circuits described above for the bit cells 100 (of FIG. 1), the access circuits 300 (of FIG. 3), and the memory bank 600 (of FIG. 6).

[0047] In various embodiments, the processor 810 includes one or more processing units. In some embodiments, each of the processing units includes one or more processor cores capable of general-purpose data processing and an associated cache memory subsystem. In such embodiments, the processor 810 is a central processing unit (CPU). In another embodiment, the processing cores are computational units, each of which has a highly parallel data micro-architecture with multiple parallel execution lanes and associated data storage buffers. In such embodiments, the processor 810 is a graphics processing unit (GPU), a digital signal processor (DSP), or the like.

[0048] In some embodiments, memory 830 includes one or more of a hard disk drive, a solid state disk, other types of flash memory, a portable solid state drive, a tape drive, and the like. Memory 830 stores an operating system (OS) 832, one or more applications represented by code 834, and at least source data 836. Memory 830 may also store intermediate and final result data generated by processor 810 when executing a particular application of code 834. Although a single operating system 832 and a single instance of code 834 and source data 836 are shown, in other embodiments, another number of these software components are stored in memory 830. Operating system 832 includes instructions for initiating the boot-up of processor 810, allocating tasks to hardware circuitry, managing resources of computing system 800, and hosting one or more virtual environments.

[0049] Each of the processor 810 and memory 830, as well as any other hardware components included in the computing system 800, includes an interface unit for communicating with each other. The interface units include queues for handling memory requests and responses, and control circuitry for communicating with each other based on a particular communication protocol. The communication protocol determines various parameters such as a power performance state that determines a supply voltage level, an operating supply voltage and an operating clock frequency, a data rate, one or more burst modes, etc.

[0050] It should be noted that one or more of the embodiments described above include software. In such embodiments, program instructions implementing the methods and / or mechanisms are carried or stored on a computer readable medium. Numerous types of media configured to store program instructions are available, including volatile or non-volatile storage in the form of hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROM (PROM), random access memory (RAM), and the like. Generally speaking, computer accessible storage media includes any storage media that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, computer accessible storage media can include magnetic or optical media, such as disks (fixed or removable), tapes, CD-ROMs, or storage media such as DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-Rays. The storage medium further includes volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (Rambus DRAM, RDRAM), static RAM (SRAM), etc.), ROM, flash memory, non-volatile memory (e.g., flash memory) accessible via a peripheral interface such as a Universal Serial Bus (USB) interface, etc. The storage medium includes a microelectromechanical system (MEMS), as well as storage media accessible via a communication medium such as a network and / or wireless link.

[0051] Additionally, in various embodiments, the program instructions include a behavioral or register-transfer level (RTL) description of the hardware functionality in a high-level programming language such as C, or a design language (HDL) such as Verilog, VHDL, or a database format such as GDSII stream format (GDS II). In some cases, the description is read by a synthesis tool that synthesizes the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware that comprises the system. The netlist can then be placed and routed to generate a data set that describes the geometry that is applied to a mask. The mask can then be used in various semiconductor manufacturing steps to generate a semiconductor circuit or circuits that correspond to the system. Alternatively, the instructions on the computer-accessible storage medium are a netlist (with or without a synthesis library) or a data set, as appropriate. Additionally, the instructions are utilized for emulation by hardware-based type emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0052] Although the above embodiments have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated, and it is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. 1. An integrated circuit comprising: an array of memory bit cells arranged in a plurality of rows and a plurality of columns for storing data; access circuitry; The access circuitry includes: generating a power supply reference voltage level for the array on a power supply connection used by memory bitcells of one or more of the plurality of columns; In response to receiving a reset request, generating a predetermined voltage level on the power supply connection that is less than a threshold voltage of a transistor used in the memory bitcell; asserting a write word line for each row of the plurality of rows; [0023] Integrated circuits.

2. the predetermined voltage level is a ground reference voltage level; 2. The integrated circuit of claim 1.

3. The access circuitry includes: asserting the word line of each row of a first portion of the plurality of rows during a first clock cycle; asserting the word line of each row of a second portion of the plurality of rows at a second clock cycle after the first clock cycle; [0023] 2. The integrated circuit of claim 1.

4. the access circuitry is configured to assert column select lines for two or more columns of the plurality of columns; 2. The integrated circuit of claim 1.

5. In response to determining that the write bit line stores reset data, the access circuit: configured to generate the power supply reference voltage level for the array on the power supply connections used by memory bitcells of the one or more columns of the plurality of columns.

2. The integrated circuit of claim 1.

6. the access circuit is configured to negate the write word line of each of the plurality of rows in response to determining that a write operation is completed.

6. The integrated circuit of claim 5.

7. The access circuitry includes: negating the word line of each row of a first portion of the plurality of rows during a third clock cycle; configured to negate the word line of each row of a second portion of the plurality of rows at a fourth clock cycle after the third clock cycle; 7. The integrated circuit of claim 6.

8. 1. A method comprising: storing data in an array of memory bit cells arranged as a plurality of rows and a plurality of columns; access circuitry of the array generating a power supply reference voltage level for the array on a power supply connection used by memory bitcells of one or more of the plurality of columns; In response to receiving a reset request, the access circuitry generating on the power supply connection a predetermined voltage level that is less than a threshold voltage of a transistor used in the memory bitcell; the access circuit asserting a write word line for each row of the plurality of rows. method.

9. the predetermined voltage level is a ground reference voltage level; 9. The method of claim 8.

10. asserting a write word line for each row of the plurality of rows; the access circuit asserting the word line of each row of a first portion of the plurality of rows during a first clock cycle; the access circuit asserting the word line of each row of a second portion of the plurality of rows at a second clock cycle after the first clock cycle.

9. The method of claim 8.

11. the access circuit asserting column select lines for two or more of the plurality of columns; 9. The method of claim 8.

12. In response to determining that the write bit line stores reset data, the access circuitry generating the power supply reference voltage level of the array on the power supply connections used by memory bitcells of the one or more columns of the plurality of columns.

9. The method of claim 8.

13. negating the write word line of each of the plurality of rows in response to the access circuit determining that a write operation is completed.

13. The method of claim 12.

14. negating the write word line of each of the plurality of rows; the access circuit negating the word line of each row of a first portion of the plurality of rows during a third clock cycle; the access circuit negating the word line of each row of a second portion of the plurality of rows in a fourth clock cycle after the third clock cycle.

14. The method of claim 13.

15. 1. A computing system comprising: a memory configured to store instructions for one or more tasks and source data to be processed by said one or more tasks; an integrated circuit configured to execute the instructions using the source data; The integrated circuit comprises: An access circuit; an array of memory bit cells arranged in a plurality of rows and a plurality of columns for storing data; The access circuitry includes: generating a power supply reference voltage level for the array on a power supply connection used by memory bitcells of one or more of the plurality of columns; In response to receiving a reset request, generating a predetermined voltage level on the power supply connection that is less than a threshold voltage of a transistor used in the memory bitcell; asserting a write word line for each row of the plurality of rows; [0023] Computing system.

16. the predetermined voltage level is a ground reference voltage level; 16. The computing system of claim 15.

17. The access circuitry includes: asserting the word line of each row of a first portion of the plurality of rows during a first clock cycle; asserting the word line of each row of a second portion of the plurality of rows at a second clock cycle after the first clock cycle; [0023] 16. The computing system of claim 15.

18. the access circuitry is configured to assert column select lines for two or more columns of the plurality of columns; 16. The computing system of claim 15.

19. In response to determining that the write bit line stores reset data, the access circuit: configured to generate the power supply reference voltage level for the array on the power supply connections used by memory bitcells of the one or more columns of the plurality of columns.

16. The computing system of claim 15.

20. the access circuit is configured to negate the write word line of each of the plurality of rows in response to determining that a write operation is completed.

20. The computing system of claim 19.

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