PACKAGE HAVING SUBSTRATE HAVING COUPLING ELEMENTS FOR INTEGRATED DEVICES - Patent application

Abstract

A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes a dielectric layer and a plurality of interconnects. The plurality of interconnects includes a first plurality of interconnects configured as a first inductor and a second plurality of interconnects configured as a second inductor. The first integrated device is configured to be coupled to the first inductor. The second integrated device is configured to be coupled to the second inductor. The second integrated device is configured to tune the first inductor via the second inductor.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 575,492, filed in the United States Patent Office on January 13, 2022, the entire contents of which are incorporated by reference into this specification as if fully set forth below in their entirety, and for all applicable purposes.

[0002] Various aspects relate to a package having a substrate and an integrated device. [Background technology]

[0003]

[0003] A package may include a substrate and an integrated device. These components are coupled together to provide a package capable of performing various electrical functions. There is a continuing need to provide better performing packages and to reduce the overall size of the package. Summary of the Invention

[0004] Various features relate to a package having a substrate and an integrated device.

[0005]

[0005] One embodiment provides a package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes a dielectric layer and a plurality of interconnects. The plurality of interconnects includes a first plurality of interconnects configured as a first inductor and a second plurality of interconnects configured as a second inductor. The first integrated device is configured to be coupled to the first inductor. The second integrated device is configured to be coupled to the second inductor. The second integrated device is configured to tune the first inductor via the second inductor.

[0006]

[0006] Another embodiment provides a package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes a means for a first inductance and a means for a second inductance. The first integrated device is configured to be coupled to the means for the first inductance. The second integrated device is configured to be coupled to the means for the second inductance. The second integrated device is configured to tune the means for the first inductance via the means for the second inductance. [Brief description of the drawings]

[0007]

[0007] Various features, properties, and advantages may become apparent from reading the detailed description set forth below in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Figure 1]

[0008] 1 illustrates an exemplary cross-sectional profile view of a package including a substrate with bonding elements. [Diagram 2]

[0009] 1 illustrates an exemplary cross-sectional profile view of a package including a substrate with several bonding elements. [Diagram 3]

[0010] 1 illustrates an exemplary cross-sectional profile view of a package including a substrate with several bonding elements. [Figure 4]

[0011] 1 illustrates an exemplary cross-sectional profile view of a package including a substrate with a bonding element. [Diagram 5]

[0012] 1 illustrates an exemplary cross-sectional profile view of a package including a substrate with several bonding elements. [Figure 6]

[0013] 1 illustrates an exemplary cross-sectional profile view of a package including a substrate with bonding elements. [Figure 7]

[0014] 1 illustrates an exemplary cross-sectional profile view of a package including a substrate with several bonding elements. [Figure 8]

[0015] 1 illustrates an exemplary cross-sectional profile view of a package including a substrate with several bonding elements. [Figure 9A]

[0016] 1 illustrates an exemplary sequence for manufacturing a package that includes a substrate with several bonding elements. [Figure 9B] 1 illustrates an exemplary sequence for manufacturing a package that includes a substrate with several bonding elements. [Figure 10]

[0017] 1 shows an exemplary flow chart of a method for manufacturing a package including a substrate with at least one bonding element. [Figure 11A]

[0018] 1 illustrates an exemplary sequence for manufacturing a substrate including at least one bonding element. [Figure 11B] 1 illustrates an exemplary sequence for manufacturing a substrate including at least one bonding element. [Figure 12]

[0019] 1 shows an exemplary flow chart of a method for manufacturing a substrate including at least one bonding element. [Figure 13]

[0020] Various electronic devices are illustrated that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008]

[0021] In the following description, specific details are described to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0009]

[0022] The present disclosure describes a package including a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects. The plurality of interconnects includes a first plurality of interconnects configured as a first inductor and a second plurality of interconnects configured as a second inductor. The first integrated device is configured to be coupled (e.g., electrically coupled) to the first inductor. The second integrated device is configured to be coupled (e.g., electrically coupled) to the second inductor. The second integrated device is configured to tune the first inductor via the second inductor. The first inductor and the second inductor may be part of a coupling element disposed in the substrate. The coupling element may be an inductive coupling element. The substrate may include several coupling elements, each including two or more inductors. The second integrated device may be configured to tune several inductors for several different integrated devices in real time. As described further below, the coupling element(s) help provide real-time tuning of one or more inductors for integrated devices configured for radio frequency (RF) functions (e.g., processing RF signals, receiving and / or transmitting RF signals), which helps provide improved package performance while keeping the package small and thin.

[0010] Exemplary Package Comprising a Substrate Having a Coupling Element Comprising a First Inductor and a Second Inductor

[0023] 1 shows a cross-sectional profile view of a package 100 including a substrate having a coupling element including a first inductor and a second inductor. The package 100 is coupled to a board 106 via a plurality of solder interconnects 110. The board 106 includes at least one board dielectric layer 160 and a plurality of board interconnects 162. The board 106 may include a printed circuit board (PCB).

[0011]

[0024] The package 100 includes a substrate 102, an integrated device 105 (e.g., a first integrated device), and an integrated device 107 (e.g., a second integrated device). The integrated device 105 is coupled to a first surface (e.g., a top surface) of the substrate 102 via a plurality of solder interconnects 150. The integrated device 107 is coupled to a second surface (e.g., a bottom surface) of the substrate 102 via a plurality of solder interconnects 170. The integrated device 107 may include a controller die. The integrated device 107 may include a controller for controlling an inductance of an inductor coupled to the integrated device 105. The integrated device 105 may be configured for radio frequency (RF) functions (e.g., processing RF signals, receiving and / or transmitting RF signals).

[0012]

[0025] The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a solder resist layer 124 and a solder resist layer 126. The substrate 102 may include at least one coupling element 104. The coupling element 104 may be an inductive coupling element (e.g., a means for inductive coupling). The coupling element 104 may include a first inductor 140 and a second inductor 142. The first inductor 140 may be a means for a first inductance. The second inductor 142 may be a means for a second inductance. The coupling element 104, the first inductor 140, and / or the second inductor 142 may be defined by interconnects from the plurality of interconnects 122. For example, the first inductor 140 may be defined by a first plurality of interconnects from the plurality of interconnects 122, and the second inductor 142 may be defined by a second plurality of interconnects from the plurality of interconnects 122. The first inductor 140 includes at least one winding, and the second inductor 142 includes at least one winding. The at least one winding of the first inductor 140 vertically overlaps with the at least one winding of the second inductor 142. The vertical overlap may be a partial overlap or a complete overlap of the windings. The at least one winding of the first inductor 140 may be disposed on a different metal layer(s) than the at least one winding of the second inductor 142. For example, one or more interconnects for the windings of the first inductor 140 can be disposed on a first metal layer of the substrate 102, and one or more interconnects for the windings of the second inductor 142 can be disposed on a second metal layer of the substrate 102. It should be noted that the first inductor 140 can have one or more windings (e.g., one or more first windings). Each winding of the first inductor 140 can be disposed on a different metal layer of the substrate 102. Similarly, the second inductor 142 can have one or more windings (e.g., one or more second windings). Each winding of the second inductor 142 can be disposed on a different metal layer of the substrate 102.In some implementations, the windings of the first inductor 140 can be intertwined (e.g., vertically intertwined and / or horizontally intertwined) with the windings of the second inductor 142. Examples of inductors having two or more windings and / or that are intertwined (e.g., vertically intertwined and / or horizontally intertwined) are further shown and described in Figures 6-8.

[0013]

[0026] The integrated device 105 and the integrated device 107 are each configured to be coupled to the coupling element 104. The integrated device 105, the integrated device 107, and the coupling element 104 vertically overlap each other (e.g., partially or completely vertically overlap). The integrated device 105 is configured to be coupled to the first inductor 140. The integrated device 107 is configured to be coupled to the second inductor 142. The integrated device 107 can be configured to control and / or tune the inductance of the second inductor 142 from the first inductor 140 in real time. The second inductor 142 can be configured to induce the inductance of the first inductor 140. For example, the second inductor 142 can be turned on to induce the inductance of the first inductor 140 for the integrated device 105. In some implementations, the second inductor 142 can be turned on to tune the inductance of the first inductor 140 for the integrated device 105 in real time. The ability of the integrated device 107 to tune the first inductor 140 for the integrated device 105 helps improve the performance of the integrated device 105 by better matching the inductance of the first inductor 140 to the various signals being processed, received, and / or transmitted by the integrated device 105, while still providing a thin and compact package 100. For example, one area of ​​package improvement is improving memory effects in the package.

[0014]

[0027] In one embodiment, the first inductor 140 may have a first inductance value (e.g., when the second inductor 142 is off). However, when the second inductor 142 is turned on, the first inductor 140 may have another inductance value. The second inductor 142 may be configured to induce the first inductor 140 to have a different inductance value (e.g., a second inductance value, a third inductance value, a fourth inductance value). For example, (i) in a first time period / first time point, the first inductor 140 may be induced to have a first inductance value, (ii) in a second time period / second time point, the first inductor 140 may be induced to have a second inductance value, and (ii) in a third time period / third time point, the first inductor 140 may be induced to have a third inductance value. The inductance value of the first inductor 140 may be controlled by the integrated device 107 through control of the second inductor 142. In some implementations, the integrated device 107 may control the second inductor 142 by controlling and / or specifying the inductance value of the second inductor 142. The above description of how to control the first inductor 140 and the second inductor 142 may be applicable to any of the inductors described in this disclosure.

[0015]

[0028] In some implementations, a package may include different configurations of integrated devices 105, integrated devices 107, and / or coupling elements 104.

[0016]

[0029] 2 shows a package 200 that includes a substrate having several coupling elements. Package 200 is similar to package 100 and includes similar components as package 100. Package 200 includes substrate 102, integrated device 107, integrated device 205a, integrated device 205b, and integrated device 205c.

[0017]

[0030] Integrated device 205a is coupled to a first surface (e.g., a top surface) of substrate 102 via a plurality of solder interconnects 150a. Integrated device 205b is coupled to a first surface (e.g., a top surface) of substrate 102 via a plurality of solder interconnects 150b. Integrated device 205c is coupled to a first surface (e.g., a top surface) of substrate 102 via a plurality of solder interconnects 150c. Integrated device 107 is coupled to a second surface (e.g., a bottom surface) of substrate 102 via a plurality of solder interconnects 170.

[0018]

[0031] The substrate 102 includes a coupling element 104a, a coupling element 104b, and a coupling element 104c. Each coupling element (e.g., 104a, 104b, 104c) can include a respective first inductor (e.g., 140a, 140b, 140c) and a respective second inductor (e.g., 142a, 142b, 142c) as described for the coupling element 104.

[0019]

[0032] The integrated device 107 and the integrated device 205a are each configured to be coupled to the coupling element 104a. The integrated device 205a is configured to be coupled to the first inductor 140a of the coupling element 104a. The integrated device 107 is configured to be coupled to the second inductor 142a of the coupling element 104a. The integrated device 107 and the integrated device 205b are each configured to be coupled to the coupling element 104b. The integrated device 205b is configured to be coupled to the first inductor 140b of the coupling element 104b. The integrated device 107 is configured to be coupled to the second inductor 142b of the coupling element 104b. The integrated device 107 and the integrated device 205c are each configured to be coupled to the coupling element 104c. The integrated device 205c is configured to be coupled to the first inductor 140c of the coupling element 104c. The integrated device 107 is configured to be coupled to the second inductor 142c of the coupling element 104c. It should be noted that the coupling elements and inductors can be disposed on the same and / or different metal layers of the substrate 102. The coupling elements and / or inductors can have different sizes, shapes, and / or different numbers of windings. Each of the coupling elements (e.g., 104a, 104b, 104c) can be defined by an interconnect from the multiple interconnects 122. The physical and functional characteristics described for coupling element 104 may be applicable to coupling element 104a, coupling element 104b, and / or coupling element 104c.

[0020]

[0033] The integrated device 107 can be configured to control and / or tune in real time the inductance of the first inductor 140a of the coupling element 104a via the second inductor 142a of the coupling element 104a. The integrated device 107 can be configured to control and / or tune in real time the inductance of the first inductor 140b of the coupling element 104b via the second inductor 142b of the coupling element 104b. The integrated device 107 can be configured to control and / or tune in real time the inductance of the first inductor 140c of the coupling element 104c via the second inductor 142c of the coupling element 104c. Thus, one integrated device (e.g., 107) can be configured to control and / or tune in real time the inductors and / or inductances coupled to several integrated devices (e.g., 205a, 205b, 205c). The integrated device (e.g., 107) can be configured to simultaneously and / or sequentially control and / or tune inductors and / or inductances coupled to several integrated devices (e.g., 205a, 205b, 205c) in real time. Thus, for example, the integrated device 107 can simultaneously control the inductance of the inductor of each of the integrated devices (e.g., 205a, 205b, 205c) while each of these integrated devices (e.g., 205a, 205b, 205c) is operating (e.g., while various signals are being processed, received, and / or transmitted by each of these integrated devices (e.g., 205a, 205b, 205c)). The integrated device 205a, the integrated device 205b, and / or the integrated device 205c can be similar to the integrated device 105. Each of the integrated devices (e.g., 205a, 205b, 205c) can be configured to process, receive, and / or transmit various signals. As described further below, each integrated device (eg, 205a, 205b, 205c) may be configured to process, receive, and / or transmit different signals (eg, signals at different frequencies).Integrated device 205a, integrated device 205b, and / or integrated device 205c may vertically overlap integrated device 107 (eg, partially vertically overlap, completely vertically overlap).

[0021]

[0034] The integrated device 107 may include a controller die. The integrated device 107 may include a controller for controlling the inductance of each inductor coupled to the integrated device 205a, the integrated device 205b, and / or the integrated device 205c. The integrated devices 205a, 205b, and / or 205c may each be configured for a radio frequency (RF) function (e.g., processing RF signals, receiving and / or transmitting RF signals). In some implementations, the integrated device 205a is configured to process, receive, and / or transmit RF signals in a first frequency range. In some implementations, the integrated device 205b is configured to process, receive, and / or transmit RF signals in a second frequency range. In some implementations, the integrated device 205c is configured to process, receive, and / or transmit RF signals in a third frequency range. Although FIG. 2 shows a package including three integrated devices for processing a signal, it is understood that the package may include more than three integrated devices for processing a signal and that the integrated device 107 may be configured to control the inductance of an inductor coupled to more than three integrated devices.

[0022]

[0035] 3 shows a package 300 including a substrate having several coupling elements. Package 300 is similar to package 200 and includes similar components as package 200. Package 300 includes substrate 102, integrated device 205a, integrated device 205b, integrated device 205c, integrated device 207a, integrated device 207b, and integrated device 207c.

[0023]

[0036] The integrated device 205a is coupled to a first surface (e.g., a top surface) of the substrate 102 via a plurality of solder interconnects 150a. The integrated device 205b is coupled to a first surface (e.g., a top surface) of the substrate 102 via a plurality of solder interconnects 150b. The integrated device 205c is coupled to a first surface (e.g., a top surface) of the substrate 102 via a plurality of solder interconnects 150c. The integrated device 207a is coupled to a second surface (e.g., a bottom surface) of the substrate 102 via a plurality of solder interconnects 170a. The integrated device 207b is coupled to a second surface (e.g., a bottom surface) of the substrate 102 via a plurality of solder interconnects 170b. The integrated device 207c is coupled to a second surface (e.g., a bottom surface) of the substrate 102 via a plurality of solder interconnects 170c.

[0024]

[0037] The substrate 102 includes coupling element 104a, coupling element 104b, and coupling element 104c. Each coupling element may include a first inductor (e.g., 140a, 140b, 140c) and a second inductor (e.g., 142a, 142b, 142c) as described for coupling element 104. Each of the coupling elements (e.g., 104a, 104b, 104c) may be defined by an interconnect from the plurality of interconnects 122. The physical and functional characteristics described for coupling element 104 may be applicable to coupling element 104a, coupling element 104b, and / or coupling element 104c.

[0025]

[0038] The integrated device 205a and the integrated device 207a are each configured to be coupled to the coupling element 104a. The integrated device 205a is configured to be coupled to the first inductor 140a of the coupling element 104a. The integrated device 207a is configured to be coupled to the second inductor 142a of the coupling element 104a. The integrated device 205b and the integrated device 207b are each configured to be coupled to the coupling element 104b. The integrated device 205b is configured to be coupled to the first inductor 140b of the coupling element 104b. The integrated device 207b is configured to be coupled to the second inductor 142b of the coupling element 104b. The integrated device 205c and the integrated device 207c are each configured to be coupled to the coupling element 104c. The integrated device 205c is configured to be coupled to the first inductor 140c of the coupling element 104c. The integrated device 207c is configured to be coupled to the second inductor 142c of the coupling element 104c. It should be noted that the coupling elements and inductors may be located on the same and / or different metal layers of the substrate 102. The coupling elements and / or inductors may have different sizes, shapes, and / or different numbers of windings.

[0026]

[0039] The integrated device 207a can be configured to control and / or tune in real time the inductance of the first inductor 140a of the coupling element 104a via the second inductor 142a of the coupling element 104a. The integrated device 207b can be configured to control and / or tune in real time the inductance of the first inductor 140b of the coupling element 104b via the second inductor 142b of the coupling element 104b. The integrated device 207c can be configured to control and / or tune in real time the inductance of the first inductor 140c of the coupling element 104c via the second inductor 142c of the coupling element 104c.

[0027]

[0040] Each of the integrated devices (e.g., 207a, 207b, 207c) may include a controller die. The integrated device 207a may include a controller for controlling an inductance of an inductor coupled to the integrated device 205a. The integrated device 207b may include a controller for controlling an inductance of an inductor coupled to the integrated device 205b. The integrated device 207c may include a controller for controlling an inductance of an inductor coupled to the integrated device 205c. The integrated devices 205a, 205b, and / or 205c may each be configured for radio frequency (RF) functions (e.g., processing RF signals, receiving and / or transmitting RF signals). In some implementations, the integrated device 205a is configured to process, receive, and / or transmit RF signals in a first frequency range. In some implementations, the integrated device 205b is configured to process, receive, and / or transmit RF signals in a second frequency range. In some implementations, the integrated device 205c is configured to process, receive, and / or transmit RF signals in a third frequency range.

[0028]

[0041] FIG. 4 illustrates a package 400 including a substrate with a coupling element. The package 400 is similar to the package 100 and includes similar components to the package 100. The package 400 includes a substrate 102, an integrated device 105, and an integrated device 107. As illustrated in FIG. 4, the integrated device 105 is coupled to the substrate 102 such that the integrated device 105 does not vertically overlap with (i) the integrated device 107 and (ii) the coupling element 104 (including the first inductor 140 and the second inductor 142). The integrated device 105 is offset from the integrated device 107 and vice versa. In some implementations, offsetting the integrated device 105 from the coupling element 104 and / or the integrated device 107 can improve the performance of the integrated device 105. For example, any magnetic field that may be generated by the coupling element 104 can have a reduced effect on the performance of the integrated device 105 due to an offset (e.g., a horizontal offset) between the coupling element 104 and the integrated device 105.

[0029]

[0042] FIG. 5 illustrates a package 500 including a substrate with several coupling elements. The package 500 is similar to the packages 200 and 400 and includes similar components to the packages 200 and 400. The package 500 includes a substrate 102, an integrated device 205a, an integrated device 205b, an integrated device 105, an integrated device 207a, an integrated device 207b, and an integrated device 207c. As illustrated in FIG. 5, the integrated device 105 is coupled to the substrate 102 such that the integrated device 105 does not vertically overlap the integrated device 207c and the coupling element 104c (including the first inductor 140c and the second inductor 142c). The integrated device 105 is offset from the integrated device 207c and vice versa. In some implementations, offsetting the integrated device 105 from the coupling element 104c and / or the integrated device 207c can improve the performance of the integrated device 105. For example, any magnetic field that may be generated by the coupling element 104c may have a reduced effect on the performance of the integrated device 105 due to an offset (e.g., a horizontal offset) between the coupling element 104c and the integrated device 105. Note that other combinations of coupling elements and integrated devices may be offset in a similar manner.

[0030]

[0043] The integrated device 105 and the integrated device 207c are each configured to be coupled to the coupling element 104c. The integrated device 105 is configured to be coupled to the first inductor 140 of the coupling element 104c. The integrated device 207c is configured to be coupled to the second inductor 142c of the coupling element 104c. The integrated device 205a and the integrated device 207a are each configured to be coupled to the coupling element 104a. The integrated device 205a is configured to be coupled to the first inductor 140a of the coupling element 104a. The integrated device 207a is configured to be coupled to the second inductor 142a of the coupling element 104a. The integrated device 205b and the integrated device 207b are each configured to be coupled to the coupling element 104b. The integrated device 205b is configured to be coupled to the first inductor 140b of the coupling element 104b. The integrated device 207b is configured to be coupled to the second inductor 142b of the coupling element 104b. It should be noted that the coupling elements and inductors may be located on the same and / or different metal layers of the substrate 102. The coupling elements and / or inductors may have different sizes, shapes, and / or different numbers of windings.

[0031]

[0044] Each of the integrated devices (e.g., 207a, 207b, 207c) may include a controller die. The integrated device 207a may include a controller for controlling an inductance of an inductor coupled to the integrated device 205a. The integrated device 207b may include a controller for controlling an inductance of an inductor coupled to the integrated device 205b. The integrated device 207c may include a controller for controlling an inductance of an inductor coupled to the integrated device 105. The integrated devices 205a, 205b, and / or 105 may each be configured for radio frequency (RF) functions (e.g., processing RF signals, receiving and / or transmitting RF signals). In some implementations, the integrated device 205a is configured to process, receive, and / or transmit RF signals in a first frequency range. In some implementations, the integrated device 205b is configured to process, receive, and / or transmit RF signals in a second frequency range. In some implementations, the integrated device 105 is configured to process, receive, and / or transmit RF signals in a third frequency range.

[0032]

[0045] The present disclosure describes a coupling element comprising a first inductor and a second inductor. In some implementations, the first inductor may be considered as a third inductor, and the second inductor may be considered as a fourth inductor. This may be the case when a substrate includes the first coupling element and the second coupling element. In some implementations, the first inductor may be considered as a fifth inductor, and the second inductor may be considered as a sixth inductor. This may be the case when a substrate includes the first coupling element, the second coupling element, and the third coupling element.

[0033]

[0046] 3, in some implementations, coupling element 104a may be a first coupling element, coupling element 104b may be a second coupling element, and coupling element 104c may be a third coupling element. In some implementations, the first inductor 140a of coupling element 104a may be a first inductor including a first plurality of windings (e.g., defined by a first plurality of interconnects), the second inductor 142a of coupling element 104a may be a second inductor including a second plurality of windings (e.g., defined by a second plurality of interconnects), and the first inductor 140b of coupling element 104b is a third inductor including a third plurality of windings (e.g., defined by a third plurality of interconnects). The second inductor 142b of the coupling element 104b may be a fourth inductor including a fourth plurality of windings (e.g., defined by a fourth plurality of interconnects), the first inductor 140c of the coupling element 104c may be a fifth inductor including a fifth plurality of windings (e.g., defined by a fifth plurality of interconnects), and the second inductor 142c of the coupling element 104c may be a sixth inductor including a sixth plurality of windings (e.g., defined by a sixth plurality of interconnects).

[0034]

[0047] As mentioned above, one or more inductors of one or more coupling elements may include several windings. For example, one or more coupling elements (e.g., 104, 104a, 104b, 104c) from package 100, package 200, package 300, package 400, and / or package 500 may be replaced with a coupling element having an inductor with several windings. FIGS. 6-8 show a package including a substrate with an inductor with several windings. In some implementations, the winding(s) of one inductor may be intertwined (e.g., vertically intertwined and / or horizontally intertwined) with the winding(s) of another inductor. The use of inductors with several windings and / or intertwined inductors may provide improved performance of the package through improved inductive coupling between the inductors and provide more precise control of the inductance value.

[0035]

[0048] FIG. 6 illustrates an embodiment of a package 600 including a substrate having a coupling element with at least one inductor having several windings (e.g., several turns). FIG. 6 may illustrate a package 600 having a similar configuration to package 100. Package 600 includes a substrate 102, an integrated device 105, a coupling element 604, and an integrated device 107. Integrated device 105 is coupled to substrate 102 via a plurality of solder interconnects 150. Integrated device 107 is coupled to substrate 102 via a plurality of solder interconnects 170. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Package 600 is coupled to board 106.

[0036]

[0049] The coupling element 604 includes a first inductor 640 and a second inductor 642. The first inductor 640 includes a first plurality of windings. The second inductor 642 includes a second plurality of windings. The first inductor 640 is intertwined (e.g., vertically intertwined and / or horizontally intertwined) with the second inductor 642. For example, the first plurality of windings of the first inductor 640 is intertwined (e.g., vertically intertwined and / or horizontally intertwined) with the second plurality of windings of the second inductor 642. The first plurality of windings of the first inductor 640 can be defined by a first plurality of interconnects from the plurality of interconnects 122. The second plurality of windings of the second inductor 642 can be defined by a second plurality of interconnects from the plurality of interconnects 122. In some implementations, a first plurality of interconnects from the plurality of interconnects 122 may be intertwined (e.g., may be vertically intertwined and / or horizontally intertwined) with a second plurality of interconnects from the plurality of interconnects 122.

[0037]

[0050] In one embodiment, the windings for the first inductor 640 can be disposed on the M1 and M3 metal layers, and the windings for the second inductor 642 can be disposed on the M2 and M4 metal layers. In another embodiment, the windings for the first inductor 640 can be disposed on the M1, M3, and M5 metal layers, and the windings for the second inductor 642 can be disposed on the M2 and M4 metal layers. In another embodiment, the windings for the first inductor 640 can be disposed on the M3 and M5 metal layers, and the windings for the second inductor 642 can be disposed on the M2 and M4 metal layers. The above are only examples of possible metal layers on which the first inductor 640 and the second inductor 642 may be disposed in a substrate. Substrates that include more or fewer metal layers may have the inductors on the same or different metal layers.

[0038]

[0051] The integrated device 105 is configured to be coupled to a first inductor 640 of the coupling element 604. The integrated device 107 is configured to be coupled to a second inductor 642 of the coupling element 604. The package 600 can be operated in a similar manner as described for the package 100.

[0039]

[0052] FIG. 7 illustrates an embodiment of a package 700 including a substrate having several coupling elements with at least one inductor having several windings. FIG. 7 may illustrate a package 700 having a similar configuration to package 200. Package 700 includes substrate 102, integrated device 107, coupling element 604a, coupling element 604b, coupling element 604c, integrated device 105a, integrated device 105b, and integrated device 105c. Integrated device 105a is coupled to substrate 102 via a plurality of solder interconnects 150a. Integrated device 105b is coupled to substrate 102 via a plurality of solder interconnects 150b. Integrated device 105c is coupled to substrate 102 via a plurality of solder interconnects 150c. Integrated device 107 is coupled to substrate 102 via a plurality of solder interconnects 170. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The package 700 is coupled to the board 106 .

[0040]

[0053] The coupling element 604a includes a first inductor 640a and a second inductor 642a. The first inductor 640a includes a first plurality of windings. The second inductor 642a includes a second plurality of windings. The first inductor 640a is intertwined (e.g., vertically intertwined and / or horizontally intertwined) with the second inductor 642a. For example, the first plurality of windings of the first inductor 640a is intertwined (e.g., vertically intertwined and / or horizontally intertwined) with the second plurality of windings of the second inductor 642a. The first plurality of windings of the first inductor 640a can be defined by a first plurality of interconnects from the plurality of interconnects 122. The second plurality of windings of the second inductor 642a can be defined by a second plurality of interconnects from the plurality of interconnects 122. In some implementations, a first plurality of interconnects from the plurality of interconnects 122 may be intertwined (e.g., may be vertically intertwined and / or horizontally intertwined) with a second plurality of interconnects from the plurality of interconnects 122.

[0041]

[0054] The coupling element 604b and the coupling element 604c may be configured and / or arranged similarly to the coupling element 604a. Thus, the coupling element 604b and / or the coupling element 604c may each include a first inductor (e.g., 640b, 640c) and a second inductor (e.g., 642b, 642c). Each of the inductors may have a respective number of windings defined by interconnects from the plurality of interconnects 122. The physical characteristics (e.g., windings) and functional characteristics described for the coupling element 604a, the first inductor 640a, and / or the second inductor 642a may be applicable to the coupling element 604b, the coupling element 604c, the first inductor 640b, the second inductor 642b, the first inductor 640c, and / or the second inductor 642c.

[0042]

[0055] The integrated device 105a is configured to be coupled to the first inductor 640a of the coupling element 604a. The integrated device 105b is configured to be coupled to the first inductor 640b of the coupling element 604b. The integrated device 105c is configured to be coupled to the first inductor 640c of the coupling element 604c. The integrated device 107 is configured to be coupled to the second inductor 642a of the coupling element 604a, the second inductor 642b of the coupling element 604b, and the second inductor 642c of the coupling element 604c. The package 700 can operate similarly to that described for the package 200 and / or the package 600. In some implementations, the second inductor 642a of the coupling element 604a, the second inductor 642b of the coupling element 604b, and the second inductor 642c of the coupling element 604c are coupled to each other (e.g., coupled in series to each other). Thus, in some implementations, turning on the second inductor for any of the coupling elements can turn on the second inductor for all of the coupling elements (eg, 604a, 604b, 604c).

[0043]

[0056] An integrated device (e.g., 107) can be configured to simultaneously and / or sequentially control and / or tune inductances of inductors coupled to several integrated devices (e.g., 105a, 105b, 105c) in real time. Thus, for example, the integrated device 107 can simultaneously control the inductance of each of the integrated devices (e.g., 105a, 105b, 105c) while each of these integrated devices (e.g., 105a, 105b, 105c) is operating (e.g., while various signals are being processed, received, and / or transmitted by each of these integrated devices (e.g., 105a, 105b, 105c)).

[0044]

[0057] FIG. 8 illustrates an embodiment of a package 800 including a substrate having several coupling elements with at least one inductor having several windings. FIG. 8 may illustrate a package 800 having a similar configuration to package 300. Package 800 includes substrate 102, integrated device 105a, integrated device 105b, integrated device 105c, coupling element 604a, coupling element 604b, coupling element 604c, integrated device 107a, integrated device 107b, and integrated device 107c. Integrated device 105a is coupled to substrate 102 via a plurality of solder interconnects 150a. Integrated device 105b is coupled to substrate 102 via a plurality of solder interconnects 150b. Integrated device 105c is coupled to substrate 102 via a plurality of solder interconnects 150c. Integrated device 107a is coupled to substrate 102 via a plurality of solder interconnects 170a. Integrated device 107b is coupled to substrate 102 via a plurality of solder interconnects 170b. Integrated device 107c is coupled to substrate 102 via a plurality of solder interconnects 170c. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122.

[0045]

[0058] The coupling element 604a includes a first inductor 640a and a second inductor 642a. The first inductor 640a includes a first plurality of windings. The second inductor 642a includes a second plurality of windings. The first inductor 640a is intertwined (e.g., vertically intertwined and / or horizontally intertwined) with the second inductor 642a. For example, the first plurality of windings of the first inductor 640a is intertwined (e.g., vertically intertwined and / or horizontally intertwined) with the second plurality of windings of the second inductor 642a. The first plurality of windings of the first inductor 640a can be defined by a first plurality of interconnects from the plurality of interconnects 122. The second plurality of windings of the second inductor 642a can be defined by a second plurality of interconnects from the plurality of interconnects 122. In some implementations, a first plurality of interconnects from the plurality of interconnects 122 may be intertwined (e.g., vertically intertwined and / or horizontally intertwined) with a second plurality of interconnects from the plurality of interconnects 122. Intertwining of inductors (e.g., vertical intertwining) may provide improved inductive coupling between the inductors and may improve real-time tuning of the inductors (e.g., improved control of tuning of the inductors).

[0046]

[0059] The coupling element 604b and the coupling element 604c may be configured and / or arranged similarly to the coupling element 604a. Thus, the coupling element 604b and / or the coupling element 604c may each include a first inductor (e.g., 640b, 640c) and a second inductor (e.g., 642b, 642c). Each of the inductors may have a respective number of windings defined by interconnects from the plurality of interconnects 122. The physical characteristics (e.g., windings) and functional characteristics described for the coupling element 604a, the first inductor 640a, and / or the second inductor 642a may be applicable to the coupling element 604b, the coupling element 604c, the first inductor 640b, the second inductor 642b, the first inductor 640c, and / or the second inductor 642c.

[0047]

[0060] The integrated device 105a is configured to be coupled to the first inductor 640 of the coupling element 604a. The integrated device 105b is configured to be coupled to the first inductor 640b of the coupling element 604b. The integrated device 105c is configured to be coupled to the first inductor 640c of the coupling element 604c. The integrated device 107a is configured to be coupled to the second inductor 642a of the coupling element 604a. The integrated device 107b is configured to be coupled to the second inductor 642b of the coupling element 604b. The integrated device 107c is configured to be coupled to the second inductor 642c of the coupling element 604c. The package 800 can operate in a similar manner as described for the package 300 and / or the package 700.

[0048]

[0061] The integrated device(s) (e.g., 107, 107a, 107b, 107c) of package 600, package 700, and / or package 800 can be configured to provide real-time tuning of the inductor for the integrated device in a similar and / or identical manner as described in Figures 1-5. It should be noted that for package 600, package 700, and package 800, any of the coupling elements and / or integrated devices (e.g., 107, 107a, 107b, 107) can be horizontally offset (e.g., no vertical overlap or partial vertical overlap) relative to the corresponding integrated device (e.g., 105, 105a, 105b, 105c) in a manner similar to that described for package 400 and / or package 500.

[0049]

[0062] The coupling elements (e.g., 104, 104a, 104b, 104c, 604, 604a, 604b, 604c) may be inductive coupling elements. The coupling elements may be means for inductive coupling. The present disclosure describes the coupling elements as comprising a first inductor and a second inductor. In some implementations, the first inductor may be considered as a third inductor, and the second inductor may be considered as a fourth inductor. This may be the case when the substrate includes the first coupling element and the second coupling element. In some implementations, the first inductor may be considered as a fifth inductor, and the second inductor may be considered as a sixth inductor. This may be the case when the substrate includes the first coupling element, the second coupling element, and the third coupling element.

[0050]

[0063] 7 and 8, in some implementations, coupling element 604a may be a first coupling element, coupling element 604b may be a second coupling element, and coupling element 604c may be a third coupling element. In some implementations, the first inductor 640a of coupling element 604a may be a first inductor including a first plurality of windings (e.g., defined by a first plurality of interconnects), the second inductor 642a of coupling element 604a may be a second inductor including a second plurality of windings (e.g., defined by a second plurality of interconnects), and the first inductor 640b of coupling element 604b is a third inductor including a third plurality of windings (e.g., defined by a third plurality of interconnects). The second inductor 642b of the coupling element 604b may be a fourth inductor including a fourth plurality of windings (e.g., defined by a fourth plurality of interconnects), the first inductor 640c of the coupling element 604c may be a fifth inductor including a fifth plurality of windings (e.g., defined by a fifth plurality of interconnects), and the second inductor 642c of the coupling element 604c may be a sixth inductor including a sixth plurality of windings (e.g., defined by a sixth plurality of interconnects).

[0051]

[0064] The integrated device (e.g., 105, 107, 205a) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 105, 107, 205a) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. An integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may be a chiplet. Chiplets may provide better yields during manufacturing, which may lower the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chiplets may be used to perform the functions of one or more chips (e.g., another integrated device). Using several chiplets to perform several functions may reduce the overall cost of the package compared to using a single chip to perform all of the functions of the package.

[0052]

[0065] 3, 5, and 8 show a one-to-one ratio between the number of integrated devices and the number of controller dies. That is, one controller die is used to control and / or tune the coupling elements for the integrated devices. However, in some implementations, a package can include a first controller die that controls and / or tunes one coupling element and a second controller die that controls and / or tunes two or more coupling elements. Thus, a package can include a different number (N) of integrated devices and a different number (M) of controller dies, where the controller die can control and / or tune a different number of coupling elements for the integrated device(s). Thus, the number of integrated devices (N) does not have to be equal to the number (M) of controller dies in the package.

[0053]

[0066] The packages (e.g., 100, 200, 300, 400, 500, 600, 700, 800) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The packages (e.g., 100, 200, 300, 400, 500, 600, 700, 800) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The packages (e.g., 100, 200, 300, 400, 500, 600, 700, 800) may be configured to support Global System for Mobile (GSM) communications, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The packages (eg, 100, 200, 300, 400, 500, 600, 700, 800) can be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0054]

[0067] Although various packages have been described, next, a sequence for manufacturing a package will be described below.

[0055] Exemplary sequence for manufacturing a package comprising a substrate having a coupling element comprising a first inductor and a second inductor

[0068] In some implementations, manufacturing a package involves several processes. FIGS. 9A - 9B show an exemplary sequence for providing or manufacturing a package. In some implementations, the sequence of FIGS. 9A - 9B can be used to provide or manufacture package 200. However, any of the packages described in the present disclosure (e.g., 100, 300, 400, 500, 600, 700, 800) can be manufactured using the processes of FIGS. 9A - 9B.

[0056]

[0069] Note that the sequence of FIGS. 9A - 9B can combine one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0057]

[0070] As shown in FIG. 9A, stage 1 shows a state after the substrate 102 is prepared. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 102 may be manufactured using the method described in FIG. 11A-FIG. 11B. In some implementations, a core substrate (e.g., a substrate including a core layer) is prepared. The substrate 102 has a coupling element 104a, a coupling element 104b, and a coupling element 104c. Each of the coupling elements may include a first inductor and a second inductor. The first inductor of the coupling element may be defined by a first plurality of interconnects from the plurality of interconnects 122. The second inductor of the coupling element may be defined by a second plurality of interconnects from the plurality of interconnects 122.

[0058]

[0071] Stage 2 illustrates the state after integrated device 205a (e.g., a first integrated device), integrated device 205b, and integrated device 205c are bonded to a first surface (e.g., a top surface) of substrate 102. Integrated device 205a may be bonded to substrate 102 via multiple solder interconnects 150a. Integrated device 205b may be bonded to substrate 102 via multiple solder interconnects 150b. Integrated device 205c may be bonded to substrate 102 via multiple solder interconnects 150c. A solder reflow process may be used to bond the integrated devices (e.g., 205a, 205b, 205c) to substrate 102.

[0059]

[0072] 9B, stage 3 shows the state after the integrated device 107 is bonded to a second surface (e.g., a bottom surface) of the substrate 102. The integrated device 107 (e.g., a second integrated device) may be bonded to the substrate 102 via a number of solder interconnects 170. A solder reflow process may be used to bond the integrated device 107 to the substrate 102.

[0060]

[0073] Stage 4 shows the condition after the plurality of solder interconnects 110 have been bonded to the second surface of the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 110 to the substrate 102. Stage 4 may show the package 200. The package 200 may be manufactured one by one or may be manufactured together as part of one or more wafers and then singulated into individual packages.

[0061] 1 is an exemplary flow diagram of a method for manufacturing a package comprising a substrate having a coupling element comprising a first inductor and a second inductor;

[0074] In some implementations, manufacturing the package includes several processes. Figure 10 shows an example flow diagram of a method 1000 of providing or manufacturing a package. In some implementations, the method 1000 of Figure 10 can be used to provide or manufacture the package 200 described in this disclosure. However, the method 1000 can be used to provide or manufacture any of the packages described in this disclosure (e.g., 100, 300, 400, 500, 600, 700, 800).

[0062]

[0075] It should be noted that the method of Figure 10 may combine one or more processes to simplify and / or clarify the method of providing or manufacturing the package. In some implementations, the order of the processes may be changed or modified.

[0063]

[0076] The method includes (at 1005) preparing a substrate (e.g., 102). The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 102 may be manufactured using the method described in FIGS. 11A-11B. In some implementations, a core substrate (e.g., a substrate including a core layer) is provided. The substrate 102 includes a coupling element 104a, a coupling element 104b, and a coupling element 104c. Each of the coupling elements may include a first inductor and a second inductor. Step 1 of FIG. 9A illustrates and describes one example of preparing a substrate including coupling elements.

[0064]

[0077] The method includes (at 1010) bonding at least one first integrated device (e.g., 105, 205) to a first surface of a substrate (e.g., 102). The first integrated device may be bonded to a first surface (e.g., top surface) of the substrate 102. The first integrated device may be bonded to the substrate 102 via a plurality of solder interconnects (e.g., 150, 150a). A solder reflow process may be used to bond the first integrated device (e.g., 205a, 205b, 205c) to the substrate 102. Stage 2 of FIG. 9A illustrates and describes one embodiment of bonding an integrated device to a substrate.

[0065]

[0078] The method includes (at 1015) bonding at least one second integrated device (e.g., 107, 207a) to a second surface of the substrate (e.g., 102). The second integrated device may be bonded to the substrate 102 via a plurality of solder interconnects (e.g., 170). A solder reflow process may be used to bond the second integrated device (e.g., 107, 207a) to the substrate 102. Step 3 of Figure 9B illustrates and describes one embodiment of bonding an integrated device to a substrate.

[0066]

[0079] The method couples a plurality of solder interconnects 110 (at 1020) to a second surface of the substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 110 to the substrate 102. Stage 4 of FIG. 9B illustrates and describes an example of coupling a solder interconnect to a substrate.

[0067] Exemplary sequence for manufacturing a substrate

[0080] In some implementations, manufacturing the substrate includes several processes. FIGS. 11A - 11B show an exemplary sequence for providing or manufacturing a substrate. In some implementations, the substrate 102 can be provided or manufactured using the sequence of FIGS. 11A - 11B. However, any of the substrates described in this disclosure can be manufactured using the processes of FIGS. 11A - 11B.

[0068]

[0081] Note that the sequence of FIGS. 11A - 11B can combine one or more steps to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of this disclosure.

[0069]

[0082] As shown in FIG. 11A, stage 1 shows the state after the carrier 1100 is prepared. A seed layer 1101 and interconnects 1102 can be disposed on the carrier 1100. The interconnects 1102 can be disposed on the seed layer 1101. An electroplating process and an etching process can be used to form the interconnects 1102. In some implementations, the carrier 1100 can be provided with a seed layer 1101 and a metal layer patterned to form the interconnects 1102. The interconnects 1102 can represent at least some of the interconnects from a plurality of interconnects 122.

[0070]

[0083] Stage 2 shows the state after the dielectric layer 1120 is formed over the carrier 1100, the seed layer 1101, and the interconnects 1102. A deposition process and / or lamination process may be used to form the dielectric layer 1120. The dielectric layer 1120 may include a prepreg and / or a polyimide. The dielectric layer 1120 may include a photo-imageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0071]

[0084] Stage 3 shows the state after the multiple cavities 1110 are formed in the dielectric layer 1120. The multiple cavities 1110 can be formed using an etching process (eg, a photoetching process) or a laser process.

[0072]

[0085] Stage 4 shows the state after interconnects 1112 have been formed in and on the dielectric layer 1120, including in and on the plurality of cavities 1110. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0073]

[0086] Stage 5 shows the state after the dielectric layer 1122 is formed over the dielectric layer 1120 and the interconnects 1112. A deposition process and / or lamination process may be used to form the dielectric layer 1122. The dielectric layer 1122 may include prepreg and / or polyimide. The dielectric layer 1122 may include a photosensitive dielectric. However, different implementations may use different materials for the dielectric layer.

[0074]

[0087] 11B, stage 6 shows the state after a plurality of cavities 1130 have been formed in the dielectric layer 1122. The plurality of cavities 1130 can be formed using an etching process (e.g., a photoetching process) or a laser process.

[0075]

[0088] Stage 7 shows the state after interconnects 1114 have been formed in and on the dielectric layer 1122, including in and on the plurality of cavities 1130. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0076]

[0089] Stage 8 illustrates the state after the carrier 1100 has been separated (e.g., detached, removed, ground) from the at least one dielectric layer 120 and the seed layer 1101, and a portion of the seed layer 1101 has been removed (e.g., etched away) to leave the substrate 102 including the at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 may represent the interconnects 1102, 1112, and / or 1114. The at least one dielectric layer 120 may represent the dielectric layer 1120 and / or the dielectric layer 1122. Some of the interconnects from the plurality of interconnects 122 may define inductors (e.g., 140, 142, 640, 642) and / or coupling elements (e.g., 104, 104a, 604a) as described herein.

[0077]

[0090] Stage 9 illustrates the state after solder resist layer 124 has been formed on a first surface of substrate 102 and solder resist layer 126 has been formed on a second surface of substrate 102. Deposition and / or lamination processes may be used to form solder resist layer 124 and / or solder resist layer 126.

[0078]

[0091] Different implementations may use different processes to form the metal layer(s) and / or the interconnects. In some implementations, the metal layer(s) may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process.

[0079] 1 is an exemplary flow diagram of a method for manufacturing a substrate;

[0092] In some implementations, manufacturing a substrate includes several processes. Figure 12 shows an example flow diagram of a method 1200 for providing or manufacturing a substrate. In some implementations, the method 1200 of Figure 12 can be used to provide or manufacture a substrate or substrates of the present disclosure. For example, the method 1200 of Figure 12 can be used to manufacture the substrate 102.

[0080]

[0093] It should be noted that the method 1200 of Figure 12 may combine one or more processes to simplify and / or clarify the method of providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0081]

[0094] The method includes (at 1205) preparing a carrier (e.g., 1100). Different implementations can use different materials for the carrier 1100. The carrier 1100 can include a seed layer (e.g., 1101). The seed layer 1101 can include a metal (e.g., copper). The carrier can include a substrate, glass, quartz, and / or a carrier tape. Step 1 of FIG. 11A illustrates and describes one embodiment of a carrier with a prepared seed layer.

[0082]

[0095] The method forms and patterns (at 1210) interconnects on the carrier 1100 and seed layer 1101. A metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and seed layer may include a metal layer. The metal layer is disposed on the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 1102). Step 1 of FIG. 11A illustrates and describes one example of forming and patterning interconnects on a seed layer and carrier.

[0083]

[0096] The method forms (at 1215) a dielectric layer 1120 over the seed layer 1101, the carrier 1100, and the interconnects 1102. A deposition process and / or a lamination process may be used to form the dielectric layer 1120. The dielectric layer 1120 may include prepreg and / or polyimide. The dielectric layer 1120 may include a photosensitive dielectric. Forming the dielectric layer 1120 may also include forming a plurality of cavities (e.g., 1110) in the dielectric layer 1120. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 2-3 of FIG. 11A illustrate and describe one embodiment of forming a dielectric layer and cavities in the dielectric layer.

[0084]

[0097] The method forms (at 1220) interconnects in and on the dielectric layer. For example, interconnects 1112 may be formed in and on dielectric layer 1120. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnects may also include forming the interconnects in cavities in the dielectric layer. Step 4 of FIG. 11A illustrates and describes one embodiment of forming interconnects in and on the dielectric layer.

[0085]

[0098] The method forms (at 1225) a dielectric layer 1122 over the dielectric layer 1120 and the interconnects 1112. A deposition process and / or a lamination process may be used to form the dielectric layer 1122. The dielectric layer 1122 may include prepreg and / or polyimide. The dielectric layer 1122 may include a photosensitive dielectric. Forming the dielectric layer 1122 may also include forming a plurality of cavities (e.g., 1130) in the dielectric layer 1122. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 5-6 of Figures 11A-11B illustrate and describe one embodiment of forming a dielectric layer and cavities in the dielectric layer.

[0086]

[0099] The method forms (at 1230) interconnects in and on the dielectric layer. For example, interconnects 1114 may be formed in and on dielectric layer 1122. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnects may also include forming the interconnects in cavities in the dielectric layer. Step 7 of FIG. 11B illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0087]

[0100] The method separates (at 1235) the carrier (e.g., 1100) from the seed layer (e.g., 1101). The carrier 1100 may be removed and / or ground. The method may also remove (at 1235) a portion of the seed layer (e.g., 1101). An etching process may be used to remove a portion of the seed layer 1101. Step 8 of FIG. 11B illustrates and describes one embodiment of carrier separation and seed layer removal.

[0088]

[0101] The method may include forming (at 1240) a solder resist layer(s) on the first surface and / or the second surface of the substrate. For example, a first solder resist layer may be formed on the first surface of the substrate and / or a second solder resist layer may be formed on the second surface of the substrate. Step 9 of FIG. 11B illustrates and describes one embodiment of providing and / or forming a solder resist layer.

[0089]

[0102] Forming the substrate interconnects includes forming a plurality of interconnects 122. Some of the interconnects from the plurality of interconnects 122 can define inductors (e.g., 140, 142, 640, 642) and / or coupling elements (e.g., 104, 104a, 604a) as described in this disclosure.

[0090]

[0103] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0091] Exemplary Electronic Devices

[0104] FIG. 13 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1302, a laptop computer device 1304, a fixed location terminal device 1306, a wearable device 1308, or an autonomous vehicle 1310 may include a device 1300 as described herein. The device 1300 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1302, 1304, 1306, and 1308 and the vehicle 1310 illustrated in FIG. 13 are merely illustrative. Other electronic devices may also feature device 1300, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0092]

[0105] One or more of the components, processes, features, and / or functions shown in Figures 1-8, 9A-9B, 10, 11A-11B, and 12-13 may be rearranged and / or combined into a single component, process, feature, or function, or may be embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from the present disclosure. It should also be noted that Figures 1-8, 9A-9B, 10, 11A-11B, and 12-13 and corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 1-8, 9A-9B, 10, 11A-11B, and 12-13 and corresponding descriptions may be used to manufacture, fabricate, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0093]

[0106] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0094]

[0107] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even though they are not in direct physical contact with each other. Object A that is coupled to object B can be coupled to at least a portion of object B. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not propagate a current between the two objects. The use of the terms "first," "second," "third," and "fourth" (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The terms "encapsulate," "encapsulating," and / or derivatives thereof, mean that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may also be considered a bottom component, and vice versa.As described in this disclosure, a first component being disposed "over" a second component can mean that the first component is disposed above or below the second component, depending on how bottom or top is optionally defined. In another example, a first component can be disposed above (e.g., above) a first surface of the second component, and a third component can be disposed above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being disposed above another component, the term "over" as used in this application can be used to mean a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but is not in direct contact with the second component, (2) that the first component is present on the second component (e.g., on a surface of the second component), and / or (3) that the first component is present within the second component (e.g., embedded within the second component). A first component that is disposed "in" a second component can be partially disposed within the second component or can be completely disposed within the second component. A value that is about X to XX can mean a value between and including X and XX. The value or values ​​between X and XX can be discrete or continuous. The term "about 'value X'" or "approximately value X" as used in this disclosure means within a range of 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0095]

[0108] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace (e.g., a trace interconnect), a via (e.g., a via interconnect), a pad (e.g., a pad interconnect), a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, the interconnects may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process.

[0096]

[0109] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. In addition, the order of operations may be rearranged. A process terminates when its operations are completed.

[0097]

[0110] In the following, further examples are described to facilitate understanding of the invention.

[0098]

[0111] Aspect 1: A package comprising: a substrate comprising a dielectric layer and a plurality of interconnects including a first plurality of interconnects configured as a first inductor and a second plurality of interconnects configured as a second inductor; a first integrated device coupled to a first surface of the substrate, the first integrated device configured to be coupled to the first inductor; and a second integrated device coupled to a second surface of the substrate, the second integrated device configured to be coupled to the second inductor and configured to tune the first inductor via the second inductor.

[0099]

[0112] Aspect 2: The package of aspect 1, wherein the first inductor and the second inductor are configured as coupling elements between the first integrated device and the second integrated device.

[0100]

[0113] Aspect 3: The package of Aspect 1 or 2, wherein at least one winding of the first inductor vertically overlaps with at least one winding of the second inductor.

[0101]

[0114] Embodiment 4: The package of embodiments 1 to 3, wherein the first integrated device vertically overlaps the second integrated device.

[0102]

[0115] Embodiment 5: The package of embodiments 1 to 3, wherein the first integrated device does not vertically overlap the second integrated device.

[0103]

[0116] Aspect 6: The package of aspects 1 to 5, further comprising a third integrated device coupled to the first surface of the substrate, wherein the plurality of interconnects includes a third plurality of interconnects configured as a third inductor, the third integrated device configured to be coupled to the third inductor, the plurality of interconnects includes a fourth plurality of interconnects configured as a fourth inductor, the second integrated device configured to be coupled to the fourth inductor, and the second integrated device configured to tune the third inductor via the fourth inductor.

[0104]

[0117] Aspect 7: The package of aspect 6, wherein the second integrated device includes a controller die configured to tune the first inductor for the first integrated device and / or the third inductor for the third integrated device based on sub-band data and / or input bandwidth of the first integrated device and / or the third integrated device. In some implementations, the controller die is configured to simultaneously tune the first inductor for the first integrated device and the third inductor for the third integrated device.

[0105]

[0118] Aspect 8: The package of aspects 1 to 5, further comprising: a third integrated device coupled to a first surface of the substrate; and a fourth integrated device coupled to a second surface of the substrate, wherein the plurality of interconnects includes a third plurality of interconnects configured as a third inductor, the third integrated device configured to be coupled to the third inductor, the plurality of interconnects includes a fourth plurality of interconnects configured as a fourth inductor, the fourth integrated device configured to be coupled to the fourth inductor, and the fourth integrated device configured to tune the third inductor via the fourth inductor.

[0106]

[0119] Aspect 9: The package of aspect 8, wherein the second integrated device includes a first controller die configured to tune a first inductor for the first integrated device based on sub-band data and / or input bandwidth of the first integrated device, and the fourth integrated device includes a second controller die configured to tune a third inductor for the third integrated device based on sub-band data and / or input bandwidth of the third integrated device.

[0107]

[0120] Aspect 10: The package of aspects 1 to 9, wherein the first inductor includes one or more windings and the second inductor includes one or more windings.

[0108]

[0121] Aspect 11: A package comprising: a substrate comprising a means for a first inductance and a means for a second inductance; a first integrated device coupled to a first surface of the substrate, the first integrated device configured to be coupled to the means for the first inductance; and a second integrated device coupled to a second surface of the substrate, the second integrated device configured to be coupled to the means for the second inductance and configured to tune the means for the first inductance via the means for the second inductance.

[0109]

[0122] Example 12: The package of example 11, wherein the means for first inductance and the means for second inductance are configured as inductive coupling elements between the first integrated device and the second integrated device.

[0110]

[0123] Aspect 13: The package of aspect 11 or 12, wherein at least one winding of the means for first inductance vertically overlaps with at least one winding of the means for second inductance.

[0111]

[0124] Embodiment 14: The package of embodiments 11 to 13, wherein the first integrated device vertically overlaps the second integrated device.

[0112]

[0125] Embodiment 15: The package of embodiments 11 to 13, wherein the first integrated device does not vertically overlap the second integrated device.

[0113]

[0126] Aspect 16: The package of aspects 11 to 15, further comprising a third integrated device coupled to a first surface of the substrate, the substrate comprising a means for a third inductance and a means for a fourth inductance, the third integrated device configured to be coupled to the means for the third inductance, the second integrated device configured to be coupled to the means for the fourth inductance, and the second integrated device configured to tune the means for the third inductance via the means for the fourth inductance.

[0114]

[0127] Aspect 17: The package of aspect 16, wherein the second integrated device includes a controller die configured to tune the means for the first inductance for the first integrated device and / or the means for the third inductance for the third integrated device based on sub-band data and / or input bandwidth of the first integrated device and / or the third integrated device. In some implementations, the controller die is configured to simultaneously tune the means for the first inductance for the first integrated device and the means for the third inductance for the third integrated device.

[0115]

[0128] Aspect 18: The package of aspects 11 to 15, further comprising a third integrated device coupled to a first surface of the substrate and a fourth integrated device coupled to a second surface of the substrate, the substrate comprising means for a third inductance and means for a fourth inductance, the third integrated device configured to be coupled to the means for the third inductance, the fourth integrated device configured to be coupled to the means for the fourth inductance, and the fourth integrated device configured to tune the means for the third inductance via the means for the fourth inductance.

[0116]

[0129] Aspect 19: The package of aspect 18, wherein the second integrated device includes a first controller die configured to tune a means for a first inductance for the first integrated device based on sub-band data and / or input bandwidth of the first integrated device, and the fourth integrated device includes a second controller die configured to tune a means for a third inductance for the third integrated device based on sub-band data and / or input bandwidth of the third integrated device.

[0117]

[0130] Aspect 20: The package of aspects 11 to 19, wherein the means for first inductance includes one or more windings, and the means for second inductance includes one or more windings.

[0118]

[0131] Aspect 21: The package of aspects 11 to 20, wherein the means for the first inductance and the means for the second inductance are part of a means for inductive coupling, the means for inductive coupling is part of a plurality of means for inductive coupling, the first integrated device is part of a first plurality of integrated devices, the second integrated device is part of a second plurality of integrated devices, and the second plurality of integrated devices is configured to control and / or tune an inductance coupled to the first plurality of integrated devices.

[0119]

[0132] Example 22: The package of example 21, wherein the number of integrated devices in the first plurality of integrated devices is the same as the number of integrated devices in the second plurality of integrated devices.

[0120]

[0133] Example 23: The package of example 21, wherein a number of integrated devices in the first plurality of integrated devices is different from a number of integrated devices in the second plurality of integrated devices.

[0121]

[0134] Example 24: The package of example 22 or 23, wherein each integrated device from the second plurality of integrated devices includes a controller die.

[0122]

[0135] Various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. a dielectric layer; and a plurality of interconnects, a first plurality of interconnects configured as a first inductor; a second plurality of interconnects configured as a second inductor; a substrate comprising a plurality of interconnects, a first integrated device comprising a die coupled to a first surface of the substrate, the first integrated device configured to be coupled to the first inductor; a second integrated device comprising a die and coupled to a second surface of the substrate, configured to be coupled to the second inductor; configured to tune the first inductor via the second inductor; a second integrated device; and A package comprising:

2. The package of claim 1 , wherein the first inductor and the second inductor are configured as coupling elements between the first integrated device and the second integrated device.

3. The package of claim 1 , wherein at least one winding of the first inductor vertically overlaps at least one winding of the second inductor.

4. The package of claim 1 , wherein the first integrated device vertically overlaps the second integrated device.

5. The package of claim 1 , wherein the first integrated device does not vertically overlap the second integrated device.

6. A third integrated device comprising a die and coupled to the first surface of the substrate; the plurality of interconnects includes a third plurality of interconnects configured as a third inductor; the third integrated device is configured to be coupled to the third inductor; the plurality of interconnects includes a fourth plurality of interconnects configured as a fourth inductor; the second integrated device is configured to be coupled to the fourth inductor; the second integrated device is configured to tune the third inductor via the fourth inductor; The package of claim 1.

7. 7. The package of claim 6, wherein the second integrated device includes a controller die configured to tune the first inductor for the first integrated device and / or the third inductor for the third integrated device based on sub-band data and / or input bandwidth of the first integrated device and / or the third integrated device.

8. A third integrated device having a die and coupled to the first surface of the substrate; a fourth integrated device comprising a die and coupled to the second surface of the substrate; Further provided with the plurality of interconnects includes a third plurality of interconnects configured as a third inductor; the third integrated device is configured to be coupled to the third inductor; the plurality of interconnects includes a fourth plurality of interconnects configured as a fourth inductor; the fourth integrated device is configured to be coupled to the fourth inductor; the fourth integrated device is configured to tune the third inductor via the fourth inductor; The package of claim 1.

9. the second integrated device includes a first controller die configured to tune the first inductor for the first integrated device based on sub-band data and / or an input bandwidth of the first integrated device; the fourth integrated device includes a second controller die configured to tune the third inductor for the third integrated device based on sub-band data and / or an input bandwidth of the third integrated device. The package of claim 8.

10. the first inductor includes one or more first windings; the second inductor includes one or more second windings; The package of claim 1.

Images