METHOD AND APPARATUS FOR CHARACTERIZING MEMORY - Patent application

Abstract

An example device (100) includes a converter circuit element (104A) having an output configured to couple to a first memory circuit (106A) from a plurality of memory circuits (106A, 106B, 106C), the converter circuit element (104A) configured to receive a first instruction formatted using a uniform protocol and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit (106A), and a logic circuit element (108) having an input configured to couple to the first memory circuit (106A), the logic circuit element (108) configured to receive a first result of the first instruction from the first memory circuit (106A) and combine the first result as an output with other results from ones of the plurality of memory circuits (106B, 106C) in response to a second instruction.

Description

[Technical field]

[0001] This description relates generally to fault detection, and more particularly to a method and apparatus for characterizing memory. [Background technology]

[0002] Fault detection refers to the process of monitoring a device to determine the frequency, location, and type of faults occurring within the device. Fault detection is used on a variety of systems across multiple industries. In some examples of fault detection, the current state of the device is recorded in a data structure known as a signature. In such examples, the recorded, measured, calculated, etc. signature of the current state of the device is compared to an expected signature. Differences between the measured signature and the expected signature may be identified as faults in the device. Summary of the Invention

[0003] For a method and apparatus for characterizing a memory, an example device includes a converter circuit element having an output configured to couple to a first memory circuit from a plurality of memory circuits, the converter circuit element configured to receive a first instruction formatted using a uniform protocol and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit, and a logic circuit element having an input coupled to the first memory circuit, the logic circuit element configured to receive a first result of the first instruction from the first memory circuit and combine the first result with other results from some of the plurality of memory circuits in an output in response to a second instruction. [Brief description of the drawings]

[0004] [Figure 1] FIG. 2 is an exemplary block diagram of computer circuitry.

[0005] [Diagram 2] FIG. 2 is an example block diagram of the converter circuitry and interconnect circuitry of FIG. 1.

[0006] [Diagram 3] FIG. 2 is an exemplary diagram of power safety requirements for the computer circuitry of FIG. 1.

[0007] [Figure 4] FIG. 2 is an exemplary diagram of backward compatibility of the computer circuitry of FIG. 1.

[0008] [Diagram 5] 2 is two graphs illustrating the performance across several example simulations of the computer circuitry of FIG. 1;

[0009] [Figure 6] 2 is a flowchart representing an example process that may be implemented using executable machine-readable instructions and / or the computer circuitry of FIG. 1 and / or, more generally, hardware configured to implement the fault detection circuitry of FIG. 1 for identifying faults in a memory.

[0010] In the figures, the same reference numbers or other reference identifiers are used to denote identical or similar (functional and / or structural) features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The drawings are not necessarily to scale. Generally, the same reference numbers in the drawings and this description refer to the same or similar parts. Although the drawings show layers and regions with distinct lines or boundaries, some or all of these lines and boundaries may be idealized. In reality, the boundaries and / or lines may not be observable, may be blended, or may be irregular.

[0012] In some examples, the current state of the device may be captured by calculating a signature based on values ​​stored in memory. The device may store multiple values ​​in various different memory circuits at any given time. The device may further implement one or more nodes, logic gates, or other communication paths, collectively referred to as interconnect circuitry, to provide data from the memory circuits to the processor circuitry. In some examples, the processor circuitry may be dedicated to fault detection functions. The processor circuitry may perform operations to test the device, access values ​​from memory, and calculate a signature based on the values. As used herein, fault detection circuitry refers to circuitry within a device whose primary function is to identify faults. Fault detection circuitry may include, but is not limited to, the interconnect circuitry and processor circuitry described above.

[0013] Two metrics used to describe the quality of fault detection circuitry include computation time and footprint. Computation time refers to both the amount of time required for the interconnect circuitry to provide data from each of the desired memory circuits to the processor circuitry and the amount of time for the processor circuitry to compute the signature. To identify faults, the device may perform tests and compute a signature based on memory values ​​changed by the tests. Because many tests interrupt the normal operation of the device, manufacturers aim to minimize the amount of time required to perform the tests, obtain the desired memory values, and compute the signature. Footprint refers to the amount of die space required to implement the fault detection function on an integrated circuit. In many instances, the fault detection circuitry may be embedded on an integrated circuit along with other computational resources, including, but not limited to, various memory circuits, other types of processor circuitry, and the like. Manufacturers may aim to minimize the footprint designated for the fault detection circuitry to reduce material assembly and allocate die space to other computational resources, and the like.

[0014] Fault detection circuitry may be designed in many ways. Some conventional solutions for detecting faults may use a centralized architecture. In a centralized architecture, a single instance of a processor circuitry may compute a signature by retrieving and processing memory values ​​from one group of memory values ​​at a time. The processor circuitry may sequentially process additional groups of memory values. Conventional solutions using a centralized architecture may use minimal footprint because die space is only required for one processor circuitry instance and corresponding interconnect circuitry. However, conventional solutions that implement fault detection using a centralized architecture may experience slower computation speeds due to sequential processing of groups of memory values.

[0015] Other conventional solutions for fault detection may use a distributed architecture. In a distributed architecture, multiple processor circuitry instances calculate each portion of the signature. The portions of the signature are combined into a completed measured signature and compared to an expected signature. In some use cases of a distributed architecture, interconnect circuitry allows access to a given type of memory circuit from a single instance of the processor circuitry. A given processor circuitry may then use the interconnect circuitry to access values ​​from one or more types of memory circuits. The number of memories accessed by a given processor circuitry instance may depend on the similarity of memory types, the amount of computational resources available for fault detection, etc. Conventional solutions using distributed architectures may have shorter computation times than centralized architectures because multiple portions of the signature are calculated in parallel by multiple processor circuitry instances in the distributed architecture. However, conventional solutions using distributed architectures may have a larger implementation area than centralized architectures. Distributed architectures are area intensive because die space is required for each of the multiple processor circuitry instances and / or for interconnect circuitry to enable multiple data paths from the memory circuitry to the multiple processor circuitry instances.

[0016] The exemplary methods, apparatus, and systems described herein detect faults in a manner that minimizes both computation time and implementation area. Advantageously, the exemplary fault detection circuitry described herein allows parallel access to memory values ​​while implementing a single instance of processor circuitry. The exemplary fault detection circuitry described herein includes an exemplary built-in self-test (BIST) circuitry, which is a type of processor circuitry dedicated to fault detection, that sends read instructions formatted using a uniform protocol to each of the various memory types. The exemplary fault detection circuitry also includes an exemplary converter circuitry instance for converting the instructions into a format usable by the corresponding specific type of memory. The multiple memory circuits are responsive to the converted read instructions and provide the memory values ​​in parallel. The exemplary interconnect circuitry within the fault detection circuitry includes a first logic circuitry that prevents the processor circuitry from accessing the memory values ​​unless the selected multiple memory values ​​meet a power safety threshold. The exemplary interconnect circuitry further includes a second logic gate circuitry that combines the selected memory values ​​into a single data path for access by the processor circuitry.

[0017] 1 is an example block diagram of computer circuitry. Example computer circuitry 100 includes example BIST circuitry 102, example converter circuitry 104A, 104B, 104C, example memories 106A, 106B, 106C, and example interconnect circuitry 108.

[0018] The exemplary computer circuitry 100 is an example of an electronic device that may include faults. Faults may be identified as differences between measured and expected memory values ​​in the exemplary memories 106A, 106B, 106C. The exemplary computer circuitry 100 includes BIST circuitry 102, converter circuitry 104C, and interconnect circuitry 108, which may be collectively referred to as exemplary fault detection circuitry 110, to identify faults based on the contents of the exemplary memories 106A, 106B, 106C. The exemplary computer circuitry 100 may include additional components not shown in FIG.

[0019] The example BIST circuitry 102 is a type of processor circuitry that controls fault detection functions within the example computer circuitry 100. The example BIST circuitry 102 may be implemented by any type of processor circuitry. For example, the BIST circuitry 102 may be implemented as one or more field programmable gate arrays (FPGAs), central processing units (CPUs), graphic processing units (GPUs), digital signal processors (DSPs), or microcontrollers, and integrated circuits such as application specific integrated circuits (ASICs) that may instantiate instructions.

[0020] The example BIST circuitry 102 may obtain the tests from any source, including, but not limited to, external devices, other components of the computer circuitry 100, etc. The example tests are non-destructive, and the values ​​stored in the example memories 106A, 106B, 106C are the same before and after the tests. In some examples, the tests include only read operations to prevent tampering with the memories 106A, 106B, 106C or corrupting previous memory values. In other examples, the tests may include both read and write operations. In such other examples, the example BIST circuitry 102 may provide instructions to the converter circuitry 104A, 104B, 104C and the interconnect circuitry 108 such that only memory values ​​that have not been overwritten by write operations are included in the measured signature.

[0021] The example BIST circuitry 102 may obtain results of read operations from one or more of the example memories 106A, 106B, 106C from the example interconnect circuitry 108 and use the data to calculate test results. In some examples, the test results may be a measured signature that another device may use for comparison. In other examples, the BIST circuitry 102 may calculate a measured signature, compare it to an expected signature, and use the test results to identify faults in the computer circuitry 100. The example BIST circuitry 102 may share the test results with another device, provide the test results to a display, or the like.

[0022] The exemplary computer circuitry 100 includes one instance of the exemplary converter circuitry 104A, 104B, 104C for each type of memory 106A, 106B, 106C. The exemplary converter circuitry 104A, 104B, 104C receives a read command from the BIST circuitry 102 and converts the command from a uniform protocol to a format specific to the corresponding memory type. In some examples, if the uniform protocol matches the format used for the corresponding memory type, a given instance of the converter circuitry 104A does not need to convert the format of the received read command. Examples of uniform and memory specific protocols are further described in conjunction with FIG. 2. The exemplary converter circuitry 104A, 104B, 104C also enable backward compatibility for fault detection use cases designed for centralized architectures. The exemplary converter circuitry 104A, 104B, 104C are further described in conjunction with FIG. 2 and FIG. 4.

[0023] The example memories 106A, 106B, 106C are different types of memory circuits within the example computer circuitry 100. For example, each of the example memories 106A, 106B, 106C may be a volatile memory or a non-volatile memory. The volatile memory may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory may be implemented by Flash memory and / or any other desired type of memory device.

[0024] Each of the example memories 106A, 106B, 106C may store any amount of data. FIG. 3 shows three memory circuits, each having a different type, for simplicity. In practice, the example computer circuitry 100 may have any number of memory circuits. Also, in practice, some memory circuits may have different types and other memory circuits may respond to read commands using the same format. The example memories 106A, 106B, 106C receive appropriately formatted read commands from the example converter circuitry 104A, 104B, and 104C, respectively. In response to the read command, the example memories 106A, 106B, 106C provide memory values ​​to the example interconnect circuitry 108.

[0025] The example interconnect circuit element 108 obtains memory values ​​from the example memories 106A, 106B, 106C. The example interconnect circuit element 108 also receives instructions from the BIST circuit element 102 describing which memory values ​​should be blocked to meet a power safety threshold. The example interconnect circuit element 108 blocks the corresponding memory values ​​and combines the remaining memory values ​​into a single data path that is connected to the BIST circuit element 102. The example interconnect circuit element 108 is further described in conjunction with FIGS.

[0026] The exemplary computer circuitry 100 includes an exemplary fault detection circuitry 110 implemented according to the teachings of the present disclosure. Advantageously, the exemplary BIST circuitry 102 can generate a single set of read instructions that can be acquired and responded to in parallel by each of the multiple types of memories 106A, 106B, 106C due to the converter circuitry 104A, 104B, 104C. Parallel processing reduces the computation time of the exemplary fault detection circuitry 110 compared to conventional solutions using a centralized architecture. Also, the exemplary BIST circuitry 102 is a single instance of a processor circuitry that computes a signature based on multiple read values. Thus, the interconnect circuitry 108 only needs to implement a data path with a single end point. As a result, the exemplary fault detection circuitry 110 requires a smaller implementation area than conventional solutions using a distributed architecture.

[0027] 2 is an example block diagram of example converter circuitry 104A, 104B, 104C and example interconnect circuitry 108 of FIG. 1. FIG. 2 includes example computer circuitry 100, which includes example BIST circuitry 102, example converter circuitry 104A, 104B, 104C, example memories 106A, 106B, 106C, and example interconnect circuitry 108. Example converter circuitry 104A, 104B, 104C includes example format circuitry 202 and example multiplexer circuitry 204. Example converter circuitry 104C further includes example format circuitry 206 and example multiplexer circuitry 208. Example memory 106C includes example memory portions 210, 212. The example interconnect circuit element 108 includes example AND gates 214A, 214B, 214C, and 214D, and example XOR gates 216A, 216B, and 216C.

[0028] The example format circuit element 202 instance receives a read instruction for signature generation formatted in a uniform protocol from the BIST circuit element 102. The example format circuit element 202 instance converts the read instruction to a format specific to the corresponding type of memory 106A, 106B, 106C. For example, the uniform protocol sent by the BIST circuit element 102 may be designed for a memory type with a single interface. However, in the example diagram of FIG. 2, the example memory 106C has two interfaces. In some examples, the interfaces may be referred to as ports. A first port may receive read and write requests for the example memory portion 210, and a second port may receive read and write requests for the example memory portion 212. As a result, the example format circuit element 202 in the example converter circuit element 104C converts the read instruction from a single-port format to a dual-port format for the example memory portion 210. Similarly, example format circuitry 206 in example converter circuitry 104C converts the read instruction from a single port format to a dual port format for example memory portion 212. In some instances where the uniform instruction provided by the BIST circuitry specifies an address to be read, a format circuitry of the converter circuitry (e.g., format circuitry 202 or 206 of converter circuitry 104C) performs an address conversion on the address specified in the uniform instruction to determine the address to provide to the respective memory portion.

[0029] The example format circuitry 202 may convert formats other than those related to the number of ports on the example memories 106A, 106B, 106C. For example, when the BIST circuitry 102 performs a test that includes only read instructions, the uniform protocol format may be a read-only memory (ROM) format. The ROM format may inform the memory circuit that only read operations can be used when generating a response to the underlying instruction. Thus, the ROM format instruction provided by the BIST circuitry may specify an address and a read enable. However, some types of memory interfaces may support messages in read and write formats. The read and write format may inform the memory circuit that both read and write operations can be used when generating a response to the underlying instruction. In such an example, the example format circuitry 202 in one or more of the example converter circuitry 104A, 104B, 104C may convert the uniform protocol read instruction from the ROM format to the read and write format by providing a disable signal to the respective memory inputs associated with writing, such as the data write and / or write enable inputs.

[0030] The example multiplexer circuitry 204, 208 instances receive the converted instruction with the memory specific format at a first input. The example multiplexer circuitry 204, 208 instances also receive the read instruction in the original format (e.g., uniform protocol format) directly from the example BIST circuitry 102 at a second input. The example multiplexer circuitry 204, 208 instances provide one of the two formatted instructions to the corresponding example memory 106A, 106B or the corresponding example memory portion 210, 212 based on a control signal from the BIST circuitry 102. In the example described in connection with FIGS. 1, 2, and 3, the example multiplexer circuitry 204, 208 instances provide the converted instruction with the memory specific format to two or more of the example memories 106A, 106B, 106C. In such an example, the example fault detection circuitry 110 may be referred to as being in a parallel read mode.

[0031] When the example BIST circuitry 102 instructs only one of the example multiplexer circuitry 204, 208 instances to provide a memory-specific read instruction to one of the example memories 106A, 106B, 106C, the example fault detection circuitry 110 may be referred to as being in a backward compatibility mode. Backward compatibility is further described in connection with FIG.

[0032] The example AND gates 214A, 214B, 214C, 214D are circuit elements that perform a logical AND operation. The example AND gates 214A, 214B, 214C, 214D each have two inputs. A first input of each of the example AND gates 214A, 214B, 214C, 214D is coupled to one type or port of memory. For example, the example AND gate 214B receives an input from the example memory 106B, the example AND gate 214C receives an input from the example memory portion 210, etc. A second input of each of the example AND gates 214A, 214B, 214C, 214D is a control signal transmitted by the BIST circuit element 102. The control signal transmitted by the BIST circuit element 102 includes either a high power supply voltage (i.e., a logic "1" bit) or a low power supply voltage (i.e., a logic "0" bit). When a given AND gate (such as example AND gate 214A) receives a control signal with a "1" bit from BIST circuitry 102, the value from the corresponding memory (such as example memory 106A) is forwarded to the corresponding XOR gate (such as example XOR gate 216A). Alternatively, when a given example AND gate receives a control signal with a "0" bit from BIST circuitry 102, the AND gate prevents the value from the corresponding memory from reaching the corresponding XOR gate. Thus, for any given set of read instruction results generated in parallel by the example memories 106A, 106B, 106C, the subset of results that the example AND gates 214A, 214B, 214C, 214D provide to the example XOR gates 216A, 216B, 216C is separate and mutually exclusive from the subset of results that the example AND gates 214A, 214B, 214C, 214D prevent from reaching the example XOR gates 216A, 216B, 216C.

[0033] The example XOR gates 216A, 216B, 216C are circuit elements that perform logical exclusive-OR operations. That is, a given XOR gate 216A outputs a "1" bit only if one of its inputs is a "1" bit and the other input is a "0" bit. If both inputs of a given XOR gate 216A are "0" bits or if both inputs are "1" bits, the example XOR gate 216A outputs a "0" bit.

[0034] The output of the example XOR gates 216A, 216B, 216C may depend on the control signal sent to the example AND gates 214A, 214B, 214C, 214D. For example, assume that the example AND gates 214A, 214B both receive a "1" bit control signal from the BIST circuit element 102. As a result, the example XOR gate 216A may receive at its first input a first sequence of "1" and "0" bits representing a response to a read operation by the example memory 106A. The example XOR gate 216A may also receive at its second input a second sequence of "1" and "0" bits representing a response to a read operation by the example memory 106B. Thus, the example XOR gate 216A outputs a sequence of "1" and "0" bits, where a "0" bit indicates that the first and second sequences store the same bit at a particular index, and a "1" bit indicates that the first and second sequences store different bits at a particular index. As an additional example, assume that the example AND gate 214C receives a "1" bit control signal from the BIST circuit element 102, and the example AND gate 214D receives a "0" bit control signal from the BIST circuit element 102. In such an example, the output of the example XOR gate 216B may correspond to an output in response to a read operation by the example memory portion 210. The example XOR gate 216C performs a logical exclusive operation on the outputs of the example XOR gates 216A, 216B, and provides the result to the example BIST circuit element 102.

[0035] 2 shows the example interconnect circuitry 108 as four AND gates and three XOR gates, in practice a different number of logic gates may be used. The number of gates may depend on the number of memories in the example computer circuitry 100, and the number and type of gates selected may determine the interconnect output produced by the final gate (e.g., XOR216C) and used to generate the signature for a given test.

[0036] The example block diagram of Figure 2 shows how the example converter circuit elements 104A, 104B, 104C and the example interconnect circuit element 108 are implemented. Advantageously, the example converter circuit elements 104A, 104B, 104C include example format circuit elements 202, 206, which allow the BIST circuit element 102 to send a single uniform read operation, eliminating the need for the processor to sequentially generate multiple memory-specific read operations, thereby reducing computation time. Also, the example interconnect circuit element 108 includes example AND gates 214A, 214B, 214C, 214D, which allow the BIST circuit element 102 to block certain memory values ​​to meet a power safety threshold.

[0037] The example block diagram also illustrates how the example interconnect circuitry 108 implements spatial compression in the example XOR gates 216A, 216B, 216C by providing a smaller amount of data to the BIST circuitry 102 than the amount received from multiple parallel read responses. For example, assume that all AND gates 214A, 214B, 214C, 214D receive a logic "1" control signal from the BIST circuitry 102, and assume that each of the memories 106A, 106B and each of the memory portions 210, 212 provided one byte of data in response to a memory-specific read operation. In such an example, the XOR gates 216A, 216B may collectively receive a total of 32 bits of data from the memories 106A, 106B, 106C, while the XOR gate 216C may output 8 bits of data corresponding to the difference between the multiple responses of the read operation. Such a reduction in data allows a single instance of the example BIST circuitry 102 to compute the entire signature, as opposed to multiple instances each computing a portion of the signature, thereby enabling the example interconnect circuitry 108 to implement the fault-detection circuitry 110 using less die space.

[0038] 3 is an exemplary diagram of power safety requirements for the computer circuitry of FIG. 1. FIG. 3 includes an exemplary computer circuitry 100 and exemplary memory start-up periods 302, 304, 306. The exemplary computer circuitry 100 includes an exemplary BIST circuitry 102, exemplary converter circuitry 104A, 104B, 104C, exemplary memories 106A, 106B, 106C, and an exemplary interconnect circuitry 108. The exemplary converter circuitry 104A, 104B, 104C includes an exemplary format circuitry 202 and an exemplary multiplexer circuitry 204. The exemplary converter circuitry 104C further includes an exemplary format circuitry 206 and an exemplary multiplexer circuitry 208. The exemplary memory 106C includes exemplary memory portions 210, 212. The example interconnect circuit element 108 includes example AND gates 214A, 214B, 214C, and 214D, and example XOR gates 216A, 216B, and 216C.

[0039] In some examples, the computer circuitry 100 may implement a power safety threshold. As used above and herein, a power safety threshold refers to the number of read or write operations that the example memories 106A, 106B, 106C may perform in parallel. The example computer circuitry 100 may implement a power safety threshold because the act of a read or write operation may be a power intensive process and may become suboptimal and / or unsafe if too many memory circuits perform the operation at the same time. In the example diagram of FIG. 3, the computer circuitry 100 implements a power safety threshold such that no more than two read or write operations occur at a given time.

[0040] The example memories 106A, 106B, 106C include valid identifier patterns to allow the BIST circuitry 102 to send uniform protocol commands to all memories while ensuring that only a given number of memory circuits respond to the commands at a given point in time. As used herein, a valid identifier pattern refers to metadata that describes which commands are valid for a particular memory. A manufacturer may assign a valid identifier pattern to each example memory 106A, 106B, 106C in the example computer circuitry 100. Different memories may have overlapping identifier patterns. In one example, a valid identifier pattern may be an allowable address range pattern. Different memories may have overlapping valid addresses. The example memory 106A receives the translated command and determines whether the command identifier (e.g., an address) matches a valid identifier pattern (e.g., a valid address range). If the command identifier and the valid identifier pattern match, the example memory 106A is enabled and generates a response to the translated command. If the instruction identifier does not match a valid identifier pattern, the example memory 106A ignores the instruction. To ensure parallel processing, multiple memories may satisfy the valid identifier pattern for a given instruction identifier. As described above, in some examples, each of memories 106A, 106B, and 106C determines whether the instruction identifier matches a valid identifier pattern. Additionally or alternatively, each converter circuit element (e.g., converter circuit element 104A, 104B, or 104C) determines whether the instruction identifier matches a valid identifier pattern associated with the respective memory and forwards only those instructions that match the valid identifier pattern to the respective memory.

[0041] To ensure that power safety thresholds are always met, at any one time, the instructions match valid identifiers of only a subset of the memories in the example computer circuitry 100. For example, the BIST circuitry 102 may broadcast a uniform protocol read instruction to all converter circuitry 104A, 104B, 104C at once, while example memories 106A, 106B and example memory portions 210, 212 that do not meet the valid identifier pattern perform no operation, and memory components that meet the valid identifier pattern perform one or more sequential read operations. The example BIST circuitry 102 may determine which memory components to enable for the read instruction based on a schedule determined by the BIST circuitry 102. Similarly, example AND gates 214A, 214B, 214C, 214D compare the instruction identifier sent and received by BIST circuitry 102 to the valid identifier patterns for each memory component and, based on the schedule, ensure that only outputs of memory components that satisfy the valid identifier pattern are provided to example XOR gates 216A, 216B, 216C. In so doing, example AND gates 214A, 214B, 214C, 214D prevent all types of outputs from memory components that were not identified by a valid identifier pattern and therefore were not actively computing the result of the read instruction from being included in the computation of the measured signature.

[0042] In the example diagram of Figure 3, the example memory 106A includes 4096 memory addresses, the example memory 106B includes 2048 memory addresses, and each of the example memory portions 210, 212 includes 1024 memory addresses. Also in the example diagram of Figure 3, the BIST circuitry 102 does not need a memory value from the memory portion 212. The example BIST circuitry 102 may not need a value from one or more types or portions of memory if the type or portions of memory were not affected by testing.

[0043] The example BIST circuitry 102 schedules memory operations into three memory activation periods. During each activation period, only two types of memories 106A, 106B, 106C perform read operations, thus meeting the power safety threshold set by the computer circuitry 100. In the example memory activation period 302, the example BIST circuitry 102 provides read instructions to the example memory 106A and the example memory portion 210 via the corresponding converter circuitry 104A, 104C. The example BIST circuitry 102 also provides a "1" bit to the AND gates 214A, 214C, while providing a "0" bit to the AND gates 214B, 214D, during the example memory activation period 302. The example memory portion 210 performs a read operation during the example memory activation period 302 to sequentially provide values ​​of all 1024 memory addresses to the example AND gate 214C. At the same time, the example memory 106A also performs a read operation and provides values ​​from memory addresses 0-1023 to the example AND gate 214A. During the example memory activation period 302, the example XOR gates 216A, 216B also forward their respective results to the example XOR gate 216C, which compresses the results by performing a logical exclusive-OR operation and provides the results to the example BIST circuit element 102.

[0044] The example memory activation period 302 ends when 1024 addresses in the memory portion 210 are read. In the example diagram schedule of FIG. 3, the example memory activation period 302 is followed by an example memory activation period 304. During the example memory activation period 304, the example BIST circuitry 102 provides read instructions to the example memory 106A and the example memory 106B via the corresponding converter circuitry 104A, 104B. The example BIST circuitry 102 also provides a "1" bit to the AND gates 214A, 214B while providing a "0" bit to the AND gates 214C, 214D during the example memory activation period 304. The example memory portion 210 performs a read operation during the example activation period 304 to sequentially provide values ​​of all 2048 memory addresses to the example AND gate 214B. At the same time, example memory 106B also performs a read operation and provides values ​​from memory addresses 1024-3071 to example AND gate 214A. During example activation period 304, example XOR gates 216A, 216B also forward their respective results to example XOR gate 216C.

[0045] The example memory activation period 304 ends when 2048 addresses in memory 106B are read. In the example diagram schedule of FIG. 3, the example memory activation period 304 is followed by an example memory activation period 306. During the example memory activation period 304, the example BIST circuitry 102 provides a read command to the example memory 106A, provides a "1" bit to the AND gate 214A, and provides a "0" bit to the example AND gates 214B, 214C, and 214D. During the example activation period 304, the example memory 106A performs a read operation to sequentially provide values ​​of all remaining 1024 memory addresses (i.e., addresses 3072-4095) to the example AND gate 214A. 3, the example BIST circuitry 102 does not require values ​​from the memory portion 212 for signature calculation, so the example memory portion 212 does not perform a read operation during the example memory activation period 306, or any portion of the schedule. However, if the example computer circuitry 100 were implemented with the example memory 106D required for signature calculation, the first 1024 memory addresses of the example memory 106D may be read during the example memory activation period 306.

[0046] 3 illustrates how the example BIST circuitry 102 ensures that any power safety thresholds set by the computer circuitry 100 are met when retrieving memory values ​​for signature calculation. Advantageously, the example BIST circuitry 102 commands the example converter circuitry 104A, 104B, 104C, and the example interconnect circuitry 108 according to a schedule to ensure that read operations are calculated in parallel as much as possible. Thus, the example fault detection circuitry 110 minimizes calculation time while complying with system level power requirements.

[0047] 4 is an exemplary diagram of the backward compatibility of the computer circuitry of FIG. 1. FIG. 4 includes an exemplary computer circuitry 100 and a memory data path 402. The exemplary computer circuitry 100 includes an exemplary BIST circuitry 102, exemplary converter circuitry 104A, 104B, 104C, exemplary memories 106A, 106B, 106C, and an exemplary interconnect circuitry 108. The exemplary converter circuitry 104A, 104B, 104C includes an exemplary format circuitry 202 and an exemplary multiplexer circuitry 204. The exemplary converter circuitry 104C further includes an exemplary format circuitry 206 and an exemplary multiplexer circuitry 208. The exemplary memory 106C includes exemplary memory portions 210, 212. The example interconnect circuit element 108 includes example AND gates 214A, 214B, 214C, and 214D, and example XOR gates 216A, 216B, and 216C.

[0048] In some examples, the BIST circuitry 102 may receive tests designed for fault detection circuitry with a centralized architecture. For example, the tests may expect the BIST circuitry 102 to sequentially obtain values ​​from example memories 106A, 106B, 106C. In such examples, the BIST circuitry 102 may enter a backward compatibility mode.

[0049] 4 illustrates a first stage of the backward compatibility mode, during which the BIST circuitry 102 accesses only memory values ​​from the example memory 106A. During the first stage, the example BIST circuitry 102 may provide a "0" to each of the instances of the example multiplexer circuitry 204, 208. As a result, each of the previous circuitry instances receives the original, untranslated read instruction from the example BIST circuitry 102.

[0050] 1, 2, and 3, the instructions provided by the example BIST circuitry 102 in the backward compatibility mode are not provided in a uniform protocol. Rather, the example BIST circuitry 102 may send instructions specifically formatted for memory 106A during the first phase. As a result, the example memories 106B, 106C may not be able to perform read operations based on the instructions.

[0051] The example memories 106B, 106C may additionally or alternatively generate error codes in response to receiving improperly formatted instructions. To prevent the error codes or other unwanted data output by the example memories 106B, 106C from being used during the first stage, the example BIST circuitry 102 may provide a "0" bit to AND gates 214B, 214C, 214D, thereby blocking the output.

[0052] In the example first phase, the XOR gates 216A, 216C forward the memory instruction results from the example memory 106A without modification to the example BIST circuitry 102. The example memory data path 402 illustrates the complete flow of data during the first phase of the backward compatibility mode. Once the example BIST circuitry 102 receives the read results from the memory 106A and calculates the partial signature, the BIST circuitry 102 may transition sequentially between stages of backward compatibility. In each stage of backward compatibility, the example BIST circuitry 102 may provide instructions to obtain memory results from a different one of the memories 106A, 106B, or memory portions 210, 212.

[0053] 4 enables the example fault detection circuitry 110 to accept instructions and provide equivalent results that were designed for traditional solutions with centralized architectures. When not in the backward compatibility mode, the example fault detection circuitry 110 may accept tests designed to enhance parallel computation and power safety threshold functionality, as described in conjunction with FIGS. 1, 2, and 3.

[0054] Figure 5 shows two graphs illustrating the performance across multiple example simulations of the computer circuitry of Figure 1. Figure 5 includes example graphs 502, 504.

[0055] The example graph 502 compares the footprint required for the example fault identification circuitry with the footprint required for a conventional solution. On the y-axis of the example graph 502, the footprint is measured in thousands of logic gates. The footprints of the conventional example with a centralized architecture, the conventional example with a distributed architecture, and the example fault detection circuitry 110 are compared for four different computer circuitry implementations. The x-axis of the example graph 502 shows the number of different volatile memory circuits (RAM) in each of the four computer circuitry implementations. The example graph 502 shows that as the number of RAM circuits in the computer circuitry increases, each type of fault detection circuitry requires additional logic gates to map the memory to one or more processor circuitry instances. The example graph 502 also shows that the example fault detection circuitry requires, on average, approximately 20% more gates than the conventional solution with a centralized architecture and 30% less gates than the conventional solution with a distributed architecture.

[0056] The example graph 504 compares the fault identification computation speed of the example computer circuitry 100 with 30 different computer circuitry implementations, each including a conventional solution for fault detection with a centralized architecture. The x-axis of the example graph 504 shows the index value assigned to each of the 30 different computer circuitry implementations. The y-axis of the example graph 504 shows the test time reduction, which measures how much faster the example fault detection circuitry 110 is at performing tests and accessing memory values ​​compared to the indexed conventional solutions. The test time reduction may be calculated by dividing the time required by a particular conventional solution to perform a particular test and compute a particular signature by the time required by the example fault detection circuitry 110 to perform the same test and compute the same signature. The example graph 504 shows that the example fault detection circuitry 110 is, on average, about 9 times faster than the conventional solution for fault detection with a centralized architecture. The magnitude of the test reduction corresponding to a particular computer circuitry may be based in part on the number of parallel operations the computer circuitry can perform due to power safety thresholds.

[0057] FIG. 6 is a flowchart representing an example process that may be implemented using executable machine-readable instructions and / or the computer circuitry of FIG. 1 and / or, more generally, hardware configured to implement the fault detection circuitry of FIG. 1 for identifying faults in memory.

[0058] The example machine-readable instructions and / or operations 600 begin when the example BIST circuitry 102 selects a subset of memory circuits based on a power safety threshold (block 602). The example BIST circuitry 102 may select the subset of memories 106A, 106B, 106C such that a power safety threshold is met, which may limit the number of memory circuits that can actively perform read and write operations in parallel.

[0059] The example BIST circuitry 102 provides a read command formatted in a uniform protocol (block 604). The example BIST circuitry 102 provides a read command to each of the example converter circuitry 104A, 104B, 104C as part of a test to identify faults in the example memories 106A, 106B, 106C. The read command may include a valid identifier pattern that indicates which memory circuits are included in the subset of block 602.

[0060] One or more of the example converter circuit elements 104A, 104B, 104C convert the read command to one or more memory-specific protocols (block 606). The example converter circuit elements 104A, 104B, 104C may analyze for valid identifier patterns to determine whether to convert the read command from the uniform protocol to a memory-specific protocol. In some examples, only converter circuit element instances that correspond to memory circuits listed in the subset of block 602 convert the read command in block 606.

[0061] The example memories 106A, 106B, 106C generate memory-specific results for the read command based on the subset of block 602 (block 608). Specifically, only the subset of memory circuits identified in the subset of block 602 may receive the read command in a readable format (i.e., a memory-specific protocol) that enables the memory circuits to generate a result. The remaining memory circuits may not receive the read command at all or may receive the read command in an unreadable format (such as a uniform protocol).

[0062] The example interconnect circuit element 108 combines the memory identification results as an output (block 610). To combine the memory identification results as an output, the example AND gates 214A, 214B, 214C allow only outputs from memory circuits listed in the valid identifier pattern (i.e., memory circuits in the subset of the block 602) to be provided to the example XOR gates 216A, 216B, 216C. The example AND gates 214A, 214B, 214C prevent any outputs from memory circuits not in the subset of the block 602 from being used to identify a fault. After receiving one or more results of the read command from the AND gates 214A, 214B, 214C, the example XOR gates 216A, 216B, 216C combine the one or more results as a smaller amount of data (i.e., the output of the block 610).

[0063] The example BIST circuitry 102 calculates a measured signature based on the outputs (block 612). The measured signature may be a value representative of a response from each of the memory circuits in the subset of blocks 602.

[0064] The example BIST circuitry 102 compares the measured signature to the expected signature (block 614). The example BIST circuitry 102 compares the measured signature to the expected signature to identify faults in the memory circuits in the subset of block 602. In some examples, the example computer circuitry 100 may repeatedly implement the operations described in the flowchart of FIG. 6, with each iteration using different memory circuits and / or different address chunks included in the valid identifier pattern. In doing so, the example computer circuitry 100 may generate multiple measured signatures such that all of the example memories 106A, 106B, 106C are tested for faults. The example machine-readable instructions and / or operations 600 end after block 614.

[0065] In this description, the term "and / or" (when used in the form A, B, and / or C, etc.) refers to any combination or subset of A, B, and C, such as (a) A only, (b) B only, (c) C only, (d) A and B, (e) A and C, (f) B and C, and (g) A, B and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to an implementation that includes (a) at least one A, (b) at least one B, and (c) at least one A and at least one B.

[0066] The example methods, apparatus, and articles of manufacture described herein improve the computation time and implementation area of ​​fault detection circuitry. Advantageously, the example fault detection circuitry 110 allows parallel access to memory values ​​while implementing a single instance of the processor circuitry (i.e., the example BIST circuitry 102). The example BIST circuitry 102 sends read instructions formatted using a uniform protocol to the example memories 106A, 106B, 106C having different protocols. The example fault detection circuitry 110 includes example converter circuitry 104A, 104B, 104C for converting the instructions to a format usable by the corresponding particular type of memory. The example fault detection circuitry 110 also includes AND gates 214A, 214B, 214C, 214D for ensuring that the total number of parallel read operations meets a power safety threshold. The example fault detection circuitry 110 further includes XOR gates 216A, 216B, 216C for performing spatial compaction and providing data to the example BIST circuitry 102 for signature calculation.

[0067] The term "couple" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with the description of this description. For example, in a first example, device A is coupled to device B if device A provides a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C, allowing device B to be controlled by device A via a control signal generated by device A, where the intervening component C does not substantially change the functional relationship between device A and device B.

[0068] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) to perform that function by a manufacturer at the time of manufacture, or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, or through the configuration and / or layout of hardware components, device interconnections, or a combination thereof.

[0069] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are used generally to mean an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0070] A circuit or device described as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and be adapted to be coupled to at least some of the passive elements and / or sources to thereby form the described structure, either at the time of manufacture or at a time thereafter, e.g., by an end user and / or a third party.

[0071] The circuits described herein may be reconfigurable to include replaced components and provide functionality at least partially similar to that available prior to the replacement of the components. Unless otherwise indicated, a component illustrated as a resistor generally represents any one or more elements coupled in series or parallel to provide the amount of impedance represented by the illustrated resistor. For example, a resistor described herein as a single component may instead be multiple resistors or capacitors, each of which may be multiple resistors coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes, each of which may be a single resistor or capacitor. Modifications in the described embodiments are possible and other embodiments are possible within the scope of the claims.

Claims

1. A device, a first circuit, receiving a first result from the first memory circuit; receiving a second result from the second memory circuit; combining the first result with the second result to generate a combined result; the first circuit configured as follows: a second circuit, determining a measured signature based on the combined result; determining whether a fault exists in at least one of the first memory circuit and the second memory circuit based on a comparison of the measured signature with an expected signature; the second circuit configured as follows: Including, the device.

2. A device as claimed in claim 1, a third circuit, Receive the action, converting the operations into a first format specific to the first memory circuit; converting the operations into a second format specific to the second memory circuit; providing the operations in the first and second formats to the first and second memory circuits to receive the first and second results from the first and second memory circuits; The device further comprises the third circuit configured to:

3. A device as claimed in claim 2, the third circuit comprises: converting the operations into a third format specific to a third memory circuit; providing the operations in the third format to the third memory circuit; The device further configured as follows.

4. A device according to claim 3, the second circuit is further configured to select the first and second memory circuits rather than the third memory circuit so as to receive first and second results from the first and second memory circuits rather than results from the third memory circuit.

5. The device of claim 4, the second circuit is further configured to select the first and second memory circuits rather than the third memory circuit based on selectively preventing transfer of results from the third memory circuit to the first circuit.

6. The device of claim 4, the second circuit is further configured to select the first and second memory circuits rather than the third memory circuit based on a valid identifier pattern; The device, wherein the valid identifier pattern indicates that the first and second memory circuits, but not the third memory circuit, are authorized to perform the operation.

7. The device of claim 4, the second circuit is further configured to select the first and second memory circuits over the third memory circuit based on a power safety threshold; The device, wherein the power safety threshold represents the number of read or write operations that are permitted to be performed in parallel by the first, second, and third memory circuits.

8. The device of claim 2, the third circuit includes a first sub-circuit configured to convert the operations into the first format and a second sub-circuit configured to convert the operations into the second format; the second circuit is further configured to transmit the operation to the first and second sub-circuits.

9. The device of claim 2, A device wherein the operation is a read operation.

10. The device of claim 1, A device wherein the first memory circuit is of a different type than the second memory circuit.

11. The device of claim 1, the first circuit includes an XOR gate configured to combine the first result and the second result to generate the combined result.

12. A method comprising: receiving a first result from the first memory circuit and a second result from the second memory circuit; combining the first result with the second result; determining a measured signature based on the combined result; determining whether a fault exists in at least one of the first memory circuit and the second memory circuit based on a comparison of the measured signature and an expected signature; A method comprising:

13. The method of claim 12, comprising: Receiving the action; transmitting the operation to the first and second circuits; converting, by the first circuit, the operations into a first format specific to the first memory circuit; converting, by the second circuit, the operations into a second format specific to the second memory circuit; providing the operations in the first and second formats to the first and second memory circuits, respectively, such that the first and second memory circuits provide the first and second results, respectively; The method further comprises:

14. The method of claim 13, transmitting the operation to a third circuit in addition to the first and second circuits; converting, by the third circuit, the operations into a third format specific to a third memory circuit; providing the operations in the third format to the third memory circuit; The method further comprises:

15. The method of claim 14, selecting the first and second memory circuits rather than the third memory circuit to receive the first and second results from the first and second memory circuits rather than the results from the third memory circuit.

16. The method of claim 15, The method, wherein selecting the first and second memory circuits over the third memory circuit includes selectively preventing transfer of results from the third memory circuit.

17. The method of claim 15, The method, wherein selecting the first and second memory circuits rather than the third memory circuit includes providing a valid identifier pattern to the first, second, and third memory circuits, the valid identifier pattern indicating that the first and second memory circuits, but not the third memory circuit, are permitted to perform the execution.

18. The method of claim 15, The method, wherein selecting the first and second memory circuits over the third memory circuit includes selecting the first and second memory circuits over the third memory circuit based on a power safety threshold, the power safety threshold representing the number of read or write operations permitted to be performed by the first, second, and third memory circuits.

19. The method of claim 13, comprising: The method, wherein the operation is a read operation.

20. The method of claim 12, The method, wherein combining the first result with the second result includes combining the first result with the second result using an XOR gate.

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