An I2C master-slave device joint verification platform and an I2C master-slave device joint verification method

Abstract

This invention discloses an I2C master-slave device joint verification platform, comprising: a design module including an I2C master device and an I2C slave device, which are connected via data lines and control lines; an interface including a first interface and a second interface; and a verification module including a first proxy module, a second proxy module, and a comparator. The first proxy module is connected to the first interface, the second proxy module is connected to the second interface, and the first and second proxy modules are connected via the comparator. The first proxy module is configured to capture first write transaction data / second read transaction data of the I2C master device through the first interface, the second proxy module is configured to capture first read transaction data / second write transaction data of the I2C slave device through the second interface, and the comparator is configured to compare the first write transaction data / second read transaction data with the first read transaction data / second write transaction data. This invention also discloses an I2C master-slave device joint verification method.

Description

Technical Field

[0001] This invention relates to the field of simulation verification technology, and in particular to an I2C master-slave device joint verification platform and an I2C master-slave device joint verification method. Background Technology

[0002] In recent years, with the continuous expansion of digital integrated circuit design scale, chip verification workload accounts for more than 70% of the chip design cycle, and building a verification platform is the core part of the verification work. It can be said that the efficiency of a verification platform and the reusability of its components directly determine the success or failure of a chip design.

[0003] To improve verification processes, commercial hardware verification languages ​​have emerged. Currently, SystemVerilog is the mainstream verification language, which can be used to build verification platforms. However, a unified standard for how to build such platforms is lacking. To standardize the construction of verification platforms and establish a unified principle between electronic design automation (EDA) vendors and users, Accellera proposed a universal verification methodology standard, which has received support from three major vendors: Mentor, Cadence, and Synopsys. UVM (Universal Verification Methodology) is a verification platform development framework based on the SystemVerilog class library. UVM provides verification engineers with rich class libraries and advanced verification techniques, enabling reuse of verification platforms from the module level to the system level, greatly improving verification efficiency. Summary of the Invention

[0004] In view of this, the purpose of this invention is to propose an I2C master-slave device joint verification platform and method. The I2C master and slave devices are connected via SCL (control line) and SDA (data line) to form a design module to be verified. This not only reflects real-world scenarios but also improves efficiency, allowing the I2C master and slave modules to be simulated and verified simultaneously. A flexible and configurable verification environment enhances the sufficiency of verification and ensures the rigor of the verification process. Furthermore, component reusability significantly reduces labor costs and improves verification efficiency.

[0005] Based on the above objectives, one aspect of the present invention provides an I2C master-slave device joint verification platform, comprising: a design module, the design module including an I2C master device and an I2C slave device, the I2C master device and the I2C slave device being connected via a data line and a control line; an interface, the interface including a first interface and a second interface, the first interface being connected to the I2C master device and the second interface being connected to the I2C slave device; and a verification module, the verification module including a first proxy module, a second proxy module and a comparator, the first proxy module being connected to the first interface, the second proxy module being connected to the second interface, and the first proxy module and the second proxy module being connected via the comparator; wherein, the first proxy module is configured to capture first write transaction data / second read transaction data of the I2C master device through the first interface, the second proxy module is configured to capture first read transaction data / second write transaction data of the I2C slave device through the second interface, and the comparator is configured to compare the first write transaction data / second read transaction data with the first read transaction data / second write transaction data.

[0006] In some embodiments, the first agent module / second agent module further includes: a sequence generator configured to generate a transaction sequence; a driver connected to the sequence generator and the first interface / second interface, configured to send write transaction instructions or read transaction instructions to the first agent module / second agent module through the first interface / second interface according to the transaction configuration sequence; and a monitor connected to the comparator and the first interface / second interface, configured to capture data from the I2C master device / I2C slave device through the first interface / second interface and send the data to the comparator for comparison.

[0007] In some implementations, the verification module further includes: a sequence generator configured to send transaction configuration instructions to the sequence generator of the first proxy module / the second proxy module.

[0008] In some implementations, the verification module is further configured to: in response to receiving a notification verifying the write direction of the design module, send a write transaction configuration instruction to the sequence generator of the first proxy module and a read transaction configuration instruction to the sequence generator of the second proxy module.

[0009] In some implementations, the first agent module is further configured to: in response to receiving a write transaction configuration instruction, generate a write transaction sequence by the sequence generator and send a write transaction stimulus to the I2C master device by the driver through the first interface; and have the monitor capture the write transaction data of the I2C master device through the first interface and send the write transaction data to the comparator.

[0010] In some implementations, the second agent module is further configured to: in response to receiving a read transaction configuration instruction, generate a read transaction sequence by the sequence generator and send a read transaction stimulus to the I2C slave device by the driver through the second interface; and have the monitor capture the read transaction data of the I2C slave device through the second interface and send the read transaction data to the comparator.

[0011] In some implementations, the verification module is further configured to: in response to receiving a notification verifying the read direction of the design module, send a read transaction configuration instruction to the sequence generator of the first proxy module and a write transaction configuration instruction to the sequence generator of the second proxy module.

[0012] In some implementations, the I2C master device / the I2C slave device is configured with an APB interface for connecting to the first interface / the second interface for data interaction.

[0013] In another aspect of this invention, a method for joint verification of I2C master and slave devices is provided. The testing method is applied to the testing platform described above and includes the following steps: a first proxy module captures first write transaction data / second read transaction data of the I2C master device through a first interface, and a second proxy module captures first read transaction data / second write transaction data of the I2C slave device through a second interface; a comparator compares the first write transaction data / second read transaction data with the first read transaction data / second write transaction data to determine whether they are consistent; in response to the determination of consistency, the verification is passed.

[0014] In some implementations, the method further includes: in response to receiving a notification of the write direction from the verification design module, the main sequence generator sends a write transaction configuration instruction to the sequence generator of the first agent module and a read transaction configuration instruction to the sequence generator of the second agent module.

[0015] This invention offers at least the following beneficial technical effects: By connecting the I2C master and slave devices via SCL (control line) and SDA (data line) to form a design module to be verified, it not only reflects real-world scenarios but also improves efficiency, allowing the I2C master and slave modules to be simulated and verified simultaneously. The flexible and configurable verification environment enhances the sufficiency of verification and ensures the rigor of the verification process. Furthermore, the reusability of components significantly reduces labor costs and improves verification efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of an embodiment of the I2C master-slave device joint verification platform provided by the present invention;

[0018] Figure 2 A schematic diagram of an embodiment of the I2C master-slave device joint verification platform provided by the present invention;

[0019] Figure 3 This is a schematic diagram of an embodiment of the I2C master-slave device joint verification method provided by the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0021] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0022] Based on the above objectives, the first aspect of the present invention proposes an I2C master-slave device joint verification platform. Figure 1 The diagram shown is a schematic representation of an embodiment of the I2C master-slave device joint verification platform provided by the present invention. Figure 1 As shown, the I2C master-slave device joint verification platform of this invention includes:

[0023] The design module includes an I2C master device and an I2C slave device, which are connected via data lines and control lines.

[0024] The interface includes a first interface and a second interface. The first interface is connected to the I2C master device, and the second interface is connected to the I2C slave device.

[0025] The verification module includes a first proxy module, a second proxy module, and a comparator. The first proxy module is connected to a first interface, the second proxy module is connected to a second interface, and the first proxy module and the second proxy module are connected through a comparator.

[0026] The first proxy module is configured to capture the first write transaction data / second read transaction data of the I2C master device through the first interface, the second proxy module is configured to capture the first read transaction data / second write transaction data of the I2C slave device through the second interface, and the comparator is configured to compare the first write transaction data / second read transaction data with the first read transaction data / second write transaction data.

[0027] In some embodiments of the present invention, the first agent module / second agent module further includes: a sequence generator configured to generate a transaction sequence; a driver connected to the sequence generator and the first interface / second interface, configured to send write transaction instructions or read transaction instructions to the first agent module / second agent module through the first interface / second interface according to the transaction configuration sequence; and a monitor connected to a comparator and the first interface / second interface, configured to capture data from the I2C master device / I2C slave device through the first interface / second interface and send the data to the comparator for comparison.

[0028] In some embodiments of the present invention, the verification module further includes: a total sequence generator configured to send transaction configuration instructions to the sequence generator of the first agent module / second agent module.

[0029] In some embodiments of the present invention, the verification module is further configured to: in response to receiving a notification of the write direction from the verification design module, send a write transaction configuration instruction to the sequence generator of the first agent module and a read transaction configuration instruction to the sequence generator of the second agent module.

[0030] In some embodiments of the present invention, the first agent module is further configured to: in response to receiving a write transaction configuration instruction, generate a write transaction sequence by a sequence generator and send a write transaction stimulus to the I2C master device through a first interface by a driver; and capture the write transaction data of the I2C master device through the first interface by a monitor and send the write transaction data to a comparator.

[0031] In some embodiments of the present invention, the second agent module is further configured to: in response to receiving a read transaction configuration instruction, generate a read transaction sequence by a sequence generator and send a read transaction stimulus to the I2C slave device by a driver through a second interface; and have a monitor capture the read transaction data of the I2C slave device through the second interface and send the read transaction data to a comparator.

[0032] In some embodiments of the present invention, the verification module is further configured to: in response to receiving a read direction notification from the verification design module, send a read transaction configuration instruction to the sequence generator of the first agent module and a write transaction configuration instruction to the sequence generator of the second agent module.

[0033] In some embodiments of the present invention, the I2C master device / I2C slave device is configured with an APB interface for connecting to a first interface / second interface for data interaction.

[0034] The specific embodiments of the present invention are further described below with reference to specific examples. Figure 2 This diagram illustrates an embodiment of the I2C master-slave device joint verification platform provided by the present invention. (See reference) Figure 2 The design module connects the I2C master and slave devices via SCL and SDA lines to form a design module that needs to be verified. This not only reflects the real-world environment but also improves efficiency, allowing the I2C (Integrated Circuit Bus) master and slave devices to be simulated and verified simultaneously. The I2C master and slave devices have SCL and SDA interfaces on one side, and standard APB interfaces on the other.

[0035] The verification module is connected via an interface for sending stimuli and exchanging data. For the verification module, this invention adopts a hierarchical structure consistent with general verification platforms, including transaction control and management. Various platform components are instantiated in the `env`, including: Sequencer, V_Sequencer, Driver, Monitor, Agent, and Scoreboard. Information exchange between each component is transmitted via a specific TLM port. V_Sequencer primarily coordinates the work of the Sequencers in the two Agents; the Agent mainly encapsulates the Sequencer, Driver, and Monitor together for easier management and operation; the Scoreboard primarily compares data to determine the correctness of test cases. Regarding the three components in the agent, Sequencer is the sequence generator, which mainly attaches sequences and then issues the relevant transaction sequences; Driver is the driver, which mainly drives the data in the transaction to the design module; Monitor mainly captures the data on the interface and sends it to the Scoreboard, which then performs data comparison.

[0036] Throughout the verification process, the data flow is divided into two directions: write and read. For the write direction, the I2C master device verification platform provides write data stimuli, and the I2C slave device verification platform provides read addresses to read the corresponding data. V_Sequence is mounted on V_Sequencer, which invokes two proxy modules. The first proxy module is configured as a write transaction, which is passed to the interface via the driver and then to the design module. Simultaneously, the monitor captures the write transaction data and sends it to the scoreboard. The second proxy module is configured as a read transaction, which is also passed to the interface via the driver and then to the design module. The design module then sends the read data to the interface, and the monitor captures the read transaction data and sends it to the scoreboard. Finally, the scoreboard compares the write and read transaction data; a correct comparison result indicates a correct test result. The read direction is the opposite of the write direction. The basic data flow of the verification platform is as follows: the incentive information for the verification module is collected in a Transaction; the Transaction is collected in a Sequence (data sequence); the Sequence is attached to a Sequencer; and then the data sequence is given to the driver component and sent to the verification module. This verification environment is flexible and configurable, and the verification components are reusable. Therefore, this invention not only improves verification sufficiency but also saves manpower costs due to component reusability.

[0037] The above description discloses only one embodiment of the present invention and should not be construed as limiting the scope of the invention. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments and making equivalent changes in accordance with the claims of the present invention are still within the scope of the present invention.

[0038] Based on the above objectives, a second aspect of the present invention proposes an I2C master-slave device joint verification method. Figure 3 The diagram shown is a schematic representation of an embodiment of the I2C master-slave device joint verification method provided by the present invention. Figure 3 As shown, the I2C master-slave device joint verification method of this invention includes: S01, the first proxy module captures the first write transaction data / second read transaction data of the I2C master device through the first interface, and the second proxy module captures the first read transaction data / second write transaction data of the I2C slave device through the second interface; S02, the comparator compares the first write transaction data / second read transaction data and the first read transaction data / second write transaction data to determine whether they are consistent; S03, in response to the determination that they are consistent, the verification is successful.

[0039] In some embodiments of the present invention, the method further includes: in response to receiving a notification of the write direction from the verification design module, the main sequence generator sends a write transaction configuration instruction to the sequence generator of the first agent module and a read transaction configuration instruction to the sequence generator of the second agent module.

[0040] It should be noted that the steps in each embodiment of the above-mentioned I2C master-slave device joint verification method can be interleaved, substituted, added, or deleted. Therefore, these reasonable permutations and combinations of the I2C master-slave device joint verification method should also fall within the protection scope of this invention, and the protection scope of this invention should not be limited to the embodiments.

[0041] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program for the I2C master-slave device joint verification method can be stored in a computer-readable storage medium. When executed, the program can include the processes of the embodiments of the above methods. The storage medium for the program can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The above computer program embodiments can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0042] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. When the computer program is executed by the processor, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0043] Furthermore, the above-described method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to perform the functions of the above-described steps or units.

[0044] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0045] In one or more exemplary designs, functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Computer-readable media include computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another. Storage media may be any available medium accessible to a general-purpose or special-purpose computer. By way of example, and not limitation, computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that may be used to carry or store the required program code in the form of instructions or data structures and is accessible to a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection may be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the aforementioned coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of media. As used herein, disks and optical discs include compact discs (CDs), laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0046] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0047] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0048] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0049] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0050] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. An I2C master-slave device joint verification platform, characterized in that, include: The design module includes an I2C master device and an I2C slave device, which are connected via data lines and control lines. The interface includes a first interface and a second interface, wherein the first interface is connected to the I2C master device and the second interface is connected to the I2C slave device; The verification module includes a first proxy module, a second proxy module, and a comparator. The first proxy module is connected to the first interface, the second proxy module is connected to the second interface, and the first and second proxy modules are connected through the comparator. The first proxy module is configured to capture the first write transaction data / second read transaction data of the I2C master device through the first interface, the second proxy module is configured to capture the first read transaction data / second write transaction data of the I2C slave device through the second interface, and the comparator is configured to compare the first write transaction data / second read transaction data with the first read transaction data / second write transaction data. The data flow in the above verification process includes write and read directions. In the write direction, the I2C master device verification platform provides write data stimulus, and the I2C slave device verification platform provides read address to read the corresponding data. In the read direction, the I2C slave device verification platform provides write data stimulus, and the I2C master device verification platform provides read address to read the corresponding data.

2. The I2C master-slave device joint verification platform according to claim 1, characterized in that, The first agent module / the second agent module further includes: Sequence generator, configured to generate transaction sequences; A driver, connected to the sequence generator and the first interface / second interface, configured to send write transaction instructions or read transaction instructions to the first agent module / second agent module through the first interface / second interface according to the transaction configuration sequence; A monitor, connected to the comparator and the first interface / second interface, is configured to capture data from the I2C master device / the I2C slave device through the first interface / second interface and send the data to the comparator for comparison.

3. The I2C master-slave device joint verification platform according to claim 2, characterized in that, The verification module also includes: A sequence generator is configured to send transaction configuration instructions to the sequence generator of the first agent module / the second agent module.

4. The I2C master-slave device joint verification platform according to claim 3, characterized in that, The verification module is further configured to: In response to receiving a notification to verify the write direction of the design module, the main sequence generator sends a write transaction configuration instruction to the sequence generator of the first agent module and a read transaction configuration instruction to the sequence generator of the second agent module.

5. The I2C master-slave device joint verification platform according to claim 4, characterized in that, The first agent module is further configured to: In response to receiving a write transaction configuration instruction, the sequence generator generates a write transaction sequence, and the driver sends a write transaction incentive to the I2C master device through the first interface; The monitor captures the write transaction data of the I2C master device through the first interface and sends the write transaction data to the comparator.

6. The I2C master-slave device joint verification platform according to claim 4, characterized in that, The second agent module is further configured to: In response to receiving a read transaction configuration instruction, the sequence generator generates a read transaction sequence, and the driver sends a read transaction incentive to the I2C slave device through the second interface; The monitor captures the read transaction data of the I2C slave device through the second interface and sends the read transaction data to the comparator.

7. The I2C master-slave device joint verification platform according to claim 3, characterized in that, The verification module is further configured to: In response to receiving a notification to verify the read direction of the design module, the main sequence generator sends a read transaction configuration instruction to the sequence generator of the first agent module and a write transaction configuration instruction to the sequence generator of the second agent module.

8. The I2C master-slave device joint verification platform according to claim 1, characterized in that, The I2C master device / the I2C slave device is configured with an APB interface for connecting to the first interface / the second interface for data interaction.

9. A method for joint verification of I2C master and slave devices, characterized in that, The verification method is applied to the verification platform according to any one of claims 1-8, and the verification method includes the following steps: The first proxy module captures the first write transaction data / second read transaction data of the I2C master device through the first interface, and the second proxy module captures the first read transaction data / second write transaction data of the I2C slave device through the second interface; The comparator compares the first write transaction data / second read transaction data with the first read transaction data / second write transaction data to determine whether they are consistent; If the response matches the judgment, the verification passes; The data flow in the above verification process includes write and read directions. In the write direction, the I2C master device verification platform provides write data stimulus, and the I2C slave device verification platform provides read address to read the corresponding data. In the read direction, the I2C slave device verification platform provides write data stimulus, and the I2C master device verification platform provides read address to read the corresponding data.

10. The I2C master-slave device joint verification method according to claim 9, characterized in that, Also includes: In response to receiving a write direction notification from the verification design module, the main sequence generator sends a write transaction configuration instruction to the sequence generator of the first agent module and a read transaction configuration instruction to the sequence generator of the second agent module.

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