Micro LED, Micro LED Array Panel and Manufacturing Method Thereof

Abstract

The micro LED includes a first type of semiconductor layer and a light emitting layer formed on the first type of semiconductor layer, the first type of semiconductor layer including a mesa structure, a trench, and an ion implantation fence separated from the mesa structure by the trench, the ion implantation fence being formed around the trench and the trench being formed around the mesa structure, and an electrical resistance of the ion implantation fence being higher than the electrical resistance of the mesa structure.

Description

[Technical field]

[0001] The present disclosure relates generally to light emitting diodes, and more particularly to micro light emitting diodes (LEDs), micro LED array panels, and methods for manufacturing the same. [Background technology]

[0002] Inorganic micropixel light-emitting diodes, also known as micro light-emitting diodes, microLEDs or μ-LEDs, are gaining importance for use in a variety of applications including self-emissive microdisplays, visible light communications, and optogenetics. MicroLEDs exhibit higher power performance than conventional LEDs due to better strain relief, improved light extraction efficiency, and uniform current spreading.

[0003] Inorganic micro-LEDs are traditionally III-V epitaxial layers formed as multiple mesas. In traditional micro-LED structures, a space is formed between adjacent micro-LEDs to avoid carriers in the epitaxial layers from diffusing from one mesa to the adjacent mesa. However, the space formed between adjacent micro-LEDs can reduce the active light-emitting area and reduce the light extraction efficiency. If there is no space between adjacent micro-LEDs, the active light-emitting area increases and carriers in the epitaxial layers diffuse laterally toward the adjacent mesas, reducing the light-emitting efficiency of the micro-LEDs. In addition, if there is no space between adjacent mesas, crosstalk will occur between adjacent micro-LEDs, interfering with the operation of the micro-LEDs.

[0004] However, smaller micro LEDs with higher current densities experience red shifts at high current densities, reduced maximum efficiency, and non-uniform emission, which are attributed to damage in the fabrication process, resulting in poor electrical injection. Furthermore, the peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) decrease significantly with decreasing chip size. The decrease in EQE is due to non-radiative recombination caused by etching damage, while the decrease in IQE is due to poor current injection and electron leakage current in micro LEDs.

[0005] The above discussion is merely intended to aid in understanding the technical problem overcome by the present disclosure, and is not an admission that the above is prior art. Summary of the Invention

[0006] An embodiment of the present disclosure provides a micro-LED, the micro-LED including a first type of semiconductor layer and a light emitting layer formed on the first type of semiconductor layer, the first type of semiconductor layer including a mesa structure, a trench, and an ion implantation fence separated from the mesa structure by the trench, the ion implantation fence being formed around the trench, the trench being formed around the mesa structure, and an electrical resistance of the ion implantation fence being higher than an electrical resistance of the mesa structure.

[0007] An embodiment of the present disclosure provides a micro LED array panel, the micro LED array panel includes a first type of semiconductor layer formed in the micro LED array panel, a light emitting layer formed on the first type of semiconductor layer, a second type of semiconductor layer formed on the light emitting layer, the first type of semiconductor layer has a P-type conductivity type and the second type of semiconductor layer has an N-type conductivity type, the first type of semiconductor layer includes a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches, a top surface of the ion implantation fences is lower than a top surface of the first type of semiconductor layer, the ion implantation fences are formed in the trenches between adjacent types of mesa structures, and an electrical resistance of the ion implantation fences is higher than an electrical resistance of the mesa structures.

[0008] An embodiment of the present disclosure provides a method for manufacturing a micro LED, the method including: providing an epitaxial structure including, in top-down order, a first type of semiconductor layer, a light emitting layer, and a second type of semiconductor layer, patterning the first type of semiconductor layer to form a mesa structure, a trench, and a fence, depositing a bottom contact on the mesa structure, and performing an ion implantation process on the fence to form an ion-implanted fence.

[0009] An embodiment of the present disclosure provides a micro LED, the micro LED includes a first type of semiconductor layer, a light emitting layer formed on the first type of semiconductor layer, and a second type of semiconductor layer formed on the light emitting layer, the first type of semiconductor layer has a P-type conductivity type, the second type of semiconductor layer has an N-type conductivity type, the second type of semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, a bottom surface of the ion implantation fence is higher than a bottom surface of the second type of semiconductor layer, the ion implantation fence is formed around the trench, the trench is formed around the mesa structure, and an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.

[0010] An embodiment of the present disclosure provides a micro LED array panel, the micro LED array panel includes a first type of semiconductor layer formed in the micro LED array panel, a light emitting layer formed on the first type of semiconductor layer, a second type of semiconductor layer formed on the light emitting layer, the first type of semiconductor layer has a P-type conductivity type and the second type of semiconductor layer has an N-type conductivity type, the second type of semiconductor layer includes a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches, a bottom surface of the ion implantation fences is higher than a bottom surface of the second type of semiconductor layer, the ion implantation fences are formed in the trenches between adjacent mesa structures, and an electrical resistance of the ion implantation fences is higher than an electrical resistance of the mesa structures.

[0011] An embodiment of the present disclosure provides a method for manufacturing a micro-LED, which includes providing an epitaxial structure including, in top-down order, a first type of semiconductor layer, a light emitting layer, and a second type of semiconductor layer, bonding the epitaxial structure to an integrated circuit (IC) backplane, patterning the second type of semiconductor layer to form a mesa structure, a trench, and a fence, depositing a top contact on the mesa structure, performing an ion implantation process on the fence, and depositing a top conductive layer on a top surface of the second type of semiconductor layer, on the top contact, and in the trench.

[0012] An embodiment of the present disclosure provides a micro LED, comprising: a first type semiconductor layer; a light emitting layer formed on the first type of semiconductor layer; a second type of semiconductor layer formed on the light emitting layer; The first type of semiconductor layer has a P-type conductivity and the second type of semiconductor layer has an N-type conductivity; the first type of semiconductor layer includes a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure; a top surface of the first ion implantation fence is lower than a top surface of the first type of semiconductor layer; the second type of semiconductor layer includes a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure; a bottom surface of the second ion implantation fence is elevated above a bottom surface of the second type of semiconductor layer; a first ion implantation fence is formed around the first trench, the first trench is formed around the first mesa structure, and an electrical resistance of the first ion implantation fence is higher than an electrical resistance of the first mesa structure; A second ion implantation fence is formed around the second trench, the second trench is formed around the second mesa structure, and the second ion implantation fence has a higher electrical resistance than the electrical resistance of the second mesa structure.

[0013] An embodiment of the present disclosure provides a micro LED array panel, the micro LED array panel comprising: a first type of semiconductor layer formed in the micro LED array panel; a light emitting layer formed on the first type of semiconductor layer; a second type of semiconductor layer formed on the light emitting layer; The first type of semiconductor layer has a P-type conductivity and the second type of semiconductor layer has an N-type conductivity; the first type of semiconductor layer includes a plurality of first mesa structures, a plurality of first trenches, and a plurality of first ion implantation fences separated from the first mesa structures by the first trenches; a top surface of the first ion implantation fence is aligned with or below a top surface of the first type of semiconductor layer; The first ion implantation fences are formed in the first trenches between adjacent first type mesa structures, respectively, and an electrical resistance of the first ion implantation fences is higher than an electrical resistance of the first mesa structures; the second type of semiconductor layer includes a plurality of second mesa structures, a plurality of second trenches, and a plurality of second ion implantation fences separated from the second mesa structures by the second trenches; a bottom surface of the second ion implantation fence is aligned with or elevated above a bottom surface of the second type of semiconductor layer; The second ion implantation fences are each formed in a second trench between adjacent second mesa structures, and the second ion implantation fences have a higher electrical resistance than the electrical resistance of the second mesa structures.

[0014] An embodiment of the present disclosure provides a method for manufacturing a micro LED, the method including step I including patterning a first type of semiconductor layer and implanting the first type of semiconductor layer with first ions, and step II including patterning a second type of semiconductor layer and implanting the second type of semiconductor layer with second ions.

[0015] Embodiments and various aspects of the present disclosure are set forth in the following detailed description and the accompanying drawings, in which various features are not drawn to scale. [Brief description of the drawings]

[0016] [Figure 1A] 1A-1C are structural diagrams illustrating side cross-sectional views of different variations of a first exemplary micro-LED according to some embodiments of the present disclosure. [Figure 1B] 1A-1C are structural diagrams illustrating side cross-sectional views of different variations of a first exemplary micro-LED according to some embodiments of the present disclosure. [Figure 1C] 1A-1C are structural diagrams illustrating side cross-sectional views of different variations of a first exemplary micro-LED according to some embodiments of the present disclosure. [Figure 1D] 1A-1C are structural diagrams illustrating side cross-sectional views of different variations of a first exemplary micro-LED according to some embodiments of the present disclosure. [Figure 1E] 1A-1C are structural diagrams illustrating side cross-sectional views of different variations of a first exemplary micro-LED according to some embodiments of the present disclosure. [Figure 1F] 1A-1C are structural diagrams illustrating side cross-sectional views of different variations of a first exemplary micro-LED according to some embodiments of the present disclosure. [Diagram 2] FIG. 2 is a structural diagram illustrating a bottom view of a first exemplary micro LED according to some embodiments of the present disclosure. [Diagram 3] FIG. 2 is a structural diagram illustrating a cross-sectional side view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. [Figure 4] FIG. 2 is a structural diagram illustrating a cross-sectional side view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. [Diagram 5] 1 is a flowchart of a method for manufacturing a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 6A]FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 501 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6B] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 502 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6C] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 503 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6D] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 504 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6E] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 505 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6F] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 506 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6G] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 507 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6H] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 508 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6I] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 509 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6J] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process at step 510 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 7] FIG. 1B is a structural diagram illustrating a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 1A according to some embodiments of the present disclosure. [Figure 8]FIG. 8 is a structural diagram showing a bottom view of the side-by-side micro-LEDs of FIG. 7 according to some embodiments of the present disclosure. [Figure 9] FIG. 4 is a structural diagram illustrating a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 3 according to some embodiments of the present disclosure. [Figure 10A] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10B] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10C] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10D] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10E] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10F] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 11] FIG. 1 is a structural diagram illustrating a top view of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 12] FIG. 1 is a structural diagram illustrating a cross-sectional side view of another variation of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 13] FIG. 1 is a structural diagram illustrating a cross-sectional side view of another variation of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 14] 1 shows a flowchart of a second exemplary method for fabricating a micro LED according to some embodiments of the present disclosure. [Figure 15A]FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1401 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15B] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1402 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15C] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1403 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15D] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1404 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15E] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1405 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15F] FIG. 15 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 1406 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 16] FIG. 10B is a structural diagram showing a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 10A according to some embodiments of the present disclosure. [Figure 17] FIG. 17 is a structural diagram showing a top view of the side-by-side micro-LEDs of FIG. 16 according to some embodiments of the present disclosure. [Figure 18] FIG. 14 is a structural diagram showing a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 13 according to some embodiments of the present disclosure. [Figure 19] FIG. 13 is a structural diagram illustrating a cross-sectional side view of a third exemplary micro LED variation according to some embodiments of the present disclosure. [Figure 20] FIG. 13 is a structural diagram illustrating a cross-sectional side view of another variation of the third exemplary micro LED according to some embodiments of the present disclosure. [Figure 21] 1 shows a flowchart of a third exemplary method for manufacturing a micro LED according to some embodiments of the present disclosure. [Figure 22A] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process at step 2110 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 22B] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process at step 2111 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 22C] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process at step 2112 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 22D] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 2113 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Diagram 23] FIG. 20 is a structural diagram illustrating a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 19 according to some embodiments of the present disclosure. [Figure 24] FIG. 21 is a structural diagram showing a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 20 according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which like numbers in different drawings represent the same or similar elements unless otherwise specified. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the present invention. Instead, these are merely examples of apparatus and methods consistent with aspects related to the present invention as set forth in the appended claims. Certain aspects of the present disclosure are described in more detail below. In the event of a conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall control.

[0018] The present disclosure provides a micro LED that can avoid non-radiative recombination on the sidewall of the mesa according to the structure of the semiconductor layer and the light emitting layer that are successively formed. Moreover, compared with conventional micro LEDs, the spacing between adjacent mesas can be significantly reduced by the ion implantation fence. Thus, the integration of micro LEDs in a chip is increased and the active light emitting efficiency is improved. Moreover, the micro LED provided by the present disclosure can also increase the active light emitting area and improve image quality.

[0019] EMBODIMENT 1 1A-1F are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0020] 1A to 1F, the micro LED includes a first type of semiconductor layer 110, a light emitting layer 130, and a second type of semiconductor layer 120. The light emitting layer 130 is formed on the first type of semiconductor layer 110, and the second type of semiconductor layer 120 is formed on the light emitting layer 130. The thickness of the first type of semiconductor layer 110 is thicker than the thickness of the second type of semiconductor layer 120.

[0021] The conductivity type of the first type semiconductor layer 110 is different from the conductivity type of the second type semiconductor layer 120. In some embodiments, the conductivity type of the first type semiconductor layer 110 is P-type and the conductivity type of the second type semiconductor layer 120 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 120 is P-type and the conductivity type of the first type semiconductor layer 110 is N-type. For example, the material of the first type semiconductor layer 110 can be selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 120 can be selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0022] The first type semiconductor layer 110 includes a mesa structure 111, a trench 112, and an ion implantation fence 113. The ion implantation fence 113 is separated from the mesa structure 111 by the trench 112. The trench 112 and the ion implantation fence 113 are formed in an annular shape around the mesa structure 111. FIG. 2 is a structural diagram illustrating a bottom view of the first exemplary micro LED shown in FIGS. 1A-1F according to some embodiments of the present disclosure. FIG. 2 illustrates a bottom view of the first type semiconductor layer 110 with the ion implantation fence 113 separated from the mesa structure 111 by the trench 112. The ion implantation fence 113 is formed around the trench 112, and the trench 112 is formed around the mesa structure 111.

[0023] The ion implantation fence 113 includes a light absorbing material that absorbs light from the mesa structure 111. The conductivity type of the light absorbing material is the same as the conductivity type of the first type semiconductor layer 110. Preferably, the light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. Furthermore, the ion implantation fence 113 is formed by implanting ions into at least the first type semiconductor layer 110. Preferably, the type of ions implanted into the first type semiconductor layer 110 is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0024] Additionally, the width of the ion implantation fence 113 is less than or equal to 50% of the diameter of the mesa structure 111. In some embodiments, the width of the ion implantation fence 113 is less than or equal to 10% of the diameter of the mesa structure 111. Preferably, the width of the ion implantation fence 113 is less than or equal to 200 nm, the diameter of the mesa structure 111 is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer 110 is less than or equal to 300 nm.

[0025] In some embodiments, the width of trench 112 is less than or equal to 50% of the diameter of mesa structure 111. In some embodiments, the width of trench 112 is less than or equal to 10% of the diameter of mesa structure 111. Preferably, the width of trench 112 is less than or equal to 200 nm.

[0026] The depth of the trench 112 is not limited. In some embodiments, the trench 112 can extend upward through the top of the first type semiconductor layer 110, but cannot reach the light emitting layer 130. In some embodiments, the trench 112 can extend upward through the top of the first type semiconductor layer 110 and can reach the light emitting layer 130. In some embodiments, the trench 112 can extend upward through the top of the first type semiconductor layer 110 and can extend into the light emitting layer 1030. In some embodiments, the trench 112 can extend upward through the first type semiconductor layer 110 and the light emitting layer 130. Additionally, the trench 112 can extend upward through the first type semiconductor layer 110 and the light emitting layer 1030 and can extend upward into the second type semiconductor layer 120.

[0027] 1A, in some embodiments, trench 112 does not extend upward through the top surface of first type semiconductor layer 110. The top surface of trench 112 is lower than the top surface of first type semiconductor layer 110. As such, the top surface of trench 112 is not in contact with light emitting layer 130.

[0028] In this embodiment, the top surface of the ion implantation fence 113 is lower than the top surface of the first type semiconductor layer 110. The top surface of the ion implantation fence 113 can be formed at any location within the first type semiconductor layer 110. Preferably, as shown in FIG. 1A, the top surface of the ion implantation fence 113 is higher than the top surface of the trench 112. Note that, as shown in FIG. 1B, in some embodiments, the top surface of the ion implantation fence 113 is aligned with the top surface of the trench 112. As shown in FIG. 1C, in some embodiments, the top surface of the ion implantation fence 113 is lower than the top surface of the trench 112. Furthermore, the bottom surface of the ion implantation fence 113 can be formed at any location, whether higher or lower than the bottom surface of the first type semiconductor layer 110. Preferably, the bottom surface of the ion implantation fence 113 is aligned with the bottom surface of the first type semiconductor layer 110. As shown in Figure 1D, in some embodiments, the bottom surface of the ion implantation fence 113 is higher than the bottom surface of the first type semiconductor layer 110. As shown in Figure 1E, in some embodiments, the bottom surface of the ion implantation fence 113 is lower than the bottom surface of the first type semiconductor layer 110.

[0029] In some embodiments, the mesa structure 111 includes a stair structure 111a, as shown in Figure IF. The mesa structure 111 can have one or more stair structures.

[0030] 3 is a structural diagram showing a side cross-sectional view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 3, the micro LED further includes a bottom isolation layer 140 filled in the trench 112. Preferably, the material of the bottom isolation layer 140 is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.

[0031] In this embodiment, an IC (integrated circuit) backplane 190 is formed under the first type semiconductor layer 110 and is electrically connected to the first type semiconductor layer 110 through a connection structure 150. In FIG. 3, the connection structure 150 is a connection pillar.

[0032] The micro LED further includes a bottom contact 160. The bottom contact 160 is formed on the bottom of the first type semiconductor layer 110. The top surface of the connection structure 150 is connected with the bottom contact 160, and the bottom surface of the connection structure 150 is connected with the IC backplane 190. As shown in FIG. 3 , the bottom contact 160 protrudes from the first type semiconductor layer 110 as the bottom contact of the micro LED.

[0033] In some embodiments, the micro LED further includes a top contact 180 and a top conductive layer 170. The top contact 180 is formed on the second type semiconductor layer 120. The top conductive layer 170 is formed on the second type semiconductor layer 120 and the top contact 180. The conductivity type of the top contact 180 is the same as the conductivity type of the second type semiconductor layer 120. For example, in some embodiments, the conductivity type of the second type semiconductor layer 120 is N-type and the conductivity type of the top contact 180 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 120 is P-type and the conductivity type of the top contact 180 is P-type. The top contact 180 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 180 is used to form an ohmic contact between the top conductive layer 170 and the second type semiconductor layer 120 to optimize the electrical properties of the micro LED. The diameter of the top contact 180 is about 20-50 nm, and the thickness of the top contact 180 is about 10-20 nm. In some embodiments, a dielectric layer is formed between the top conductive layer and the second type semiconductor layer.

[0034] 4 is a structural diagram showing a cross-sectional side view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 4, the connection structure 150 is a metal bonding layer for bonding the micro LED with an IC backplane 190. Furthermore, the bottom contact 160 is a bottom contact layer in this variation.

[0035] Figure 5 shows a flowchart of a method 500 for fabricating a first exemplary micro LED, such as the micro LED shown in Figure 3, according to some embodiments of the present disclosure. The method 500 for fabricating a micro LED includes steps 501-510. Figures 6A-6J are structural diagrams showing cross-sectional side views of a micro LED fabrication process at each step (i.e., steps 501-510) corresponding to the method 500 shown in Figure 5, according to some embodiments of the present disclosure.

[0036] 5 and 6A-6J, an epitaxial structure is provided in step 501. As shown in FIG. 6A, the epitaxial structure includes, from top to bottom, a first type semiconductor layer 610, a light emitting layer 630, and a second type semiconductor layer 620. The epitaxial structure is grown on a substrate 600. The substrate 600 can be GaN, GaAs, etc.

[0037] In step 502, referring to FIG. 6B, a first type semiconductor layer 610 is patterned to form mesa structures 611, trenches 613, and fences 613'.

[0038] 6B, first type semiconductor layer 610 is etched and the etching is stopped above light emitting layer 630 to avoid etching light emitting layer 630 during the patterning process. The bottom of trench 612 does not reach light emitting layer 630. First type semiconductor layer 610 is etched by a conventional dry etching method, such as a plasma etching method, as would be understood by one of ordinary skill in the art.

[0039] In step 503, referring to FIG. 6C, a bottom contact 660 is deposited on the mesa structure 611.

[0040] Before the bottom contact 660 is deposited, a first protective mask (not shown) is used to protect the area where the bottom contact 660 is not to be formed. Then, the material of the bottom contact 660 is deposited on the first protective mask and on the first type of semiconductor layer 610 by a conventional deposition method such as physical vapor deposition or chemical vapor deposition. After the deposition process, the first protective mask is removed from the first type of semiconductor layer 610, and the material on the first protective mask is also removed together with the first protective mask to form the bottom contact 660 on the mesa structure 611.

[0041] In step 504, and with reference to Figure 6D, an ion implantation process is performed within fence 613'. The arrows indicate the direction of the ion implantation process.

[0042] As shown in FIG. 6D in conjunction with FIG. 6C, an ion implantation step implants ions into fence 613' (as shown in FIG. 6C) to form ion-implanted fence 613 (as shown in FIG. 6D). Prior to the ion implantation step, a second protective mask (not shown) is formed in the areas where ions are not to be implanted. Ions are then implanted into the exposed fence 613'. The second protective mask is then removed by conventional chemical etching methods, as will be understood by those skilled in the art. Preferably, the implantation energy is 0-500 Kev and the implantation dose is 1E10-9E17.

[0043] In step 505, referring to Figure 6E, a bottom isolation layer 640 is deposited over the substrate 600. That is, the bottom isolation layer 640 is deposited on the first type semiconductor layer 610. The first type semiconductor layer 610 and the bottom contact 660 are covered by the bottom isolation layer 640, and the trench 612 is filled by the bottom isolation layer 640. The bottom isolation layer 640 is deposited by conventional chemical vapor deposition.

[0044] In step 506, referring to Figure 6F, the bottom isolation layer 640 is patterned to expose the bottom contact 660. The bottom isolation layer 640 is etched by photo-etching and dry-etching methods.

[0045] In step 507, and referring to Figure 6G, a metal material 650' is deposited over the substrate 600. That is, the metal material 650' is deposited on the bottom isolation layer 640 and the bottom contact 660. The metal material is deposited by conventional physical vapor deposition.

[0046] In step 508, referring to Figure 6H, the top of the metal material is polished down to the top of the bottom isolation layer 640 to form connection structures 650, such as connection pillars. In some embodiments, the metal material is polished by a chemical mechanical polishing (CMP) process.

[0047] In step 509, referring to FIG. 6I, the connection pillars 650 are bonded to the IC backplane 690. The epitaxial structure is first turned upside down. Then, by a metal bonding process, the connection pillars 650 are bonded to the contact pads of the IC backplane 690. After that, the substrate 600 is removed by a conventional separation method such as laser stripping or chemical etching. The arrows indicate the direction of removal of the substrate 600.

[0048] In step 510, referring to FIG. 6J, a top contact 680 and a top conductive layer 670 may be sequentially deposited on the second type semiconductor layer 620 by conventional deposition techniques.

[0049] Some embodiments of the present disclosure further provide a micro LED array panel, which includes a plurality of micro LEDs as described above, as shown in Figures 1A-1F, 3 and 4. These micro LEDs may be arranged in an array within the micro LED array panel.

[0050] 7 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 1A according to some embodiments of the present disclosure. As shown in FIG. 7, the micro LED array panel includes a first type semiconductor layer 710 formed continuously in the micro LED array panel, a light emitting layer 730 formed continuously on the first type semiconductor layer 710, and a second type semiconductor layer 720 formed continuously on the light emitting layer 730.

[0051] The conductivity type of the first type semiconductor layer 710 is different from the conductivity type of the second type semiconductor layer 720. For example, in some embodiments, the conductivity type of the first type semiconductor layer 710 is P-type and the conductivity type of the second type semiconductor layer 720 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 720 is P-type and the conductivity type of the first type semiconductor layer 710 is N-type. The thickness of the first type semiconductor layer 710 is greater than the thickness of the second type semiconductor layer 720. In some embodiments, the material of the first type semiconductor layer 710 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 720 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0052] The first type semiconductor layer 710 includes a plurality of mesa structures 711, a plurality of trenches 712, and a plurality of ion implantation fences 713 separated from the mesa structures 711 by the trenches 712. The top surface of the ion implantation fences 713 is lower than the top surface of the first type semiconductor layer 710. The trenches 712 do not extend upward through the top of the first type semiconductor layer 710. The top of the trenches 712 is lower than the top surface of the first type semiconductor layer 710. Thus, the top surface of the trenches 712 is not in contact with the light emitting layer 730. The relationship between the top surface of the ion implantation fences 713, the top surface of the first type semiconductor layer 710, and the top surface of the trenches 712 can be seen in the micro LED shown in FIG. 1B-FIG. 1D, and will not be further described here. Additionally, the relationship between the bottom surface of the ion implantation fence 713 and the bottom surface of the first type semiconductor layer 710 can be seen in the micro LEDs illustrated in Figures 1D-1E and will not be further described herein. In another embodiment, the mesa structure can have one or more stair structures, as can be seen in the mesa structure illustrated in Figure 1F.

[0053] 8 is a structural diagram illustrating a bottom view of the side-by-side micro LEDs of FIG. 7 according to some embodiments of the present disclosure. As shown in FIG. 8, ion implant fences 713 are formed in trenches 712 between adjacent mesa structures 711. Furthermore, in each micro LED, ion implant fences 713 are formed around trenches 712, and trenches 712 are formed around mesa structures 711. An electrical resistance of ion implant fences 713 is higher than an electrical resistance of mesa structures 711.

[0054] In some embodiments, the spacing between adjacent sidewalls of adjacent ones of the mesa structures 711 can be adjusted. For example, in some embodiments, the spacing between adjacent sidewalls of the mesa structures 711 is 50% or less of the diameter of the mesa structures 711. In some embodiments, the spacing between adjacent sidewalls of the mesa structures 711 is 30% or less of the diameter of the mesa structures 711. Preferably, the spacing between adjacent sidewalls of the mesa structures 711 is 600 nm or less. Furthermore, in some embodiments, the width of the ion implantation fence 713 can be adjusted. For example, the width of the ion implantation fence 713 can be 50% or less of the diameter of the mesa structures 711. In some embodiments, the width of the ion implantation fence 713 can be 10% or less of the diameter of the mesa structures 711. Preferably, in a micro LED array panel, the width of the ion implantation fence 713 is 200 nm or less.

[0055] 9 is a structural diagram showing a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 3 in a micro LED array panel according to some embodiments of the present disclosure. As shown in FIG. 9, the micro LED array panel further includes a bottom isolation layer 940 formed on the first type semiconductor layer 910 and filled in the trench 912. Preferably, in some embodiments, the material of the bottom isolation layer 940 is one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2. Also, an IC backplane 990 is continuously formed below the first type semiconductor layer 910 and electrically connected with the first type semiconductor layer 910 through a connection structure 950. The micro LED array panel further includes a bottom contact 960 formed on the bottom of the first type semiconductor layer 910. Further details of the bottom isolation layer 940, IC backplane 990, bottom contacts 960 and connection structures 950 are shown in the micro-LEDs of Figures 3 and 4, which correspond to the isolation layer 140, IC backplane 190, bottom contacts 160 and connection structures 150, respectively, and will not be described further.

[0056] In this embodiment, the micro LED array panel further includes a top contact 980 and a top conductive layer 970. The top contact 980 is formed on the second type semiconductor layer 920. The top conductive layer 970 is formed on the second type semiconductor layer 920 and the top contact 980. The conductivity type of the top contact 980 is the same as the conductivity type of the second type semiconductor layer 920, for example, in some embodiments, the conductivity type of the second type semiconductor layer 920 is N-type and the conductivity type of the top contact 980 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 920 is P-type and the conductivity type of the top contact 980 is P-type. The top contact 980 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 980 is used to form an ohmic contact between the top conductive layer 970 and the second type semiconductor layer 920 to optimize the electrical properties of the micro LEDs. The diameter of the top contact 980 is about 20 to 50 nm, and the thickness of the top contact 980 is about 10 to 20 nm.

[0057] The micro LED array panel can be manufactured by a method 500 shown in FIG. 5, which will not be described further.

[0058] In some embodiments, a dielectric layer is formed between the top conductive layer and the second type semiconductor layer.

[0059] EMBODIMENT 2 10A-10F are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 10A, the micro LED includes a first type of semiconductor layer 1010, a light emitting layer 1030, and a second type of semiconductor layer 1020. The conductivity type of the first type of semiconductor 1010 is different from the conductivity type of the second type of semiconductor layer 1020. For example, the conductivity type of the first type of semiconductor 1010 is P-type, and the conductivity type of the second type of semiconductor layer 1020 is N-type.

[0060] The second type semiconductor layer 1020 includes a mesa structure 1021, a trench 1022, and an ion implantation fence 1023 separated from the mesa structure 1021. The bottom surface of the ion implantation fence 1023 is located higher than the bottom surface of the second type semiconductor layer 1020. Furthermore, the ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021. The electrical resistance of the ion implantation fence 1023 is higher than the electrical resistance of the mesa structure 1021.

[0061] The ion implantation fence 1023 comprises a light absorbing material that absorbs light from the mesa structure 1021. The conductivity type of the light absorbing material is the same as the conductivity type of the second semiconductor layer 1020. Preferably, the light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN. Furthermore, the ion implantation fence 1023 is formed by implanting ions into at least the second type semiconductor layer 1020. Preferably, the ion type implanted into the second type semiconductor layer 1020 is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0062] Further, the width of the ion implantation fence 1023 is less than or equal to 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the ion implantation fence 1023 is less than or equal to 10% of the diameter of the mesa structure 1021. Preferably, the width of the ion implantation fence 1023 is less than or equal to 200 nm. The diameter of the mesa structure 1021 is less than or equal to 2500 nm. The thickness of the second type semiconductor layer 1020 is less than or equal to 100 nm.

[0063] In some embodiments, the width of trench 1022 is less than or equal to 50% of the diameter of mesa structure 1021. In some embodiments, the width of trench 1022 is less than or equal to 10% of the diameter of mesa structure 1021. Preferably, the width of trench 1022 is less than or equal to 200 nm.

[0064] 11 is a structural diagram illustrating a top view of a second exemplary micro LED according to some embodiments of the present disclosure. FIG. 11 illustrates a top view of a second type of semiconductor layer 1020 in which an ion implant fence 1023 is separated from a mesa structure 1021 by a trench 1022. Here, the ion implant fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021.

[0065] The depth of the trench 1022 is not limited. In some embodiments, the trench 1022 can extend down through the bottom of the second type semiconductor layer 1020, but cannot reach the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and can reach the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and into the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and the light emitting layer 1030. Additionally, the trench 1022 can extend down through the second type semiconductor layer 1020 and the light emitting layer 1030 and into the first type semiconductor layer 1010.

[0066] 10A, the trench 1022 does not extend down through the bottom surface of the second type semiconductor layer 1020. The bottom surface of the trench 1022 is higher than the bottom of the second type semiconductor layer 1020. As such, the bottom of the trench 1022 is not in contact with the light emitting layer 1030.

[0067] In some embodiments, the bottom of the ion implantation fence 1023 is lower than or aligned with the bottom of the trench 1022. The bottom of the ion implantation fence 1023 can be formed anywhere within the first type semiconductor layer 1010. Preferably, the bottom of the ion implantation fence 1023 is lower than the bottom of the trench 1022, as shown in FIG. 10A. In some embodiments, the bottom of the ion implantation fence 1023 is aligned with the bottom of the trench 1022, as shown in FIG. 10B. In some embodiments, the bottom of the ion implantation fence 1023 is higher than the bottom of the trench 1022, as shown in FIG. 10C.

[0068] Additionally, in some embodiments, the top surface of the ion implantation fence 1023 can be formed at any location. Preferably, the top surface of the ion implantation fence 1023 is aligned with the top surface of the second type semiconductor layer 1020. However, in some embodiments, the top surface of the ion implantation fence 1023 is higher than the top surface of the second type semiconductor layer 1020, as shown in FIG. 10D. In some embodiments, the top surface of the ion implantation fence 1023 is lower than the top surface of the second type semiconductor layer 1020, as shown in FIG. 10E.

[0069] In some embodiments, the mesa structure 1021 includes one stair structure 1021a, as shown in Figure 10F. In some embodiments, the mesa structure 1021 can have multiple stair structures.

[0070] 12 is a structural diagram showing a cross-sectional side view of another variation of the second exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 12, the micro LED further includes a bottom isolation layer 1040 formed under the first type semiconductor layer 1010. Preferably, the material of the bottom isolation layer 1040 is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.

[0071] In this embodiment, an integrated circuit (IC) backplane 1090 is formed under the first type semiconductor layer 1010 and electrically connected to the first type semiconductor layer 1010 through a connection structure 1050. In FIG. 12, the connection structure 1050 is a connection pillar. The micro LED further includes a bottom contact 1060 formed at the bottom of the first type semiconductor layer 1010. The top surface of the connection structure 1050 is connected to the bottom contact 1060, and the bottom of the connection structure 1050 is connected to the IC backplane 1090. In this embodiment, the bottom contact 1060 protrudes from the first type semiconductor layer 1010 as the bottom contact of the micro LED.

[0072] Further, in some embodiments, the micro LED further includes a top contact 1080 and a top conductive layer 1070. The top contact 1080 is formed on the second type semiconductor layer 1020. The top conductive layer 1070 is formed on the top surface of the second type semiconductor layer 1020, covering the top contact 1080 and filling in the trench 1022. Thus, the top conductive layer 1070 is formed on the top surface and sidewalls of the mesa structure 1021 and on the top surface and sidewalls of the ion implantation fence. The conductivity type of the top contact 1080 is the same as the conductivity type of the second type semiconductor layer 1020. For example, the conductivity type of the second type semiconductor layer 1020 is N-type, and the conductivity type of the top contact 1080 is N-type. The top contact 1080 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 1080 is used to form an ohmic contact between the top conductive layer 1070 and the second type semiconductor layer 1020 to optimize the electrical properties of the micro LED. The diameter of the top contact 1080 is about 20-50 nm, and the thickness of the top contact 1080 is about 10-20 nm.

[0073] 13 is a structural diagram showing a side cross-sectional view of another variation of the second exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 13, the connection structure 1050 can be a metal bonding layer for bonding the micro LED with an IC backplane 1090. Furthermore, in this embodiment, the bottom contact 1060 is a bottom contact layer.

[0074] In some embodiments, the micro LED further includes a dielectric layer formed on the surface of the second type semiconductor layer, on the bottom surface of the top conductive layer, and filling the trench. The dielectric layer includes an opening for exposing the top contact. Thus, the top conductive layer can be connected with the top contact through the opening. Preferably, the material of the dielectric layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.

[0075] Figure 14 shows a flowchart of a method 1400 for fabricating a second exemplary LED, e.g., the micro LED shown in Figure 13, according to some embodiments of the present disclosure. As shown in Figure 14, the micro LED fabrication method includes steps 1401-1406. Figures 15A-15F are structural diagrams showing cross-sectional side views of the micro LED fabrication process at each step (i.e., steps 1401-1406) of the method 1400 shown in Figure 14, according to some embodiments of the present disclosure.

[0076] 14 and 15A-15F. In step 1401, an epitaxial structure is provided. As shown in FIG. 15A, the epitaxial structure includes, from top to bottom, a first type semiconductor layer 1510, a light emitting layer 1530, and a second type semiconductor layer 1520. The epitaxial structure is grown on a substrate 1500. The substrate 1500 can be GaN, GaAs, etc.

[0077] Preferably, before turning the epitaxial structure upside down, a bottom contact layer 1560 used as a bottom contact is deposited on the top surface of the first type semiconductor layer 1510. Then, a metal bonding layer used as a connection structure 1550 is deposited on the top surface of the bottom contact layer 1560.

[0078] In step 1402, referring to Fig. 15B, the epitaxial structure is bonded to an IC backplane 1590. The epitaxial structure is first turned upside down. Then, the connection structure 1550 is bonded to the contact pads of the IC backplane 1590 by a metal bonding process. Finally, the substrate 1500 is removed by a conventional separation method such as laser stripping or chemical etching. The arrow indicates the removal direction of the substrate 1500.

[0079] In step 1403, referring to FIG. 15C, second type semiconductor layer 1520 is patterned to form mesa structures 1521, trenches 1522, and fences 1523'. Second type semiconductor layer 1520 is etched and the etching is stopped above light emitting layer 1530 to avoid etching light emitting layer 1530 during the patterning process. The bottom of trench 1522 in FIG. 15C does not reach light emitting layer 1530. Second type semiconductor layer 1520 is etched by a conventional dry etching method, such as a plasma etching method, as would be understood by one skilled in the art.

[0080] In step 1404, referring to FIG. 15D, a top contact 1580 is deposited on the mesa structure 1521. Before the top contact 1580 is deposited, a first protective mask (not shown) is used to protect the area where the top contact 1580 is not to be formed. Then, the material of the top contact 1580 is deposited on the first protective mask and on the second type of semiconductor layer 1520 by a conventional deposition method such as physical vapor deposition or chemical vapor deposition. After the deposition step, the first protective mask is removed from the second type of semiconductor layer 1520, and the material on the first protective mask is also removed together with the first protective mask to form the top contact 1580 on the mesa structure 1521.

[0081] In step 1405, referring to FIG. 15E, an ion implantation process is performed in the fence 1523'. Referring also to FIG. 15D, the ion implantation process implants ions into the fence 1523' (as shown in FIG. 15D) to form the ion implanted fence 1523 (as shown in FIG. 15E). The arrows indicate the direction of the ion implantation process. Prior to the ion implantation process, a second protective mask (not shown) is formed in the areas where ions are not to be implanted. Ions are then implanted into the exposed fence 1523' (as shown in FIG. 15D). The second protective mask is then removed by conventional chemical etching methods, as would be understood by one skilled in the art. Preferably, the implantation energy is between 0 and 500 KeV, and the implantation dose is between 1E10 and 9E17.

[0082] Note that in some embodiments, the top contact 1580 may be formed after the ion implantation step.

[0083] 15F, a top conductive layer 1570 is deposited on top of the second type semiconductor layer 1520 and on the top contact 1580, filling the trench 1522. The top conductive layer 1570 is deposited by conventional physical vapor deposition.

[0084] Alternatively, a sidewall dielectric layer can be formed in trench 1522 prior to depositing top conductive layer 1570. A microlens can be further formed on top conductive layer 1570, as can be appreciated by one skilled in the art.

[0085] If the connection structure 1550 is a connection pillar, step 1402 can be replaced by step 1402', which includes depositing a bottom contact on the first type semiconductor layer, depositing a bottom isolation layer on the entire substrate, patterning the bottom isolation layer to expose the bottom contact, depositing a metal material on the entire substrate, polishing the top of the metal material to the top of the bottom insulating layer to form a connection pillar, and bonding the connection pillar with an IC backplane. The epitaxial structure is first flipped upside down, and the connection pillar is bonded with a contact pad of an IC backplane by a metal bonding process. Step 1402' can also be further understood by referring to the description of Figures 6C and 6E-6I in embodiment 1, which will not be described in further detail in this specification.

[0086] Some embodiments of the present disclosure further provide a micro LED array panel, which includes a plurality of micro LEDs as described above, as shown in Figures 10A-10F, 12 and 13. These micro LEDs may be arranged in an array within the micro LED array panel.

[0087] 16 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 10A according to some embodiments of the present disclosure. As shown in FIG. 16, the micro LED array panel includes a first type semiconductor layer 1610 formed continuously in the micro LED array panel, a light emitting layer 1630 formed continuously on the first type semiconductor layer 1610, and a second type semiconductor layer 1620 formed continuously on the light emitting layer 1630.

[0088] The second type semiconductor layer 1620 includes a number of mesa structures 1621, a number of trenches 1622, and a number of ion implantation fences 1623 separated from the mesa structures 1621 by the trenches 1622. The bottom surfaces of the ion implantation fences 1623 are higher than the bottom surface of the second type semiconductor layer 1620.

[0089] FIG. 17 is a structural diagram illustrating a top view of the side-by-side micro LEDs of FIG. 16 according to some embodiments of the present disclosure. FIG. 17 illustrates a top view of a second type semiconductor layer 1620 with an ion implantation fence 1623 formed in a trench 1622 between adjacent mesa structures 1621. The electrical resistance of the ion implantation fence 1623 is higher than the electrical resistance of the mesa structures 1621. The ion implantation fence 1623 is formed around the trench 1622, and the trench 1622 is formed around the mesa structures 1621.

[0090] The trench 1622 does not extend down through the bottom of the second type semiconductor layer 1620. The bottom of the trench 1622 is higher than the bottom of the second type semiconductor layer 1620. Thus, the bottom of the trench 1622 is not in contact with the light emitting layer 1630. In some embodiments, the trench 1622 can extend down through the bottom of the second type semiconductor layer 1620, but cannot reach the light emitting layer 1630. In some embodiments, the trench 1622 can extend down through the second type semiconductor layer 1620 and reach the light emitting layer 1630. In some embodiments, the trench 1622 can extend down through the second type semiconductor layer 1620 and into the light emitting layer 1630. In some embodiments, the trench 1622 can extend down through the second type semiconductor layer 1620 and into the light emitting layer 1630. Further, in some embodiments, the second trench 1622 can extend downward through the second type semiconductor layer 1620 and the light emitting layer 1630 and then downward into the first type semiconductor layer 1610. The changes in the relationship between the bottom surface of the ion implantation fence 1623, the bottom surface of the second type semiconductor layer 1620, and the bottom of the trench 1622 generally correspond to those shown for the micro LEDs of Figures 10A-10C and will not be described further herein. Further, in some embodiments, the changes in the relationship between the top surface of the ion implantation fence 1623 and the top surface of the second type semiconductor layer 1620 generally correspond to those shown for the micro LEDs of Figures 10C-10E and will not be described further herein. In some embodiments, the mesa structure can have one or more staircase structures, as shown in Figure 10F.

[0091] In some embodiments, the spacing between adjacent sidewalls of adjacent ones of the mesa structures 1621 can be adjusted. For example, in some embodiments, the spacing between adjacent sidewalls of the mesa structures 1621 is 50% or less of the diameter of the mesa structures 1621. In some embodiments, the spacing between adjacent sidewalls of the mesa structures 1621 is 30% or less of the diameter of the mesa structures 1621. Preferably, the spacing between adjacent sidewalls of the mesa structures 1621 is 600 nm or less. Furthermore, in some embodiments, the width of the ion implantation fence 1623 can be adjusted. For example, the width of the ion implantation fence 1623 can be 50% or less of the diameter of the mesa structures 1621. In some embodiments, the width of the ion implantation fence 1623 can be 10% or less of the diameter of the mesa structures 1621. Preferably, in a micro LED array panel, the width of the ion implantation fence 1623 is 200 nm or less.

[0092] Figure 18 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of Figure 13 in a micro LED array panel according to some embodiments of the present disclosure. As shown in Figure 18, the micro LED array panel further includes a top contact 1880 and a top conductive layer 1870. Further details of the top contact 1880 and the top conductive layer 1870 can also be understood by reference to the micro LEDs shown in Figures 10A-10F, 12 and 13, which will not be described further herein.

[0093] Further, referring back to FIG. 18 , an IC backplane 1890 is formed below the first type semiconductor layer 1810 and electrically connected to the first type semiconductor layer 1810 via a connection structure 1850. The micro LED array panel further includes a bottom contact 1860 formed at the bottom of the first type semiconductor layer 1810. The connection structure 1850 may be a metal bonding layer for bonding the micro LEDs with the IC backplane 1890. Further, in some embodiments, the bottom contact 1860 is a bottom contact layer. Further details of the bottom isolation layer 1840, the IC backplane 1890, the bottom contact 1860, and the connection structure 1850 can be understood by also referring to FIG. 13 , which will not be further described here.

[0094] Further details regarding the characteristics of the micro LEDs and ion implanted fences in the micro LED array panel can also be understood by reference to the micro LEDs as shown in Figures 10A-10F, which will not be described further herein.

[0095] The micro LED array panel shown in FIG. 18 can be manufactured by the method for manufacturing the micro LEDs 1400 shown in FIG. 14, which will not be described further here.

[0096] EMBODIMENT 3 19 is a structural diagram showing a cross-sectional side view of a variation of a third exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 19, the micro LED includes at least a first type of semiconductor layer 1910, a light emitting layer 1930, and a second type of semiconductor layer 1920. The conductivity type of the first type of semiconductor layer 1910 is different from the conductivity type of the second type of semiconductor layer 1920. For example, in some embodiments, the conductivity type of the first type of semiconductor layer 1910 is P type, and the conductivity type of the second type of semiconductor layer 1920 is N type. In some embodiments, the conductivity type of the second type of semiconductor layer 1920 is P type, and the conductivity type of the first type of semiconductor layer 1910 is N type. The thickness of the first type of semiconductor layer 1910 is greater than the thickness of the second type of semiconductor layer 1920. In some embodiments, the material of the first type semiconductor layer 1910 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer 1920 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0097] The first type semiconductor layer 1910 includes a first mesa structure 1911, a first trench 1912, and a first ion implantation fence 1913. The first trench 1912 does not extend upward through a top surface of the first type semiconductor layer 1910. The second type semiconductor layer 1920 includes a second mesa structure 1921, a second trench 1922, and a second ion implantation fence 1923 separated from the second mesa structure 1921. The second trench 1922 does not extend downward through a bottom of the second type semiconductor layer 1920.

[0098] In some embodiments, the center of the first mesa structure 1911 is aligned with the center of the second mesa structure 1921. The center of the first trench 1912 is aligned with the center of the second trench 1922. The center of the first ion implantation fence 1913 is aligned with the center of the second ion implantation fence 1923.

[0099] A bottom view of the first type semiconductor layer 1910 is similar to the bottom view shown in FIG. 2. A first ion implantation fence 1913 is separated from a first mesa structure 1911 by a first trench 1912. The first ion implantation fence 1913 is formed around the first trench 1912, which is formed around the first mesa structure 1911. A top view of the second type semiconductor layer 1920 is similar to the top view shown in FIG. 11, where a second ion implantation fence 1923 is separated from a second mesa structure 1921 by a second trench 1922. The second ion implantation fence 1923 is formed around the second trench 1922, which is formed around the second mesa structure 1921.

[0100] The relationship between the top surface of the first ion implantation fence 1913, the top surface of the first trench 1912, and the top surface of the first type semiconductor layer 1910 is the same as that of the modified micro LED of the first embodiment shown in Figures 1A-1C, which will not be further described here. The relationship between the bottom of the first ion implantation fence 1913, the bottom of the first trench 1912, and the bottom of the first type semiconductor layer 1910 is the same as that of the modified micro LED of the first embodiment shown in Figures 1C-1E, which will not be further described here. Furthermore, in some embodiments, the first mesa structure 1911 can have one or more staircase structures, as shown in Figure 1F.

[0101] The relationship between the bottom of the second ion-implanted fence 1923, the bottom of the second trench 1922, and the bottom of the second type semiconductor layer 1920 is the same as that of the modified micro LED of the second embodiment shown in Figures 10A-10C, and will not be further described here. The relationship between the top surface of the second ion-implanted fence 1923, the top surface of the second trench 1922, and the top surface of the second type semiconductor layer 1920 is the same as that of the modified micro LED of the second embodiment shown in Figures 10C-10E, and will not be further described here. Furthermore, in some embodiments, the second mesa structure 1921 can have one or more staircase structures, as shown in Figure 10F.

[0102] 20 is a structural diagram showing a side cross-sectional view of another variation of the third exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 20, the micro LED further includes a bottom isolation layer 2030 filled in the first trench 2012. Preferably, the material of the bottom isolation layer 2030 is one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2. The IC backplane 2090 is formed under the first type semiconductor layer 2010 and electrically connected with the first type semiconductor layer 2010 through a connection structure 2050. In this specification, the connection structure 2050 is a connection pillar. The micro LED further includes a bottom contact 2060 formed at the bottom of the first type semiconductor layer 2010. Further details of the bottom isolation layer 2040, the IC backplane 2090, the connection structure 2050, and the bottom contacts 2060 can be known by reference to the description of embodiment 1, which will not be described further here.

[0103] The micro LED further includes a top contact 2080 and a top conductive layer 2070. The top contact 2080 is formed on the second type semiconductor layer 2020. The top conductive layer 2070 is formed on top of the second type semiconductor layer 2020 and the top contact 2080, filling the second trench 2022. Further details regarding the top contact 2080 and the top conductive layer 2070 can be known by referring to the description of the second embodiment, which will not be further described here.

[0104] In some embodiments, the micro LED further includes a dielectric layer formed on the surface of the second type semiconductor layer, on the bottom surface of the top conductive layer, and filling the second trench. The dielectric layer includes an opening for exposing the top contact. Thus, the top conductive layer can be connected with the top contact through the opening. Preferably, the material of the dielectric layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2. Further details regarding the dielectric layer can be known by referring to embodiment 2, which will not be further described here.

[0105] Further details regarding the micro LED shown in FIG. 20, including the first ion-implanted fence 2013 and the second ion-implanted fence 2023, can be found by reference to the descriptions of embodiments 1 and 2, and will not be described further here.

[0106] 21 shows a flowchart of a third exemplary method 2100 for manufacturing a micro LED according to some embodiments of the present disclosure. The method 2100 includes at least step I and step II.

[0107] In step I, a first type of semiconductor layer is patterned, and then ions are implanted into the first type of semiconductor layer to form a first ion implantation fence.

[0108] In step II, after the second type of semiconductor layer is patterned, ions are implanted into the second type of semiconductor layer to form a second ion implantation fence.

[0109] Referring to FIG. 21, process I includes at least steps 2101-2109, and process II includes at least steps 2110-2113.

[0110] For process I, steps 2101-2109 are similar to steps 501-509 of method 500 shown in Figure 5. A cross-sectional side view of a micro LED fabricated according to steps 2101-2109 is similar to that shown in Figures 6A-6I. See Figure 21 and Figures 6A-6I. In step 2101, referring to Figure 6A, an epitaxial structure is provided.

[0111] In step 2102, referring to FIG. 6B, a first type semiconductor layer 610 is patterned to form mesa structures 611, trenches 612, and fences 613'.

[0112] In step 2103, referring to FIG. 6C, a bottom contact 660 is deposited on the mesa structure 611.

[0113] In step 2104, with reference to FIG. 6D, an ion implantation process is performed within fence 613'.

[0114] In step 2105, referring to FIG. 6E, a bottom isolation layer 640 is deposited over the substrate 600.

[0115] In step 2106, with reference to FIG. 6F, the bottom isolation layer 640 is patterned to expose the bottom contact 660.

[0116] In step 2107, referring to FIG. 6G, a metal material 650' is deposited over the substrate 600.

[0117] In step 2108, referring to FIG. 6H, the top of the metal material 650' is polished down to the top of the bottom isolation layer 640 to form the connecting pillars 650.

[0118] In step 2109, referring to FIG. 6I, the connection pillars 650 are bonded with the IC backplane 690 and the substructure 600 is removed.

[0119] 22A-22D are structural diagrams illustrating cross-sectional side views of a micro LED manufacturing process in steps 2110-2113 of the method 2100 shown in FIG. 21, according to some embodiments of the present disclosure. With reference to FIG. 21 and FIG. 22A-22D, in step 2110, with reference to FIG. 22A, a second type semiconductor layer 2220 is patterned to form mesa structures 2221, trenches 2222, and fences 2223′.

[0120] In step 2111, referring to FIG. 22B, a top contact 2280 is deposited on the mesa structure 2221.

[0121] In step 2112, with reference to Figure 22C, an ion implantation process is performed within fence 2223'. The arrows indicate the direction of the ion implantation process.

[0122] In step 2113, referring to FIG. 22D, a top conductive layer 2270 is deposited over the top of the second type semiconductor layer 2220 and the top contact 2280 and in the trenches 2222.

[0123] Further details of step I can be known by referring to the description of steps 501 to 509 in embodiment 1. Further details of step II can be known by referring to the description of steps 1403 to 1406 in embodiment 2, which will not be further described here.

[0124] Some embodiments of the present disclosure further provide a micro LED array panel, which includes a plurality of micro LEDs as described above, as shown in Figures 19 and 20. These micro LEDs may be arranged in an array within the micro LED array panel.

[0125] 23 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 19 in a micro LED array panel according to some embodiments of the present disclosure. As shown in FIG. 23, the micro LED array panel includes at least a first type semiconductor layer 2310 formed continuously in the micro LED array panel, a light emitting layer 2330 formed continuously on the first type semiconductor layer 2310, and a second type semiconductor layer 2320 formed continuously on the light emitting layer 2330.

[0126] The first type semiconductor layer 2310 includes a plurality of first mesa structures 2311, a plurality of first trenches 2312, and a plurality of first ion implantation fences 2313 separated from the first mesa structures via the first trenches 2312. The top surface of the first ion implantation fences 2313 is lower than the top surface of the first type semiconductor layer 2310. Referring back to FIG. 8, the bottom view of the micro LED array panel without an IC backplane is similar to the bottom view shown in FIG. 8. The first ion implantation fences 2313 are formed in the first trenches 2312 between adjacent first type mesa structures. The electrical resistance of the first ion implantation fences 2313 is higher than the electrical resistance of the first mesa structures. Furthermore, the first ion implantation fences 2313 are formed around the first trenches 2312, and the first trenches 2312 are formed around the first mesa structures.

[0127] The second type semiconductor layer 2320 includes a plurality of second mesa structures 2321, a plurality of second trenches 2322, and a plurality of second ion implantation fences 2323 separated from the second mesa structures 2321 via the second trenches 2322. The bottom surface of the second ion implantation fences 2323 is higher than the bottom surface of the second type semiconductor layer 2320. The top view of the micro LED array panel is similar to the top view shown in FIG. 17, and the second ion implantation fences 2323 are formed in the second trenches 2322 between adjacent second mesa structures 2321. The electrical resistance of the second ion implantation fences 2323 is higher than the electrical resistance of the second mesa structures 2321. The second ion implantation fences 2323 are formed around the second trenches 2322, and the second trenches 2322 are formed around the second mesa structures 2321.

[0128] In some embodiments, the spacing between adjacent sidewalls of the first mesa structure 2311 can be adjusted. For example, the spacing between adjacent sidewalls of the first mesa structure 2311 is 50% or less of the diameter of the first mesa structure 2311. In some embodiments, the spacing between adjacent sidewalls of the first mesa structure 2311 is 30% or less of the diameter of the first mesa structure 2311. Preferably, the spacing between adjacent sidewalls of the first mesa structure 2311 is 600 nm or less. Furthermore, in some embodiments, the width of the first ion implantation fence 2313 can be adjusted. For example, the width of the first ion implantation fence 2313 is 50% or less of the diameter of the first mesa structure 2311. In some embodiments, the width of the first ion implantation fence 2313 is 10% or less of the diameter of the first mesa structure 2311. Preferably, in some embodiments, in a micro LED array panel, the width of the first ion implantation fence 2313 is 200 nm or less. The spacing between adjacent sidewalls of the second mesa structure 2321 is 50% or less of the diameter of the second mesa structure 2321. In some embodiments, the spacing between adjacent sidewalls of the second mesa structure 2321 is 30% or less of the diameter of the second mesa structure 2321. Preferably, the spacing between adjacent sidewalls of the second mesa structure 2321 is 600 nm or less. Furthermore, the width of the second ion implantation fence 2323 is 50% or less of the diameter of the second mesa structure 2321. In some embodiments, the width of the second ion implantation fence 2323 is 10% or less of the diameter of the second mesa structure 2321. Preferably, in a micro LED array panel, the width of the second ion implantation fence 2323 is 200 nm or less.

[0129] 24 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 20 in a micro LED array panel according to some embodiments of the present disclosure. As shown in FIG. 24, the micro LED array panel further includes a bottom isolation layer 2440 filled in the first trench 2412. Preferably, the material of the bottom isolation layer 2440 is one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2. Furthermore, an IC backplane 2490 is formed below the first type semiconductor layer 2410 and electrically connected to the first type semiconductor layer 2410 through a connection structure 2450. The micro LED array panel further includes a bottom contact 2460 formed at the bottom of the first type semiconductor layer 2410. The top surface of the connection structure 2450 is connected to the bottom contact 2460, and the bottom of the connection structure 2450 is connected to the IC backplane 2490. The bottom contact 2460 is a protruding contact. In some embodiments, referring to FIG. 4, the connection structure 2450 can be a metal bonding layer for bonding the micro-LEDs with an IC backplane 2490. Further, in some embodiments, the bottom contact 2460 is a bottom contact layer.

[0130] Referring back to FIG. 24 , the micro LED array panel further includes a top contact 2480 and a top conductive layer 2470. The top contact 2480 is formed on the second type semiconductor layer 2420. The top conductive layer 2470 is formed on the top of the second type semiconductor layer 2420 and the top contact 2480, filling the second trench 2422. The conductivity type of the top contact 2480 is the same as the conductivity type of the second type semiconductor layer 2420. For example, the conductivity type of the second type semiconductor layer 2420 is N-type, and the conductivity type of the top contact 2480 is N-type. The top contact 2480 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 2480 is used to form an ohmic contact between the top conductive layer 2470 and the second type semiconductor layer 2420 to optimize the electrical properties of the micro LED. The diameter of the top contact 2480 is about 20-50 nm, and the thickness of the top contact 2480 is about 10-20 nm.

[0131] Further detailed characteristics of the micro LEDs in the micro LED array panel can be known by reference to the micro LEDs above, which will not be described further here.

[0132] The manufacturing method of the micro LED array panel at least includes: manufacturing the micro LEDs. The details of the manufacturing of the micro LEDs can be known by referring to the description of steps 501-509 in embodiment 1 and the description of steps 1403-1406 in embodiment 2, which will not be further described here.

[0133] In the first to third embodiments, a microlens may further be formed on or above the top surface of the second type semiconductor layer, such as on the top surface of the upper conductive layer, as can be understood by those skilled in the art.

[0134] The micro LEDs herein have a very small volume. The micro LEDs may be organic or inorganic LEDs. The micro LEDs may be applied to a micro LED array panel. The light emitting area of ​​the micro LED array panel is very small, for example 1 mm x 1 mm, 3 mm x 5 mm. In some embodiments, the light emitting area is the area of ​​the micro LED array in the micro LED array panel. The micro LED array panel includes one or more micro LED arrays forming a pixel array in which the micro LEDs are pixels, such as a 1600 x 1200, 680 x 480, or 1920 x 1080 pixel array. The diameter of the micro LEDs is in the range of about 200 nm to 2 μm. An IC backplane is formed on the back of the micro LED array and electrically connected to the micro LED array. The IC backplane receives signals such as image data from the outside via signal lines and controls whether or not the corresponding micro LEDs are made to emit light.

[0135] It should be noted that, as used herein, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another and do not require or imply an actual relationship or order between those entities or operations. Additionally, the words "comprising," "having," "containing," and "including," as well as other similar forms, are intended to have equivalent meanings and be open-ended, in that the item or items following any one of these words are not intended to be an exhaustive listing of such item or items, nor are they intended to be limited to only the item or items listed.

[0136] As used herein, unless otherwise stated, the term "or" includes all possible combinations unless impracticable. For example, if it is stated that a database can include A or B, the database can include A, or B, or A and B, unless otherwise stated or impracticable. As a second example, if it is stated that a database can include A, B, or C, the database can include A, or B, or C, or A and B, or A and B and C, unless otherwise stated or impracticable.

[0137] In the foregoing specification, the embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. Certain adaptations and modifications may be made to the described embodiments. Other embodiments may be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims. It is also intended that the order of steps depicted in the figures is for illustrative purposes only, and is not intended to be limited to the particular order of steps. Thus, one skilled in the art can appreciate that these steps may be performed in different orders while performing the same method.

[0138] In the drawings and specification, illustrative embodiments have been disclosed. However, many variations and modifications to these embodiments may be made. Thus, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A micro LED, a first type semiconductor layer; a light emitting layer formed on the first type semiconductor layer; the first type of semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure by the trench, the ion implantation fence being formed around the trench, the trench being formed around the mesa structure, and an electrical resistance of the ion implantation fence being higher than an electrical resistance of the mesa structure; Micro LED.

2. 10. The micro-LED of claim 1 , wherein a top surface of the ion implanted fence is lower than a top surface of the first type semiconductor layer.

3. 10. The micro-LED of claim 1, wherein a bottom surface of the ion implanted fence is aligned with or elevated above a bottom surface of the first type semiconductor layer.

4. 10. The micro LED of claim 1 , wherein the trench does not extend upwardly through a top surface of the first type semiconductor layer.

5. 5. The micro-LED of claim 4, wherein a top surface of the ion implanted fence is elevated above or aligned with a top surface of the trench.

6. The micro-LED of claim 4 , wherein a top surface of the ion implanted fence is lower than a top surface of the trench.

7. 10. The micro LED of claim 1, further comprising a second type semiconductor layer formed on said light emitting layer, said second type semiconductor layer having a different conductivity type than said first type semiconductor layer.

8. the mesa structure, the trench, and the ion implantation fence are a first mesa structure, a first trench, and a first ion implantation fence, respectively; the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure; a bottom surface of the second ion implantation fence is located higher than a bottom surface of the second type semiconductor layer; the second ion implantation fence is formed around the second trench; the second trench is formed around the second mesa structure; and an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure.

8. The micro LED of claim 7.

9. 9. The micro-LED of claim 8, wherein the second trench does not extend downward through the bottom surface of the second type semiconductor layer.

10. 10. The micro-LED of claim 9, wherein the bottom surface of the second ion-implanted fence is lower than or aligned with a bottom surface of the second trench.

11. 10. The micro-LED of claim 9, wherein the bottom surface of the second ion-implanted fence is higher than a bottom surface of the second trench.

12. 9. The micro-LED of claim 8, wherein a top surface of the second ion-implanted fence is aligned with or lower than a top surface of the second type of semiconductor layer.

13. 9. The micro-LED of claim 8, wherein the first mesa structure comprises one or more stair structures and the second mesa structure comprises one or more stair structures.

14. 9. The micro LED of claim 8, wherein a width of the first trench is less than or equal to 50% of a diameter of the first mesa structure and a width of the second trench is less than or equal to 50% of the diameter of the second mesa structure.

15. 15. The micro LED of claim 14, wherein the width of the first trench is less than or equal to 200 nm and the width of the second trench is less than or equal to 200 nm.

16. 9. The microLED of claim 8, wherein the first ion-implanted fence comprises a first light absorbing material and the second ion-implanted fence comprises a second light absorbing material, a conductivity type of the first light absorbing material being the same as the conductivity type of the first type of semiconductor and a conductivity type of the second light absorbing material being the same as the conductivity type of the second type of semiconductor, and the first light absorbing material and the second light absorbing material being selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

17. 8. The micro-LED of claim 7, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

18. 10. The micro-LED of claim 1 further comprising a bottom isolation layer filled in said trench.

19. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 20. The micro-LED of claim 18, wherein the micro-LED is selected from one or more of:

20. 8. The micro LED of claim 7, further comprising a top contact and a top conductive layer formed on a top surface of the second type semiconductor layer.

21. 9. The micro LED of claim 8, further comprising a top conductive layer and a top contact, said top contact formed on a top surface of said second mesa structure, and said top conductive layer formed on a top surface and sidewalls of said second mesa structure, on a top surface and sidewalls of said second ion implanted fence, and filling said second trench.

22. 9. The micro LED of claim 8, wherein ions implanted in the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F, and ions implanted in the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

23. 9. The micro LED of claim 8, wherein the first ion implantation fence is formed by implanting ions into at least the first type of semiconductor layer and the second ion implantation fence is formed by implanting ions into at least the second type of semiconductor layer.

24. 9. The micro LED of claim 8, wherein a width of the first ion implanted fence is less than or equal to 50% of a diameter of the first mesa structure and a width of the second ion implanted fence is less than or equal to 50% of the diameter of the second mesa structure.

25. the width of the first ion implantation fence is less than or equal to 200 nm, the diameter of the first mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 100 nm; the width of the second ion implantation fence is 200 nm or less, the diameter of the second mesa structure is 2500 nm or less, and the thickness of the second type semiconductor layer is 100 nm or less; 25. The micro LED of claim 24.

26. 8. The micro LED of claim 7, wherein the material of the first type semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and the material of the second type semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.

27. 10. The micro-LED of claim 1, further comprising an integrated circuit (IC) backplane formed below said first type semiconductor layer, and a connection structure electrically connecting said IC backplane with said first type semiconductor layer.

28. 28. The micro-LED of claim 27, wherein the connection structure is a connection pillar or a metal bonding layer.

29. 28. The micro-LED of claim 27, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

30. 30. A micro LED array panel comprising a plurality of micro LEDs according to any one of claims 1 to 29.

31. 1. A micro LED array panel, comprising: a first type of semiconductor layer formed within the micro LED array panel; a light emitting layer formed on the first type semiconductor layer; a second type of semiconductor layer formed on the light emitting layer; Equipped with The first type of semiconductor layer has a P-type conductivity, and the second type of semiconductor layer has an N-type conductivity; the first type of semiconductor layer comprises a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches; a top surface of the ion implantation fence is lower than a top surface of the first type semiconductor layer; the ion implantation fence is formed in the trench between adjacent mesa structures; the electrical resistance of the ion implantation fence is higher than the electrical resistance of the mesa structure; Micro LED array panel.

32. 32. The micro LED array panel of claim 31 , wherein the ion implantation fence is formed around the periphery of the trench, and the trench is formed around the periphery of the mesa structure.

33. 32. The micro LED array panel of claim 31 , wherein a bottom surface of the ion implanted fence is aligned with or elevated above a bottom surface of the first type semiconductor layer.

34. 32. The micro LED array panel of claim 31 , wherein a spacing between adjacent sidewalls of the mesa structure is less than or equal to 50% of a diameter of the mesa structure.

35. 35. The micro LED array panel of claim 34, wherein the spacing between adjacent sidewalls of the mesa structures is less than or equal to 600 nm.

36. 32. The micro LED array panel of claim 31 , wherein the ion implanted fence absorbs light from the mesa structure, the ion implanted fence comprising a light absorbing material selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

37. 32. The micro LED array panel of claim 31 , wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

38. 32. The micro LED array panel of claim 31 , further comprising a bottom isolation layer filled in the trenches.

39. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 40. The micro LED array panel of claim 38, wherein the micro LED array panel is selected from one or more of:

40. 32. The micro LED array panel of claim 31 , wherein the ions implanted in the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

41. 32. The micro LED array panel of claim 31 , wherein the ion implanted fence is formed by implanting ions into at least the first type semiconductor layer.

42. 32. The micro LED array panel of claim 31 , wherein a width of the ion implanted fence is less than or equal to 50% of a diameter of the mesa structure.

43. 43. The micro LED array panel of claim 42, wherein the width of the ion implanted fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and a thickness of the first type semiconductor layer is less than or equal to 300 nm.

44. 32. The micro LED array panel of claim 31 , wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

45. 32. The micro LED array panel of claim 31 further comprising a top contact formed on a top surface of the second type semiconductor layer.

46. 32. The micro LED array panel of claim 31 , further comprising an integrated circuit (IC) backplane beneath the first type semiconductor layer and connection structures electrically connecting the IC backplane with the first type semiconductor layer.

47. 47. The micro LED array panel of claim 46, wherein the connection structures are connection pillars.

48. 47. The micro LED array panel of claim 46, further comprising a bottom contact formed below a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

49. 32. The micro LED array panel of claim 31 , wherein the trenches do not extend upwardly through the top surface of the first type semiconductor layer.

50. 50. The micro LED array panel of claim 49, wherein the top surface of the ion implanted fence is elevated above or aligned with a top surface of the trench.

51. 50. The micro LED array panel of claim 49, wherein the top surface of the ion implanted fence is lower than a top surface of a trench.

52. 32. The micro LED array panel of claim 31 , wherein the mesa structure comprises one or more stair structures.

53. A method for manufacturing a micro LED, comprising: Providing an epitaxial structure comprising, in top-to-bottom order, a first type of semiconductor layer, a light emitting layer, and a second type of semiconductor layer; patterning the first type semiconductor layer to form mesa structures, trenches, and fences; depositing a bottom contact on the mesa structure; performing an ion implantation process within the fence to form an ion implanted fence; A method comprising:

54. after patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence; depositing a bottom isolation layer over the first type semiconductor layer and the bottom contact; patterning the bottom isolation layer to expose the bottom contact; depositing a metallic material over the bottom isolation layer and the bottom contact; polishing the metal material to a top surface of the bottom isolation layer to form a connection structure; inverting the epitaxial structure and bonding the connection structure to an integrated circuit (IC) backplane; 54. The method of claim 53, further comprising:

55. When depositing a metal material on the bottom isolation layer and the bottom contact, the material of the bottom isolation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 55. The method of claim 54, wherein the at least one of the following is selected from one or more of:

56. 55. The method of claim 54, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.

57. 57. The method of claim 56, wherein inverting the epitaxial structure to bond the connection structure to the integrated circuit (IC) backplane further comprises removing the substrate.

58. After the epitaxial structure is turned upside down and the connection structure is bonded to the IC backplane, forming a top contact and a top conductive layer on the top surface of the second type semiconductor layer; 57. The method of claim 56, further comprising:

59. depositing the bottom contact on the mesa structure; forming a protective mask to protect areas where the bottom contact will not be deposited; depositing the bottom contact material over the protective mask and over the first type semiconductor layer; removing the protective mask from the first type semiconductor layer and removing the material above the protective mask to form the bottom contact on the mesa structure; 54. The method of claim 53, further comprising:

60. performing an ion implantation process in the fence to form the ion implanted fence; forming a protective mask over areas not to be implanted while leaving the fence exposed; implanting ions into the fence; removing said protective mask; 54. The method of claim 53, further comprising:

61. 61. The method of claim 60, wherein said ion implantation step in said fence to form an ion implanted fence is performed with an energy of between 0 and 500 KeV.

62. 61. The method of claim 60, wherein a dose of between 1E10 and 9E17 is implanted when performing the ion implantation step in the fence to form the ion implanted fence.

63. 61. The method of claim 60, wherein the ion implantation step is performed in the fence to form an ion implanted fence by implanting ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F into the ion implanted fence.

64. 61. The method of claim 60, wherein when performing the ion implantation step in the fence to form the ion implanted fence, the width of the ion implanted fence is less than or equal to 50% of a diameter of the mesa structure.

65. 61. The method of claim 60, wherein when performing the ion implantation step in the fence to form the ion implantation fence, the width of the ion implantation fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 300 nm.

66. 54. The method of claim 53, wherein when patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is less than or equal to 50% of a diameter of the mesa structure.

67. 54. The method of claim 53, wherein a conductivity type of the first type semiconductor layer is P-type and a conductivity type of the second type semiconductor layer is N-type, a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

68. 68. The method of claim 67, wherein the ion implanted fence comprises a light absorbing material.

69. 69. The method of claim 68, wherein the light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

70. A micro LED, a first type semiconductor layer; a light emitting layer formed on the first type semiconductor layer; a second type of semiconductor layer formed on the light emitting layer; Equipped with The first type of semiconductor layer has a P-type conductivity, and the second type of semiconductor layer has an N-type conductivity; the second type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the bottom surface of the ion implantation fence being higher than the bottom surface of the second type semiconductor layer; the ion implantation fence is formed around the trench, the trench is formed around the mesa structure, and an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure; Micro LED.

71. 71. The micro LED of claim 70, wherein the trench does not extend downward through the bottom surface of the second type semiconductor layer.

72. 72. The micro LED of claim 71 , wherein the bottom surface of the ion implanted fence is lower than or aligned with a bottom surface of the trench.

73. 72. The micro LED of claim 71 , wherein the bottom surface of the ion implanted fence is elevated above a bottom surface of the trench.

74. 71. The microLED of claim 70, wherein a top surface of the ion implanted fence is aligned with or lower than a top surface of the second type semiconductor layer.

75. 71. The micro LED of claim 70, wherein the mesa structure comprises one or more stair structures.

76. 71. The micro LED of claim 70, wherein the width of the trench is no more than 50% of a diameter of the mesa structure.

77. 77. The micro LED of claim 76, wherein the width of the trench is less than or equal to 200 nm.

78. 71. The microLED of claim 70, wherein the ion implanted fence comprises a light absorbing material, the light absorbing material being selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

79. 71. The micro LED of claim 70, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

80. 71. The micro LED of claim 70, further comprising a dielectric layer filled within the trench.

81. The material of the dielectric layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 81. The micro-LED of claim 80, wherein the micro-LED is selected from one or more of:

82. 71. The micro LED of claim 70, further comprising a top conductive layer formed on a top and sidewalls of said mesa structure, on a top and sidewalls of said ion implanted fence, and filled within said trench.

83. 71. The micro LED of claim 70, wherein ions implanted in the ion implanted fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

84. 71. The micro LED of claim 70, wherein the ion implanted fence is formed by implanting ions into at least the second type semiconductor layer.

85. 71. The micro LED of claim 70, wherein a width of the ion implanted fence is no more than 50% of a diameter of the mesa structure.

86. 86. The microLED of claim 85, wherein the width of the ion implanted fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and a thickness of the second type semiconductor layer is less than or equal to 100 nm.

87. 71. The microLED of claim 70, wherein the material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

88. 71. The micro LED of claim 70, further comprising a top contact formed on a top surface of the second type semiconductor layer.

89. 71. The micro-LED of claim 70, further comprising an integrated circuit (IC) backplane underlying said first type semiconductor layer and a connection structure electrically connecting said IC backplane with said first type semiconductor layer.

90. 88. The micro LED of claim 87, wherein the connection structure is a connection pillar or a metal bonding layer.

91. 88. The micro LED of claim 87, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

92. 1. A micro LED array panel, comprising: a first type of semiconductor layer formed within the micro LED array panel; a light emitting layer formed on the first type semiconductor layer; a second type of semiconductor layer formed on the light emitting layer; Equipped with The first type of semiconductor layer has a P-type conductivity, and the second type of semiconductor layer has an N-type conductivity; the second type semiconductor layer comprises a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches, the bottom surfaces of the ion implantation fences being higher than the bottom surface of the second type semiconductor layer; the ion implantation fence is formed in the trench between adjacent mesa structures; the electrical resistance of the ion implantation fence is higher than the electrical resistance of the mesa structure; Micro LED array panel.

93. 93. The micro LED array panel of claim 92, wherein the ion implantation fence is formed around the periphery of the trench, and the trench is formed around the periphery of the mesa structure.

94. 93. The micro LED array panel of claim 92, wherein a top surface of the ion implanted fence is aligned with or lower than a top surface of the second type semiconductor layer.

95. 93. The micro LED array panel of claim 92, wherein a spacing between adjacent sidewalls of the mesa structure is less than or equal to 50% of a diameter of the mesa structure.

96. 96. The micro LED array panel of claim 95, wherein a spacing between adjacent sidewalls of the mesa structure is less than or equal to 600 nm.

97. 93. The micro LED array panel of claim 92, wherein the ion implanted fence absorbs light from the mesa structure, the ion implanted fence comprising a light absorbing material selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

98. 93. The micro LED array panel of claim 92, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

99. 93. The micro LED array panel of claim 92, further comprising a dielectric layer filled within the trenches.

100. The material of the dielectric layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 100. The micro LED array panel of claim 99, wherein the micro LED array panel is selected from one or more of:

101. 93. The micro LED array panel of claim 92, further comprising a top conductive layer formed on a top surface and sidewalls of said mesa structure, on a top surface and sidewalls of said ion implanted fences and filled within said trenches.

102. 93. The micro LED array panel of claim 92, wherein ions implanted in the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

103. 93. The micro LED array panel of claim 92, wherein the ion implanted fence is formed by implanting ions into at least the second type semiconductor layer.

104. 93. The micro LED array panel of claim 92, wherein a width of the ion implanted fence is less than or equal to 50% of a diameter of the mesa structure.

105. 105. The micro LED array panel of claim 104, wherein the width of the ion implanted fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and a thickness of the second type semiconductor layer is less than or equal to 100 nm.

106. 93. The micro LED array panel of claim 92, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

107. 93. The micro LED array panel of claim 92, further comprising a top contact formed on a top surface of the second type semiconductor layer.

108. 93. The micro LED array panel of claim 92, further comprising an integrated circuit (IC) backplane underlying said first type semiconductor layer and connection structures electrically connecting said IC backplane with said first type semiconductor.

109. 109. The micro LED array panel of claim 108, wherein the connection structures are connection pillars or metal bonding layers.

110. 109. The micro LED array panel of claim 108, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

111. 93. The micro LED array panel of claim 92, wherein the trenches do not extend downward through the bottom surface of the second type semiconductor layer.

112. 112. The micro LED array panel of claim 111, wherein the bottom surface of the ion implanted fence is lower than or aligned with a bottom surface of the trench.

113. 112. The micro LED array panel of claim 111, wherein the bottom surface of the ion implanted fence is higher than the bottom surface of the trench.

114. A method for manufacturing a micro LED, comprising: Providing an epitaxial structure comprising, in top-to-bottom order, a first type of semiconductor layer, a light emitting layer, and a second type of semiconductor layer; bonding the epitaxial structure to an integrated circuit (IC) backplane; patterning the second type semiconductor layer to form mesa structures, trenches, and fences; depositing a top contact on the mesa structure; performing an ion implantation process within the fence; depositing a top conductive layer on the top surface of the second type semiconductor layer, on the top contact, and in the trench; A method comprising:

115. Providing the epitaxial structure includes: depositing a bottom contact layer on a top surface of the first type semiconductor layer; depositing a metal bonding layer on an upper surface of the bottom contact layer; 115. The method of claim 114, further comprising:

116. Bonding the epitaxial structure to the IC backplane comprises: turning the epitaxial structure upside down; bonding said metal bonding layer to a contact pad of said IC backplane; 116. The method of claim 115, further comprising:

117. 117. The method of claim 116, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.

118. Bonding the epitaxial structure to the IC backplane comprises:

118. The method of claim 117, further comprising removing the substrate.

119. patterning the second type semiconductor layer to form the mesa structure, the trench, and the fence includes: Etching the second type semiconductor layer down to a surface of the light emitting layer.

115. The method of claim 114, further comprising:

120. depositing the top contact on the mesa structure; forming a protective mask; depositing the top contact material over the protective mask; removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask to form the top contact on the mesa structure; 115. The method of claim 114, further comprising:

121. performing the ion implantation step within the fence, forming a protective mask over areas not to be implanted while leaving the fence exposed; implanting ions into the fence; removing said protective mask; 115. The method of claim 114, further comprising:

122. 122. The method of claim 121, wherein the step of implanting ions into the fence is performed with an energy of between 0 and 500 KeV.

123. 122. The method of claim 121, wherein a dose of between 1E10 and 9E17 is implanted when performing the ion implantation step in the fence.

124. 122. The method of claim 121, wherein the ion implantation step in the fence comprises implanting the ion implantation fence with ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

125. 122. The method of claim 121, wherein a width of the ion implantation fence is less than or equal to 50% of a diameter of the mesa structure when performing the ion implantation step within the fence.

126. 122. The method of claim 121, wherein when performing the ion implantation step within the fence, the width of the ion implantation fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the second type semiconductor layer is less than or equal to 100 nm.

127. 115. The method of claim 114, wherein a conductivity type of the first type semiconductor layer is P-type and a conductivity type of the second type semiconductor layer is N-type, a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

128. 128. The method of claim 127, wherein the ion implanted fence comprises a light absorbing material.

129. 129. The method of claim 128, wherein the light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

130. A micro LED, a first type semiconductor layer; a light emitting layer formed on the first type semiconductor layer; a second type of semiconductor layer formed on the light emitting layer; Equipped with The first type of semiconductor layer has a P-type conductivity, and the second type of semiconductor layer has an N-type conductivity; the first type semiconductor layer comprises a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure, the top surface of the first ion implantation fence being lower than the top surface of the first type semiconductor layer; the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure, the bottom surface of the second ion implantation fence being higher than the bottom surface of the second type semiconductor layer; the first ion implantation fence is formed around the first trench, the first trench is formed around the first mesa structure, and an electrical resistance of the first ion implantation fence is higher than an electrical resistance of the first mesa structure; the second ion implantation fence is formed around the second trench, the second trench is formed around the second mesa structure, and an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure; Micro LED.

131. a center of the first mesa structure is aligned with a center of the second mesa structure, a center of the first trench is aligned with a center of the second trench, and a center of the first ion implantation fence is aligned with a center of the second ion implantation fence.

131. The micro LED of claim 130.

132. a bottom surface of the first ion implantation fence is aligned with or above a bottom surface of the first type semiconductor layer, and / or a top surface of the second ion implantation fence is aligned with or below a top surface of the second type semiconductor layer.

131. The micro LED of claim 130.

133. 131. The micro LED of claim 130, wherein the first trench does not extend upward through the top surface of the first type semiconductor layer and / or the second trench does not extend downward through the bottom surface of a second type semiconductor layer.

134. 134. The micro LED of claim 133, wherein the top surface of the first ion implanted fence is higher than or aligned with a top surface of the first trench, and / or the bottom surface of the second ion implanted fence is lower than or aligned with a bottom surface of the second trench.

135. 134. The micro LED of claim 133, wherein the top surface of the first ion implanted fence is lower than a top surface of the first trench and / or the bottom surface of the second ion implanted fence is higher than a bottom surface of the second trench.

136. 131. The micro LED of claim 130, wherein the first mesa structure comprises one or more stair structures and / or the second mesa structure comprises one or more stair structures.

137. 131. The micro LED of claim 130, wherein a width of the first trench is less than or equal to 50% of a diameter of the first mesa structure and / or a width of the second trench is less than or equal to 50% of a diameter of the second mesa structure.

138. 138. The micro LED of claim 137, wherein the width of the first trench is less than or equal to 200 nm and / or the width of the second trench is less than or equal to 200 nm.

139. 131. The microLED of claim 130, wherein the first ion implanted fence comprises a first light absorbing material and / or the second ion implanted fence comprises a second light absorbing material, the first light absorbing material selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and / or the second light absorbing material selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

140. 131. The micro LED of claim 130, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

141. 131. The micro LED of claim 130, further comprising a bottom isolation layer filled in the first trench and a dielectric layer filled in the second trench.

142. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ and / or the material of the dielectric layer is selected from one or more of SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 142. The micro LED of claim 141, wherein the micro LED is one or more of:

143. 131. The micro LED of claim 130, further comprising an upper conductive layer formed on a top surface and sidewalls of the second mesa structure, on a top surface and sidewalls of the second ion implanted fence and filled within the second trench.

144. 131. The micro LED of claim 130, wherein ions implanted in the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F, and / or ions implanted in the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

145. 131. The micro LED of claim 130, wherein the first ion implanted fence is formed by implanting ions into at least the first type of semiconductor layer and / or the second ion implanted fence is formed by implanting ions into at least the second type of semiconductor layer.

146. 131. The micro LED of claim 130, wherein a width of the first ion implanted fence is less than or equal to 50% of a diameter of the first mesa structure and / or a width of the second ion implanted fence is less than or equal to 50% of a diameter of the second mesa structure.

147. the width of the first ion implantation fence is 200 nm or less, the diameter of the first mesa structure is 2500 nm or less, and the thickness of the first type of semiconductor layer is 100 nm or less; and / or the width of the second ion implantation fence is 200 nm or less, the diameter of the second mesa structure is 2500 nm or less, and the thickness of the second type semiconductor layer is 300 nm or less; 147. The micro LED of claim 146.

148. 131. The microLED of claim 130, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN and / or a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

149. 131. The micro LED of claim 130, further comprising a top contact formed on a top surface of the second type semiconductor layer.

150. 131. The micro-LED of claim 130, further comprising an integrated circuit (IC) backplane underlying said first type semiconductor layer and a connection structure electrically connecting said IC backplane with said first type semiconductor layer.

151. 151. The micro LED of claim 150, wherein the connection structure is a connection pillar or a metal bonding layer.

152. 151. The micro LED of claim 150, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

153. 1. A micro LED array panel, comprising: a first type of semiconductor layer formed within the micro LED array panel; a light emitting layer formed on the first type semiconductor layer; a second type of semiconductor layer formed on the light emitting layer; Equipped with The first type of semiconductor layer has a P-type conductivity, and the second type of semiconductor layer has an N-type conductivity; the first type semiconductor layer comprises a plurality of first mesa structures, a plurality of first trenches, and a plurality of first ion implantation fences separated from the first mesa structures by the first trenches; a top surface of the first ion implantation fence is aligned with or below a top surface of the first type semiconductor layer; the first ion implantation fences are formed in the first trenches between adjacent first type mesa structures, and an electrical resistance of the first ion implantation fences is higher than an electrical resistance of the first mesa structures; The second type of semiconductor layer comprises a plurality of second mesa structures, a plurality of second trenches, and a plurality of second ion implantation fences separated from the second mesa structures by the second trenches. a bottom surface of the second ion implantation fence is aligned with or elevated above a bottom surface of the second type semiconductor layer; the second ion implantation fences are formed in the second trenches between adjacent second mesa structures, and an electrical resistance of the second ion implantation fences is higher than an electrical resistance of the second mesa structures; Micro LED array panel.

154. 154. The micro LED array panel of claim 153, wherein a center of the first mesa structure is aligned with a center of the second mesa structure, a center of the first trench is aligned with a center of the second trench, and a center of the first ion implantation fence is aligned with a center of the first ion implantation fence.

155. 154. The micro LED array panel of claim 153, wherein the first ion implantation fence is formed around the first trench, the first trench being formed around the first mesa structure, and the second ion implantation fence is formed around the second trench, and the second trench is formed around the second mesa structure.

156. a bottom surface of the first ion implantation fence is aligned with or elevated above a bottom surface of the first type semiconductor layer; a top surface of the second ion implantation fence is aligned with or below a top surface of the second type semiconductor layer; 156. The micro LED array panel of claim 155.

157. 154. The micro LED array panel of claim 153, wherein a spacing between adjacent sidewalls of the first mesa structure is less than or equal to 50% of a diameter of the first mesa structure, and a spacing between adjacent sidewalls of the second mesa structure is less than or equal to 50% of a diameter of the second mesa structure.

158. 158. The micro LED array panel of claim 157, wherein the spacing between adjacent sidewalls of the first mesa structure is less than or equal to 600 nm and the spacing between adjacent sidewalls of the second mesa structure is less than or equal to 600 nm.

159. 154. The micro LED array panel of claim 153, wherein the first ion implanted fence absorbs light from the first mesa structure and the second ion implanted fence absorbs light from the second mesa structure, the first ion implanted fence comprises a first light absorbing material and the second ion implanted fence comprises a second light absorbing material, the first light absorbing material selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the second light absorbing material selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

160. 154. The micro LED array panel of claim 153, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

161. 154. The micro LED array panel of claim 153, further comprising a bottom isolation layer filled in the first trenches and a dielectric layer filled in the second trenches.

162. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ and the material of the dielectric layer is selected from one or more of SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 162. The micro LED array panel of claim 161, wherein the micro LED array panel is selected from one or more of:

163. 154. The micro LED array panel of claim 153, further comprising a top conductive layer formed on a top surface and sidewalls of said second mesa structure, on a top surface and sidewalls of said second ion implanted fence, and filled within said second trench.

164. 154. The micro LED array panel of claim 153, wherein the first ions implanted in the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F and the second ions implanted in the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

165. 154. The micro LED array panel of claim 153, wherein the first ion implanted fence is formed by implanting ions into at least the first type semiconductor layer.

166. 154. The micro LED array panel of claim 153, wherein a width of the first ion implanted fence is less than or equal to 50% of a diameter of the first mesa structure and a width of the second ion implanted fence is less than or equal to 50% of a diameter of the second mesa structure.

167. the width of the ion implantation fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 300 nm; and 167. The micro LED array panel of claim 166, wherein the width of the second ion implanted fence is less than or equal to 200 nm, the diameter of the second mesa structure is less than or equal to 2500 nm, and a thickness of the second type semiconductor layer is less than or equal to 100 nm.

168. 154. The micro LED array panel of claim 153, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

169. 154. The micro LED array panel of claim 153, further comprising a top contact formed on a top surface of the second type semiconductor layer.

170. 154. The micro LED array panel of claim 153, further comprising an integrated circuit (IC) backplane formed beneath said first type semiconductor layer, and connection structures electrically connecting said IC backplane with said first type semiconductor layer.

171. 171. The micro LED array panel of claim 170, wherein the connection structures are connection pillars or metal bonding layers.

172. 171. The micro LED array panel of claim 170, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

173. 154. The micro LED array panel of claim 153, wherein the first trenches do not extend upwardly through the top surface of the first type semiconductor layer and the second trenches do not extend downwardly through the bottom surface of the second type semiconductor layer.

174. 174. The micro LED array panel of claim 173, wherein the top surface of the first ion implanted fence is higher than or aligned with a top surface of the first trench and the bottom surface of the second ion implanted fence is lower than or aligned with a bottom surface of the first trench.

175. 174. The micro LED array panel of claim 173, wherein the top surface of the first ion implanted fence is lower than a top surface of the first trench and the bottom surface of the second ion implanted fence is higher than a bottom surface of the second trench.

176. A method for manufacturing a micro LED, comprising: Step I includes patterning a first type of semiconductor layer and implanting first ions into the first type of semiconductor layer; Step II includes patterning a second type of semiconductor layer and implanting second ions into the second type of semiconductor layer. A method comprising:

177. The step I comprises: Providing an epitaxial structure comprising, in top-to-bottom order, a first type of semiconductor layer, a light emitting layer, and a second type of semiconductor layer; patterning the first type semiconductor layer to form mesa structures, trenches, and fences; depositing a bottom contact on the mesa structure; performing an ion implantation process within the fence to form an ion implanted fence; depositing a bottom isolation layer over the first type semiconductor layer and the bottom contact; patterning the bottom isolation layer to expose the bottom contact; depositing a metallic material over the bottom isolation layer and the bottom contact; polishing the metal material to a top surface of the bottom isolation layer to form a connection structure; inverting the epitaxial structure and bonding the connection structure to an integrated circuit (IC) backplane; 177. The method of claim 176, further comprising:

178. depositing the bottom contact on the mesa structure; forming a protective mask to protect areas where the bottom contact is not to be deposited; depositing the bottom contact material over the protective mask and over the first type semiconductor layer; removing the protective mask from the first type semiconductor layer and removing the material above the protective mask to form the bottom contact on the mesa structure; 178. The method of claim 177, further comprising:

179. performing the ion implantation process within the fence to form the ion implanted fence; forming a protective mask over areas not to be implanted while leaving the fence exposed; implanting ions into the fence; removing said protective mask; 178. The method of claim 177, further comprising:

180. 180. The method of claim 179, wherein said ion implantation step in said fence to form said ion implanted fence comprises implanting at an energy between 0 and 500 KeV and implanting a dose between 1E10 and 9E17.

181. 180. The method of claim 179, wherein when the ion implantation step is performed in the fence to form the ion implanted fence, ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F are implanted in the fence.

182. 180. The method of claim 179, wherein when performing the ion implantation step in the fence to form the ion implantation fence, a width of the ion implantation fence is 50% or less of a diameter of the mesa structure, the width of the ion implantation fence is 200 nm or less, the diameter of the mesa structure is 2500 nm or less, and a thickness of the first type semiconductor layer is 300 nm or less.

183. 178. The method of claim 177, wherein when patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is less than or equal to 50% of a diameter of the mesa structure.

184. the mesa structure, the trench, and the fence are a first mesa structure, a first trench, and a first fence, respectively; The step II comprises: patterning the second type semiconductor layer to form a second mesa structure, a second trench, and a second fence; depositing a top contact on the second mesa structure; performing an ion implantation process within the second fence; depositing a top conductive layer on a top surface of the second type semiconductor layer, on the top contact, and in the second trench; 177. The method of claim 176, further comprising:

185. Depositing the top contact on the second mesa structure comprises: forming a protective mask; depositing the top contact material over the protective mask; removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask to form a top contact on the second mesa structure; 185. The method of claim 184, further comprising:

186. Performing the ion implantation step within the second fence includes: forming a protective mask over areas not to be implanted while leaving the second fence exposed; implanting the ions into the second fence; removing said protective mask; 185. The method of claim 184, further comprising:

187. 184. The method of claim 183, wherein the ion implantation step in the second fence is performed with an energy of 0 to 500 KeV and a dose of 1E10 to 9E17.

188. 184. The method of claim 183, wherein when performing the ion implantation step in the second fence, ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F are implanted into the second fence.

189. 184. The method of claim 183, wherein when performing the ion implantation step within the second fence, a width of the second ion implantation fence is less than or equal to 50% of a diameter of the second mesa structure, the width of the second ion implantation fence is less than or equal to 200 nm, the diameter of the second mesa structure is less than or equal to 2500 nm, and a thickness of the second type semiconductor layer is less than or equal to 100 nm.

190. providing the epitaxial structure, the epitaxial structure being grown on a substrate, and inverting the epitaxial structure to bond the connection structure to the IC backplane; Removing the substrate.

178. The method of claim 177, further comprising:

191. When the bottom isolation layer is deposited on the first type semiconductor layer and the bottom contact, the material of the bottom isolation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 178. The method of claim 177, wherein the method is selected from one or more of:

192. 178. The method of claim 177, wherein the ion implanted fence comprises a light absorbing material.

194. 200. The method of claim 192, wherein the light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

194. 178. The method of claim 177, wherein the conductivity type of the first type semiconductor layer is P-type and the conductivity type of the second type semiconductor layer is N-type, the material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

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