Micro LED, Micro LED Array Panel and Manufacturing Method Thereof

Abstract

The micro LED includes a first type of semiconductor layer, a first type of cap layer formed on the first type of semiconductor layer, and a light emitting layer formed on the first type of cap layer, the first type of semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the ion implantation fence is formed around the trench, the trench is formed around the mesa structure, and an electrical resistance of the first ion implantation fence is higher than an electrical resistance of the first mesa structure.

Description

[Technical field]

[0001] The present disclosure relates generally to light emitting diodes, and more particularly to micro light emitting diodes (LEDs), micro LED array panels, and methods for manufacturing the same. [Background technology]

[0002] Inorganic micropixel light-emitting diodes, also known as micro light-emitting diodes, micro LEDs or μ-LEDs, are gaining importance due to their use in a variety of applications including self-emissive microdisplays, visible light communications, and optogenetics. Micro LEDs exhibit higher output performance than conventional LEDs due to better strain relief, increased light extraction efficiency, and uniform current spreading. Micro LEDs also exhibit improved thermal effects, fast response speeds, wider operating temperature ranges, higher resolution, color gamut and contrast, as well as lower power consumption and can be operated at higher current densities compared to conventional LEDs.

[0003] Inorganic micro-LEDs are traditionally III-V epitaxial layers formed as multiple mesas. In traditional micro-LED structures, a space is formed between adjacent micro-LEDs to avoid carriers in the epitaxial layers from diffusing from one mesa to the adjacent mesa. However, the space formed between adjacent micro-LEDs can reduce the active light-emitting area and reduce the light extraction efficiency. If there is no space between adjacent micro-LEDs, the active light-emitting area will increase and carriers in the epitaxial layers will diffuse laterally toward the adjacent mesas, reducing the light-emitting efficiency of the micro-LEDs. In addition, if there is no space between adjacent mesas, crosstalk will occur between adjacent micro-LEDs, interfering with the operation of the LEDs.

[0004] However, smaller micro LEDs with higher current densities experience red shifts at high current densities, reduced maximum efficiency, and non-uniform emission, which are attributed to damage in the fabrication process, resulting in poor electrical injection. Furthermore, the peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) decrease significantly with decreasing chip size. The decrease in EQE is due to non-radiative recombination caused by etching damage, while the decrease in IQE is due to poor current injection and electron leakage current in micro LEDs.

[0005] The above discussion is merely intended to aid in understanding the technical problem overcome by the present disclosure, and is not an admission that the above is prior art. Summary of the Invention

[0006] An embodiment of the present disclosure provides a micro-LED, the micro-LED including a first type of semiconductor layer, a first type of cap layer formed on the first type of semiconductor layer, and a light emitting layer formed on the first type of cap layer, the first type of semiconductor layer including a mesa structure, a trench, and an ion-implanted fence separated from the mesa structure, the ion-implanted fence being formed around the trench, the trench being formed around the mesa structure, and an electrical resistance of the first ion-implanted fence being higher than an electrical resistance of the first mesa structure.

[0007] An embodiment of the present disclosure provides a micro LED array panel, the micro LED array panel includes a first type of semiconductor layer formed in the micro LED array panel, a first type of cap layer formed on the first type of semiconductor layer, a light emitting layer formed on the first type of cap layer, a second type of cap layer formed on the light emitting layer, and a second type of semiconductor layer formed on the second type of cap layer, the first type being P-type and the second type being N-type, the first type of semiconductor layer includes a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches, a top surface of the ion implantation fences is lower than or aligned with a top surface of the first type of semiconductor layer, the ion implantation fences are formed between adjacent mesa structures around the trenches, and an electrical resistance of the ion implantation fences is higher than an electrical resistance of the mesa structures.

[0008] An embodiment of the present disclosure provides a method for manufacturing a micro LED, the method includes providing an epitaxial structure including, in top-down order, a first type of semiconductor layer, a first type of cap layer, a light emitting layer, a second type of cap layer, and a second type of semiconductor layer, patterning the first type of semiconductor layer to form a mesa structure, a trench, and a fence, depositing a bottom contact on the mesa structure, and performing an ion implantation process on the fence to form an ion-implanted fence.

[0009] An embodiment of the present disclosure provides a micro LED, the micro LED includes a first type of semiconductor layer, a first type of cap layer formed on the first type of semiconductor layer, a light emitting layer formed on the first type of cap layer, a second type of cap layer formed on the light emitting layer, and a second type of semiconductor layer formed on the second type of cap layer, the first type being P-type and the second type being N-type, the second type of semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, a bottom surface of the ion implantation fence is not lower than a bottom surface of the second type of semiconductor layer, the ion implantation fence is formed around the trench, the trench is formed around the mesa structure, and an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure.

[0010] An embodiment of the present disclosure provides a micro LED array panel, comprising: a first type of semiconductor layer formed in the micro LED array panel, a first type of cap layer formed on the first type of semiconductor layer, a light emitting layer formed on the first type of cap layer, a second type of cap layer formed on the light emitting layer, and a second type of semiconductor layer formed on the second type of cap layer, the first type being P-type and the second type being N-type, the second type of semiconductor layer comprising a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches, a bottom surface of the ion implantation fences being higher than or aligned with a bottom surface of the second type of semiconductor layer, the ion implantation fences being formed around the trenches and between adjacent mesa structures, and an electrical resistance of the ion implantation fences being higher than an electrical resistance of the mesa structures.

[0011] An embodiment of the present disclosure provides a method for manufacturing a micro LED, the method including: providing an epitaxial structure including, in top-down order, a first type of semiconductor layer, a first type of cap layer, a light emitting layer, a second type of cap layer, and a second type of semiconductor layer, bonding the epitaxial structure with an integrated circuit (IC) backplane, patterning the second type of semiconductor layer to form a mesa structure, a trench, and a fence, depositing a top contact on the mesa structure, performing an ion implantation process on the fence, and depositing a top conductive layer on a top surface of the second type of semiconductor layer, on the top contact, and in the trench.

[0012] An embodiment of the present disclosure provides a micro LED, the micro LED includes a first type of semiconductor layer, a first type of cap layer formed on the first type of semiconductor layer, a light emitting layer formed on the first type of cap layer, a second type of cap layer formed on the light emitting layer, and a second type of semiconductor layer formed on the second type of cap layer, the first type being P-type and the second type being N-type, the first type of semiconductor layer includes a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure, the top surface of the first ion implantation fence is lower than or aligned with the top surface of the first type of semiconductor layer, and the second ... first mesa structure includes a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure, the first mesa structure includes a first mesa structure, a first trench, and a first mesa structure, the first mesa structure includes a first mesa structure, a first mesa structure, and a first mesa structure. the second ion implantation fence is formed around the first trench, the first trench is formed around the first mesa structure, and an electrical resistance of the first ion implantation fence is higher than an electrical resistance of the first mesa structure; the second ion implantation fence is formed around the second trench, the second trench is formed around the second mesa structure, and an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure.

[0013] An embodiment of the present disclosure provides a micro LED array panel, the micro LED array panel includes a first type of semiconductor layer formed in the micro LED array panel, a first type of cap layer formed on the first type of semiconductor layer, a light emitting layer formed on the first type of cap layer, a second type of cap layer formed on the light emitting layer, and a second type of semiconductor layer formed on the second type of cap layer, the first type being P-type and the second type being N-type, the first type of semiconductor layer includes a plurality of first mesa structures, a plurality of first trenches, and a plurality of first ion implantation fences separated from the first mesa structures by the first trenches, and a top surface of the first ion implantation fences is lower than or aligned with a top surface of the first type of semiconductor layer. a first ion implantation fence is formed around the first trench and between adjacent first type mesa structures, the electrical resistance of the first ion implantation fence being higher than the electrical resistance of the first mesa structure; the second type semiconductor layer includes a plurality of second mesa structures, a plurality of second trenches, and a plurality of second ion implantation fences separated from the second mesa structures by the second trenches, the bottom surface of the second ion implantation fence being higher than or aligned with the bottom surface of the second type semiconductor layer; the second ion implantation fence is formed around the second trench and between adjacent second mesa structures, the electrical resistance of the second ion implantation fence being higher than the electrical resistance of the second mesa structure.

[0014] An embodiment of the present disclosure provides a method for manufacturing a micro LED, the method including step I including patterning a first type of semiconductor layer and implanting the first type of semiconductor layer with first ions, and step II including patterning a second type of semiconductor layer and implanting the second type of semiconductor layer with second ions.

[0015] Embodiments and various aspects of the present disclosure are set forth in the following detailed description and the accompanying drawings, in which various features are not drawn to scale. [Brief description of the drawings]

[0016] [Figure 1A] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1B] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1C] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1D] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1E] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1F] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1G] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1H] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Diagram 2] FIG. 2 is a structural diagram illustrating a bottom view of a first exemplary micro LED according to some embodiments of the present disclosure. [Diagram 3] FIG. 2 is a structural diagram illustrating a cross-sectional side view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. [Figure 4] FIG. 2 is a structural diagram illustrating a cross-sectional side view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. [Diagram 5]1 is a flowchart of a method for manufacturing a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 6A] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 501 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6B] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 502 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6C] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 503 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6D] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 504 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6E] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 505 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6F] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 506 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6G] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 507 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6H] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 508 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6I] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 509 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6J] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process at step 510 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 7]FIG. 1C is a structural diagram illustrating a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 1B according to some embodiments of the present disclosure. [Figure 8] FIG. 8 is a structural diagram showing a bottom view of the side-by-side micro-LEDs of FIG. 7 according to some embodiments of the present disclosure. [Figure 9] FIG. 4 is a structural diagram illustrating a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 3 according to some embodiments of the present disclosure. [Figure 10A] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10B] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10C] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10D] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10E] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10F] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10G] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10H] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 11] FIG. 1 is a structural diagram illustrating a top view of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 12A]FIG. 13 is a structural diagram illustrating a cross-sectional side view of another variation of the second exemplary micro LED according to some embodiments of the present disclosure. [Figure 12B] FIG. 13 is a structural diagram illustrating a cross-sectional side view of another variation of the second exemplary micro LED according to some embodiments of the present disclosure. [Figure 13] FIG. 1 is a structural diagram illustrating a cross-sectional side view of another variation of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 14] 1 shows a flowchart of a second exemplary method for fabricating a micro LED according to some embodiments of the present disclosure. [Figure 15A] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1401 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15B] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1402 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15C] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1403 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15D] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1404 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15E] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1405 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15F] FIG. 15 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 1406 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 16] FIG. 10C is a structural diagram showing a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 10B according to some embodiments of the present disclosure. [Figure 17] FIG. 17 is a structural diagram showing a top view of the side-by-side micro-LEDs of FIG. 16 according to some embodiments of the present disclosure. [Figure 18A] 1A-1C are structural diagrams illustrating side-by-side cross-sectional views of different variations of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 18B] 1A-1C are structural diagrams illustrating side-by-side cross-sectional views of different variations of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 18C] 1A-1C are structural diagrams illustrating side-by-side cross-sectional views of different variations of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 19] FIG. 13 is a structural diagram illustrating a cross-sectional side view of a third exemplary micro LED variation according to some embodiments of the present disclosure. [Figure 20] FIG. 13 is a structural diagram illustrating a cross-sectional side view of another variation of the third exemplary micro LED according to some embodiments of the present disclosure. [Figure 21] 1 shows a flowchart of a third exemplary method for manufacturing a micro LED according to some embodiments of the present disclosure. [Figure 22A] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process at step 2110 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 22B] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process at step 2111 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 22C] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process at step 2112 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 22D] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 2113 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 23] FIG. 20 is a structural diagram illustrating a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 19 according to some embodiments of the present disclosure. [Figure 24]FIG. 21 is a structural diagram showing a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 20 according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which like numbers in different drawings represent the same or similar elements unless otherwise specified. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the present invention. Instead, these are merely examples of apparatus and methods consistent with aspects related to the present invention as set forth in the appended claims. Certain aspects of the present disclosure are described in more detail below. In the event of a conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall control.

[0018] The present disclosure provides a micro LED that can avoid non-radiative recombination on the sidewall of the mesa according to the structure of the semiconductor layer and the light emitting layer that are successively formed. Moreover, compared with conventional micro LEDs, the spacing between adjacent mesas can be significantly reduced by the ion implantation fence. Thus, the integration of micro LEDs in a chip is increased and the active light emitting efficiency is improved. Moreover, the micro LED provided by the present disclosure can also increase the active light emitting area and improve image quality.

[0019] EMBODIMENT 1 1A-1H are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure.

[0020] 1A-1H, the micro LED includes a first type semiconductor layer 110, a first type cap layer 114, a light emitting layer 130, a second type cap layer 124, and a second type semiconductor layer 120. The light emitting layer 130 is formed on the first type cap layer 114 above the first type semiconductor layer 110, and the second type semiconductor layer 120 is formed on the second type cap layer 124 above the light emitting layer 130. The thickness of the first type semiconductor layer 110 is thicker than the thickness of the second type semiconductor layer 120.

[0021] The conductivity type of the first type semiconductor layer 110 is different from the conductivity type of the second type semiconductor layer 120. In some embodiments, the conductivity type of the first type semiconductor layer 110 is P-type and the conductivity type of the second type semiconductor layer 120 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 120 is P-type and the conductivity type of the first type semiconductor layer 110 is N-type. For example, the material of the first type semiconductor layer 110 can be selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 120 can be selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0022] The first-type cap layer 114 has a conductivity type that is the same as that of the first-type semiconductor layer 110, and the second-type cap layer 124 has a conductivity type that is the same as that of the second-type semiconductor layer 120. The first-type semiconductor layer 110 includes a mesa structure 111, a trench 112, and an ion implantation fence 113. The ion implantation fence 113 is separated from the mesa structure 111 by the trench 112. The trench 112 and the ion implantation fence 113 are formed in a ring shape around the mesa structure 111.

[0023] The ion implantation fence 113 includes a light absorbing material that absorbs light from the mesa structure 111. The conductivity type of the light absorbing material is the same as the conductivity type of the first semiconductor layer 110. Preferably, the light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. Furthermore, the ion implantation fence 113 is formed by implanting ions into at least the first type semiconductor layer 110. Preferably, the type of ions implanted into the first type semiconductor layer 110 is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0024] Additionally, the width of the ion implantation fence 113 is less than or equal to 50% of the diameter of the mesa structure 111. In some embodiments, the width of the ion implantation fence 113 is less than or equal to 10% of the diameter of the mesa structure 111. Preferably, the width of the ion implantation fence 113 is less than or equal to 200 nm, the diameter of the mesa structure 111 is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer 110 is less than or equal to 300 nm.

[0025] In some embodiments, the width of trench 112 is less than or equal to 50% of the diameter of mesa structure 111. In some embodiments, the width of trench 112 is less than or equal to 10% of the diameter of mesa structure 111. Preferably, the width of first trench 112 is less than or equal to 200 nm.

[0026] In some embodiments, the top surface of the ion implantation fence 113 is not higher than the top surface of the first type semiconductor layer 110. Thus, the ion implantation fence 113 can contact the first type cap layer 114 but cannot contact the light emitting layer 130. The top surface of the ion implantation fence 113 can be formed anywhere in the first type semiconductor layer 110. As shown in FIG. 1A, a trench 112 extends upward through the first type semiconductor layer 110 to the first type cap layer 114. The top surface of the trench 112 is aligned with the top surface of the first type semiconductor layer 110. The top surface of the ion implantation fence 113 is aligned with the top surface of the trench 112. FIG. 2 is a structural diagram illustrating a bottom view of the first exemplary micro-LED shown in FIG. 1A according to some embodiments of the present disclosure. FIG. 2 illustrates a bottom view of the first type semiconductor layer 110 with the ion implantation fence 113 separated from the mesa structure 111 by the trench 112. An ion implantation fence 113 is formed around the trench, which in turn is formed around the mesa structure 111. The trench extends up through the first type semiconductor layer 110 to the first type cap layer 114, such that the first type cap layer 114 is visible through the trench in a bottom view.

[0027] 1B, in some embodiments, the top surface of the ion implantation fence 113 is lower than the top surface of the trench 112. Additionally, in some embodiments, the trench 112 extends upward through the first type semiconductor layer 110 and into the first type cap layer 114. In some embodiments, the trench 112 extends upward through the first type semiconductor layer 110 and the first type cap layer 114 and further into the light emitting layer 130. In some embodiments, the trench 112 extends upward through the first type semiconductor layer 110 and the first type cap layer 114 and further into the light emitting layer 130. In some embodiments, the trench 112 extends upward through the first type semiconductor layer 110, the first type cap layer 114, and the light emitting layer 130. Furthermore, in some embodiments, the trench 112 extends upward through the first type semiconductor layer 110, the first type cap layer 114, and the light emitting layer 130, and further extends upward into the second type cap layer 124. Further, in some embodiments, the trench 112 extends upward through the first type semiconductor layer 110, the first type cap layer 114, the light emitting layer 130, and the second type cap layer 124, and further extends upward into the second type semiconductor layer 120.

[0028] With reference to Figure 1C, in some embodiments, trench 112 does not extend upward through first type semiconductor layer 110. The top surface of ion implant fence 113 is higher than the top surface of trench 112. With reference to Figure 1D, in some embodiments, the top surface of ion implant fence 113 is aligned with the top surface of trench 112. With reference to Figure 1E, in some embodiments, the top surface of ion implant fence 113 is lower than the top surface of trench 112.

[0029] Additionally, the bottom surface of the ion implantation fence 113 can be formed at any location. Preferably, the bottom surface of the ion implantation fence 113 is aligned with the bottom surface of the first type semiconductor layer 110. With reference to FIG. 1F, in some embodiments, the bottom surface of the ion implantation fence 113 is higher than the bottom surface of the first type semiconductor layer 110. With reference to FIG. 1G, in some embodiments, the bottom surface of the ion implantation fence 113 is lower than the bottom surface of the first type semiconductor layer 110.

[0030] In some embodiments, the mesa structure 111 includes a stair structure 111a, as shown in Figure 1H. In some embodiments, the mesa structure 111 can have one or more stair structures.

[0031] 3 is a structural diagram showing a side cross-sectional view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 3, the micro LED further includes a bottom isolation layer 140 filled in the trench 112. Preferably, the material of the bottom isolation layer 140 is SiO 2 , SiNx, Al 2 O 3 , AlN, HfO 2 , TiO 2 , or ZrO 2 is selected from one or more of:

[0032] In this embodiment, an integrated circuit (IC) backplane 190 is formed below the first type semiconductor layer 110 and is electrically connected to the first type semiconductor layer 110 through a connection structure 150. As shown in FIG. 3, the connection structure 150 is a connection pillar.

[0033] The micro LED further includes a bottom contact 160. The bottom contact 160 is formed on the bottom of the first type semiconductor layer 110. The top surface of the connection structure 150 is connected to the bottom contact 160, and the bottom surface of the connection structure 150 is connected to the IC backplane 190.

[0034] Referring to FIG. 3 , in some embodiments, the micro LED further includes a top contact 180 and a top conductive layer 170. The top contact 180 is formed on the second type semiconductor layer 120. The top conductive layer 170 is formed on the second type semiconductor layer 120 and the top contact 180. The conductivity type of the top contact 180 is the same as the conductivity type of the second type semiconductor layer 120. For example, in some embodiments, the conductivity type of the second type semiconductor layer 120 is N-type and the conductivity type of the top contact 180 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 120 is P-type and the conductivity type of the top contact 180 is P-type. The top contact 180 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 180 is used to form an ohmic contact between the top conductive layer 170 and the second type semiconductor layer 120 to optimize the electrical properties of the micro LED. The diameter of the top contact 180 is about 20-50 nm, and the thickness of the top contact 180 is about 10-20 nm. In some embodiments, a dielectric layer is formed between the top conductive layer 170 and the second type semiconductor layer 120, as described below with reference to FIG.

[0035] 4 is a structural diagram showing a cross-sectional side view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 4, the connection structure 150 is a metal bonding layer for bonding the micro LED with an IC backplane 190. Furthermore, the bottom contact 160 is a bottom contact layer in this variation.

[0036] Figure 5 shows a flowchart of a method 500 for fabricating a first exemplary micro LED, such as the micro LED shown in Figure 3, according to some embodiments of the present disclosure. The method 500 for fabricating a micro LED includes steps 501-510. Figures 6A-6J are structural diagrams showing cross-sectional side views of a micro LED fabrication process at each step (i.e., steps 501-510) corresponding to the method 500 shown in Figure 5, according to some embodiments of the present disclosure.

[0037] 5 and 6A-6J. In step 501, an epitaxial structure is provided. As shown in FIG. 6A, the epitaxial structure includes, from top to bottom, a first type semiconductor layer 610, a first type cap layer 614, a light emitting layer 630, a second type cap layer 624, and a second type semiconductor layer 620. The epitaxial structure is grown on a substrate 600. The substrate 600 can be GaN, GaAs, etc.

[0038] In step 502, referring to FIG. 6B, a first type semiconductor layer 610 is patterned to form mesa structures 611, trenches 613, and fences 613'.

[0039] 6B, first type semiconductor layer 610 is etched and the etching is stopped above first type cap layer 614 to avoid etching light emitting layer 630 during the patterning process. The bottom of trench 612 does not reach light emitting layer 630. First type semiconductor layer 610 is etched by a conventional dry etching method, such as a plasma etching method, as would be understood by one of ordinary skill in the art.

[0040] In step 503, referring to FIG. 6C, a bottom contact 660 is deposited on the mesa structure 611.

[0041] Before the bottom contact 660 is deposited, a first protective mask (not shown) is used to protect the area where the bottom contact 660 is not to be formed. Then, the material of the bottom contact 660 is deposited on the first protective mask and on the first type of semiconductor layer 610 by a conventional deposition method such as physical vapor deposition or chemical vapor deposition. After the deposition process, the first protective mask is removed from the first type of semiconductor layer 610, and the material on the first protective mask is also removed together with the first protective mask to form the bottom contact 660 on the mesa structure 611.

[0042] In step 504, and with reference to Figure 6D, an ion implantation process is performed within fence 613'. The arrows indicate the direction of the ion implantation process.

[0043] As shown in FIG. 6D, an ion implantation step implants ions into fence 613' (as shown in FIG. 6C) to form ion implant fence 613 (as shown in FIG. 6D). Prior to the ion implantation step, a second protective mask (not shown) is formed in the areas where ions are not to be implanted. Ions are then implanted into the exposed fence 613'. The second protective mask is then removed by conventional chemical etching methods, as will be understood by those skilled in the art. Preferably, the implantation energy is between 0 and 500 Kev, and the implantation dose is between 1E10 and 9E17.

[0044] In step 505, referring to Figure 6E, a bottom isolation layer 640 is deposited over the substrate 600. That is, the bottom isolation layer 640 is deposited on the first type semiconductor layer 610. The first type semiconductor layer 610 and the bottom contact 660 are covered by the bottom isolation layer 640, and the trench 612 is filled by the bottom isolation layer 640. The bottom isolation layer 640 is deposited by conventional chemical vapor deposition.

[0045] In step 506, referring to Figure 6F, the bottom isolation layer 640 is patterned to expose the bottom contact 660. The bottom isolation layer 640 is etched by photo-etching and dry-etching methods.

[0046] In step 507, and referring to Figure 6G, a metal material 650' is deposited over the substrate 600. That is, the metal material 650' is deposited on the bottom isolation layer 640 and the bottom contact 660. The metal material is deposited by conventional physical vapor deposition.

[0047] In step 508, referring to Figure 6H, the top of the metal material is polished down to the top of the bottom isolation layer 640 to form connection structures 650, such as connection pillars. In some embodiments, the metal material is polished by a chemical mechanical polishing (CMP) process.

[0048] In step 509, referring to FIG. 6I, the connection pillars 650 are bonded to the IC backplane 690. The epitaxial structure is first turned upside down. Then, a metal bonding process bonds the connection pillars 650 to the contact pads of the IC backplane 690. The substrate 600 is then removed by conventional separation methods such as laser stripping or chemical etching. The arrows indicate the direction of removal of the substrate 600.

[0049] In step 510, referring to FIG. 6J, a top contact 680 and a top conductive layer 670 may be sequentially deposited on the second type semiconductor layer 620 by conventional deposition techniques.

[0050] Some embodiments of the present disclosure further provide a micro LED array panel, which includes a plurality of micro LEDs as described above, as shown in Figures 1A-1F, 3 and 4. These micro LEDs may be arranged in an array within the micro LED array panel.

[0051] 7 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 1B according to some embodiments of the present disclosure. As shown in FIG. 7, the micro LED array panel includes a first type of semiconductor layer 710 formed continuously in the micro LED array panel, a first type of cap layer 714 formed continuously on the first type of semiconductor layer 710, a light emitting layer 730 formed continuously on the first type of cap layer 714, a second type of cap layer 724 formed continuously on the light emitting layer 730, and a second type of semiconductor layer 720 formed continuously on the second type of cap layer 724.

[0052] The conductivity type of the first type semiconductor layer 710 is different from the conductivity type of the second type semiconductor layer 720. For example, in some embodiments, the conductivity type of the first type semiconductor layer 710 is P-type and the conductivity type of the second type semiconductor layer 720 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 720 is P-type and the conductivity type of the first type semiconductor layer 710 is N-type. The thickness of the first type semiconductor layer 710 is greater than the thickness of the second type semiconductor layer 720. In some embodiments, the material of the first type semiconductor layer 710 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 720 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. The conductivity type of the first type cap layer 714 is the same as the conductivity type of the first type semiconductor layer 710, and the conductivity type of the second type cap layer 724 is the same as the conductivity type of the second type semiconductor layer 720.

[0053] The first type semiconductor layer 710 includes a plurality of mesa structures 711, a plurality of trenches 712, and a plurality of ion implantation fences 713 separated from the mesa structures 711 by the trenches 712. The top surface of the ion implantation fences 713 is not higher than the top surface of the first type semiconductor layer 710. Therefore, the ion implantation fences 713 cannot reach the light emitting layer 730. The top of the ion implantation fences 713 can be formed at any position. Furthermore, the bottom surface of the ion implantation fences 713 can be formed at any position. The relationship between the top surface of the ion implantation fences 713, the top surface of the first type semiconductor layer 710, and the top surface of the trenches 712 can be seen in the micro LED shown in Figures 1A to 1E, and will not be further described here. Furthermore, the relationship between the bottom surface of the ion implantation fences 713 and the bottom surface of the first type semiconductor layer 710 can be seen in the micro LED shown in Figures 1E to 1G, and will not be further described here. In another embodiment, the mesa structure can have one or more stair structures, as seen in the mesa structure shown in FIG. 1H.

[0054] 8 is a structural diagram illustrating a bottom view of the side-by-side micro LEDs of FIG. 7 according to some embodiments of the present disclosure. As shown in FIG. 8, ion implantation fences 713 are formed in trenches 712 between adjacent mesa structures 711. Furthermore, in each micro LED, ion implantation fences 713 are formed around trenches 712, which are formed around mesa structures 711. The electrical resistance of ion implantation fences 713 is higher than the electrical resistance of mesa structures 711. The trenches extend upward through first type semiconductor layer 710 to first type cap layer 714, such that first type cap layer 714 is visible through the trenches in the bottom view.

[0055] In some embodiments, the spacing between adjacent sidewalls of adjacent ones of the mesa structures 711 can be adjusted. For example, in some embodiments, the spacing between adjacent sidewalls of the mesa structures 711 is 50% or less of the diameter of the mesa structures 711. In some embodiments, the spacing between adjacent sidewalls of the mesa structures 711 is 30% or less of the diameter of the mesa structures 711. Preferably, the spacing between adjacent sidewalls of the mesa structures 711 is 600 nm or less. Furthermore, in some embodiments, the width of the ion implantation fence 713 can be adjusted. For example, the width of the ion implantation fence 713 can be 50% or less of the diameter of the mesa structures 711. In some embodiments, the width of the ion implantation fence 713 can be 10% or less of the diameter of the mesa structures 711. Preferably, in a micro LED array panel, the width of the ion implantation fence 713 is 200 nm or less.

[0056] 9 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 1B in a micro LED array panel according to some embodiments of the present disclosure. As shown in FIG. 9, the micro LED array panel further includes a bottom isolation layer 940 formed on the first type semiconductor layer 910 and filled in the trench 912. Preferably, in some embodiments, the material of the bottom isolation layer 940 is SiO 2 , SiNx, Al 2 O 3 , AlN, HfO 2 , TiO 2 , or ZrO 29. The first type semiconductor layer 910 includes a first insulating layer 920, a second insulating layer 930, a third insulating layer 940, a fourth insulating layer 950, and a fourth insulating layer 960. The first type semiconductor layer 910 includes a first insulating layer 920, a second insulating layer 940, and a fourth insulating layer 950. The first type semiconductor layer 910 includes a first insulating layer 930, a fourth insulating layer 940, and a fifth insulating layer 950. The first type semiconductor layer 910 includes a first insulating layer 940, a fourth insulating layer 950, and a fourth insulating layer 960. The first type semiconductor layer 910 includes a first insulating layer 940, a fourth insulating layer 950, and a fourth insulating layer 960. The first type semiconductor layer 910 includes a second insulating layer 950, a fourth insulating layer 960, and a fourth insulating layer 970. The first type semiconductor layer 910 includes a second insulating layer 970, a fourth insulating layer 980, and a fourth insulating layer 990. The first type semiconductor layer 910 includes a second insulating layer 990, a fourth insulating layer 9 ... first insulating layer 940, a fourth insulating layer 990, and a fourth insulating layer 990. The first type semiconductor layer 910 includes a second insulating layer 990, a fourth insulating layer 990, and a fourth insulating layer 990.

[0057] In this embodiment, the micro LED array panel further includes a top contact 980 and a top conductive layer 970. The top contact 980 is formed on the second type semiconductor layer 920. The top conductive layer 970 is formed on the second type semiconductor layer 920 and the top contact 980. The conductivity type of the top contact 980 is the same as the conductivity type of the second type semiconductor layer 920. For example, in some embodiments, the conductivity type of the second type semiconductor layer 920 is N-type and the conductivity type of the top contact 980 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 920 is P-type and the conductivity type of the top contact 980 is P-type. The top contact 980 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 980 is used to form an ohmic contact between the top conductive layer 970 and the second type semiconductor layer 920 to optimize the electrical properties of the micro LEDs. The diameter of the top contact 980 is about 20 to 50 nm, and the thickness of the top contact 980 is about 10 to 20 nm.

[0058] In some embodiments, a dielectric layer is formed between the top conductive layer and the second type of semiconductor layer (see FIG. 13).

[0059] The micro LED array panel can be manufactured by a method 500 shown in FIG. 5, which will not be described further.

[0060] EMBODIMENT 2 10A-10H are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. As shown in FIG. 10A, in some embodiments, the micro-LED includes a first type of semiconductor layer 1010, a first type of cap layer 1014, a light-emitting layer 1030, a second type of cap layer 1024, and a second type of semiconductor layer 1020. The conductivity type of the first type of semiconductor 1010 is different from the conductivity type of the second type of semiconductor layer 1020. For example, the conductivity type of the first type of semiconductor 1010 is P-type, and the conductivity type of the second type of semiconductor layer 1020 is N-type. The thickness of the first type of semiconductor layer 1010 is thicker than the thickness of the second type of semiconductor layer 1020. The material of the first type semiconductor layer 1010 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer 1020 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. The conductivity type of the first type cap layer 1014 is the same as the conductivity type of the first type semiconductor layer 1010, and the conductivity type of the second type cap layer 1024 is the same as the conductivity type of the second type semiconductor layer 1020.

[0061] The second type semiconductor layer 1020 includes a mesa structure 1021, a trench 1022, and an ion implantation fence 1023 separated from the mesa structure 1021. The bottom surface of the ion implantation fence 1023 is not lower than the bottom surface of the second type semiconductor layer 1020. Therefore, the ion implantation fence 1023 can reach the second type cap layer 1024 but cannot reach the light emitting layer 1030. The bottom surface of the ion implantation fence 1023 can be formed at any position. Furthermore, the ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021. The electrical resistance of the ion implantation fence 1023 is higher than the electrical resistance of the mesa structure 1021.

[0062] The ion implantation fence 1023 includes a light absorbing material that absorbs light from the mesa structure 1021. The conductivity type of the light absorbing material is the same as the conductivity type of the second semiconductor layer 1020. Preferably, the light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN. Furthermore, the ion implantation fence 1023 is formed by implanting ions into at least the second type semiconductor layer 1020. Preferably, the ions implanted into the second type semiconductor layer 1020 to form the ion implantation fence 1013 are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0063] Also, the width of the ion implantation fence 1023 can be adjusted. For example, in some embodiments, the width of the ion implantation fence 1023 is 50% or less of the diameter of the mesa structure 1021. In some embodiments, the width of the ion implantation fence 1023 is 10% or less of the diameter of the mesa structure 1021. Preferably, the width of the ion implantation fence 1023 is 200 nm or less. The diameter of the mesa structure 1021 is 2500 nm or less. The thickness of the second type semiconductor layer 1020 is 100 nm or less.

[0064] In some embodiments, the width of trench 1022 is less than or equal to 50% of the diameter of mesa structure 1021. In some embodiments, the width of trench 1022 is less than or equal to 10% of the diameter of mesa structure 1021. Preferably, the width of trench 1022 is less than or equal to 200 nm.

[0065] The depth of the trench 1022 is not limited. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and into the second type cap layer 1024. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and the second type cap layer 1024 to the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and the second type cap layer 1024 to the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020, the second type cap layer 1024, and the light emitting layer 1030. Further, in some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020, the second type cap layer 1024, and the light emitting layer 1030, and can extend down into the first type cap layer 1014. Further, in some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020, the second type cap layer 1024, the light emitting layer 1030, and the first type cap layer 1014, and can extend down into the first type semiconductor layer 1010.

[0066] In some embodiments, as shown in FIG. 10A, the trench 1022 extends down through the bottom surface of the second type semiconductor layer 1020 to the top surface of the second type cap layer 1024. The bottom surface of the trench 1022 is aligned with the bottom of the second type semiconductor layer 1020. Also, the bottom surface of the second ion implantation fence 1023 is aligned with the bottom surface of the second trench 1022. FIG. 11 is a structural diagram illustrating a top view of the second exemplary micro LED shown in FIG. 10A. FIG. 11 illustrates a top view of the second type semiconductor layer 1020 with the ion implantation fence 1023 separated from the mesa structure 1021 by the trench 1022. Here, the ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021. The trenches 1022 extend down through the bottom surface of the second type semiconductor layer 1020 to the top surface of the second type cap layer 1024 so that the second type cap layer 1024 is visible through the trenches 1022 in a top view.

[0067] In some embodiments, the bottom of the ion implantation fence 1023 is higher than the bottom of the trench 1022, as shown in FIG. 10B. In some embodiments, the trench 1022 does not extend down through the bottom of the second type semiconductor layer 1020, as shown in FIG. 10C. The bottom of the ion implantation fence 1023 is lower than the bottom of the trench 1022. In some embodiments, the bottom of the ion implantation fence 1023 is aligned with the bottom of the trench 1022, as shown in FIG. 10D. In some embodiments, the bottom of the ion implantation fence 1023 is higher than the bottom of the trench 1022, as shown in FIG. 10E.

[0068] Additionally, in some embodiments, the top surface of the ion implantation fence 1023 can be formed at any location. Preferably, the top surface of the ion implantation fence 1023 is aligned with the top surface of the second type semiconductor layer 1020. In some embodiments, the top surface of the ion implantation fence 1023 is higher than the top surface of the second type semiconductor layer 1020, as shown in FIG. 10F. In some embodiments, the top surface of the ion implantation fence 1023 is lower than the top surface of the second type semiconductor layer 1020, as shown in FIG. 10G.

[0069] In some embodiments, the mesa structure 1021 includes one stair structure 1021a, as shown in Figure 10H. In some embodiments, the mesa structure 1021 can have multiple stair structures.

[0070] 12A and 12B are structural diagrams illustrating side cross-sectional views of another variation of a second exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 12A, the micro LED further includes a bottom isolation layer 1040 formed under the first type semiconductor layer 1010. Preferably, the material of the bottom isolation layer 1040 is SiO 2 , SiNx, or Al 2 O 3 The first type semiconductor layer 1010 may include a first semiconductor layer 1010, a second semiconductor layer 1020, a third semiconductor layer 1020, a fourth semiconductor layer 1030, a fifth semiconductor layer 1040, a sixth semiconductor layer 1040, a sixth semiconductor layer 1050, a seventh semiconductor layer 1060, a eighth semiconductor layer 1070, a eighth semiconductor layer 1080, a eighth semiconductor layer 109 ...

[0071] Further, in some embodiments, the micro LED further includes a top contact 1080 and a top conductive layer 1070. The top contact 1080 is formed on the second type semiconductor layer 1020. The top conductive layer 1070 is formed on the top surface of the second type semiconductor layer 1020 and on the top surface of the top contact 1080, and is filled in the second trench 1022. The conductivity type of the top contact 1080 is the same as the conductivity type of the second type semiconductor layer 1020. For example, the conductivity type of the second type semiconductor layer 1020 is N-type, and the conductivity type of the top contact 1080 is N-type. The top contact 1080 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 1080 is used to form an ohmic contact between the top conductive layer 1070 and the second type semiconductor layer 1020 to optimize the electrical properties of the micro LED. The diameter of the top contact 1080 is about 20 to 50 nm, and the thickness of the top contact 1080 is about 10 to 20 nm.

[0072] 12B, the connection structure 1050 can be a metal bonding layer for bonding the micro-LEDs with an IC backplane 1090. Furthermore, in this embodiment, the bottom contact 1060 is a bottom contact layer.

[0073] 13 is a structural diagram showing a side cross-sectional view of another variation of a second exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 13, the micro LED further includes a dielectric layer 1071 formed on the surface of the second type semiconductor layer 1020, on the bottom surface of the top conductive layer 1070, and filling the trench 1023. The dielectric layer 1071 includes an opening for exposing the top contact 1080. Thus, the top conductive layer 1070 can be connected with the top contact 1080 through the opening. Preferably, the material of the dielectric layer 1071 is SiO 2 , SiNx, Al 2 O 3 , AlN, HfO 2 , TiO 2 , or ZrO 2 is selected from one or more of:

[0074] Figure 14 shows a flowchart of a method 1400 for fabricating a second exemplary micro LED, such as the micro LED shown in Figure 12B, according to some embodiments of the present disclosure. As shown in Figure 14, the micro LED fabrication method includes steps 1401-1406. Figures 15A-15F are structural diagrams showing cross-sectional side views of the micro LED fabrication process at each step (i.e., steps 1401-1406) of the method 1400 shown in Figure 14, according to some embodiments of the present disclosure.

[0075] 14 and 15A-15F. In step 1401, an epitaxial structure is provided. As shown in FIG. 15A, the epitaxial structure includes, from top to bottom, a first type semiconductor layer 1510, a first type cap layer 1514, a light emitting layer 1530, a second type cap layer 1524, and a second type semiconductor layer 1520. The epitaxial structure is grown on a substrate 1500. The substrate 1500 can be GaN, GaAs, etc.

[0076] Preferably, before turning the epitaxial structure upside down, a bottom contact layer 1560 used as a bottom contact is deposited on the top surface of the first type semiconductor layer 1510. Then, a metal bonding layer used as a connection structure 1550 is first deposited on the top surface of the bottom contact layer 1560.

[0077] In step 1402, referring to Fig. 15B, the epitaxial structure is bonded to an IC backplane 1590. The epitaxial structure is first turned upside down. Then, a metal bonding process is used to bond the connection structures 1550 to the contact pads of the IC backplane 1590. Finally, the substrate 1500 is removed by conventional separation methods such as laser stripping or chemical etching. The arrows indicate the direction of removal of the substrate 1500.

[0078] In step 1403, referring to FIG. 15C, second type semiconductor layer 1520 is patterned to form mesa structures 1521, trenches 1522, and fences 1523'. Second type semiconductor layer 1520 is etched, stopping above light emitting layer 1530 to avoid etching light emitting layer 1530 during the patterning process. Second type semiconductor layer 1520 in FIG. 15B is etched down to light emitting layer 1530 to form trenches 1522. Second type semiconductor layer 1520 is etched by conventional dry etching methods, such as plasma etching methods, as would be understood by one of ordinary skill in the art.

[0079] In step 1404, referring to FIG. 15D, a top contact 1580 is deposited on the mesa structure 1521. Before the top contact 1580 is deposited, a first protective mask (not shown) is used to protect the area where the top contact 1580 is not to be formed. Then, the material of the top contact 1580 is deposited on the first protective mask and on the second type of semiconductor layer 1520 by a conventional deposition method such as physical vapor deposition or chemical vapor deposition. After the deposition step, the first protective mask is removed from the second type of semiconductor layer 1520, and the material on the first protective mask is also removed together with the first protective mask to form the top contact 1580 on the mesa structure 1521.

[0080] In step 1405, referring to FIG. 15E, an ion implantation process is performed in the fence 1523'. Referring also to FIG. 15D, the ion implantation process implants ions into the fence 1523' (as shown in FIG. 15D) to form the ion-implanted fence 1523 (as shown in FIG. 15E). The arrows indicate the direction of the ion implantation process. Prior to the ion implantation process, a second protective mask (not shown) is formed in the areas where ions are not to be implanted. Ions are then implanted into the exposed fence 1523' (as shown in FIG. 15D). The second protective mask is then removed by conventional chemical etching methods, as will be understood by those skilled in the art. Preferably, the implantation energy is between 0 and 500 KeV, and the implantation dose is between 1E10 and 9E17.

[0081] 15F, a top conductive layer 1570 is deposited on top of the second type semiconductor layer 1520 and on the top contact 1580, and filling the trench 1522. The top conductive layer 1570 is deposited by conventional physical vapor deposition.

[0082] 13, a dielectric layer 1071 can be formed in trench 1022 prior to depositing top conductive layer 1070. As can be appreciated by those skilled in the art, microlenses can be further formed on the top conductive layer.

[0083] Some embodiments of the present disclosure further provide a micro LED array panel, which includes a plurality of micro LEDs as described above, as shown in Figures 10A-10H, 12A, 12B and 13. These micro LEDs may be arranged in an array within the micro LED array panel.

[0084] 16 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 10B in a micro LED array panel according to some embodiments of the present disclosure. As shown in FIG. 16, the micro LED array panel includes a first type semiconductor layer 1610 formed continuously in the micro LED array panel, a first type cap layer 1614 formed continuously on the first type semiconductor layer 1610, a light emitting layer 1630 formed continuously on the first type cap layer 1614, a second type cap layer 1624 formed continuously on the light emitting layer 1630, and a second type semiconductor layer 1620 formed continuously on the second type cap layer 1624.

[0085] The second type semiconductor layer 1620 includes a plurality of mesa structures 1621, a plurality of trenches 1622, and a plurality of ion implantation fences 1623 separated from the mesa structures 1621 by the trenches 1622. The bottom surfaces of the ion implantation fences 1623 are not lower than the bottom surface of the second type semiconductor layer 1620.

[0086] FIG. 17 is a structural diagram illustrating a top view of the side-by-side micro LEDs of FIG. 16 according to some embodiments of the present disclosure. FIG. 17 illustrates a top view of a second type semiconductor layer 1620 with an ion implantation fence 1623 formed in a trench 1622 between adjacent mesa structures 1621. The electrical resistance of the ion implantation fence 1623 is higher than the electrical resistance of the mesa structures 1621. The ion implantation fence 1623 is formed around the trench 1622, and the trench 1622 is formed around the mesa structures 1621.

[0087] The variations in the relationship between the bottom surface of the ion implantation fence 1623, the bottom surface of the second type semiconductor layer 1620, and the bottom of the trench 1622 generally correspond to those shown for the micro LEDs of Figures 10A-10E and will not be described further herein. Furthermore, in some embodiments, the variations in the relationship between the top surface of the ion implantation fence 1623 and the top surface of the second type semiconductor layer 1620 generally correspond to those shown for the micro LEDs of Figures 10E-10G and will not be described further herein. In some embodiments, the mesa structure can have one or more staircase structures, as shown in Figure 10H.

[0088] In some embodiments, the spacing between adjacent sidewalls of adjacent ones of the mesa structures 1621 can be adjusted. For example, in some embodiments, the spacing between adjacent sidewalls of the mesa structures 1621 is 50% or less of the diameter of the mesa structures 1621. In some embodiments, the spacing between adjacent sidewalls of the mesa structures 1621 is 30% or less of the diameter of the mesa structures 1621. Preferably, the spacing between adjacent sidewalls of the mesa structures 1621 is 600 nm or less. Furthermore, in some embodiments, the width of the ion implantation fence 1623 can be adjusted. For example, in some embodiments, the width of the ion implantation fence 1623 can be 50% or less of the diameter of the mesa structures 1621. In some embodiments, the width of the ion implantation fence 1623 can be 10% or less of the diameter of the mesa structures 1621. Preferably, in a micro LED array panel, the width of the ion implantation fence 1623 is 200 nm or less.

[0089] 18A-18C are structural diagrams illustrating side cross-sectional views of second exemplary adjacent micro LEDs in a micro LED array panel according to some embodiments of the present disclosure. As shown in FIG. 18A and FIG. 18C, the micro LED array panel further includes a top contact 1880 and a top conductive layer 1870. Further details of the top contact 1880 and the top conductive layer 1870 can be understood with reference to also the micro LEDs illustrated in FIG. 10A-10H, FIG. 12A and FIG. 12B, and FIG. 13, which will not be described further herein.

[0090] 18A and 18C, an IC backplane 1890 is formed below the first type semiconductor layer 1810 and electrically connected to the first type semiconductor layer 1810 via a connection structure 1850. The micro LED array panel further includes a bottom contact 1860 formed at a bottom of the first type semiconductor layer 1810. The connection structure 1850 may be a metal bonding layer for bonding the micro LEDs with the IC backplane 1890. Furthermore, in some embodiments, the bottom contact 1860 is a bottom contact layer. Further details of the IC backplane 1890, the bottom contact 1860, and the connection structure 1850 may be understood by also referring to FIG. 13, which will not be further described here.

[0091] As shown in Figure 18A, the bottom surface of the trench is aligned with the top surface of the second type cap layer 1824. That is, the bottom surface of the trench is in contact with the second type cap layer 1824. As shown in Figures 18B and 18C, the bottom surface of the trench is higher than the top surface of the second type cap layer 1824. That is, the bottom surface of the trench is not in contact with the second type cap layer 1824.

[0092] Further details regarding the characteristics of the micro LEDs and ion implanted fences in the micro LED array panel can also be understood by reference to the micro LEDs as shown in Figures 10A-10H, which will not be described further herein.

[0093] The micro LED array panel shown in Figures 18A-18C can be manufactured by the manufacturing method of the micro LEDs 1400 shown in Figure 14, which will not be further described here.

[0094] EMBODIMENT 3 19 is a structural diagram illustrating a cross-sectional side view of a variation of a third exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 19, the micro LED includes at least a first type of semiconductor layer 1910, a first type of cap layer 1914, a light emitting layer 1930, a second type of cap layer 1924, and a second type of semiconductor layer 1920. The conductivity type of the first type of semiconductor layer 1910 is different from the conductivity type of the second type of semiconductor layer 1920. For example, in some embodiments, the conductivity type of the first type of semiconductor layer 1910 is P-type and the conductivity type of the second type of semiconductor layer 1920 is N-type. In some embodiments, the conductivity type of the second type of semiconductor layer 1920 is P-type and the conductivity type of the first type of semiconductor layer 1910 is N-type. The thickness of the first type of semiconductor layer 1910 is greater than the thickness of the second type of semiconductor layer 1920. In some embodiments, the thickness of the first type semiconductor layer 1910 can be less than the thickness of the second type semiconductor layer 1920. In some embodiments, the material of the first type semiconductor layer 1910 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer 1920 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0095] The first-type cap layer 1914 has the same conductivity type as the first-type semiconductor layer 1910 , and the second-type cap layer 1924 has the same conductivity type as the second-type semiconductor layer 1920 .

[0096] The first type semiconductor layer 1910 includes a first mesa structure 1911, a first trench 1912, and a first ion implantation fence 1913 separated from the first mesa structure 1911. The second type semiconductor layer 1920 includes a second mesa structure 1921, a second trench 1922, and a second ion implantation fence 1923 separated from the second mesa structure 1921.

[0097] In some embodiments, the center of the first mesa structure 1911 is aligned with the center of the second mesa structure 1921, the center of the first trench 1912 is aligned with the center of the second trench 1922, and the center of the first ion implantation fence 1913 is aligned with the center of the second ion implantation fence 1923.

[0098] The relationship between the top surface of the first ion implantation fence 1913, the top surface of the first trench 1912, and the top surface of the first type semiconductor layer 1910 is the same as that of the micro LED of the first embodiment shown in Figures 1A-1D, which will not be further described here. The relationship between the bottom of the first ion implantation fence 1913, the bottom of the first trench 1912, and the bottom of the first type semiconductor layer 1910 is the same as that of the micro LED of the first embodiment shown in Figures 1D-1G, which will not be further described here. Furthermore, in some embodiments, the first mesa structure 1911 can have one or more staircase structures, as shown in Figure 1H.

[0099] The relationship between the bottom of the second ion implantation fence 1923, the bottom of the second trench 1922, and the bottom of the second type semiconductor layer 1920 is the same as that of the micro LED of the second embodiment shown in Figures 10A-10E, and will not be further described here. The relationship between the top surface of the second ion implantation fence 1923, the top surface of the second trench 1922, and the top surface of the second type semiconductor layer 1920 is the same as that of the micro LED of the second embodiment shown in Figures 10E-10G, and will not be further described here. Furthermore, in some embodiments, the second mesa structure 1921 can have one or more staircase structures, as shown in Figure 10H.

[0100] 20 is a structural diagram showing a side cross-sectional view of another variation of the third exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 20, the micro LED further includes a bottom isolation layer 2040 filled in the first trench 2012. Preferably, the material of the bottom isolation layer 2040 is SiO 2, SiNx, Al 2 O 3 , AlN, HfO 2 , TiO 2 , or ZrO 2 The bottom isolation layer 2040, the IC backplane 2090, the connection structure 2050, and the bottom contact 2060 are one or more of the following: The IC backplane 2090 is formed under the first type semiconductor layer 2010 and is electrically connected to the first type semiconductor layer 2010 through the connection structure 2050. In this specification, the connection structure 2050 is a connection pillar. The micro LED further includes a bottom contact 2060 formed at the bottom of the first type semiconductor layer 2010. Further details of the bottom isolation layer 2040, the IC backplane 2090, the connection structure 2050, and the bottom contact 2060 can be known by referring to the description of the first embodiment, which will not be further described here.

[0101] The micro LED further includes a top contact 2080 and a top conductive layer 2070. The top contact 2080 is formed on the second type semiconductor layer 2020. The top conductive layer 2070 is formed on top of the second type semiconductor layer 2020 and the top contact 2080, filling the second trench 2022. Further details regarding the top contact 2080 and the top conductive layer 2070 can be known by reference to the description of embodiment 2, which will not be further described here. In some embodiments, a dielectric layer 1071 as shown in FIG. 13 can be formed on the surface of the second type semiconductor layer 2020, which can be known by reference to the description of FIG. 13, which will not be further described here.

[0102] Further details regarding the micro LED shown in FIG. 20, including the first ion-implanted fence 2013 and the second ion-implanted fence 2023, can be found by reference to the descriptions of embodiments 1 and 2, and will not be described further here.

[0103] 21 shows a flowchart of a third exemplary method 2100 for manufacturing a micro LED according to some embodiments of the present disclosure. The method 2100 includes at least step I and step II.

[0104] In step I, a first type of semiconductor layer is patterned, and then ions are implanted into the first type of semiconductor layer to form a first ion implantation fence.

[0105] In step II, after the second type of semiconductor layer is patterned, ions are implanted into the second type of semiconductor layer to form a second ion implantation fence.

[0106] Referring to FIG. 21, process I includes at least steps 2101-2109, and process II includes at least steps 2110-2113.

[0107] For process I, steps 2101-2109 are similar to steps 501-509 of method 500 shown in FIG. 5. The cross-sectional side views of the micro LEDs fabricated according to steps 2101-2109 are similar to those shown in FIG. 6A-6I. Please refer to FIG. 21 and FIG. 6A-6I. In step 2101, referring to FIG. 6A, an epitaxial structure is provided. As shown in FIG. 6A, the epitaxial structure includes, from top to bottom, a first type semiconductor layer 610, a first type cap layer 614, a light emitting layer 630, a second type cap layer 624 and a second type semiconductor layer 620.

[0108] In step 2102, referring to FIG. 6B, a first type semiconductor layer 610 is patterned to form mesa structures 611, trenches 612, and fences 613'.

[0109] In step 2103, referring to FIG. 6C, a bottom contact 660 is deposited on the mesa structure 611.

[0110] In step 2104, with reference to FIG. 6D, an ion implantation process is performed within fence 613'.

[0111] In step 2105, referring to FIG. 6E, a bottom isolation layer 640 is deposited over the substrate 600.

[0112] In step 2106, with reference to FIG. 6F, the bottom isolation layer 640 is patterned to expose the bottom contact 660.

[0113] In step 2107, referring to FIG. 6G, a metal material 650' is deposited over the substrate 600.

[0114] In step 2108, referring to FIG. 6H, the top of the metal material 650' is polished down to the top of the bottom isolation layer 640 to form the connecting pillars 650.

[0115] In step 2109, referring to FIG. 6I, the connection pillars 650 are bonded with the IC backplane 690 and the substructure 600 is removed.

[0116] 22A-22D are structural diagrams illustrating cross-sectional side views of a micro LED manufacturing process in steps 2110-2113 of the method 2100 shown in FIG. 21, according to some embodiments of the present disclosure. With reference to FIG. 21 and FIG. 22A-22D, in step 2110, with reference to FIG. 22A, a second type semiconductor layer 2220 is patterned to form mesa structures 2221, trenches 2222, and fences 2223′.

[0117] In step 2111, referring to FIG. 22B, a top contact 2280 is deposited on the mesa structure 2221.

[0118] In step 2112, with reference to Figure 22C, an ion implantation process is performed within fence 2223'. The arrows indicate the direction of the ion implantation process.

[0119] In step 2113, referring to FIG. 22D, a top conductive layer 2270 is deposited over the top of the second type semiconductor layer 2220 and the top contact 2280 and in the trenches 2222.

[0120] Further details of step I can be known by referring to the description of steps 501 to 509 in embodiment 1. Further details of step II can be known by referring to the description of steps 1403 to 1406 in embodiment 2, which will not be further described here.

[0121] Some embodiments of the present disclosure further provide a micro LED array panel, which includes a plurality of micro LEDs as described above, as shown in Figures 19 and 20. These micro LEDs may be arranged in an array within the micro LED array panel.

[0122] 23 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 19 in a micro LED array panel according to some embodiments of the present disclosure. As shown in FIG. 23, the micro LED array panel includes at least a first type semiconductor layer 2310 formed continuously in the micro LED array panel, a first type cap layer 2314 formed continuously on the first type semiconductor layer 2310, a light emitting layer 2330 formed continuously on the first type cap layer 2314, a second type cap layer 2324 formed continuously on the light emitting layer 2330, and a second type semiconductor layer 2320 formed continuously on the second type cap layer 2324.

[0123] The first type semiconductor layer 2310 includes a plurality of first mesa structures 2311, a plurality of first trenches 2312, and a plurality of first ion implantation fences 2313 separated from the first mesa structures via the first trenches 2312. The top surface of the first ion implantation fences 2313 is lower than the top surface of the first type semiconductor layer 2310. Referring back to FIG. 8, the bottom view of the micro LED array panel without IC backplane is similar to the bottom view shown in FIG. 8. The first ion implantation fences 2313 are formed around the first trenches 2312 and between adjacent first type mesa structures. The electrical resistance of the first ion implantation fences 2313 is higher than the electrical resistance of the first mesa structures. Furthermore, the first ion implantation fences 2313 are formed around the first trenches 2312, and the first trenches 2312 are formed around the first mesa structures.

[0124] The second type semiconductor layer 2320 includes a plurality of second mesa structures 2321, a plurality of second trenches 2322, and a plurality of second ion implantation fences 2323 separated from the second mesa structures 2321 via the second trenches 2322. The bottom surface of the second ion implantation fences 2323 is higher than the bottom surface of the second type semiconductor layer 2320. The top view of the micro LED array panel is similar to the top view shown in FIG. 17 in that the second ion implantation fences 2323 are formed around the second trenches 2322 and between adjacent second mesa structures 2321. The electrical resistance of the second ion implantation fences 2323 is higher than the electrical resistance of the second mesa structures 2321. A second ion implantation fence 2323 is formed around the second trench 2322 , which is formed around the second mesa structure 2321 .

[0125] In some embodiments, the spacing between adjacent sidewalls of the first mesa structure 2311 can be adjusted. For example, in some embodiments, the spacing between adjacent sidewalls of the first mesa structure 2311 is 50% or less of the diameter of the first mesa structure 2311. In some embodiments, the spacing between adjacent sidewalls of the first mesa structure 2311 is 30% or less of the diameter of the first mesa structure 2311. Preferably, the spacing between adjacent sidewalls of the first mesa structure 2311 is 600 nm or less. Furthermore, in some embodiments, the width of the first ion implantation fence 2313 can be adjusted. For example, in some embodiments, the width of the first ion implantation fence 2313 is 50% or less of the diameter of the first mesa structure 2311. In some embodiments, the width of the first ion implantation fence 2313 is 10% or less of the diameter of the first mesa structure 2311. Preferably, in some embodiments, in a micro LED array panel, the width of the first ion implantation fence 2313 is 200 nm or less. The spacing between adjacent sidewalls of the second mesa structure 2321 is 50% or less of the diameter of the second mesa structure 2321. In some embodiments, the spacing between adjacent sidewalls of the second mesa structure 2321 is 30% or less of the diameter of the second mesa structure 2321. Preferably, the spacing between adjacent sidewalls of the second mesa structure 2321 is 600 nm or less. Furthermore, the width of the second ion implantation fence 2323 is 50% or less of the diameter of the second mesa structure 2321. In some embodiments, the width of the second ion implantation fence 2423 is 10% or less of the diameter of the second mesa structure 2421. Preferably, in a micro LED array panel, the width of the second ion implantation fence 2323 is 200 nm or less.

[0126] 24 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 20 in a micro LED array panel according to some embodiments of the present disclosure. As shown in FIG. 24, the micro LED array panel further includes a bottom isolation layer 2440 filled in the first trench 2412. Preferably, the material of the bottom isolation layer 2440 is SiO 2 , SiNx, Al 2 O3 , AlN, HfO 2 , TiO 2 , or ZrO 2 24. In addition, the IC backplane 2490 is formed under the first type semiconductor layer 2410 and electrically connected with the first type semiconductor layer 2410 through the connection structure 2450. The micro LED array panel further includes a bottom contact 2460 formed at the bottom of the first type semiconductor layer 2410. The top surface of the connection structure 2450 is connected with the bottom contact 2460, and the bottom of the connection structure 2450 is connected with the IC backplane 2490. The bottom contact 2460 is a protruding contact. In some embodiments, referring to FIG. 4, the connection structure 2450 can be a metal bonding layer for bonding the micro LEDs with the IC backplane 2490. Furthermore, in some embodiments, the bottom contact 2460 is a bottom contact layer. In some embodiments, a dielectric layer 1071 as shown in FIG. 13 can be formed on the surface of the second type semiconductor layer 2420, which can be understood by referring to the description of FIG. 13 and will not be further described here.

[0127] Referring back to FIG. 24 , the micro LED array panel further includes a top contact 2480 and a top conductive layer 2470. The top contact 2480 is formed on the second type semiconductor layer 2420. The top conductive layer 2470 is formed on the top of the second type semiconductor layer 2420 and the top contact 2480, filling the second trench 2422. The conductivity type of the top contact 2480 is the same as the conductivity type of the second type semiconductor layer 2420. For example, the conductivity type of the second type semiconductor layer 2420 is N-type, and the conductivity type of the top contact 2480 is N-type. The top contact 2480 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 2480 is used to form an ohmic contact between the top conductive layer 2470 and the second type semiconductor layer 2420 to optimize the electrical properties of the micro LED. The diameter of the top contact 2480 is about 20-50 nm, and the thickness of the top contact 2480 is about 10-20 nm.

[0128] Further detailed characteristics of the micro LEDs in the micro LED array panel can be known by reference to the micro LEDs above, which will not be described further here.

[0129] The manufacturing method of the micro LED array panel at least includes: manufacturing the micro LEDs. The details of the manufacturing of the micro LEDs can be known by referring to the description of steps 501-509 in embodiment 1 and the description of steps 1403-1406 in embodiment 2, which will not be further described here.

[0130] In the first to third embodiments, a microlens may further be formed on or above the top surface of the second type semiconductor layer, such as on the top surface of the upper conductive layer, as can be understood by those skilled in the art.

[0131] The micro LEDs herein have a very small volume. The micro LEDs may be organic or inorganic LEDs. The micro LEDs may be applied to a micro LED array panel. The light emitting area of ​​the micro LED array panel is very small, for example 1 mm x 1 mm, 3 mm x 5 mm. In some embodiments, the light emitting area is the area of ​​the micro LED array in the micro LED array panel. The micro LED array panel includes one or more micro LED arrays forming a pixel array in which the micro LEDs are pixels, such as a 1600 x 1200, 680 x 480, or 1920 x 1080 pixel array. The diameter of the micro LEDs is in the range of about 200 nm to 2 μm. An IC backplane is formed on the back of the micro LED array and electrically connected to the micro LED array. The IC backplane receives signals such as image data from the outside via signal lines and controls whether or not the corresponding micro LEDs are made to emit light.

[0132] It should be noted that, as used herein, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another and do not require or imply an actual relationship or order between those entities or operations. Additionally, the words "comprising," "having," "containing," and "including," as well as other similar forms, are intended to have equivalent meanings and be open-ended, in that the item or items following any one of these words are not intended to be an exhaustive listing of such item or items, nor are they intended to be limited to only the item or items listed.

[0133] As used herein, unless otherwise stated, the term "or" includes all possible combinations unless impracticable. For example, if it is stated that a database can include A or B, the database can include A, or B, or A and B, unless otherwise stated or impracticable. As a second example, if it is stated that a database can include A, B, or C, the database can include A, or B, or C, or A and B, or A and B and C, unless otherwise stated or impracticable.

[0134] In the foregoing specification, the embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. Certain adaptations and modifications may be made to the described embodiments. Other embodiments may be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims. It is also intended that the order of steps depicted in the figures is for illustrative purposes only, and is not intended to be limited to the particular order of steps. Thus, one skilled in the art can appreciate that these steps may be performed in different orders while performing the same method.

[0135] In the drawings and specification, illustrative embodiments have been disclosed. However, many variations and modifications to these embodiments may be made. Thus, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A micro LED, a first type semiconductor layer; a first type cap layer formed on the first type semiconductor layer; a light-emitting layer formed on the first type of cap layer; Equipped with 1. A micro LED, comprising: a first type of semiconductor layer comprising a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the ion implantation fence being formed around the trench, the trench being formed around the mesa structure, and an electrical resistance of the ion implantation fence being higher than an electrical resistance of the mesa structure.

2. 10. The micro-LED of claim 1 , wherein a top surface of the ion implanted fence is no higher than a top surface of the first type semiconductor layer.

3. 10. The micro-LED of claim 1, wherein a bottom surface of the ion implanted fence is aligned with or elevated above a bottom surface of the first type semiconductor layer.

4. 10. The micro LED of claim 1 , wherein the trench extends upward through a top surface of the first type semiconductor layer to a bottom surface of the first type cap layer.

5. 5. The micro-LED of claim 4, wherein a top surface of the ion implanted fence is no higher than a top surface of the trench.

6. 10. The micro LED of claim 1 , wherein the trench does not extend upwardly through a top surface of the first type semiconductor layer.

7. 7. The micro-LED of claim 6, wherein a top surface of the ion implanted fence is not lower than a top surface of the trench.

8. The micro-LED of claim 6 , wherein a top surface of the ion implanted fence is lower than a top surface of the trench.

9. a second type of capping layer formed on the light-emitting layer; a second type semiconductor layer formed on the second type cap layer, The conductivity type of the second type semiconductor layer is different from the conductivity type of the first type semiconductor layer.

2. The micro LED of claim 1 .

10. the mesa structure, the trench, and the ion implantation fence are a first mesa structure, a first trench, and a first ion implantation fence, respectively; the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure; a bottom surface of the second ion implantation fence is not lower than a bottom surface of the second type semiconductor layer; the second ion implantation fence is formed around the second trench, the second trench is formed around the second mesa structure, and an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure; 10. The micro LED of claim 9.

11. 11. The micro LED of claim 10, wherein the second trench extends through the bottom surface of the second type semiconductor layer down to a top surface of the second type cap layer.

12. 12. The micro-LED of claim 11 , wherein the bottom surface of the second ion implanted fence is elevated above or aligned with a bottom surface of the second trench.

13. 11. The micro-LED of claim 10, wherein the second trench does not extend downward through the bottom surface of the second type semiconductor layer.

14. 14. The micro-LED of claim 13, wherein the bottom surface of the second ion implanted fence is lower than or aligned with a bottom surface of the second trench.

15. 14. The micro-LED of claim 13, wherein the bottom surface of the second ion-implanted fence is higher than a bottom surface of the second trench.

16. 11. The micro LED of claim 10, wherein a top surface of the second ion implanted fence is aligned with or is lower than a top surface of the second type semiconductor layer, or the top surface of the second ion implanted fence is higher than the top surface of the second type semiconductor layer.

17. 11. The micro-LED of claim 10, wherein the first mesa structure comprises one or more stair structures and the second mesa structure comprises one or more stair structures.

18. 11. The micro LED of claim 10, wherein a width of the first trench is less than or equal to 50% of a diameter of the first mesa structure and a width of the second trench is less than or equal to 50% of a diameter of the second mesa structure.

19. 20. The micro LED of claim 18, wherein the width of the first trench is less than or equal to 200 nm and the width of the second trench is less than or equal to 200 nm.

20. 11. The microLED of claim 10, wherein the first ion-implanted fence comprises a first light absorbing material and the second ion-implanted fence comprises a second light absorbing material, the conductivity type of the first light absorbing material being the same as the conductivity type of the first type of semiconductor and the conductivity type of the second light absorbing material being the same as the conductivity type of the second type of semiconductor, and the first light absorbing material and the second light absorbing material being selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, AlGaN.

21. 10. The micro-LED of claim 9, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

22. 10. The micro-LED of claim 1 further comprising a bottom isolation layer filled in said trench.

23. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 23. The micro-LED of claim 22, wherein the micro-LED is selected from one or more of:

24. 10. The micro LED of claim 9, further comprising a top contact and a top conductive layer, said top contact and said top conductive layer formed on a top surface of said second type semiconductor layer.

25. 11. The micro LED of claim 10, further comprising a top conductive layer and a top contact, said top contact formed on a top surface of said second mesa structure, and said top conductive layer formed on a top surface and sidewalls of said second mesa structure, on a top surface and sidewalls of said second ion implanted fence, and filling said second trench.

26. 11. The micro LED of claim 10, wherein ions implanted in the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F, and ions implanted in the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

27. 11. The micro LED of claim 10, wherein the first ion implantation fence is formed by implanting ions into at least the first type of semiconductor layer and the second ion implantation fence is formed by implanting ions into at least the second type of semiconductor layer.

28. 11. The micro LED of claim 10, wherein a width of the first ion implanted fence is less than or equal to 50% of a diameter of the first mesa structure and a width of the second ion implanted fence is less than or equal to 50% of a diameter of the second mesa structure.

29. the width of the first ion implantation fence is less than or equal to 200 nm, the diameter of the first mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 100 nm; the width of the second ion implantation fence is less than or equal to 200 nm, the diameter of the second mesa structure is less than or equal to 2500 nm, and the thickness of the second type semiconductor layer is less than or equal to 100 nm; 29. The micro LED of claim 28.

30. 10. The micro LED of claim 9, wherein the material of the first type semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and the material of the second type semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.

31. 10. The micro-LED of claim 1, further comprising an integrated circuit (IC) backplane underlying said first type semiconductor layer and a connection structure electrically connecting said IC backplane with said first type semiconductor layer.

32. 32. The micro LED of claim 31 , wherein the connection structure is a connection pillar or a metal bonding layer.

33. 32. The micro-LED of claim 31, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

34. 34. A micro LED array panel comprising a plurality of micro LEDs according to any one of claims 1 to 33.

35. 1. A micro LED array panel, comprising: a first type of semiconductor layer formed within the micro LED array panel; a first type cap layer formed on the first type semiconductor layer; a light-emitting layer formed on the first type of capping layer; a second type of capping layer formed on the light-emitting layer; a second type semiconductor layer formed on the second type cap layer; Equipped with the first type is P-type and the second type is N-type; the first type semiconductor layer comprises a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches, a top surface of the ion implantation fences being lower than or aligned with a top surface of the first type semiconductor layer; the ion implantation fence is formed between adjacent mesa structures around the trench, the electrical resistance of the ion implantation fence being higher than the electrical resistance of the mesa structures; Micro LED array panel.

36. 36. The micro LED array panel of claim 35, wherein the ion implantation fence is formed around the periphery of the trench, and the trench is formed around the periphery of the mesa structure.

37. 36. The micro LED array panel of claim 35, wherein a bottom surface of the ion implanted fence is aligned with or elevated above a bottom surface of the first type semiconductor layer.

38. 36. The micro LED array panel of claim 35, wherein a spacing between adjacent sidewalls of the mesa structure is less than or equal to 50% of a diameter of the mesa structure.

39. 40. The micro LED array panel of claim 38, wherein the spacing between adjacent sidewalls of the mesa structures is less than or equal to 600 nm.

40. 36. The micro LED array panel of claim 35, wherein the ion implanted fence absorbs light from the mesa structure, the ion implanted fence comprising a light absorbing material selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

41. 36. The micro LED array panel of claim 35, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

42. 36. The micro LED array panel of claim 35, further comprising a bottom isolation layer filled in the trenches.

43. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 43. The micro LED array panel of claim 42, wherein the micro LED array panel is selected from one or more of:

44. 36. The micro LED array panel of claim 35, wherein ions implanted in the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

45. 36. The micro LED array panel of claim 35, wherein the ion implanted fence is formed by implanting ions into at least the first type semiconductor layer.

46. 36. The micro LED array panel of claim 35, wherein a width of the ion implanted fence is less than or equal to 50% of a diameter of the mesa structure.

47. 47. The micro LED array panel of claim 46, wherein the width of the ion implanted fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 300 nm.

48. 36. The micro LED array panel of claim 35, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

49. 36. The micro LED array panel of claim 35, further comprising a top contact formed on a top surface of the second type semiconductor layer.

50. 36. The micro LED array panel of claim 35, further comprising an integrated circuit (IC) backplane formed below said first type semiconductor layer, and connection structures electrically connecting said IC backplane with said first type semiconductor layer.

51. 51. The micro LED array panel of claim 50, wherein the connection structures are connection pillars or metal bonding layers.

52. 51. The micro LED array panel of claim 50, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

53. 36. The micro LED array panel of claim 35, wherein the trenches extend upward through a top surface of the first type semiconductor layer to a bottom surface of the first type cap layer.

54. 36. The micro LED array panel of claim 35, wherein a top surface of the ion implanted fence is lower than or aligned with a top surface of the trench.

55. 36. The micro LED array panel of claim 35, wherein the trenches do not extend upwardly through a top surface of the first type semiconductor layer.

56. 56. The micro LED array panel of claim 55, wherein the top surface of the ion implanted fence is elevated above or aligned with a top surface of the trench.

57. 56. The micro LED array panel of claim 55, wherein the top surface of the ion implanted fence is lower than a top surface of the trench.

58. A method for manufacturing a micro LED, comprising: providing an epitaxial structure comprising, in top-to-bottom order, a first type of semiconductor layer, a first type of capping layer, a light emitting layer, a second type of capping layer, and a second type of semiconductor layer; patterning the first type semiconductor layer to form mesa structures, trenches, and fences; depositing a bottom contact on the mesa structure; performing an ion implantation process within the fence to form an ion implanted fence; A method comprising:

59. after patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence; depositing a bottom isolation layer over the first type semiconductor layer and the bottom contact; patterning the bottom isolation layer to expose the bottom contact; depositing a metallic material over the bottom isolation layer and the bottom contact; polishing the metal material to a top surface of the bottom isolation layer to form a connection structure; inverting the epitaxial structure and bonding the connection structure to an integrated circuit (IC) backplane; 60. The method of claim 58, further comprising:

60. When depositing a metal material on the bottom isolation layer and the bottom contact, the material of the bottom isolation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 60. The method of claim 59, wherein the method is selected from one or more of:

61. 60. The method of claim 59, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.

62. Inverting the epitaxial structure and bonding the connection structure to the IC backplane includes: Removing the substrate.

62. The method of claim 61, further comprising:

63. After the epitaxial structure is turned upside down and the connection structure is bonded to the IC backplane, forming a top contact and a top conductive layer on the top surface of the second type semiconductor layer; 62. The method of claim 61, further comprising:

64. depositing the bottom contact on the mesa structure; forming a protective mask to protect areas where the bottom contact will not be deposited; depositing the bottom contact material over the protective mask and over the first type semiconductor layer; removing the protective mask from the first type semiconductor layer and removing the material above the protective mask to form the bottom contact on the mesa structure; 60. The method of claim 58, further comprising:

65. performing an ion implantation process in the fence to form the ion implanted fence; forming a protective mask over areas not to be implanted while leaving the fence exposed; implanting ions into the fence; removing said protective mask; 60. The method of claim 58, further comprising:

66. 66. The method of claim 65, wherein said ion implantation step in said fence to form said ion implanted fence is performed with an energy of between 0 and 500 Kev.

67. 66. The method of claim 65, wherein a dose of between 1E10 and 9E17 is implanted when performing the ion implantation step in the fence to form the ion implanted fence.

68. 66. The method of claim 65, wherein the ion implantation step is performed in the fence to form an ion-implanted fence by implanting ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F into the ion-implanted fence.

69. 66. The method of claim 65, wherein when performing the ion implantation step in the fence to form the ion implanted fence, the width of the ion implanted fence is less than or equal to 50% of a diameter of the mesa structure.

70. 66. The method of claim 65, wherein when performing the ion implantation step in the fence to form the ion implanted fence, the width of the ion implanted fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 300 nm.

71. 60. The method of claim 58, wherein when patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is less than or equal to 50% of a diameter of the mesa structure.

72. 59. The method of claim 58, wherein a conductivity type of the first type semiconductor layer is P-type and a conductivity type of the second type semiconductor layer is N-type, a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

73. 60. The method of claim 58, wherein the ion implanted fence comprises a light absorbing material.

74. 74. The method of claim 73, wherein the light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

75. A micro LED, a first type semiconductor layer; a first type cap layer formed on the first type semiconductor layer; a light-emitting layer formed on the first type of capping layer; a second type of capping layer formed on the light-emitting layer; a second type semiconductor layer formed on the second type cap layer; Equipped with The first type is P-type and the second type is N-type; the second type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the bottom surface of the ion implantation fence being not lower than the bottom surface of the second type semiconductor layer; the ion implantation fence is formed around the trench, the trench is formed around the mesa structure, and an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure; Micro LED.

76. 76. The microLED of claim 75, wherein a top surface of the ion implanted fence is aligned with or is lower than a top surface of the second type semiconductor layer, or the top surface of the ion implanted fence is higher than a top surface of the second type semiconductor layer.

77. 76. The micro LED of claim 75, wherein the trench extends through the bottom surface of the second type semiconductor layer down to a top surface of the second type cap layer.

78. 78. The micro LED of claim 77, wherein the bottom surface of the ion implanted fence is elevated above or aligned with a bottom surface of the trench.

79. 76. The micro LED of claim 75, wherein the trench does not extend downward through the bottom surface of the second type semiconductor layer.

80. 80. The micro LED of claim 79, wherein the bottom surface of the ion implanted fence is lower than or aligned with a bottom surface of the trench.

81. 80. The micro LED of claim 79, wherein the bottom surface of the ion implanted fence is elevated above a bottom surface of the trench.

82. 76. The micro LED of claim 75, wherein the mesa structure comprises one or more stair structures.

83. 76. The micro LED of claim 75, wherein the width of the trench is no more than 50% of a diameter of the mesa structure.

84. 84. The microLED of claim 83, wherein the trench has a width of 200 nm or less.

85. 76. The microLED of claim 75, wherein the ion implanted fence comprises a light absorbing material, the light absorbing material being selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

86. 76. The micro LED of claim 75, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

87. 76. The micro LED of claim 75, further comprising a dielectric layer filled within the trench.

88. The material of the dielectric layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 88. The micro-LED of claim 87, wherein the micro-LED is selected from one or more of:

89. 76. The micro LED of claim 75, further comprising a top conductive layer formed on a top and sidewalls of said mesa structure, on a top and sidewalls of said ion implanted fence, and filled within said trench.

90. 76. The micro LED of claim 75, wherein ions implanted in the ion implanted fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

91. 76. The micro LED of claim 75, wherein the ion implanted fence is formed by implanting ions into at least the second type semiconductor layer.

92. 76. The micro LED of claim 75, wherein a width of the ion implanted fence is less than or equal to 50% of a diameter of the mesa structure.

93. 76. The microLED of claim 75, wherein the width of the ion implanted fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the second type semiconductor layer is less than or equal to 300 nm.

94. 76. The microLED of claim 75, wherein the material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

95. 76. The micro LED of claim 75 further comprising a top contact formed on a top surface of the second type semiconductor layer.

96. 76. The micro LED of claim 75, further comprising an integrated circuit (IC) backplane formed beneath said first type semiconductor layer, and connection structures electrically connecting said IC backplane with said first type semiconductor layer.

97. 97. The micro LED of claim 96, wherein the connection structure is a connection pillar or a metal bonding layer.

98. 97. The micro-LED of claim 96, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

99. 1. A micro LED array panel, comprising: a first type of semiconductor layer formed within the micro LED array panel; a first type cap layer formed on the first type semiconductor layer; a light-emitting layer formed on the first type of capping layer; a second type of capping layer formed on the light-emitting layer; a second type semiconductor layer formed on the second type cap layer; the first type is P-type and the second type is N-type; the second type semiconductor layer comprises a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches, the bottom surfaces of the ion implantation fences being higher than or aligned with a bottom surface of the second type semiconductor layer; the ion implantation fences are formed around the trenches and between adjacent mesa structures, the electrical resistance of the ion implantation fences being higher than the electrical resistance of the mesa structures; Micro LED array panel.

100. 100. The micro LED array panel of claim 99, wherein the ion implantation fence is formed around the periphery of the trench, and the trench is formed around the periphery of the mesa structure.

101. 100. The micro LED array panel of claim 99, wherein a top surface of the ion implanted fence is aligned with or lower than a top surface of the second type semiconductor layer.

102. 100. The micro LED array panel of claim 99, wherein a spacing between adjacent sidewalls of the mesa structure is less than or equal to 50% of a diameter of the mesa structure.

103. 103. The micro LED array panel of claim 102, wherein the spacing between adjacent sidewalls of the mesa structures is less than or equal to 600 nm.

104. 100. The micro LED array panel of claim 99, wherein the ion implanted fence absorbs light from the mesa structure, the ion implanted fence comprising a light absorbing material selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

105. 100. The micro LED array panel of claim 99, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

106. 100. The micro LED array panel of claim 99, further comprising a dielectric layer filled in the trenches.

107. The material of the dielectric layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 107. The micro LED array panel of claim 106, wherein the micro LED array panel is selected from one or more of:

108. 100. The micro LED array panel of claim 99, further comprising a top conductive layer formed on a top and sidewalls of said mesa structure, on a top and sidewalls of said ion implanted fence and filling said trenches.

109. 100. The micro LED array panel of claim 99, wherein the ions implanted in the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

110. 100. The micro LED array panel of claim 99, wherein the ion implanted fence is formed by implanting ions into at least the second type semiconductor layer.

111. 100. The micro LED array panel of claim 99, wherein a width of the ion implanted fence is less than or equal to 50% of a diameter of the mesa structure.

112. 112. The micro LED array panel of claim 111, wherein the width of the ion implanted fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and a thickness of the second type semiconductor layer is less than or equal to 100 nm.

113. 100. The micro LED array panel of claim 99, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

114. 100. The micro LED array panel of claim 99, further comprising a top contact formed on a top surface of the second type semiconductor layer.

115. 100. The micro LED array panel of claim 99, further comprising an integrated circuit (IC) backplane formed below said first type semiconductor layer, and connection structures electrically connecting said IC backplane with said first type semiconductor layer.

116. 116. The micro LED array panel of claim 115, wherein the connection structures are connection pillars or metal bonding layers.

117. 116. The micro LED array panel of claim 115, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

118. 100. The micro LED array panel of claim 99, wherein the trenches extend through the bottom surface of the second type semiconductor layer down to a top surface of the second type cap layer.

119. 119. The micro LED array panel of claim 118, wherein the bottom surface of the ion implanted fence is higher than or aligned with the bottom surface of the trench.

120. 100. The micro LED array panel of claim 99, wherein the trenches do not extend downward through the bottom surface of the second type semiconductor layer.

121. 121. The micro LED array panel of claim 120, wherein the bottom surface of the ion implanted fence is lower than or aligned with a bottom surface of the trench.

122. 100. The micro LED array panel of claim 99, wherein the bottom surface of the ion implanted fence is higher than a bottom surface of the trench.

123. A method for manufacturing a micro LED, comprising: providing an epitaxial structure comprising, in top-to-bottom order, a first type of semiconductor layer, a first type of capping layer, a light emitting layer, a second type of capping layer, and a second type of semiconductor layer; bonding the epitaxial structure to an integrated circuit (IC) backplane; patterning the second type semiconductor layer to form mesa structures, trenches, and fences; depositing a top contact on the mesa structure; performing an ion implantation process within the fence; depositing a top conductive layer on the top surface of the second type semiconductor layer, on the top contact, and in the trench; A method comprising:

124. Providing the epitaxial structure includes: depositing a bottom contact layer on a top surface of the first type semiconductor layer; depositing a metal bonding layer on an upper surface of the bottom contact layer; 124. The method of claim 123, further comprising:

125. Bonding the epitaxial structure to the IC backplane comprises: turning the epitaxial structure upside down; bonding said metal bonding layer to a contact pad of said IC backplane; 125. The method of claim 124, further comprising:

126. 126. The method of claim 125, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.

127. Bonding the epitaxial structure to the IC backplane comprises: Removing the substrate.

127. The method of claim 126, further comprising:

128. patterning the second type semiconductor layer to form the mesa structure, the trench, and the fence includes: Etching the second type semiconductor layer down to a surface of the light emitting layer.

124. The method of claim 123, further comprising:

129. depositing the top contact on the mesa structure; forming a protective mask; depositing the top contact material over the protective mask; removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask to form the top contact on the mesa structure; 124. The method of claim 123, further comprising:

130. performing the ion implantation step within the fence, forming a protective mask over areas not to be implanted while leaving the fence exposed; implanting ions into the fence; removing said protective mask; 124. The method of claim 123, further comprising:

131. 131. The method of claim 130, wherein the step of implanting ions into the fence is performed with an energy of between 0 and 500 KeV.

132. 131. The method of claim 130, wherein a dose of between 1E10 and 9E17 is implanted when performing the ion implantation step in the fence.

133. 131. The method of claim 130, wherein the ion implantation step in the fence comprises implanting the ion implantation fence with ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

134. 131. The method of claim 130, wherein a width of the ion implantation fence is less than or equal to 50% of a diameter of the mesa structure when performing the ion implantation step within the fence.

135. 131. The method of claim 130, wherein when performing the ion implantation step within the fence, the width of the ion implantation fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the second type semiconductor layer is less than or equal to 100 nm.

136. 124. The method of claim 123, wherein a conductivity type of the first type semiconductor layer is P-type and a conductivity type of the second type semiconductor layer is N-type, a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

137. 137. The method of claim 136, wherein the ion implanted fence comprises a light absorbing material.

138. 138. The method of claim 137, wherein the light absorbing material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

139. A micro LED, a first type semiconductor layer; a first type cap layer formed on the first type semiconductor layer; a light-emitting layer formed on the first type of capping layer; a second type of capping layer formed on the light-emitting layer; a second type semiconductor layer formed on the second type cap layer; Equipped with the first type is P-type and the second type is N-type; the first type semiconductor layer comprises a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure, the top surface of the first ion implantation fence being lower than or aligned with the top surface of the first type semiconductor layer; the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure, the bottom surface of the second ion implantation fence being higher than or aligned with the bottom surface of the second type semiconductor layer; the first ion implantation fence is formed around the first trench, the first trench is formed around the first mesa structure, and an electrical resistance of the first ion implantation fence is higher than an electrical resistance of the first mesa structure; the second ion implantation fence is formed around the second trench, the second trench is formed around the second mesa structure, and an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure.

140. 140. The micro LED of claim 139, wherein a center of the first mesa structure is aligned with a center of the second mesa structure, a center of the first trench is aligned with a center of the second trench, and a center of the first ion implantation fence is aligned with a center of the second ion implantation fence.

141. a bottom surface of the first ion implantation fence is aligned with or above a bottom surface of the first type semiconductor layer, and a top surface of the second ion implantation fence is aligned with or below a top surface of the second type semiconductor layer; or 140. The micro LED of claim 139, wherein the bottom surface of the first ion implanted fence is lower than the bottom surface of the first type semiconductor layer and the top surface of the second ion implanted fence is higher than the top surface of the second type semiconductor layer.

142. 140. The micro LED of claim 139, wherein the first trench extends upward through the top surface of the first type semiconductor layer to a bottom surface of the first type cap layer, and / or the second trench extends downward through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.

143. 143. The micro LED of claim 142, wherein the top surface of the first ion implanted fence is lower than or aligned with a top surface of the first trench and / or the bottom surface of the second ion implanted fence is higher than or aligned with a bottom surface of the second trench.

144. 140. The micro LED of claim 139, wherein the first trench does not extend upward through the top surface of the first type semiconductor layer to a bottom surface of the first type cap layer, and / or the second trench does not extend downward through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.

145. 145. The micro LED of claim 144, wherein the top surface of the first ion implanted fence is higher than or aligned with a top surface of the first trench, and / or the bottom surface of the second ion implanted fence is lower than or aligned with a bottom surface of the second trench.

146. 145. The micro LED of claim 144, wherein the top surface of the first ion implanted fence is lower than a top surface of the first trench and / or the bottom surface of the second ion implanted fence is higher than a bottom surface of the second trench.

147. 140. The micro LED of claim 139, wherein the first mesa structure comprises one or more stair structures and / or the second mesa structure comprises one or more stair structures.

148. 140. The micro LED of claim 139, wherein a width of the first trench is less than or equal to 50% of a diameter of the first mesa structure and / or a width of the second trench is less than or equal to 50% of a diameter of the second mesa structure.

149. 149. The micro LED of claim 148, wherein the width of the first trench is less than or equal to 200 nm and / or the width of the second trench is less than or equal to 200 nm.

150. the first ion implanted fence comprises a first light absorbing material and / or the second ion implanted fence comprises a second light absorbing material; 140. The microLED of claim 139, wherein the first light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and / or the second light absorbing material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

151. 140. The micro LED of claim 139, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

152. 140. The micro LED of claim 139, further comprising a bottom isolation layer filled in the trench and a dielectric layer filled in the second trench.

153. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ and / or the material of the dielectric layer is selected from one or more of SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 153. The micro-LED of claim 152, wherein the micro-LED is selected from one or more of:

154. 140. The micro LED of claim 139, further comprising an upper conductive layer formed on a top surface and sidewalls of the second mesa structure, on a top surface and sidewalls of the second ion implanted fence, and filled within the second trench.

155. 140. The micro LED of claim 139, wherein ions implanted in the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F, and / or ions implanted in the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

156. 140. The micro LED of claim 139, wherein the first ion implanted fence is formed by implanting ions into at least the first type of semiconductor layer and / or the second ion implanted fence is formed by implanting ions into at least the second type of semiconductor layer.

157. 140. The micro LED of claim 139, wherein a width of the first ion implanted fence is less than or equal to 50% of a diameter of the first mesa structure and / or a width of the second ion implanted fence is less than or equal to 50% of a diameter of the second mesa structure.

158. the width of the first ion implantation fence is 200 nm or less, the diameter of the first mesa structure is 2500 nm or less, and the thickness of the first type of semiconductor layer is 300 nm or less; and / or the width of the second ion implantation fence is less than or equal to 200 nm, the diameter of the second mesa structure is less than or equal to 2500 nm, and the thickness of the second type semiconductor layer is less than or equal to 300 nm; 158. The micro LED of claim 157.

159. 140. The microLED of claim 139, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and / or a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

160. 140. The micro LED of claim 139, further comprising a top contact formed on a top surface of the second type semiconductor layer.

161. 140. The micro LED of claim 139, further comprising an integrated circuit (IC) backplane formed beneath said first type semiconductor layer, and connection structures electrically connecting said IC backplane with said first type semiconductor layer.

162. 162. The micro LED of claim 161 , wherein the connection structure is a connection pillar or a metal bonding layer.

163. 162. The micro LED of claim 161, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

164. 1. A micro LED array panel, comprising: a first type of semiconductor layer formed within the micro LED array panel; a first type cap layer formed on the first type semiconductor layer; a light-emitting layer formed on the first type of capping layer; a second type of capping layer formed on the light-emitting layer; a second type semiconductor layer formed on the second type cap layer; Equipped with the first type is P-type and the second type is N-type; the first type semiconductor layer comprises a plurality of first mesa structures, a plurality of first trenches, and a plurality of first ion implantation fences separated from the first mesa structures by the first trenches, a top surface of the first ion implantation fences being lower than or aligned with a top surface of the first type semiconductor layer; the first ion implantation fence is formed around the first trench and between adjacent first type mesa structures, the first ion implantation fence having a higher electrical resistance than the first mesa structure; the second type semiconductor layer comprises a plurality of second mesa structures, a plurality of second trenches, and a plurality of second ion implantation fences separated from the second mesa structures by the second trenches, the bottom surfaces of the second ion implantation fences being higher than or aligned with a bottom surface of the second type semiconductor layer; the second ion implantation fence is formed around the second trench and between adjacent second mesa structures, and an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structures; Micro LED array panel.

165. 165. The micro LED array panel of claim 164, wherein a center of the first mesa structure is aligned with a center of the second mesa structure, a center of the first trench is aligned with a center of the second trench, and a center of the first ion implantation fence is aligned with a center of the second ion implantation fence.

166. 165. The micro LED array panel of claim 164, wherein the first ion implantation fence is formed around the first mesa structure, the first trench is formed around the first mesa structure, the second ion implantation fence is formed around the second mesa structure, and the second trench is formed around the second mesa structure.

167. a bottom surface of the first ion implantation fence is aligned with or elevated above a bottom surface of the first type semiconductor layer; and / or a top surface of the second ion implantation fence is aligned with or below a top surface of the second type semiconductor layer; 165. The micro LED array panel of claim 164.

168. 165. The micro LED array panel of claim 164, wherein a spacing between adjacent sidewalls of the first mesa structure is less than or equal to 50% of a diameter of the first mesa structure and / or a spacing between adjacent sidewalls of the second mesa structure is less than or equal to 50% of a diameter of the second mesa structure.

169. 169. The micro LED array panel of claim 168, wherein the spacing between adjacent sidewalls of the first mesa structure is less than or equal to 600 nm and the spacing between adjacent sidewalls of the second mesa structure is less than or equal to 600 nm.

170. 165. The micro LED array panel of claim 164, wherein the first ion implanted fence absorbs light from the first mesa structure and the second ion implanted fence absorbs light from the second mesa structure.

171. 165. The micro LED array panel of claim 164, wherein a thickness of the first type of semiconductor layer is greater than a thickness of the second type of semiconductor layer.

172. 165. The micro LED array panel of claim 164, further comprising a bottom isolation layer filled in the first trenches and a dielectric layer filled in the second trenches.

173. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ and the material of the dielectric layer is selected from one or more of SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 173. The micro LED array panel of claim 172, wherein the micro LED array panel is selected from one or more of:

174. 165. The micro LED array panel of claim 164, further comprising a top conductive layer formed on a top surface and sidewalls of said second mesa structure, on a top surface and sidewalls of said second ion implanted fence, and filled within said second trench.

175. 165. The micro LED array panel of claim 164, wherein ions implanted in the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F, and / or ions implanted in the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

176. 165. The micro LED array panel of claim 164, wherein the first ion implanted fence is formed by implanting ions into at least the first type semiconductor layer.

177. 165. The micro LED array panel of claim 164, wherein a width of the first ion implanted fence is less than or equal to 50% of a diameter of the first mesa structure and a width of the second ion implanted fence is less than or equal to 50% of a diameter of the second mesa structure.

178. the width of the first ion implantation fence is less than or equal to 200 nm, the diameter of the first mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 300 nm; 179. The micro LED array panel of claim 178, wherein the width of the second ion implanted fence is less than or equal to 200 nm, the diameter of the second mesa structure is less than or equal to 2500 nm, and a thickness of the second type semiconductor layer is less than or equal to 100 nm.

179. 165. The micro LED array panel of claim 164, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and / or a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

180. 165. The micro LED array panel of claim 164, further comprising a top contact formed on a top surface of the second type semiconductor layer.

181. 165. The micro LED array panel of claim 164, further comprising an integrated circuit (IC) backplane formed beneath said first type semiconductor layer, and connection structures electrically connecting said IC backplane with said first type semiconductor layer.

182. 182. The micro LED array panel of claim 181, wherein the connection structure is a connection pillar or a metal bonding layer.

183. 182. The micro LED array panel of claim 181, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

184. 165. The micro LED array panel of claim 164, wherein the first trenches extend upward through the top surface of the first type semiconductor layer to a bottom surface of the first type cap layer, and / or the second trenches extend downward through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.

185. 185. The micro LED array panel of claim 184, wherein the top surface of the first ion implanted fence is lower than or aligned with a top surface of the first trench and / or the bottom surface of the second ion implanted fence is higher than or aligned with a bottom surface of the second trench.

186. 165. The micro LED array panel of claim 164, wherein the first trenches do not extend upward through the top surface of the first type semiconductor layer to a bottom surface of the first type cap layer, and / or the second trenches do not extend downward through the bottom surface of the second type semiconductor layer to a top surface of the second type cap layer.

187. 187. The micro LED array panel of claim 186, wherein the top surface of the first ion implanted fence is higher than or aligned with a top surface of the first trench and / or the bottom surface of the second ion implanted fence is lower than or aligned with a bottom surface of the second trench.

188. 187. The micro LED array panel of claim 186, wherein the top surface of the first ion implanted fence is lower than a top surface of the first trench and / or the bottom surface of the second ion implanted fence is higher than a bottom surface of the second trench.

189. A method for manufacturing a micro LED, comprising: Step I includes patterning a first type of semiconductor layer and implanting first ions into the first type of semiconductor layer; Step II includes patterning a second type of semiconductor layer and implanting second ions into the second type of semiconductor layer. A method comprising:

190. The step I comprises: providing an epitaxial structure comprising, in top-to-bottom order, a first type of semiconductor layer, a first type of capping layer, a light emitting layer, a second type of capping layer, and a second type of semiconductor layer; patterning the first type semiconductor layer to form mesa structures, trenches, and fences; depositing a bottom contact on the mesa structure; performing an ion implantation process within the fence to form an ion implanted fence; depositing a bottom isolation layer over the first type semiconductor layer and the bottom contact; patterning the bottom isolation layer to expose the bottom contact; depositing a metallic material over the bottom isolation layer and the bottom contact; polishing the metal material to a top surface of the bottom isolation layer to form a connection structure; inverting the epitaxial structure and bonding the connection structure to an integrated circuit (IC) backplane; 190. The method of claim 189, further comprising:

191. depositing the bottom contact on the mesa structure; forming a protective mask to protect areas where the bottom contact will not be deposited; depositing the bottom contact material over the protective mask and over the first type semiconductor layer; removing the protective mask from the first type semiconductor layer and removing the material above the protective mask to form the bottom contact on the mesa structure; 190. The method of claim 189, further comprising:

192. performing the ion implantation process within the fence to form the ion implanted fence; forming a protective mask over areas not to be implanted while leaving the fence exposed; implanting ions into the fence; removing said protective mask; 191. The method of claim 190, further comprising:

193. 200. The method of claim 192, wherein the ion implantation step in the fence to form the ion implanted fence is performed with an energy of 0 to 500 Kev and a dose of 1E10 to 9E17.

194. 200. The method of claim 192, wherein when the ion implantation step is performed in the fence to form the ion-implanted fence, ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F are implanted in the fence.

195. 200. The method of claim 192, wherein when performing the ion implantation step in the fence to form the ion implantation fence, a width of the ion implantation fence is 50% or less of a diameter of the mesa structure, the width of the ion implantation fence is 200 nm or less, the diameter of the mesa structure is 2500 nm or less, and a thickness of the first type semiconductor layer is 300 nm or less.

196. 202. The method of claim 190, wherein when patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is no more than 50% of a diameter of the mesa structure.

197. the mesa structure, the trench, and the fence are a first mesa structure, a first trench, and a first fence, respectively; The step II comprises: patterning the second type semiconductor layer to form a second mesa structure, a second trench, and a second fence; depositing a top contact on the second mesa structure; performing an ion implantation process within the second fence; depositing a top conductive layer on a top surface of the second type semiconductor layer, on the top contact, and in the second trench; 190. The method of claim 189, further comprising:

198. Depositing the top contact on the second mesa structure comprises: forming a protective mask; depositing the top contact material over the protective mask; removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask to form a top contact on the second mesa structure; 200. The method of claim 197, further comprising:

199. Performing the ion implantation step within the second fence includes: forming a protective mask over areas not to be implanted while leaving the second fence exposed; implanting the ions into the second fence; removing said protective mask; 200. The method of claim 197, further comprising:

200. 200. The method of claim 197, wherein the ion implantation step in the second fence is performed with an energy of 0 to 500 KeV and a dose of 1E10 to 9E17.

201. 200. The method of claim 197, wherein when performing the ion implantation step in the second fence, ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F are implanted into the second fence.

202. 200. The method of claim 197, wherein when performing the ion implantation step within the second fence, a width of the second ion implantation fence is less than or equal to 50% of a diameter of the second mesa structure, the width of the second ion implantation fence is less than or equal to 200 nm, the diameter of the second mesa structure is less than or equal to 2500 nm, and a thickness of the second type semiconductor layer is less than or equal to 100 nm.

203. providing the epitaxial structure, the epitaxial structure being grown on a substrate, and inverting the epitaxial structure to bond the connection structure to the IC backplane; Removing the substrate. Further comprising: The method of claim 190.

204. When depositing the bottom isolation layer on the first type semiconductor layer and the bottom contact, the material of the bottom isolation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 191. The method of claim 190, wherein the method is selected from one or more of:

205. 191. The method of claim 190, wherein the ion implanted fence comprises a light absorbing material.

206. 206. The method of claim 205, wherein the conductivity type of the light absorbing material is the same as the conductivity type of the first type semiconductor layer, and the light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

207. 200. The method of claim 190, wherein the conductivity type of the first type semiconductor layer is P-type and the conductivity type of the second type semiconductor layer is N-type, the material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

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