MEMORY CHECKPIN PROCESSING METHOD, MEMORY CHECKPIN PROCESSING APPARATUS, COMPUTER DEVICE, AND COMPUTER PROGRAM

Abstract

The present application relates to a method, device, equipment, storage medium, and computer program product for processing check pins of a memory. The method is applicable to the application scenarios of cloud technology and in-vehicle terminals, and includes the steps of: receiving a first data signal and a sampling pulse signal returned from each check pin of a target memory based on a first data read command; obtaining a first delay parameter by time-shifting each first data signal by a delay circuit so that the target level value of each first data signal after time-shifting is aligned with the sampling pulse signal; receiving a second data signal returned from each check pin of the target memory, obtaining a second delay parameter by time-shifting each target data signal in each second data signal by a delay circuit so that the target level value of each second data signal after time-shifting is aligned; and determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter. This method can ensure the accuracy of sampling the data signal based on the sampling pulse signal.

Description

[Technical field]

[0001] This application claims priority from a Chinese patent application filed with the China Patent Office on May 9, 2022, bearing application number 202210497004X and entitled "Memory check pin processing method, device, equipment, and storage medium," the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of computer technology, and in particular to a memory checkpin processing method, device, apparatus, storage medium, and computer program product. [Background technology]

[0003] High Bandwidth Memory (HBM) is a new type of internal memory with high speed and bandwidth, which is mainly applied in the field of artificial intelligence chips. The transmission path of the read data signal of HBM is easily affected by chip process, operating voltage, environmental temperature, and crosstalk between signals, which results in errors in the transmitted read data signal. Therefore, it is necessary to detect whether there is a transmission error in the read data signal.

[0004] In the conventional detection method, a read data signal is mainly transmitted together with a parity check (PAR) signal of the read data signal and a sampling pulse signal of the read data signal, whereby the receiving side samples the parity check signal based on the sampling pulse signal to obtain check information, and further checks whether there is a transmission error in the read data signal based on the check information.

[0005] However, the parity check signal may also be affected by the chip process, operating voltage, environmental temperature, and crosstalk between signals, which may cause a misalignment between the parity check signal and the sampling pulse signal. When the receiving side samples the parity check signal based on the sampling pulse signal, a sampling error may occur, resulting in incorrect check information being obtained, and the check result of the data signal may also become erroneous. Summary of the Invention [Problem to be solved by the invention]

[0006] According to various embodiments of the present application, a memory checkpin processing method, apparatus, device, storage medium, and computer program product are provided. [Means for solving the problem]

[0007] According to a first aspect, the present application provides a method for memory checkpinning performed by a computing device, the method comprising: sending a first data read command to a target memory; receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; obtaining a first delay parameter by time-shifting each of the first data signals by a delay circuit such that a target level value of each of the first data signals after time-shifting is aligned with the sampling pulse signal; When receiving the second data signal returned from each of the check pins of the target memory, the delay circuit time-shifts the target data signal in each of the second data signals so that the target level values ​​in each of the second data signals after time shifting are aligned, thereby obtaining a second delay parameter; determining a sampling delay parameter for the check pin based on the first delay parameter and the second delay parameter.

[0008] According to a second aspect, the present application further provides an apparatus for processing a check pin of a memory, the apparatus comprising: a command sending module for sending a first data read command to the target memory; a signal receiving module for receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; a signal time shifting module for obtaining a first delay parameter by time-shifting each of the first data signals by a delay circuit so that the target level value of each of the first data signals after time shifting is aligned with the sampling pulse signal; and, upon receiving a second data signal returned from each of the check pins of the target memory, for obtaining a second delay parameter by time-shifting a target data signal in each of the second data signals by the delay circuit so that the target level value of each of the second data signals after time shifting is aligned; and a delay determination module that determines a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0009] According to a third aspect, the present application further provides a computer device, the computer device comprising a memory and a processor, the memory storing a computer program, the processor executing the computer program to: sending a first data read command to a target memory; receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; obtaining a first delay parameter by time-shifting each of the first data signals by a delay circuit such that a target level value of each of the first data signals after time-shifting is aligned with the sampling pulse signal; When receiving the second data signal returned from each of the check pins of the target memory, the delay circuit time-shifts the target data signal in each of the second data signals so that the target level values ​​in each of the second data signals after time shifting are aligned, thereby obtaining a second delay parameter; determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0010] According to a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored therein, the computer program being capable of, when executed by a processor, sending a first data read command to a target memory; receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; obtaining a first delay parameter by time-shifting each of the first data signals by a delay circuit such that a target level value of each of the first data signals after time-shifting is aligned with the sampling pulse signal; When receiving the second data signal returned from each of the check pins of the target memory, the delay circuit time-shifts the target data signal in each of the second data signals so that the target level values ​​in each of the second data signals after time shifting are aligned, thereby obtaining a second delay parameter; determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0011] According to a fifth aspect, the present application further provides a computer program product, the computer program product including a computer program that, when executed by a processor, sending a first data read command to a target memory; receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; obtaining a first delay parameter by time-shifting each of the first data signals by a delay circuit such that a target level value of each of the first data signals after time-shifting is aligned with the sampling pulse signal; When receiving the second data signal returned from each of the check pins of the target memory, the delay circuit time-shifts the target data signal in each of the second data signals so that the target level values ​​in each of the second data signals after time shifting are aligned, thereby obtaining a second delay parameter; determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0012] The details of one or more embodiments of the application are set forth in the drawings and description below. Other features and advantages of the application will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0013] The drawings described herein are intended to provide further understanding of the present application and constitute a part of the present application. The schematic examples and the description thereof are intended to serve the purpose of interpreting the present application and are not to be construed as unduly limiting the present application. [Figure 1] FIG. 1 is a diagram illustrating an application environment of a memory check pin processing method according to an embodiment. [Diagram 2] FIG. 13 is a schematic diagram of a read command in one embodiment. [Diagram 3] FIG. 4 is a schematic diagram of read data in one embodiment. [Figure 4] FIG. 11 is a schematic diagram of read data in another embodiment. [Diagram 5] FIG. 11 is a schematic diagram of read data in another embodiment. [Figure 6] FIG. 11 is a schematic diagram of read data in another embodiment. [Figure 7] 5 is a schematic diagram of a data signal and a sampling pulse signal in one embodiment. FIG. [Figure 8] FIG. 1 is a schematic diagram of the flow of a memory check pin processing method in one embodiment. [Figure 9] FIG. 13 is a schematic diagram of the function of mode register bit MR7 in one embodiment. [Figure 10] FIG. 2 is a schematic diagram of a MISR circuit according to one embodiment. [Figure 11] FIG. 13 is a schematic diagram of the function of mode register bit MR0 in one embodiment. [Figure 12] FIG. 4 is a schematic diagram of a structure of read data in one embodiment. [Figure 13] FIG. 2 is a schematic diagram of a delay circuit according to an embodiment. [Figure 14] FIG. 13 is a schematic diagram of a delay circuit according to another embodiment. [Figure 15] FIG. 2 is a schematic diagram of the time shift effect of a data signal in one embodiment. [Figure 16] FIG. 13 is a schematic diagram of the time shift effect of a data signal in another embodiment. [Figure 17] FIG. 1 is an architecture diagram of a memory check pin processing system in one embodiment. [Figure 18] FIG. 2 is a block diagram showing the configuration of a memory check pin processing device according to an embodiment of the present invention; [Figure 19] FIG. 13 is a block diagram showing the configuration of a memory check pin processing device according to another embodiment. [Figure 20] FIG. 2 is a diagram showing the internal configuration of a computer device according to an embodiment. [Figure 21]FIG. 11 is a diagram showing the internal configuration of a computer device according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In order to make the object, configuration and advantages of the present application clearer, the present application will be described in more detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are merely for the purpose of interpreting the present application, and are not intended to limit the present application.

[0015] The memory check pin processing method provided in the embodiments of the present application is executed by a computer device, and is specifically applicable to the application environment shown in Fig. 1. Here, the terminal 102 communicates with the server 104 through a network. The memory check pin processing method may be executed by the terminal 102 or the server 104, or may be executed by the terminal 102 and the server 104 in cooperation. In some embodiments, the terminal 102 and the server 104 are provided with memory controllers. The memory check pin processing method may be specifically executed by the memory controller. When the memory check pin processing method is executed by the terminal 102, the terminal 102 sends a first data read command to the target memory, receives a first data signal and a sampling pulse signal returned from each check pin of the target memory, obtains a first delay parameter by time-shifting each of the first data signals by a delay circuit so that the target level value in each of the first data signals after the time shift is aligned with the sampling pulse signal, receives a second data signal returned from each check pin of the target memory, obtains a second delay parameter by time-shifting the target data signal in each of the second data signals by a delay circuit so that the target level value in each of the second data signals after the time shift is aligned, and determines the sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0016] Here, the terminal 102 may be, but is not limited to, a smartphone, tablet computer, laptop, desktop computer, smart speaker, smart watch, smart voice interaction device, smart home appliance, in-vehicle terminal, etc., with an AI chip built in. The AI ​​chip may be a chip combining an AI processor and a memory (e.g., a high-bandwidth memory). The memory may include a data storage area and a controller. Alternatively, the controller may exist independently and control the memory.

[0017] The server 104 may be an independent physical server with an AI chip built in, or a service node in a blockchain system. Each service node in the blockchain system configures a peer-to-peer (P2P) network, and the P2P protocol is an application layer protocol that runs on a protocol called the Transmission Control Protocol (TCP).

[0018] In addition, the server 104 may be a server cluster consisting of multiple physical servers with AI chips built in, or may be a cloud server that provides base cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0019] The terminal 102 and the server 104 can be connected to each other by a communication connection method such as Bluetooth, Universal Serial Bus (USB), or a network. The present application is not limited thereto.

[0020] Before describing the memory check pin processing method provided in the embodiment of the present application, a data read process of a memory in a conventional configuration will be described first.

[0021] In the conventional configuration, the computer device sends one burst data read command to the target memory, and then the target memory reads the read data according to the received read command, and returns the read data to the computer device. Figure 2 shows a schematic diagram of one read (READ) command sent in the conventional configuration. Here, the burst length can be 2 or 4. Figure 3 shows a schematic diagram of the read data (DQ) returned according to the read (READ) command. The relevant timing parameters included in Figure 3 are as follows: tDQSCK(min / max) refers to the minimum and maximum time range between the rising edge of RDQS_c (or the falling edge of RDQS_t) and the rising edge of CK_c (or the falling edge of CK_t). tDQSCK describes the time delay between the rising edge of RDQS and the rising edge of CK. tQSH describes the time delay that the RDQS signal lasts at high level. tQSL describes the time delay that the RDQS signal lasts at low level. tLZ(min / max) describes the minimum and maximum time range for the read data from a sustained high impedance state to a low impedance state. tHZ(min / max) describes the minimum and maximum time range for the read data from a sustained low impedance state to a high impedance state. tDQSQ describes the time delay from the rising edge of RDQS_t (or the falling edge of RDQS_c) to the read of DQ, DM, and DBI data. tQH describes the time delay from the rising edge of RDQS_t (or the falling edge of RDQS_c) to the read and stable holding of DQ, DM, and DBI data. RDQS (Read DQ Strobe) is the read data strobe, also called the sampling pulse signal. DQ is the read data bus, also called the read data. DM (Data Mask) is the data mask. DBI (Data Bus Inversion) is the data bus inversion.Here, burst refers to a method in which adjacent memory cells in the same row of a target memory continuously transmit data, and the number of cycles of continuous transmission is the burst length (BL).

[0022] In the conventional configuration, after the computer device transmits one burst data read command to the target memory, the target memory not only transmits the read data back to the computer device based on the received read command, but also transmits the parity check data of the read data back to the computer device. Here, the parity check signal corresponding to the parity check data may be transmitted simultaneously with the read data signal of the read data, or may be transmitted after the read data signal of the read data. Usually, the number of delay cycles of the parity check signal with respect to the read data signal is described by a parity check latency (PL) parameter. Specifically, the PL parameter may be set to 0 to 3 clock cycles. The setting of the PL parameter is controlled by the mode register bit MR4 (Mode Register 4) of the HBM. Specifically, it is as shown in the table below. [Table 1]

[0023] The role of the PL parameter is explained by taking an example. As shown in FIG. 4, since the corresponding read burst length BL (Read Burst Length)=2, PL=0, and Read Latency RL (Read Latency)=7, the read data signal reaches the rising edge of the clock at time T7. Since PL=0, the parity check signal similarly reaches the rising edge of the clock at time T7. Referring to FIG. 5, since the corresponding read burst length RL (Read Burst Length)=2, PL=1, and Read Latency RL (Read Latency)=6, the read data signal reaches the rising edge of the clock at time T6. Since PL=1, the parity check signal similarly reaches the rising edge of the clock at time T7.

[0024] As can be seen from the above description, when the computer device sends a data read command to the target memory, the target memory returns a read data signal (DQ), a parity check signal (PAR) of the read data signal, and a corresponding sampling pulse signal (RDQS) to the computer device, as shown in FIG. 6. The computer device obtains the data and parity check data to be read by sampling the read data signal and the parity check signal using RDQS as a sampling signal. Therefore, the sampling accuracy is highest only when the centers of the eye patterns of the sampling pulse signal and the parity check signal are aligned. Here, ACT is a row activation command, and PRE is a precharge command.

[0025] The accuracy of sampling will be described below with an example. As shown in FIG. 7, Data is sampled with CLK. In the HBM read check data scenario, CLK is the RDQS signal returned from the HBM DRAM, and Data includes the PAR data returned from the HBM DRAM. In FIG. 7A, the rising edge of CLK (i.e., the sampling edge) is at the center position of Data. In this case, the accuracy of sampling is the highest. In FIG. 7B and FIG. 7C, the center position of Data may not be aligned with the rising edge of CLK. In FIG. 7B, the rising edge of CLK has drifted from the data window of Data. In FIG. 7C, the rising edge of CLK has not drifted from the data window of Data, but the distance between the sampling edge and the establishment (or withdrawal) edge of Data is too close, so a timing violation of setup timing (or hold timing) occurs in this sampling. In both the situations shown in FIG. 7B and FIG. 7C, a sampling error of the read data occurs.

[0026] In one embodiment, a memory checkpin processing method is provided, as shown in Fig. 8. This method is described by taking the case where it is applied to the computer device (terminal or server) of Fig. 1 as an example. The method includes the following steps:

[0027] In S802, a first data read command is sent to the target memory.

[0028] Here, the target memory may be a High Bandwidth Memory (HBM), specifically, an HBM Dynamic Random Access Memory (DRAM). The first data read command is for reading data from the target memory.

[0029] In the embodiment of the present application, sending one first data read command to the target memory is equivalent to starting one read operation on the target memory. The read operation in the embodiment of the present application is generally a burst read operation. Burst refers to a method in which adjacent memory cells in the same row of the target memory continuously transmit data, and the number of cycles of continuous transmission is the burst length (BL: Burst Lengths).

[0030] Specifically, the computer device generates a first data read command, sends the first data read command to the target memory in the target mode, and the target memory reads read data from the register cell of the target memory according to the received data read command. Figure 2 is a schematic diagram of the first data read command in an embodiment of the present application.

[0031] Here, the target mode is one of the operation modes of the memory, and the operation mode of the memory may be specifically set by a mode register, which is for defining a specific operation mode of the HBM. This definition includes burst length, burst type, CAS delay, operation mode, and write burst mode selection. The operation mode in the embodiment of the present application is specifically set by mode register bit MR7. Specifically, see the function description information of mode register bit MR7 shown in FIG. 9.

[0032] In one embodiment, the computing device also needs to set an operation mode of the target memory before sending the first data read command to the target memory. The process of setting the operation mode of the target memory specifically includes: sending an operation mode setting command to the target memory, so that the target memory sets the operation mode to the target mode according to the operation mode setting command; and when the target memory is in the target mode, sending the first data read command to the target memory in the target mode.

[0033] Here, the target mode is a Data Word (DWORD) read Linear Feedback Shift Register (LFSR) mode.

[0034] Specifically, the computer device may set the target memory to a data word read linear feedback shift register (DWORD LFSR) mode, and then send a first data read command to the target memory in the data word read linear feedback shift register mode, and the target memory may read read data according to the received first data read command in the data word read linear feedback shift register mode, and store the read data in a register cell of the target memory, so that the computer device can obtain the read data stored in the register cell.

[0035] In the above embodiment, the computing device sends an operation mode setting command to the target memory, so that the target memory sets the operation mode to the target mode according to the operation mode setting command, and in the target mode, the memory returns a first data signal and a sampling pulse signal through each check pin, and can further determine the sampling delay parameter of the check pin.

[0036] In one embodiment, the process of the target memory setting the operating mode to the target mode based on the operating mode setting command includes the steps of initializing a read command processing circuit of the target memory and setting the operating mode of the read command processing circuit to the target mode based on the operating mode setting command.

[0037] Here, the operation mode setting command includes 8 data bits, and different commands are generated by changing the values ​​of different data bits. The command processing circuit may be a multiple-input shift register (MISR) circuit.

[0038] In addition, the multiple-input shift register (MISR) circuit may include a plurality of flip-flops and a plurality of input selectors alternately coupled in series with each other, and the plurality of input selectors may correspond to a plurality of flip-flops, respectively. FIG. 10 shows a schematic diagram of a MISR circuit in one embodiment. FIG. 10 shows four flip-flops and four input selectors for storing and outputting four data bits. Referring to FIG. 10, when both M0 and M1 of the input control signals are 1, that is, when both M0 and M1 of the input control signals are input at a logic high level, the MISR circuit corresponds to a multiple-input shift register mode, that is, the MISR circuit can perform the function of a multiple-input shift register. When the M0 bit of the input control signal is 0 and the M1 bit is 1, that is, when the M0 of the input control signal is input at a logic low level and the M1 is input at a logic high level, the MISR circuit corresponds to a simple register mode, that is, the MISR circuit can perform the function of a simple register. When the M0 bit of the input control signal is 1 and the M1 bit is 0, i.e., when the M0 bit of the input control signal is input at a logic high level and the M1 bit is input at a logic low level, the MISR circuit corresponds to a linear feedback shift register mode (LFSR mode), i.e., the MISR circuit can perform the function of a linear feedback shift register (LFSR).

[0039] As can be seen, if a command processing circuit supports 20 data bits, then the corresponding MISR circuit may include 20 flip-flops and 20 input selectors for storing and outputting the 20 data bits. This 20-bit MISR circuit can be mathematically described by the following polynomial:

number

[0040] If the command processing circuit supports 4 data bits, the corresponding MISR circuit may include 4 flip-flops and 4 input selectors for storing and outputting the 4 data bits. This 4-bit MISR circuit can be mathematically described by the following polynomial:

number

[0041] Specifically, the computer equipment generates an initialization command and transmits the initialization command to the target memory, the target memory receives the initialization command and then initializes the read command processing circuit based on the initialization command, the computer equipment then transmits an operation mode setting command to the target memory, and the initialized target memory sets the operation mode of the read command processing circuit of the target memory to the target mode based on the operation mode setting command.

[0042] For example, the HBM sets the DWORD MISR circuit to the DWORD read LFSR mode by setting the mode register MR7 of the HBM. The steps of setting the HBM to the DWORD read LFSR mode are specifically as follows. First, the command value of MR7 is set to 8'b00000001. Referring to FIG. 9, OP0 is 1, which indicates the enablement of the DWORD Loopback mode, OP[5:3] is 3'b000, which indicates the default value of the DWORD register is reset to 0xAAAAAh, and the other bits are all default values. This initializes the read command processing circuit based on the command of this MR7. Next, the command value of MR7 is set to 8'b00001011. Here, OP0 is 1, which indicates the enablement of DWORD Loopback mode, OP[2:1] is 2'b01, which indicates the reading of the value of the MISR register (since the value was reset during the initialization process, the value read is 0xAAAAAh), OP[5:3] is 3'b001, which sets the DWORD register to read LFSR mode, and all other bits are default values. As a result, based on this MR7 command, the operation mode of the read command processing circuit of the target memory is set to DWORD read LFSR mode.

[0043] In the above embodiment, the read command processing circuit of the target memory is initialized, and the operation mode of the read command processing circuit is set to the target mode according to the operation mode setting command, so that in the target mode, the target memory returns the first data signal and the sampling pulse signal through each check pin, and the sampling delay parameter of the check pin can be further determined.

[0044] In S804, the first data signal and the sampling pulse signal returned from each check pin of the target memory are received.

[0045] Here, the first data signal is generated based on the target data bits in the read data, and the read data is data that the target memory reads from the register of the target memory based on the first data read command.

[0046] In addition, the operating mode of the target memory is the target mode, and the data output from each check pin in the target mode does not represent the check data of the read data, but rather returns the value of the target data bit in the read data that is close to each pin to the corresponding check pin.

[0047] Specifically, when the target memory receives the first data read command, it performs a read operation based on the first data read command to obtain read data, returns the value of the target data bit in the read data to the corresponding check pin, and outputs the value of the target data bit as a first data signal by the check pin.

[0048] For example, the read data and parity check pins of a single channel of an HBM DRAM includes the following associated interfaces: [Table 2]

[0049] For example, in DWORD read LFSR mode, the data returned from the check pins does not really represent the contents of the check data of the read data, and is not affected by the setting corresponding to the DQ bus read parity check of MR0. Here, the function description information of the mode register bit MR0 is as shown in Figure 11. In DWORD read LFSR mode, the HBM DRAM returns the target data bits in the read data (DQ) that are close to each check pin to the corresponding check pin. The following table shows the data bits of the read data that are actually returned corresponding to each check (PAR) pin. [Table 3]

[0050] In the read LFSR mode, PAR[0] does not represent the parity check data of the 32-bit data of DQ[31:0], but simply returns the value of DQ[2] to PAR[0]. Similarly, it returns the value of DQ

[34] to PAR[1], the value of DQ

[66] to PAR[2], and the value of DQ

[98] to PAR[3]. At the same time, the setting of PL no longer works, and PAR and DQ arrive at the same time, i.e., it returns to the delay when PL=0.

[0051] Referring to the schematic diagram of the read data structure shown in FIG. 12, one complete data word (DWORD) in the embodiment of the present application can be divided into four groups, DWORD0, DWORD1, DWORD2, and DWORD3. Here, each DWORD is divided into a total of four data units, Byte0, Byte1, Byte2, and Byte3. That is, the 128-bit read data (DQ) is distributed to 16 Bytes, and each Byte contains 8-bit DQ. As shown in FIG. 12, the 19th bit to the 0th bit of each Byte are respectively the data word of the falling edge of DBI and the data word of the rising edge of DBI, the data word of the falling edge and the data word of the rising edge of each bit of 8-bit DQ, the data word of the falling edge of DM, and the data word of the rising edge of DBI. That is, each Byte contains a 20-bit value, and when the DWORD register is reset, the value becomes 0xAAAAAh. Therefore, the initial values ​​of each check pin are as shown in the table below. [Table 4]

[0052] As can be seen, the number of check pins is the same as the number of first data signals. For example, if the number of check pins is four, the number of corresponding first data signals is also four. For example, if the check pins are PAR[0], PAR[1], PAR[2], and PAR[3], respectively, the read data are data1, data2, data3, and data4, and the first data signal returned from PAR[0] is generated based on the value of the data bit DQ[2] of data1, data2, data3, and data4, respectively, the first data signal returned from PAR[1] is generated based on the value of the data bit DQ

[34] of data1, data2, data3, and data4, respectively, the first data signal returned from PAR[2] is generated based on the value of the data bit DQ

[66] of data1, data2, data3, and data4, respectively, and the first data signal returned from PAR[3] is generated based on the value of the data bit DQ

[98] of data1, data2, data3, and data4, respectively.

[0053] In S806, a first delay parameter is obtained by time-shifting each of the first data signals by a delay circuit such that a target level value in each of the first data signals after the time shift is aligned with the sampling pulse signal.

[0054] Here, each check pin has a corresponding delay circuit. The delay circuit is for time-shifting the data signal returned from the corresponding check pin. Time-shifting refers to moving the data signal in time. Specifically, the data signal can be time-shifted by adjusting the time delay in the transmission path corresponding to each data signal. The time-shifting direction specifically includes a first direction and a second direction. Here, the first direction refers to the direction in which time is delayed, and the second direction refers to the direction in which time is advanced.

[0055] The target level value may be the first high level of the first data signal. The target level value being aligned with the sampling pulse signal refers to the first high level of the first data signal being aligned with the rising edge of the sampling pulse signal. The first high level of the first data signal being aligned with the rising edge of the sampling pulse signal may specifically be at least one of the following: the rising edge of the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal, the falling edge of the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal, and the center of the eye pattern of the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal.

[0056] The first delay parameter is a delay time for aligning the center of the first high-level eye pattern of the first data signal after the time shift with the sampling pulse signal, i.e., when the first data signal is time-shifted by the first delay parameter, the center of the first high-level eye pattern of the first data signal after the time shift is aligned with the rising edge of the sampling pulse signal.

[0057] Referring to FIG. 7, assuming that Data in FIG. 7C is a first data signal received by a check pin and the center of the first high level eye pattern of the first data signal is to the left of the rising edge of the sampling pulse signal (CLK), the delay circuit corresponding to the check pin time shifts the first data signal in a first direction with a first delay parameter, thereby achieving that the center of the first high level eye pattern of the first data signal after the time shift shown in FIG. 7A is aligned with the rising edge of the sampling pulse signal (CLK).

[0058] FIG. 13 shows a schematic diagram of a delay circuit in an embodiment. Here, the delay circuit corresponding to each check pin includes a plurality of delay elements (DE), each of the delay elements includes four inverter circuits, and each of the DEs includes a tap outlet. As shown in FIG. 14, a step counter controls the data signal to be output from any of the tap outlets, thereby achieving the purpose of time shifting the data signal. Here, the time difference between two adjacent tap outlets is one time shift step size. For example, in the initial state, the first data signal of a certain check pin is output from the i-th tap outlet of the delay circuit. That is, in the default state, the computer device receives the first data signal from the i-th tap outlet of the delay circuit. When it is necessary to perform a time shift in the first direction on the first data signal, the first data signal can be received from the i+1th or later tap outlet to achieve the purpose of time shifting the first data signal in the first direction. If it is necessary to perform time shifting in a second direction on the first data signal, the purpose of performing time shifting in the second direction on the first data signal can be achieved by receiving the first data signal from the tap outlet after the (i-1)th tap outlet.

[0059] In one embodiment, S806 specifically includes the steps of: obtaining a first time shift parameter by time shifting each first data signal along a first direction by a delay circuit, such that a rising edge of a target level value in each first data signal after the time shift is aligned with a rising edge of a sampling pulse signal; obtaining a second time shift parameter by time shifting each first data signal along a second direction by a delay circuit, such that a falling edge of a target level value in each first data signal after the time shift is aligned with a rising edge of a sampling pulse signal, where the first direction and the second direction are opposite directions; and determining a first delay parameter corresponding to each check pin based on the first time shift parameter and the second time shift parameter.

[0060] A specific process of time-shifting each of the first data signals along the first direction is as follows. After obtaining the first data signal, the computer device sets a time shift length corresponding to each check pin, and returns to the step of sending a first data read command to the target memory; after receiving the first data signal returned from each check pin again, the computer device time-shifts the first data signal by the set time shift length, and determines whether the rising edge of the target level value in the first data signal after the time shift is aligned with the sampling pulse signal; if the rising edge of the target level value in the first data signal corresponding to each check pin is aligned with the sampling pulse signal, the computer device determines the set time shift length and first direction corresponding to each check pin as the first time shift parameter corresponding to each pin; if the rising edge of the target level value in the first data signal corresponding to at least one of the check pins is not aligned with the sampling pulse signal, the computer device sets the time shift length corresponding to each check pin again until the rising edge of the target level value in the first data signal corresponding to each check pin is aligned with the sampling pulse signal, and returns to the step of sending a first data read command to the target memory; if the rising edge is aligned with the sampling pulse signal, the computer device determines the time shift length and first direction corresponding to each check pin as the first time shift parameter of the corresponding check pin.

[0061] Taking one of the check pins as an example, referring to Figure 15, the data signal corresponding to phase 0 is the first data signal received by the computer device from the i-th (initial default) tap outlet of the delay circuit, that is, the data signal corresponding to phase 0 is the first data signal that has not been time-shifted. After receiving the first data signal, the computer device sets the time shift direction of the check pin to be the first direction and the time shift length to be n (n refers to the number of time shifts) by the delay circuit shown in Figure 14, that is, receives the first data signal from the i+nth tap outlet, returns to the step of sending the first data read command to the target memory, receives the first data signal from the i+nth tap outlet after receiving the first data signal returned from each check pin again, obtains the first data signal after time shift, judges whether the rising edge of the target level value of the first data signal after time shift is aligned with the sampling pulse signal, and determines the time shift length and first direction corresponding to the check pin when aligned as the first time shift parameter of the check pin. As shown in Figure 15, the data signal corresponding to phase 1 is the first data signal after time shifting after several time shifts.

[0062] A specific process of time-shifting each of the first data signals along the second direction is as follows. After obtaining the first data signal, the computer device sets a time shift length corresponding to each check pin, and returns to the step of sending a first data read command to the target memory; after receiving the first data signal returned from each check pin again, the computer device time-shifts the first data signal by the set time shift length, and determines whether the falling edge of the target level value in the first data signal after the time shift is aligned with the sampling pulse signal; if the falling edge of the target level value in the first data signal corresponding to each check pin is aligned with the sampling pulse signal, the computer device determines the set time shift length and second direction corresponding to each check pin as the second time shift parameter corresponding to each pin; if the falling edge of the target level value in the first data signal corresponding to at least one of the check pins is not aligned with the sampling pulse signal, the computer device sets a time shift length corresponding to the at least one check pin again until the falling edge of the target level value in the first data signal corresponding to each check pin is aligned with the sampling pulse signal, and returns to the step of sending a first data read command to the target memory; if the falling edge is aligned with the sampling pulse signal, the computer device determines the time shift length and second direction corresponding to each check pin as the second time shift parameter of the corresponding check pin.

[0063] An example will be described by taking one of the check pins. Referring to FIG. 15, the data signal corresponding to phase 0 is the first data signal received by the computer device from the i-th (initial default) tap outlet of the delay circuit. That is, the data signal corresponding to phase 0 is the first data signal that has not been time-shifted. After receiving the first data signal, the computer device sets the time shift direction of the check pin to the second direction and the time shift length to a time shift step size of n (n indicates the number of time shifts) by the delay circuit shown in FIG. 14, that is, receives the first data signal from the in-th tap outlet, returns to the step of transmitting the first data read command to the target memory, receives the first data signal from the in-th tap outlet after receiving the first data signal returned from each check pin again, and obtains the first data signal after time shifting, and determines whether the falling edge of the target level value of the first data signal after time shifting is aligned with the sampling pulse signal, and determines the time shift length corresponding to the check pin when aligned as the second time shift parameter of the check pin. As shown in FIG. 15, the data signal corresponding to phase 2 is the first data signal after undergoing several time shifts.

[0064] In one embodiment, after obtaining the first time shift parameter and the second time shift parameter of a check pin, the computer device inputs the first time shift parameter and the second time shift parameter into the following formula to determine the first delay parameter of the check pin:

number

[0065] In the above embodiment, the computer device obtains a first time shift parameter by time-shifting each of the first data signals along a first direction by a delay circuit, so that a rising edge of a target level value in each of the first data signals after the time shift is aligned with a rising edge of the sampling pulse signal, obtains a second time shift parameter by time-shifting each of the first data signals along a second direction opposite to the first direction by a delay circuit, so that a falling edge of a target level value in each of the first data signals after the time shift is aligned with a rising edge of the sampling pulse signal, and determines a first delay parameter corresponding to each check pin according to the first time shift parameter and the second time shift parameter. Thus, after subsequently receiving the data signal returned from each check pin, i.e., after receiving the parity check signal, the second delay parameter can be further determined by time-shifting the parity check signal by the determined first delay parameter, so that the parity check signal after the time shift is aligned with the rising edge of the sampling pulse signal.

[0066] In S808, when a second data signal returned from each check pin of the target memory is received, a second delay parameter is obtained by time-shifting the target data signal in each second data signal by a delay circuit so that the target level values ​​in each second data signal after the time shift are aligned.

[0067] In one embodiment, the computing device may time-shift each of the first data signals by a delay circuit so that the target level value of each of the first data signals after the time shift is aligned with the sampling pulse signal, and then send a second data read command to the target memory, and receive the second data signal and the sampling pulse signal returned from each check pin of the target memory.

[0068] Here, the second data read command may be the same as or different from the first data read command, the second data signal is generated based on the target data bits in the read data, and the read data is data read from the register of the target memory by the target memory based on the second data read command.

[0069] In addition, the operating mode of the target memory is the target mode, and the data output from each check pin in the target mode does not represent the check data of the read data, but rather returns the value of the target data bit in the read data that is close to each pin to the corresponding check pin.

[0070] Specifically, when the target memory receives the second data read command, it performs a read operation based on the second data read command to obtain read data, returns the value of the target data bit in the read data to the corresponding check pin, and outputs the value of the target data bit as a second data signal through the check pin.

[0071] In one embodiment, the computer device may obtain the fourth sampling data by sampling the second data signal time-shifted by the first delay parameter with the sampling pulse signal after obtaining the second data signal. The process of the computer device obtaining the second delay parameter by time-shifting the target data signals in the second data signal by the delay circuit so that the target level values ​​in each second data signal after time-shifting are aligned specifically includes: determining that the target data signals in the second data signal are not aligned with the target level values ​​in other second data signals when the target data bits of the target sampling data in each fourth sampling data are different from the target data bits of the other fourth sampling data; and obtaining the second delay parameter by time-shifting the target data signals in the second data signal by the delay circuit so that the target level values ​​in each second data signal after time-shifting are aligned.

[0072] Specifically, the computer device obtains a second data signal, and then uses a delay circuit to initially time-shift the second data signal with a first delay parameter to obtain an initial time-shifted second data signal, samples the initial time-shifted second data signal with a sampling pulse signal to obtain fourth sampling data, searches for target sampling data in which target data bits are different from target data bits of the other fourth sampling data, determines that the initial time-shifted second data signal corresponding to the target sampling data is not aligned with the other initial time-shifted second data signals, modifies time-shifts the target data signal in the initial time-shifted second data signal by the delay circuit, so that the target level values ​​in each time-shifted second data signal are aligned, and determines the time shift length of the target data signal in the modified time-shift process as the second delay parameter.

[0073] In addition, after the computer device uses the delay circuit to initially time-shift the second data signal corresponding to each check pin with the first delay parameter, the center of the eye pattern of the target level value of the obtained second data signal after the initial time shift corresponds to the rising edge of the sampling pulse signal, and the rising edge of the corresponding sampling pulse signal may be a rising edge in the same clock cycle or a rising edge in a different clock cycle. As shown in FIG. 16A, for the second data signal corresponding to each of the four PAR pins PAR[0] to PAR[3], after the second data signal is initially time-shifted with the first delay parameter corresponding to each of the PAR pins, the result shown in FIG. 16B is obtained. As can be seen from FIG. 16B, the center of the eye pattern of the target level value of the second data signal after the initial time shift of PAR[0], PAR[1], and PAR[3] is aligned with the rising edge of the second clock cycle, and the center of the eye pattern of the target level value of the second data signal after the initial time shift of PAR[2] is aligned with the rising edge of the third clock cycle. After the fourth sampling data is obtained by sampling the second data signal after the initial time shift of each of PAR[0], PAR[1], and PAR[3], the target data bits of PAR[0], PAR[1], and PAR[3] are all the 1st bit, and the target data bit of the fourth sampling data of PAR[2] is the 2nd bit. Therefore, the fourth sampling data of PAR[2] is determined as the target sampling data, and the second data signal after the initial time shift corresponding to the fourth sampling data of PAR[2] is determined as the target second data signal.The delay circuit performs a correction time shift on the second data signal after the initial time shift of PAR[2] until the target level value of the obtained second data signal after the correction time shift of PAR[2] is aligned with the target level values ​​of the second data signals after the initial time shift of PAR[0], PAR[1], and PAR[3] (as shown in FIG. 16C), and determines the time shift length and direction of the correction time shift corresponding to the second data signal after the correction time shift of PAR[2] when the target level value is aligned as the second delay parameter of PAR[2]. The second delay parameter may be determined to be 0 for PAR[0], PAR[1], and PAR[3] that are not subjected to the correction time shift.

[0074] In one embodiment, the computer device obtains a second data signal, and then uses a delay circuit to initially time-shift the second data signal with a first delay parameter to obtain an initial time-shifted second data signal, and samples the initial time-shifted second data signal with a sampling pulse signal to obtain fourth sampling data, and determines that if the target data bits of each fourth sampling data are the same, the target level values ​​of the initial time-shifted second data signal corresponding to each fourth sampling data are aligned, and determines the second delay parameter corresponding to each check pin to be 0.

[0075] In the above embodiment, the computer device obtains fourth sampling data by sampling each second data signal time-shifted by the first delay parameter with the sampling pulse signal, and determines that the target data signal in the second data signal is not aligned with the target level value in the other second data signals when the target data bit of the target sampling data in the fourth sampling data is different from the target data bit of the other fourth sampling data, and obtains a second time shift parameter by time-shifting the target data signal in each second data signal by the delay circuit so that the target level values ​​in each second data signal after time shifting are aligned. Thus, the sampling delay parameter of each check pin can be determined based on the second delay parameter. Thus, after subsequently receiving the data signal returned from each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted with the determined sampling delay parameter so that the parity check signal after time shifting is aligned with the sampling pulse signal, and the accuracy of sampling the parity check signal based on the sampling pulse signal is ensured.

[0076] In S810, a sampling delay parameter of the check pin is determined based on the first delay parameter and the second delay parameter.

[0077] Specifically, the computer device obtains the first delay parameter and the second delay parameter corresponding to each check pin, and then calculates the sum of the corresponding first delay parameter and the second delay parameter, and determines the obtained sum as the sampling delay parameter of the corresponding check pin, so that after subsequently receiving the data signal returned from each check pin, i.e., after receiving the parity check signal, the parity check signal can be time-shifted by the determined sampling delay parameter, so that the parity check signal after time-shifting is aligned with the sampling pulse signal, and the accuracy of sampling the parity check signal according to the sampling pulse signal is ensured.

[0078] In the above embodiment, the computer device sends a first data read command to the target memory, receives the first data signal and the sampling pulse signal returned from each check pin of the target memory, and obtains a first delay parameter by time-shifting each of the first data signals by the delay circuit so that the target level value of each of the first data signals after time-shifting is aligned with the sampling pulse signal; receives the second data signal returned from each check pin of the target memory, and obtains a second delay parameter by time-shifting each of the target data signals in each of the second data signals by the delay circuit so that the target level value of each of the second data signals after time-shifting is aligned with the sampling pulse signal; and determines the sampling delay parameter of the check pin according to the first delay parameter and the second delay parameter. Thus, after subsequently receiving the data signal returned from each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted with the determined sampling delay parameter so that the parity check signal after time-shifting is aligned with the sampling pulse signal, and the accuracy of sampling the parity check signal according to the sampling pulse signal is ensured.

[0079] In one embodiment, the computer device obtains a first data signal, and then samples the first data signal with a sampling pulse signal to obtain first sampling data. The process of the computer device time-shifting each of the first data signals along a first direction by a delay circuit, so that the rising edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal to obtain a first time shift parameter specifically includes: time-shifting each of the first data signals along the first direction by a delay circuit, sampling the first data signals time-shifted along the first direction with a sampling pulse signal to obtain second sampling data, determining that the rising edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal when the value of the target data bit in each of the second sampling data is the same as the target value corresponding to the target data bit in the first sampling data, and determining the time shift length corresponding to each of the second sampling data as the first time shift parameter.

[0080] After acquiring the first data signal, the computer device samples the first data signal with a sampling pulse signal to acquire the first sampling data. The value of the data bit corresponding to the target level value of the first data signal in the acquired first sampling data should be 1. When the rising edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, that is, when the rising edge of the first high level in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, the value of the data bit of the corresponding bit obtained by sampling the first data signal after the time shift based on the sampling pulse signal should be 0. As shown in FIG. 15, the data signal corresponding to phase 0 is the first data signal without the time shift, and the value of the data bit of the first bit in the first sampling data obtained by sampling the first data signal with the sampling pulse signal should be 1. The data signal corresponding to phase 1 is the first data signal with the time shift, and the value of the data bit of the first bit in the first sampling data obtained by sampling the first data signal after the time shift with the sampling pulse signal should be 0.

[0081] Based on this, in the embodiment of the present application, a data bit corresponding to a target level value of the first data signal in the first sampling data is determined as a target data bit, and a target value corresponding to the target data bit in the first sampling data is set to 0.

[0082] Specifically, after obtaining each first data signal, the computer device returns to the step of sampling the first data signal at the rising edge of the sampling pulse signal to obtain each first sampling data, and sending a first data read command to the target memory, time-shifting each first data signal along a first direction by a delay circuit to obtain each time-shifted first data signal, sampling each time-shifted first data signal at the rising edge of the sampling pulse signal to obtain each second sampling data, determining whether a value of a target data bit in each second sampling data is equal to a target value corresponding to the target data bit in the corresponding first sampling data, and if the value of the target data bit in the second sampling data is equal to the target value corresponding to the target data bit in the corresponding first sampling data, determining that the rising edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, and determining the time shift length and the first direction of the time-shifted first data signal corresponding to the second sampling data as a first time shift parameter.

[0083] For example, when a target data bit in the first sampling data obtained by sampling a first data signal of a certain check pin is a second data bit, the value of the second data bit is 1, and the corresponding target value is 0, the second sampling data is obtained by sampling the time-shifted first data signal time-shifted along the first direction, and then the value of the second data bit in the second sampling data is obtained. When the value of the second data bit in the second sampling data is 0, it is determined that the rising edge of the target level value of the time-shifted first data signal time-shifted along the first direction is aligned with the rising edge of the sampling pulse signal, and the time shift length and the first direction in which the time-shifted first data signal is time-shifted along the first direction are determined as first time shift parameters.

[0084] In the above embodiment, the computer device obtains first sampling data by sampling the first data signal with the sampling pulse signal, time-shifts each of the first data signals along a first direction by a delay circuit, obtains second sampling data by sampling the first data signal time-shifted along the first direction with the sampling pulse signal, and determines that if the value of the target data bit in each of the second sampling data is the same as the target value corresponding to the target data bit in the first sampling data, the rising edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal, and determines the time shift length corresponding to each of the second sampling data as a first time shift parameter. Furthermore, the sampling delay parameter of the check pin can be determined based on the first time shift parameter. Thus, after subsequently receiving the data signal returned from each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted with the determined sampling delay parameter so that the parity check signal after time shifting is aligned with the sampling pulse signal, thereby ensuring the accuracy of sampling the parity check signal based on the sampling pulse signal.

[0085] In one embodiment, if there is second sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, return to the step of sending a first data read command to the target memory until the rising edge of the target level value in each first data signal after the acquired time shift is aligned with the rising edge of the sampling pulse signal, and determine the time shift length corresponding to each second sampling data as the first time shift parameter.

[0086] Specifically, the computer device obtains each second sampling data by sampling each first data signal time-shifted along the first direction at a rising edge of the sampling pulse signal, determines whether a value of a target data bit in each second sampling data is the same as a target value corresponding to the target data bit in the corresponding first sampling data, and if a value of the target data bit in at least one second sampling data is different from a target value corresponding to the target data bit in the corresponding first sampling data, determines that a rising edge of a target level value in each first data signal after time-shifting corresponding to the at least one second sampling data is not aligned with a rising edge of the sampling pulse signal, returns to the step of sending a first data read command to the target memory until a rising edge of the target level value in each acquired first data signal after time-shifting is aligned with a rising edge of the sampling pulse signal, and determines a time shift length and a first direction corresponding to each first data signal after time-shifting when aligned as a first time shift parameter.

[0087] For example, when the target data bit in the first sampling data obtained by sampling the first data signal of a certain check pin is the second data bit, the value of the second data bit is 1, and the corresponding target value is 0, the second sampling data is obtained by sampling the first data signal after time shifting along the first direction, and then the value of the second data bit in the second sampling data is obtained. When the value of the second data bit in the second sampling data is 1, that is, when the value of the second data bit in the second sampling data, which is 1, is different from the target value 0, it is determined that the rising edge of the target level value of the first data signal after time shifting along the first direction does not align with the rising edge of the sampling pulse signal, and the step returns to the step of sending the first data read command to the target memory until the rising edge of the target level value in each of the acquired first data signals after time shifting aligns with the rising edge of the sampling pulse signal, and the time shift length and the first direction corresponding to each first data signal after each time shift when they align are determined as the first time shift parameters.

[0088] In the above embodiment, when there exists second sampling data whose target data bit value is different from the target value corresponding to the target data bit in the first sampling data, the computer device returns to the step of sending the first data read command to the target memory until the rising edge of the target level value in each first data signal after the acquired time shift is aligned with the rising edge of the sampling pulse signal, and determines the time shift length corresponding to each second sampling data as the first time shift parameter. Furthermore, the sampling delay parameter of the check pin can be determined based on the first time shift parameter. Thus, after subsequently receiving the data signal returned from each check pin, that is, after receiving the parity check signal, the parity check signal after the time shift can be time shifted with the determined sampling delay parameter so that the parity check signal after the time shift is aligned with the sampling pulse signal, and the accuracy of sampling the parity check signal based on the sampling pulse signal is ensured.

[0089] In one embodiment, the computer device obtains a first data signal, and then samples the first data signal with a sampling pulse signal to obtain first sampling data. The process of the computer device time-shifting each of the first data signals along a second direction by the delay circuit so that the falling edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal to obtain a second time shift parameter specifically includes: time-shifting each of the first data signals along the second direction by the delay circuit; sampling the first data signals time-shifted along the second direction with the sampling pulse signal to obtain third sampling data; determining that the falling edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal when the value of the target data bit in each of the third sampling data is the same as the target value corresponding to the target data bit in the first sampling data; and determining the time shift length corresponding to each of the third sampling data as the second time shift parameter.

[0090] After acquiring the first data signal, the computer device samples the first data signal with a sampling pulse signal to acquire the first sampling data. The value of the data bit corresponding to the target level value of the first data signal in the acquired first sampling data should be 1. When the falling edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, that is, when the falling edge of the first high level in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, the value of the data bit of the corresponding bit obtained by sampling the first data signal after the time shift based on the sampling pulse signal should be 0. As shown in FIG. 15, the data signal corresponding to phase 0 is the first data signal without the time shift, and the value of the data bit of the first bit in the first sampling data obtained by sampling the first data signal with the sampling pulse signal should be 1. The data signal corresponding to phase 2 is the first data signal with the time shift, and the value of the data bit of the first bit in the first sampling data obtained by sampling the first data signal after the time shift with the sampling pulse signal should be 0.

[0091] Based on this, in the embodiment of the present application, a data bit corresponding to a target level value of the first data signal in the first sampling data is determined as a target data bit, and a target value corresponding to the target data bit in the first sampling data is set to 0.

[0092] Specifically, after obtaining each first data signal, the computer equipment returns to the step of obtaining each first sampling data by sampling the first data signal at the rising edge of the sampling pulse signal, and sending a first data read command to the target memory, time-shifting each first data signal along the second direction by a delay circuit respectively to obtain each time-shifted first data signal, sampling each time-shifted first data signal at the rising edge of the sampling pulse signal to obtain each third sampling data, and determining that if the value of the target data bit in the third sampling data is the same as the target value corresponding to the target data bit in the corresponding first sampling data, the rising edge of the target level value in each time-shifted first data signal is aligned with the rising edge of the sampling pulse signal, and determining the time shift length and second direction of the time-shifted first data signal corresponding to the third sampling data as the second time shift parameter.

[0093] For example, when the target data bit in the first sampling data obtained by sampling the first data signal of a certain check pin is the second data bit, the value of the second data bit is 1, and the corresponding target value is 0, the third sampling data is obtained by sampling the time-shifted first data signal time-shifted along the second direction, and then the value of the second data bit in the third sampling data is obtained. When the value of the second data bit in the third sampling data is 0, it is determined that the falling edge of the target level value of the time-shifted first data signal time-shifted along the second direction is aligned with the rising edge of the sampling pulse signal, and the time shift length and the second direction in which the time-shifted first data signal is time-shifted along the second direction are determined as second time shift parameters.

[0094] In the above embodiment, the computer device obtains first sampling data by sampling the first data signal with the sampling pulse signal, time-shifts each of the first data signals along the second direction by a delay circuit, obtains third sampling data by sampling the first data signals time-shifted along the second direction with the sampling pulse signal, and determines that if the value of the target data bit in each of the third sampling data is the same as the target value corresponding to the target data bit in the first sampling data, the falling edge of the target level value in each of the first data signals after time-shifting is aligned with the rising edge of the sampling pulse signal, and determines the time shift length corresponding to each of the third sampling data as the second time shift parameter. Furthermore, the sampling delay parameter of the check pin can be determined based on the second time shift parameter. Thus, after subsequently receiving the data signal returned from each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted with the determined sampling delay parameter so that the parity check signal after time-shifting is aligned with the sampling pulse signal, thereby ensuring the accuracy of sampling the parity check signal based on the sampling pulse signal.

[0095] In one embodiment, when there is third sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, the step returns to the step of sending a first data read command to the target memory until the falling edge of the target level value in each first data signal after the acquired time shift is aligned with the rising edge of the sampling pulse signal, and the time shift length corresponding to each third sampling data is determined as the second time shift parameter.

[0096] Specifically, the computer device obtains each third sampling data by sampling each first data signal time-shifted along the second direction based on the rising edge of the sampling pulse signal, judges whether a value of a target data bit in each third sampling data is the same as a target value corresponding to the target data bit in the corresponding first sampling data, and determines that a falling edge of a target level value in each first data signal after time-shifting corresponding to the at least one third sampling data is not aligned with a rising edge of the sampling pulse signal if the value of the target data bit in at least one third sampling data is different from a target value corresponding to the target data bit in the corresponding first sampling data, and returns to the step of sending a first data read command to the target memory until the falling edge of the target level value in each acquired first data signal after time-shifting is aligned with the rising edge of the sampling pulse signal, and determines a time shift length and a second direction corresponding to each first data signal after time-shifting when aligned as a second time shift parameter.

[0097] For example, when the target data bit in the first sampling data obtained by sampling the first data signal of a certain check pin is the second data bit, the value of the second data bit is 1, and the corresponding target value is 0, the third sampling data is obtained by sampling the first data signal after time shifting along the second direction, and then the value of the second data bit in the third sampling data is obtained. When the value of the second data bit in the third sampling data is 1, that is, when the value of the second data bit in the third sampling data, which is 1, is different from the target value 0, it is determined that the falling edge of the target level value of the first data signal after time shifting along the second direction does not align with the rising edge of the sampling pulse signal, and the step returns to the step of sending the first data read command to the target memory until the falling edge of the target level value in each of the acquired first data signals after time shifting aligns with the rising edge of the sampling pulse signal, and the time shift length and the second direction corresponding to each first data signal after each time shift when they align are determined as the second time shift parameter.

[0098] In the above embodiment, when there is third sampling data whose target data bit value is different from the target value corresponding to the target data bit in the first sampling data, the computer device returns to the step of sending the first data read command to the target memory until the falling edge of the target level value in each first data signal after the acquired time shift is aligned with the rising edge of the sampling pulse signal, and determines the time shift length corresponding to each third sampling data as the second time shift parameter. Furthermore, the sampling delay parameter of the check pin can be determined based on the second time shift parameter. Thus, after subsequently receiving the data signal returned from each check pin, that is, after receiving the parity check signal, the parity check signal after the time shift can be time shifted with the determined sampling delay parameter so that the parity check signal after the time shift is aligned with the sampling pulse signal, and the accuracy of sampling the parity check signal based on the sampling pulse signal is ensured.

[0099] This application further provides an application scenario in which the memory check pin processing method is applied. Specifically, referring to the system architecture diagram shown in FIG. 17, the application of the memory check pin processing method in the application scenario is as follows:

[0100] In step 1, the operating mode of the HBM DRAM is set to the target mode.

[0101] Specifically, the mode setting unit of the HBM host sends an operation mode setting command to the HBM DRAM, which sets the HBM DRAM to the DWORD read LFSR mode based on the operation mode setting command.

[0102] Step 2 is to send a read command to the HBM DRAM.

[0103] Specifically, the HBM host sends a read command to the HBM DRAM through the command sending unit, the HBM DRAM analyzes the received read command, inputs the analysis result to the DWORD MISR circuit, outputs the read data through the DWORD MISR circuit, and returns the target data bit in the read data to the HBM host through the read PAR sending unit.

[0104] Step 3 receives the read PAR data returned from each PAR pin.

[0105] Specifically, it receives the read PAR data signal and the sampling pulse signal (RDQS) returned from each PAR pin.

[0106] Step 4 is the per PAR training stage.

[0107] Specifically, the read PAR training unit judges whether the center of the first high level eye pattern of each PAR data signal is aligned with the rising edge of the sampling pulse signal (RDQS). If all are aligned, execute step 5. If the center of the first high level eye pattern of at least one read PAR data signal is not aligned with the rising edge of the sampling pulse signal (RDQS), the read PAR path delay control circuit adjusts the delay of the PAR path corresponding to the at least one read PAR data signal, and returns to step 2 and step 3, and after receiving each read PAR data signal, time-shifts the corresponding read PAR data signal by the determined delay, and judges whether the center of the first high level eye pattern of each PAR data signal after each time-shift is aligned with the rising edge of the sampling pulse signal (RDQS). If all are aligned, execute step 5. If the center of the first high-level eye pattern of at least one time-shifted PAR data signal is not aligned with the rising edge of the sampling pulse signal (RDQS), adjust the delay of the PAR path corresponding to the at least one time-shifted PAR data signal by the read PAR path delay control circuit until the centers of the first high-level eye patterns of all time-shifted PAR data signals are aligned with the rising edge of the sampling pulse signal (RDQS), and return to step 2 and step 3. Determine the delay corresponding to each PAR pin when aligned as a first delay parameter.

[0108] For example, as shown in FIG. 15, the initial state of the data signal of a certain PAR pin is phase 0, and the value of the second data bit of the sampling data obtained by sampling the read PAR data signal in this phase 0 state based on the pulse signal is 1.

[0109] The Step Counter gradually increases the circuit delay corresponding to the PAR pin, and finally, the data signal of the PAR pin reaches the state of Phase 1. The value of the second data bit of the sampled data obtained by sampling the read PAR data signal in this phase 1 state is 0. At this time, the value of the Step Counter is recorded as R_CNT, and R_CNT is the first delay parameter of the PAR pin.

[0110] By adjusting the Step Counter, the circuit delay corresponding to the PAR pin is gradually reduced, and finally, the data signal of the PAR pin reaches the state of Phase 2. The value of the second data bit of the sampling data obtained by sampling the read PAR data signal in this phase 2 state is 0. At this time, the value of the Step Counter is recorded as L_CNT, and L_CNT is the second delay parameter of the PAR pin.

[0111] It can be seen that when the circuit delay of the PAR pin is (R_CNT+L_CNT) / 2, the PAR data signal output from the delay circuit of the PAR pin can be aligned with the rising edge of the sampling pulse clock.

[0112] Step 5 is the per slice training stage.

[0113] Return to step 2 and step 3, and initially time-shift the read PAR data signal returned from each PAR pin by the first delay parameter determined in step 4 to obtain the read PAR data signal after the initial time shift. The read PAR training unit determines whether the first high level of each read PAR data signal after the initial time shift is aligned. If the first high level of at least one read PAR data signal after the initial time shift is not aligned with the first high level of other read PAR data signals after the initial time shift, the read PAR path delay control circuit adjusts the delay of the PAR path corresponding to the at least one read PAR data signal, and returns to step 2 and step 3, and after receiving each read PAR data signal, time-shifts the corresponding read PAR data signal by the determined first delay parameter and delay, and time-shifts the other read PAR data signals by the determined first delay parameter, and determines whether the first high level of each time-shifted PAR data signal is aligned. If the first high level of at least one time-shifted read PAR data signal is not aligned with the first high level of the other time-shifted read PAR data signals, the read PAR path delay control circuit adjusts the delay of the PAR path corresponding to the at least one read PAR data signal until the first high levels of each time-shifted PAR data signal are aligned, and then returns to step 2 and step 3, and determines the delay determined at this stage for each time-shifted read PAR data signal when they are aligned as a second delay parameter.

[0114] For example, after receiving the initial time-shifted read PAR data signal from the delay circuit of each PAR pin in this step, sample each initial time-shifted read PAR data signal with a sampling pulse to obtain each sampling data, and determine that the first high level of each initial time-shifted read PAR data signal is aligned if the first "1" data bit of each sampling data is the same. If the first "1" data bit of at least one sampling data is different from the first "1" data bit of other sampling data (as shown in FIG. 16B), determine that the first high level of at least one initial time-shifted read PAR data signal is not aligned with the first high level of other initial time-shifted read PAR data signals, and adjust the delay of the PAR path corresponding to the at least one read PAR data signal by the read PAR path delay control circuit until the first high levels of each time-shifted read PAR data signal are aligned (as shown in FIG. 16C), and return to step 2 and step 3, and determine the delay determined in this step of each time-shifted read PAR data signal when aligned as the second delay parameter.

[0115] According to the above memory checkpin processing method, the following technical effects can be achieved.

[0116] 1. Before the initial operation of the bring up of the HBM chip, the mechanism of the present application can be used to train the read PAR pin, so that if a sampling error occurs in the read PAR channel of the chip due to back-end timing non-convergence and HBM chip production failure during the initial operation of the HBM chip, the accuracy of the PAR data returned from the HBM DRAM during the initial operation of the chip can be guaranteed, and no error occurs in the process of the HBM Host checking the read data.

[0117] 2. If the HBM chip detects significant drift in process, voltage and temperature (PVT), the chip can be configured by software to train the read PAR pin, ensuring that the PVT drift will not cause data transmission errors on the chip's read PAR channel.

[0118] 3. The periodic read PAR training mechanism included in the hardware can be used to periodically train the read PAR of the HBM chip, which ensures that no read PAR sampling miss occurs during the operation of the chip.

[0119] 4. This application supports one-step read PAR training set by software, so that the read PAR training of the whole chip can be set by software alone. The software can perform this operation when the system is not busy, so that it can ensure that no sampling miss occurs on the read PAR pins and ensure the efficiency of the whole system.

[0120] It should be understood that although each step in the flowcharts according to the above embodiments is shown in sequence according to the direction of the arrows, these steps are not necessarily performed in sequence according to the order shown by the arrows. Unless expressly described in this specification, there is no strict restriction on the order of execution of these steps. These steps may be performed in other orders. In addition, at least some of the steps in the flowcharts according to the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, and may be performed at different times. The order of execution of these steps or stages is also not necessarily performed sequentially, and may be performed in place of or in alternation with other steps, or at least some of the steps or stages in other steps.

[0121] Based on the same inventive concept, the embodiments of the present application further provide a memory check pin processing device for implementing the memory check pin processing method according to the above. The implementation configuration for solving the problem provided by this device is similar to the implementation configuration described in the above method, so that the specific limitations of the embodiments of one or more memory check pin processing devices provided below can be referred to the limitations of the memory check pin processing method described above, and further description will be omitted here.

[0122] In one embodiment, as shown in Figure 18, a memory check pin processing apparatus is provided. The apparatus includes a command sending module 1802, a signal receiving module 1804, a signal time shifting module 1806, and a delay determining module 1808, where: The command sending module 1802 sends a first data read command to the target memory.

[0123] The signal receiving module 1804 receives the first data signal and the sampling pulse signal returned from each check pin of the target memory.

[0124] The signal time shift module 1806 obtains a first delay parameter by time shifting each of the first data signals by a delay circuit so that the target level value in each of the first data signals after the time shift is aligned with the sampling pulse signal, and upon receiving a second data signal returned from each check pin of the target memory, obtains a second delay parameter by time shifting the target data signal in each of the second data signals by a delay circuit so that the target level value in each of the second data signals after the time shift is aligned.

[0125] The delay determination module 1808 determines a sampling delay parameter for the check pin based on the first delay parameter and the second delay parameter.

[0126] In the above embodiment, a first data read command is sent to the target memory, a first data signal and a sampling pulse signal are received from each check pin of the target memory, and a first delay parameter is obtained by time-shifting each of the first data signals by a delay circuit so that the target level value of each of the first data signals after time-shifting is aligned with the sampling pulse signal; when a second data signal is received from each check pin of the target memory, a second delay parameter is obtained by time-shifting each of the target data signals in each of the second data signals by a delay circuit so that the target level value of each of the second data signals after time-shifting is aligned; and a sampling delay parameter of the check pin is determined according to the first delay parameter and the second delay parameter. Thus, after subsequently receiving the data signal returned from each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted with the determined sampling delay parameter so that the parity check signal after time-shifting is aligned with the sampling pulse signal, and the accuracy of sampling the parity check signal according to the sampling pulse signal is ensured.

[0127] In one embodiment, as shown in FIG. 19 , the apparatus further includes a mode setting module 1810, where the mode setting module 1810 sends an operation mode setting command to the target memory, such that the target memory sets the operation mode to the target mode based on the operation mode setting command, and the command sending module 1802 further sends a first data read command to the target memory in the target mode.

[0128] In one embodiment, the mode setting module 1810 further initializes a read command processing circuit of the target memory and sets the operation mode of the read command processing circuit to the target mode based on the operation mode setting command.

[0129] In one embodiment, the first data signal is generated based on target data bits in read data, the read data being data read by the target memory from a register of the target memory based on the first data read command.

[0130] In one embodiment, the signal time shift module 1806 further obtains a first time shift parameter by time shifting each first data signal along a first direction by a delay circuit, such that a rising edge of a target level value in each first data signal after the time shift is aligned with a rising edge of the sampling pulse signal; obtains a second time shift parameter by time shifting each first data signal along a second direction opposite to the first direction by a delay circuit, such that a falling edge of a target level value in each first data signal after the time shift is aligned with a rising edge of the sampling pulse signal; and determines a first delay parameter corresponding to each check pin based on the first time shift parameter and the second time shift parameter.

[0131] In one embodiment, the signal time shift module 1806 further comprises: sampling the first data signal with the sampling pulse signal to obtain first sampling data; time shifting each of the first data signals along a first direction by a delay circuit; obtaining second sampling data by sampling the first data signals time-shifted along the first direction with the sampling pulse signal; determining that when a value of a target data bit in each of the second sampling data is the same as a target value corresponding to the target data bit in the first sampling data, a rising edge of a target level value in each of the first data signals after time shifting is aligned with a rising edge of the sampling pulse signal; and determining a time shift length corresponding to each of the second sampling data as a first time shift parameter.

[0132] In one embodiment, when there is second sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, the signal time shift module 1806 further returns to the step of sending a first data read command to the target memory via the command sending module 1802 until the rising edge of the target level value in each first data signal after the acquired time shift is aligned with the rising edge of the sampling pulse signal, and determines a time shift length corresponding to each second sampling data as a first time shift parameter.

[0133] In one embodiment, the signal time shift module 1806 further comprises: sampling the first data signal with the sampling pulse signal to obtain first sampling data; time shifting each of the first data signals along the second direction by a delay circuit; obtaining third sampling data by sampling the first data signals time-shifted along the second direction with the sampling pulse signal; determining that when the value of the target data bit in each of the third sampling data is the same as the target value corresponding to the target data bit in the first sampling data, the falling edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal; and determining a time shift length corresponding to each of the third sampling data as a second time shift parameter.

[0134] In one embodiment, when there is third sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, the signal time shift module 1806 further returns to the step of sending a first data read command to the target memory via the command sending module 1802 until the falling edge of the target level value in each first data signal after the acquired time shift is aligned with the rising edge of the sampling pulse signal, and determines the time shift length corresponding to each third sampling data as a second time shift parameter.

[0135] In one embodiment, after time-shifting each first data signal by a delay circuit so that the target level value in each first data signal after time-shifting is aligned with the sampling pulse signal, the command sending module 1802 further sends a second data read command to the target memory, and the signal receiving module 1804 further receives the second data signal and the sampling pulse signal returned from each check pin of the target memory.

[0136] In one embodiment, the signal time shift module 1806 further obtains fourth sampling data by sampling each second data signal time-shifted by the first delay parameter with a sampling pulse signal, and determines that the target data signal in the second data signal is not aligned with the target level value in the other second data signals when the target data bits of the target sampling data in each fourth sampling data are different from the target data bits of the other fourth sampling data, and obtains a second delay parameter by time-shifting the target data signal in the second data signal respectively by a delay circuit, so that the target level values ​​in each second data signal after time shifting are aligned.

[0137] Each module of the check pin processing device in the memory may be realized in whole or in part by software, hardware, or a combination thereof. Each module may be embedded in or stand-alone from the processor of the computer device in the form of hardware, or may be stored in the memory of the computer device in the form of software, thereby facilitating the processor to call and execute the operations corresponding to each module.

[0138] In one embodiment, a computer device is provided. The computer device may be a server, and its internal configuration diagram may be as shown in FIG. 20. The computer device includes a processor, a memory, an input / output interface (I / O: Input / Output), and a communication interface. Here, the processor, the memory, and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. Here, the processor of the computer device provides a calculation and control function. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the execution of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is for storing parity check data. The input / output interface of the computer device is for exchanging information between the processor and an external device. The communication interface of the computer device is for communicating with an external terminal via a network connection. When the computer program is executed by the processor, it realizes a check pin processing method for a memory.

[0139] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal configuration diagram may be as shown in FIG. 21. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Here, the processor, the memory, and the input / output interface are connected via a system bus, and the communication interface, the display unit, and the input device are connected to the system bus via the input / output interface. Here, the processor of the computer device provides a calculation and control function. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the execution of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is for exchanging information between the processor and an external device. The communication interface of the computer device is for communicating with an external terminal in a wired or wireless manner, and the wireless manner may be realized by WIFI, a mobile cellular network, a near field communication (NFC), or other technologies. When the computer program is executed by the processor, it realizes the checkpin processing method of the memory. The display unit of the computer device is for forming a visually visible screen, and may be a display screen, a projection device, or a virtual reality imaging device. The display screen may be a liquid crystal display screen or an E-ink display screen. The input device of the computer device may be a touch layer superimposed on the display screen, a button, a trackball, or a touch pad provided on the housing of the computer device, or an external keyboard, touch pad, mouse, etc.

[0140] As will be understood by those skilled in the art, the configurations shown in Figures 20 and 21 are merely block diagrams of some configurations according to the present invention, and do not limit the computer device to which the present invention is applied. A specific computer device may include more or fewer components than those shown, may combine some components, or may have a different arrangement of components.

[0141] In one embodiment, there is further provided a computing device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, performs the steps of each of the method embodiments described above.

[0142] In one embodiment, a computer readable storage medium is provided having a computer program stored thereon which, when executed by a processor, performs the steps in each of the method embodiments described above.

[0143] In one embodiment, a computer program product is provided that includes a computer program which, when executed by a processor, performs the steps of each of the method embodiments described above.

[0144] It should be explained that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to analytical data, stored data, display data, etc.) related to this application are all information and data authorized by the user or fully authorized by each party, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0145] As can be understood by those skilled in the art, all or part of the flow of the method of the above embodiments may be executed by instructing relevant hardware via a computer program. The computer program may be stored in a non-volatile computer-readable storage medium. When the computer program is executed, the flow of each of the above-mentioned method embodiments is executed. Here, any reference to memory, database, or other medium used in each embodiment provided in this application may include at least one of non-volatile and volatile memory. The non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory may include random access memory (RAM), external cache, etc. By way of illustration and not limitation, the RAM may be in many forms, such as, for example, a static random access memory (SRAM) or a dynamic random access memory (DRAM). The database according to the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a distributed database based on a blockchain. The processor according to the embodiments provided herein may be, but is not limited to, a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, and the like.

[0146] The components of the above-mentioned embodiments may be combined in any combination. For the sake of brevity, not all possible combinations of the components of the above-mentioned embodiments are described. However, the combinations of these components should be considered to be within the scope described in this specification unless there is a contradiction.

[0147] The above examples merely show some embodiments of the present application, and the explanations are specific and detailed, but they should not be understood as limitations on the patent scope of the present application. However, those skilled in the art can make some modifications and improvements without departing from the concept of the present application. All of these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of the attached claims.

Claims

1. 1. A method for memory checkpin processing, implemented by a computer device, comprising: sending a first data read command to a target memory; receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; obtaining a first delay parameter by time-shifting each of the first data signals using a delay circuit such that a target level value of each of the first data signals after time shifting is aligned with the sampling pulse signal; receiving a second data signal returned from each of the check pins of the target memory, time-shifting a target data signal in each of the second data signals by the delay circuit so that the target level values ​​in each of the second data signals after time shifting are aligned, thereby obtaining a second delay parameter; determining a sampling delay parameter for the check pin based on the first delay parameter and the second delay parameter. A method comprising:

2. The method further includes sending an operation mode setting command to the target memory, whereby the target memory sets an operation mode to a target mode based on the operation mode setting command; The step of sending a first data read command to a target memory comprises: sending a first data read command to a target memory in the target mode; 2. The method of claim 1 .

3. The step of setting the operation mode to the target mode based on the operation mode setting command includes: initializing a read command processing circuit of the target memory; setting an operation mode of the read command processing circuit to the target mode based on the operation mode setting command.

3. The method of claim 2 .

4. the first data signal is generated based on a target data bit in read data; the read data is data read by the target memory from a register of the target memory based on the first data read command; 2. The method of claim 1 .

5. the step of obtaining a first delay parameter by time-shifting each of the first data signals by a delay circuit such that a target level value of each of the first data signals after time shifting is aligned with the sampling pulse signal, obtaining a first time shift parameter by time-shifting each of the first data signals along a first direction using the delay circuit such that a rising edge of a target level value in each of the first data signals after time shifting is aligned with a rising edge of the sampling pulse signal; obtaining a second time shift parameter by time-shifting each of the first data signals along a second direction by the delay circuit such that a falling edge of a target level value in each of the first data signals after time shifting is aligned with a rising edge of the sampling pulse signal, the first direction and the second direction being opposite directions; determining a first delay parameter corresponding to each of the check pins based on the first time shift parameter and the second time shift parameter; 2. The method of claim 1 .

6. The method further includes the step of sampling the first data signal with the sampling pulse signal to obtain first sampling data; the step of obtaining a first time shift parameter by time-shifting each of the first data signals along a first direction by the delay circuit such that a rising edge of a target level value in each of the first data signals after time shifting is aligned with a rising edge of the sampling pulse signal, time-shifting each of the first data signals along a first direction by the delay circuits; obtaining second sampled data by sampling the first data signal time-shifted along the first direction with the sampling pulse signal; determining that when a value of a target data bit in each of the second sampled data is equal to a target value corresponding to the target data bit in the first sampled data, a rising edge of a target level value in each of the first data signals after time shifting is aligned with a rising edge of the sampling pulse signal; determining a time shift length corresponding to each of the second sampling data as a first time shift parameter; 6. The method of claim 5 .

7. if there is second sampling data whose value of a target data bit is different from the target value corresponding to the target data bit in the first sampling data, returning to the step of sending a first data read command to the target memory until the rising edge of the target level value in each of the first data signals after the acquired time shift is aligned with the rising edge of the sampling pulse signal; determining a time shift length corresponding to each of the second sampling data as a first time shift parameter; 7. The method of claim 6.

8. The method further includes the step of sampling the first data signal with the sampling pulse signal to obtain first sampling data; the step of obtaining a second time shift parameter by time-shifting each of the first data signals along a second direction using the delay circuit such that a falling edge of a target level value in each of the first data signals after time shifting is aligned with a rising edge of the sampling pulse signal, time-shifting each of the first data signals along a second direction by the delay circuits; Sampling the first data signal time-shifted along the second direction with the sampling pulse signal to obtain third sampled data; determining that, if a value of a target data bit in each of the third sampled data is equal to a target value corresponding to the target data bit in the first sampled data, a falling edge of a target level value in each of the first data signals after time shifting is aligned with a rising edge of the sampling pulse signal; determining a time shift length corresponding to each of the third sampling data as a second time shift parameter; 6. The method of claim 5 .

9. if there is a third sampling data whose value of a target data bit is different from the target value corresponding to the target data bit in the first sampling data, returning to the step of sending a first data read command to the target memory until the falling edge of the target level value in each of the first data signals after the acquired time shift is aligned with the rising edge of the sampling pulse signal; determining a time shift length corresponding to each of the third sampling data as a second time shift parameter; 9. The method of claim 8.

10. a delay circuit time-shifts each of the first data signals so that a target level value of each of the first data signals after the time shift is aligned with the sampling pulse signal; sending a second data read command to the target memory; receiving a second data signal and a sampling pulse signal returned from each check pin of the target memory; 2. The method of claim 1 .

11. obtaining fourth sampled data by sampling each of the second data signals time-shifted based on the first delay parameter with the sampling pulse signal; The step of obtaining a second delay parameter by time-shifting a target data signal in each of the second data signals by the delay circuit so that the target level values ​​in each of the second data signals after time shifting are aligned includes: determining that the target data signal in the second data signal is not aligned to the target level value in the other second data signals when the target data bits of the target sample data in each of the fourth sample data are different from the target data bits of the other fourth sample data; and obtaining a second delay parameter by time-shifting each of the target data signals in the second data signal by the delay circuit so that the target level values ​​in each of the second data signals after time shifting are aligned.

11. The method of claim 10.

12. A memory check pin processing device, comprising: a command sending module for sending a first data read command to the target memory; a signal receiving module for receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; a signal time shifting module for obtaining a first delay parameter by time-shifting each of the first data signals by a delay circuit so that a target level value of each of the first data signals after time shifting is aligned with the sampling pulse signal; and, upon receiving a second data signal returned from each of the check pins of the target memory, for obtaining a second delay parameter by time-shifting a target data signal in each of the second data signals by the delay circuit so that a target level value of each of the second data signals after time shifting is aligned; a delay determination module for determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter. An apparatus comprising:

13. A computing device comprising a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the method according to any one of claims 1 to 11.

14. A computer program product causing a computer to carry out the method according to any one of claims 1 to 11.

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