Latch array with mask write functionality - Patents.com

Abstract

A latch array with mask write functionality includes a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs each coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs each coupled to the set of write bit lines; and an array of slave latches, wherein the slave latches in a column of the array include a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs each coupled to the set of write bit lines.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This patent application claims priority to pending U.S. non-provisional application Ser. No. 17 / 574,431, filed Jan. 12, 2022, and assigned to the assignee of this patent application, which is expressly incorporated by reference herein as if fully set forth below and for all applicable purposes.

[0002] Aspects of the present disclosure relate generally to memory circuits, and more particularly to latch arrays with mask write functionality. [Background technology]

[0003] Static random access memories (SRAMs) and dynamic random access memories (DRAMs) are often used in circuits such as integrated circuits (ICs), including system-on-chip (SOC) type ICs. SRAM and DRAM memory circuits typically operate under a relatively high memory voltage domain to ensure that data transfer margins are met. Latch arrays, which also store data, are becoming increasingly popular because they typically operate under a relatively low logic voltage domain, which makes them much more power efficient than SRAMs and DRAMs. Thus, there has been a move to replace or substitute SRAMs and DRAMs with latch arrays in the design of circuits such as ICs and SoCs. Summary of the Invention

[0004] SUMMARY OF THE DISCLOSURE The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005] One aspect of the disclosure relates to a latch array including a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs each coupled to a set of bit lines, a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs each coupled to the set of write bit lines, and an array of slave latches arranged in columns and rows, where the slave latches in a column of the array include a second set of data inputs coupled to the set of bit lines and a second set of write bit inputs each coupled to the set of write bit lines.

[0006] Another aspect of the disclosure relates to a method that includes providing a deasserted write bit signal to a target slave latch in a set of slave latches, providing a first set of data signals to the set of slave latches, respectively, providing a first slave clock to the set of slave latches to write data to one or more of the set of slave latches based on one or more of the first set of data signals, respectively, and operating the target slave latch to retain previously stored data in response to the deasserted write bit signal while the slave clock causes the respective writing of data to one or more of the set of slave latches based on the one or more of the first set of data signals.

[0007] Another aspect of the disclosure relates to an apparatus including means for providing a deasserted write bit signal to a target slave latch in a set of slave latches, means for providing a first set of data signals to the set of slave latches, respectively, means for providing a first slave clock to the set of slave latches to write data to one or more of the set of slave latches based on one or more of the first set of data signals, respectively, and means for operating the target slave latch to retain previously stored data in response to the deasserted write bit signal while the first slave clock causes the writing of data to one or more of the set of slave latches based on one or more of the first set of data signals, respectively.

[0008] Another aspect of the disclosure relates to a wireless communication device, the wireless communication device including at least one antenna, a transceiver coupled to the at least one antenna, one or more signal processing cores coupled to the transceiver, a latch array coupled to the one or more signal processing cores, the latch array including a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data respectively, and a first set of data outputs respectively coupled to a set of bit lines, a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to the set of write bit lines, and an array of slave latches arranged in columns and rows, the slave latches in a column of the array including a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines.

[0009] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed, and the described implementations are intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0010] [Figure 1A] 1 shows a block / schematic diagram of an exemplary memory circuit according to one embodiment of the present disclosure. [Figure 1B] 1B illustrates a bit diagram of exemplary data stored in the memory circuit of FIG. 1A according to one embodiment of the disclosure. [Figure 1C] 1B illustrates a flow diagram of an exemplary method for writing data to the memory circuit of FIG. 1A, according to one embodiment of the present disclosure. [Figure 2A] FIG. 2 shows a block / schematic diagram of an exemplary memory circuit having mask write functionality, according to one aspect of the present disclosure. [Figure 2B] 2B shows a flow diagram of an exemplary method for writing data to the memory circuit of FIG. 2A according to one embodiment of the disclosure. [Diagram 3] 1 illustrates a block / schematic diagram of an exemplary latch array according to one aspect of the disclosure. [Figure 4A] FIG. 1 illustrates a block / schematic diagram of an exemplary latch array with mask write functionality, according to one aspect of the present disclosure. [Figure 4B] 4B illustrates a timing diagram of an exemplary data write and write mask operation performed by the latch array of FIG. 4A according to another aspect of the disclosure. [Diagram 5] FIG. 2 illustrates a schematic diagram of an exemplary slave latch according to another aspect of the disclosure. [Figure 6] 1 shows a schematic diagram of another exemplary slave latch according to another aspect of the present disclosure. [Figure 7] 1 illustrates a schematic diagram of yet another exemplary slave latch in accordance with an aspect of the present disclosure. [Figure 8] FIG. 1 illustrates a flow diagram of an exemplary method for writing and masking data to a latch array, according to one aspect of the present disclosure. [Figure 9] 1 illustrates a block diagram of an exemplary wireless communication device according to another aspect of the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The detailed description of the present invention, described below in conjunction with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0012] 1A illustrates a block / schematic diagram of an exemplary memory circuit 100 according to one embodiment of the present disclosure. Memory circuit 100 may be a static random access memory (SRAM) type or a dynamic random access memory (DRAM) type memory circuit.

[0013] In particular, memory circuit 100 includes a two-dimensional array of memory cells C00 through C75. In this embodiment, the size of the array is eight rows and six columns (e.g., an 8×6 memory array). However, it should be understood that the size of the memory array, including the number of rows and columns, may vary depending on the application. Memory cells C00 through C05 through C70 through C75 are common to rows 0 through 7, respectively. Memory cells C00 through C70 through C05 through C75 are common to columns 0 through 5, respectively. As discussed, each of memory cells C00 through C75 may be implemented as an SRAM cell or a DRAM cell.

[0014] The memory circuit 100 further includes a word line (WL) decoder 110, a write driver 120, a sense amplifier 130, and a memory buffer 140. The WL decoder 110 includes a first input configured to receive a write enable (we) signal, a second input configured to receive a read enable (re) signal, and a third input configured to receive an address (ADDR). The WL decoder 110 includes a set of outputs that are respectively coupled to a set of word lines (e.g., metallization traces) WL0 through WL7. The set of word lines WL0 through WL7 are in turn respectively coupled to rows of cells C00-C05 through C70-C75.

[0015] The write driver 120 includes an input configured to receive a write enable (we) signal and a set of data inputs configured to receive a set of data D0 through D5, respectively. The write driver 120 is coupled to a set of complementary bit lines (BL) (e.g., metallization traces).

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[0016] The sense amplifier 130 (which may also be referred to as a memory read circuit) includes an input configured to receive a read enable (re) signal. The sense amplifier 130 is connected to the complementary bit line

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[0017] FIG. 1B illustrates a bit diagram of exemplary data stored in memory circuit 100 according to another embodiment of the disclosure. The horizontal axis of the bit diagram identifies columns 0-5 of the memory cells. The vertical axis of the bit diagram identifies rows 0-7 of the memory cells. The array of boxes below and to the right of the column and row identifiers indicate the data in memory cells C00-C75. For example, a first row of cells C00-C05 stores data 1, 0, 1, 0, 1, and 0, respectively. A second row of cells C10-C15 stores data 0, 1, 0, 1, 0, and 1, respectively, and so on in a similar manner. In this example, a write operation of memory circuit 100 focuses on cells C50-C55 in a sixth row coupled to word line WL5. The data stored in these cells C50-C55 are 0, 1, 0, 1, 0, 1, respectively.

[0018] 1C illustrates a flow diagram of an exemplary method 150 for writing data to the memory circuit 100, according to one embodiment of the present disclosure. According to the method 150, data or a word stored in the fifth row of cells C50-C55 is first transferred to the memory buffer 140 (block 160). In this regard, an address provided to the WL decoder 110 points to the sixth row of cells C10-C15, and in response to the read enable (re) signal being asserted, the WL decoder 110 generates an asserted select signal on the word line WL5 (as well as deasserted select signals on the word lines WL0-WL4 and WL6-7). The asserted select signal on the word line WL5 selects the memory cells C50-C55 for data read purposes. Furthermore, in response to the read enable (re) being asserted, the sense amplifier 130 selects the complementary bit lines C50-C55 from the complementary bit lines C10-C15.

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[0019] Further, according to the data write method 150, one or more of the data bits D0-D5 in the memory buffer 140 are modified (block 170). As shown in FIG. 1B, the bits shown in the darker shaded boxes are the modified bits and the bits in the lighter shaded boxes are the unmodified bits. Thus, the data write method 150 includes modifying the word stored in the memory buffer 140 to change the data 1, 1, 0 stored in the memory cells C51, C53, and C54, respectively. Although not explicitly shown, the set of data outputs of the memory buffer 140 are coupled to the set of data inputs D0-D5 of the write driver 120, respectively.

[0020] Next, the modified word in the memory buffer 140 is re-written (block 180) to the memory cells C50-C55, respectively, according to the data write method 150. In this regard, the address provided to the WL decoder 110 again points to the fifth row of memory cells C50-C55 (e.g., the target memory cells of the write operation). Next, the write enable (we) signal is asserted. In response to the asserted write enable (we) signal, the WL decoder 110 generates an asserted select signal on the word line WL5 coupled to the target memory cells C50-C55 (and generates deasserted select signals on the word lines WL0-WL4 and WL6-WL7 coupled to the non-target memory cells C00-C45 and memory cells C60-C75). The asserted select signal on the word line WL5 selects the target memory cells C50-C55 for data write purposes.

[0021] In response to a write enable (we) signal, the write driver 120 also writes the complementary bit lines D0 to D5 based on the data D0 to D5 received from the memory buffer 140.

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[0022] There are several drawbacks associated with memory circuit 100. As described, a write operation of memory circuit 100 generally involves three major operations: transferring a word (where one or more bits need to be overwritten) from a memory cell column to memory buffer 140, block 160, modifying one or more bits of the word stored in memory buffer 140, block 170, and writing the modified word back to the memory cell column, block 180. Thus, data write method 150 involves significant latency due to the three required operations. This is true even if some of the bits of the word do not need to be modified, such as the bits stored in memory cells C50, C52, and C54 (lighter shaded boxes).

[0023] 2A illustrates a block / schematic diagram of an exemplary memory circuit 200 having masked write functionality, according to one aspect of the disclosure. As discussed above, memory circuit 200 uses masked write functionality to enable data writing in a single operation, as opposed to the three operations previously described with respect to memory circuit 200. As described in more detail below, the masked write functionality substantially isolates one or more non-targeted memory cells of a word from data operations of one or more targeted memory cells of the same word.

[0024] More specifically, memory circuit 200 is similar to memory circuit 100. Memory circuit 200 includes a two-dimensional array of memory cells C00-C75, a WL decoder 210, a write driver 220, and may also include sense amplifiers and memory buffers, which are not shown in FIG. 2A for simplicity. Similarly, the array of memory cells C00-C75 is arranged into eight rows C00-C05 to C70-C75, and six columns C00-C70 to C05-C75 (e.g., an 8×6 memory array). Each of memory cells C00-C75 may be an SRAM memory cell or a DRAM memory cell.

[0025] Similarly, the WL decoder 210 includes a first input for receiving a write enable (we) signal, a second input for receiving an address (ADDR) identifying a row of memory cells including one or more cells to which data is to be written, and a set of outputs coupled to the word lines WL0-WL7, respectively. As previously mentioned, the set of word lines WL0-WL7 are coupled to the rows of cells C00-C05 through C70-C75, respectively. Similarly, the write driver 220 includes an input configured to receive a write enable (we) signal, a set of data inputs configured to receive a set of data D0-D5, and complementary bit lines WL0-WL7.

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[0026] Memory circuit 200 differs from memory circuit 100 in that write driver 220 further includes masked write functionality. In this regard, write driver 220 further includes another set of inputs configured to receive a set of write bit signals WB0 through WB5 that specify the bits of the identified word to be written (or an inference of which bits, if any, of the selected word should be masked from the data write operation).

[0027] For example, if memory circuit 200 is an SRAM memory circuit, when writing data "1" to an SRAM cell, write driver 220 may drive complementary bit lines

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[0028] 2B illustrates a flow diagram of an exemplary method 250 for writing data to the memory circuit 200 according to one embodiment of the disclosure. According to the method 250, in response to a write bit signal identifying bits to be masked from a write operation, such as bits stored in memory cells C50, C52, and C55 of the memory data embodiment illustrated in FIG. 1B, and in response to an asserted write enable signal (we), the write driver 220 generates 1 / 1 or floats (block 260) the bit lines coupled to the memory cells C50, C52, and C55 for which the data write operation is to be masked. The write driver 220 also generates appropriate signals on the bit lines coupled to the memory cells C51, C53, and C54 to which data is to be written.

[0029] At the same time, an address is provided to the WL decoder 210, which, as explained, points to the target memory cells C50-C55. In response to the asserted write enable (we) signal, the WL decoder 210 generates an asserted select signal on word line WL5 coupled to the target memory cells C50-C55 (and deasserted select signals on word lines WL0-WL4 and word lines WL6-WL7 coupled to the non-target memory cells C00-C45 and memory cells C60-C75).

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[0030] Also at the same time, according to method 250, in response to a write enable (we) signal, write driver 220 writes complementary bit lines D1, D3, and D4 based on new data D1, D3, and D4 and write bits WB0, WB2, and WB5.

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[0031] FIG. 3 illustrates a block / schematic diagram of an exemplary latch array 300 according to one embodiment of the present disclosure. A latch array is another type of memory circuit that uses latches to store data, as opposed to SRAM and DRAM memory cells. Latch arrays used in integrated circuits (ICs), such as systems-on-chips (SOCs), are becoming more common due to their relatively low power consumption compared to that of SRAM or DRAM memory circuits. Generally, this is because the voltage domain (MX) associated with SRAM and DRAM memory circuits is much higher than the voltage domain (CX) used in logic circuits. When a latch array is built with logic circuits, the latch array may use a lower logic voltage domain (CX) due to consuming less power compared to SRAM or DRAM memory circuits on the MX voltage domain.

[0032] In particular, latch array 300 includes a set of clock gating circuits (CGCs) 310-0 through 310-3, a set of master latches 320-0 through 320-3, a two-dimensional array of slave latches 330-00 through 330-33, and a set of multiplexers 340-0 through 340-3. In this embodiment, the array of slave latches is arranged in four (4) rows (4) of slave latches 330-00 through 330-03 through 330-30 through 330-33, and four (4) columns (4) of slave latches 330-00 through 330-30 through 330-03 through 330-33 (e.g., a 4×4 latch array). Similarly, it should be understood that the size and dimensions of latch array 300 may vary depending on the particular application in which it is used.

[0033] The set of clock gating circuits (CGCs) 310-0 to 310-3 each includes a set of clock inputs configured to receive a master clock (clk). The set of clock gating circuits (CGCs) 310-0 to 310-3 further includes a set of enable inputs configured to receive a write address (WADDR) that may include a write enable (we) signal. In this embodiment, the write address is two bits long to uniquely address each of the set of clock gating circuits (CGCs) 310-0 to 310-3. The set of clock gating circuits 310-0 to 310-3 further includes a set of slave clock outputs (SCLK) respectively coupled to the set of word lines WL0 to WL3. The set of word lines WL0 to WL3 are respectively coupled to the set of clock inputs of the rows of slave latches 330-00 to 330-03 to 330-30 to 330-33.

[0034] The set of master latches 320-0 to 320-3 includes a set of clock inputs configured to receive a master clock clk. Additionally, the set of master latches 320-0 to 320-3 each includes a set of data inputs (d) configured to receive a set of data D0 to D3. Additionally, the set of master latches 320-0 to 320-3 each includes a set of data outputs (q) coupled to a set of bit lines BL0 to BL3, respectively. The set of bit lines BL0 to BL3 are coupled to the set of data inputs (d) of the columns of slave latches 330-00 to 330-30 to 330-03 to 330-33, respectively.

[0035] Each of the sets of multiplexers 340-0 through 340-3 includes a set of data inputs that are respectively coupled to the set of data outputs (q) of each of the columns of slave latches 330-00 through 330-30 through 330-03 through 330-33. For clarity, multiplexer 340-0 includes a set of data inputs that are respectively coupled to the set of data outputs (q) of slave latches 330-00 through 330-30 in column "0". Multiplexer 340-1 includes a set of data inputs that are respectively coupled to the set of data outputs (q) of slave latches 330-01 through 330-31 in column "1". Multiplexer 340-2 includes a set of data inputs coupled to the set of data outputs (q) of slave latches 330-02 to 330-32 in column "2", respectively, and multiplexer 340-3 includes a set of data inputs coupled to the set of data outputs (q) of slave latches 330-03 to 330-33 in column "3", respectively. The set of multiplexers 340-0 to 340-3 further includes a set of select inputs configured to receive a read address (RADDR). Additionally, the set of multiplexers 340-0 to 340-3 includes a set of data outputs configured to generate output signals or read data Q0 to Q3, respectively.

[0036] A write operation of latch array 300 may be as follows: A write address pointing to the row of slave latches to which data is to be written is provided to the set of clock gating circuits (CGCs) 310-0 through 310-3. In this particular embodiment, the write address points to the third row of slave latches 330-20 through 330-23. Also, new data D0-D3 to be written to the third row of slave latches 330-20 through 330-23 is provided to the set of data inputs of the set of master latches 320-0 through 320-3, respectively.

[0037] In response to the high phase of the master clock clk, the set of master latches 320-0 through 320-3 become opaque and new data D0 through D3 are provided to the set of bit lines BL0 through BL3, respectively. Additionally, in response to the write enable (we) being asserted and a write address pointing to the third row of slave latches 330-20 through 330-23, the clock gating circuit (CGC) 310-2 generates a slave clock sclk that is provided to the row of slave latches 330-20 through 330-23 via word line WL2. Because the other clock gating circuits (CGCs) 310-0, 310-1, and 310-3 are not addressed in this data write embodiment, these clock gating circuits (CGCs) 310-0, 310-1, and 310-3 do not generate the slave clock sclk on word lines WL0, WL1, and WL3, respectively.

[0038] The slave clock sclk may be substantially 180° out of phase with the master clock clk. Thus, in response to a low phase of the slave clock sclk, the row of slave latches 330-20 through 330-23 become transparent to accept new data D0 through D3 on the set of bit lines BL0 through BL3, respectively. The next high phase of the slave clock sclk places the row of slave latches 330-20 through 330-23 in an opaque state to hold or store the data D0 through D3, respectively. The next low phase of the master clock clk also places the set of master latches 320-0 through 320-3 in a transparent state to accept the next new data D0 through D3, respectively.

[0039] The read operation of latch array 300 is straightforward: a read address causes the set of multiplexers 340-0 to 340-3 to output data stored in the row of slave latches identified by the read address. For example, if data stored in the third row of slave latches 330-20 to 330-23 is to be read, the read address causes the set of multiplexers 340-0 to 340-3, respectively, to select the second input from the left. These inputs of the set of multiplexers 340-0 to 340-3 are coupled to the set of data outputs (q) of the third row of slave latches 330-20 to 330-23, respectively. Thus, the data stored in the third row of slave latches 330-20 to 330-23 is produced at the output data Q0 to Q3, respectively, at the set of outputs of the set of multiplexers 340-0 to 340-3.

[0040] As described, the latch array 300 is generally more power efficient than SRAM or DRAM memory circuits, but the latch array 300 does not have a mask write functionality. That is, according to the data write operation described above, all of the slave latches belonging to a row or word line are overwritten with new data D0 to D3 even if some of the data does not need to be overwritten. For example, assuming that the data stored in the slave latches 330-21 and 330-22 are overwritten with new data D1 and D2, and the data stored in the slave latches 330-20 and 330-23 need to remain the same, the write operation of the latch array 330 still requires that the same data D0 and D3 are provided to the slave latches 330-20 and 330-23, respectively. In some situations, the application using the latch array 300 may not know the value of the data that will not be overwritten. Therefore, in such cases, it is desirable to provide the latch array with a mask write functionality.

[0041] 4A illustrates a block / schematic diagram of an exemplary latch array 400 with mask write functionality, according to one embodiment of the disclosure. In summary, the latch array 400 is reconfigured to provide mask write functionality, as described in more detail below. Similar to the latch array 300, the latch array 400 is a 4×4 latch array, however, it should be understood that the latch array 400 may be implemented to have a different size, and the number of rows may differ from the number of columns.

[0042] Latch array 400 is similar to latch array 300 in that the latch array 400 includes a set of clock gating circuits (CGCs) 410-0 through 410-3 (a set of clock input portions configured to receive a master clock clk, a set of input portions configured to receive a write address / write enable (we) signal, and a set of slave clock output portions (SCLK) respectively connected to a set of word lines WL0 through WL3), a first set of master-slave latches 420-0 through 420-3 (a set of clock input portions configured to receive the master clock clk, a set of data input portions (d) configured to receive data D0 through D3 written to the latch array 400, and a set of data output portions (q) respectively connected to a set of bit lines BL0 through BL3), and a two-dimensional array of slave latches 430-00 through 430-33, where rows of the slave latches 430-00 through 430-03 through 430-30 through 430-33 include a set of slave clock input portions connected to the set of word lines WL0 through WL3, the set of data outputs (q) are connected to a set of data input portions of a set of multiplexers 440-0 through 440-3, and columns of the slave latches 430-00 through 430-30 through 430-03 through 430-33 include a set of data input portions (d) respectively connected to the set of bit lines BL0 through BL3).

[0043] For mask write functionality, the latch array 400 further includes a second set of master latches 450-0 through 450-3. The second set of master latches 450-0 through 450-3 each include a set of clock inputs configured to receive a master clock clk. The second set of master latches 450-0 through 450-3 each include a set of write bit inputs (d) configured to receive a set of write bit signals wb0 through wb3. The second set of master latches 450-0 through 450-3 each include a set of write bit outputs (q) coupled to a set of write bit lines WB0 through WB3, respectively. The column of slave latches 430-00 through 430-30 through 430-03 through 430-33 each include a set of write bit inputs (wbt) coupled to a set of write bit lines WB0 through WB3, respectively. It should be understood that in some implementations, the first set of master latches 420-0 to 420-3 and the second set of master latches 450-0 to 450-3 may be the same or different. A mask write operation of latch array 400 is described below with reference to FIG. 4B.

[0044] 4B illustrates a timing diagram of an exemplary masked write operation performed by latch array 400 on a target slave latch according to another aspect of the disclosure. The horizontal axis of the timing diagram represents time. The time axis is divided into two write periods #1 and #2. The vertical axis represents, from top to bottom, the master clock (clk), the write enable signal (we), the data signal (d), the write bit signal (wbt), and the complementary write bit signal (wbt).

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[0045] According to the first write cycle #1, the write bit signal (wbt) is asserted with a high logic voltage (1), which means that data is written to the target slave latch (or, by corollary, the target slave latch is not masked). As shown, at time t 1 Prior to a rising edge of the master clock (clk) at time t1, a write enable signal (we) is asserted, a data signal (d) is present at the input of a corresponding master latch in the first set, and a write bit signal (wbt) is present at the input of a corresponding master latch in the second set. In response to a rising edge of the master clock (clk) at time t1, the corresponding master latch in the first set transfers the data signal (d) onto the corresponding bit line, and the corresponding master latch in the second set transfers the complementary write bit signal (wbt) (as the master latch in the second set may invert the write bit signal (wbt)).

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[0046] As described in further greater detail herein with reference to various exemplary slave latch implementations, complementary slave clocks

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[0047] According to the second write cycle #2, the write bit signal (wbt) is deasserted with a low logic voltage (0), meaning that the target slave latch is masked and will not accept the "don't care" data signal (d) on the corresponding bit line. As shown, at time t 5 Prior to a rising edge of the master clock at time t5, a write enable signal (we) is asserted, a "don't care" data signal (d) is present at the input of a corresponding master latch in the first set, and a write bit signal (wbt) is present at the input of a corresponding master latch in the second set. In response to a rising edge of the master clock (clk) at time t5, the corresponding master latch in the first set transfers the "don't care" data signal (d) onto the corresponding bit line, and the corresponding master latch in the second set transfers the complementary write bit signal (wbt)

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[0048] 5 illustrates a schematic diagram of an exemplary slave latch 500 according to another aspect of the disclosure. Slave latch 500 may be an implementation of any of slave latches 430-00 to 430-33 of latch array 400. In summary, slave latch 500 asserts a slave clock CLK in response to write bit signal wbt being deasserted (meaning a write mask is applied to slave latch 500).

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[0049] The clock gating circuit 530 is configured to clock the write bit signal wbt when it is asserted (e.g., a logical one (1)) (or when the complementary write bit signal

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[0050] More specifically, the clock gating circuit 530 generates a complementary write bit signal

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[0051] If the slave latch 500 is transparent, the data gating circuit 510 is configured to transmit a data signal (d) received via a corresponding bit line to an output of the data gating circuit 510 (and an input of the data latch circuit 520). If the slave latch 500 is opaque, the data gating circuit 510 is configured to gate the data signal (d).

[0052] More specifically, the data gating circuit 510 includes a first field effect transistor (FET) M1, a second FET M2, a third FET M3, and a fourth FET M4 coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). The first FET M1 and the second FET M2 may be implemented as p-channel metal oxide semiconductor field effect transistors (PMOS FETs). The third FET M3 and the fourth FET M4 may be implemented as n-channel metal oxide semiconductor field effect transistors (NMOS FETs). The gates of the first FET M1 and the fourth FET M4 are coupled together and to corresponding bit lines for receiving a data signal (d). The gates of the second FET M2 and the third FET M3 are coupled to the output of an inverter 534 and a NOR gate 532 to provide an internal complementary slave clock.

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[0053] If the slave latch 500 is transparent, the data latch circuit 520 is open to receive a data signal (d) from the output of the data gating circuit 510. If the slave latch 500 is opaque, the data latch circuit 520 is closed to hold the received data (d).

[0054] More specifically, the data latch circuit 520 includes a fifth FET M5, a sixth FET M6, a seventh FET M7, and an eighth FET M8 coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss. The fifth FET M5 and the sixth FET M6 may be implemented as PMOS FETs. The seventh FET M7 and the eighth FET M8 may be implemented as NMOS FETs. The input of the data latch circuit 520 is at the node between the FETs M6 and M7 (e.g., their drains), which is the same node as the output of the data gating circuit 510. The gates of the FETs M5 and M8 are both coupled to the data output (q) of the slave latch 500, which is coupled to the input of a corresponding multiplexer (e.g., one of the multiplexers 440-0 to 440-3). The gates of FET M6 and FET M7 are coupled to the outputs of NOR gate 532 and inverter 534 to generate the internal non-complementary slave clock sclk, respectively. i and internal complementary slave clock

number

[0055] In operation, when data is to be written to the slave latch 500 (the slave latch is transparent), the complementary write bit signal

number

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[0056] Data should be retained by slave latch 500 (slave latch is opaque) under two conditions: (1) complementary slave clock

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number

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[0057] 6 illustrates a schematic diagram of an exemplary slave latch 600 according to another aspect of the disclosure. Slave latch 600 may be an implementation of any of slave latches 430-00 to 430-33 of latch array 400. In summary, slave latch 600 gates data signal (d) in response to write bit signal wbt being deasserted (meaning a write mask is applied to slave latch 600), and otherwise data signal (d) is gated by the slave clock

number

[0058] The signal buffer circuit 630 buffers the complementary slave clock received via the corresponding word line.

number

number

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[0059] More specifically, the signal buffer circuit 630 outputs a complementary write bit signal

number

number

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[0060] If the slave latch 600 is transparent, the data gating circuit 610 is configured to transmit a data signal (d) received via a corresponding bit line to an output of the data gating circuit 610 (and an input of the data latch circuit 620). If the slave latch 600 is opaque, the data gating circuit 610 is configured to gate the data signal (d).

[0061] More specifically, the data gating circuit 610 includes a first FET M1, a second FET M2, a ninth FET M9, a tenth FET M10, a third FET M3, and a fourth FET M4 coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). The first FET M1, the second FET M2, and the ninth FET M9 may be implemented as PMOS FETs. The tenth FET M10, the third FET M3, and the fourth FET M4 may be implemented as NMOS FETs. The gates of the first FET M1 and the fourth FET M4 are coupled together and to corresponding bit lines for receiving a data signal (d). The gates of the second FET M2 and the third FET M3 are coupled to the outputs of inverters 638 and 634 to provide an internal complementary slave clock.

number

number

[0062] When the slave latch 600 is transmissive, the data latch circuit 620 is open to receive a data signal (d) from the output of the data gating circuit 610. When the slave latch 600 is opaque, the data latch circuit 620 is closed to hold the data (q).

[0063] More specifically, the data latch circuit 620 includes a fifth FET M5, a first pair of parallel FETs M6, a second pair of parallel FETs M7, and an eighth FET M8 coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss. The fifth FET M5 and the first pair of parallel FETs M6 may be implemented as PMOS FETs. The second pair of parallel FETs M7 and the eighth FET M8 may be implemented as NMOS FETs. The input of the data latch circuit 620 is at the node between the first and second pairs of FETs M6 and M7 (e.g., their drains), which is the same node as the output of the data gating circuit 610. The gates of the FETs M5 and M8 are both coupled to the data output (q) of the slave latch 600, which is coupled to the input of a corresponding multiplexer (e.g., one of the multiplexers 440-0 to 440-3). A first set of gates of the pair of FETs M6 and M7 are coupled to the outputs of inverters 634 and 638, respectively, to generate the internal non-complementary slave clock sclk. i and internal complementary slave clock

number

number

[0064] In operation, when data is to be written to the slave latch 600 (the slave latch is transparent), the complementary write bit signal

number

number

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[0065] Data should be retained by slave latch 600 (slave latch is opaque) under two conditions: (1) complementary slave clock

number

[0066]

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[0067] 7 shows a schematic diagram of an exemplary slave latch 700 according to another aspect of the disclosure. Slave latch 700 may be an implementation of any of slave latches 430-00 to 430-33 of latch array 400. In summary, slave latch 600 feeds back the data (q) held by the slave latch in response to write bit signal wbt being deasserted (meaning a write mask is applied to slave latch 700), otherwise the data signal (d) is fed back in response to the slave clock

number

[0068] The signal buffer circuit 740 buffers the complementary slave clock received via the corresponding word line.

number

number

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[0069] More specifically, the signal buffer circuit 740 outputs a complementary write bit signal

number

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[0070] When the write bit signal wbt is asserted, the multiplexer 710 passes the data signal (d) to the input of the data gating circuit 720, and when the write bit signal wbt is deasserted, the multiplexer 710 passes the output data signal (q) (the data previously stored in the slave latch 700) to the input of the data gating circuit 720.

[0071] More specifically, multiplexer 710 includes a first transmission (pass) gate M9 and a second transmission (pass) gate M10. The first transmission gate M9 includes an input terminal coupled to a corresponding bit line for receiving a data signal (d). The first transmission gate M9 also receives an internal non-complementary write bit signal wbt i and the complementary write bit signal

number

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[0072] When the slave latch 700 is transparent, the data gating circuit 720 is configured to transmit the data signal (d) or (q) from the multiplexer 710 to the output of the data gating circuit 720 (and to the input of the data latch circuit 730). When the slave latch 700 is opaque, the data gating circuit 720 is configured to gate the data signal (d) or (q).

[0073] More specifically, the data gating circuit 720 includes a first FET M1, a second FET M2, a third FET M3, and a fourth FET M4 coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss (e.g., ground). The first FET M1 and the second FET M2 may be implemented as PMOS FETs. The third FET M3 and the fourth FET M4 may be implemented as NMOS FETs. The gates of the first FET M1 and the fourth FET M4 are coupled together and to the output of the multiplexer 710. The gates of the second FET M2 and the third FET M3 are coupled to the outputs of inverters 748 and 744 to provide an internal complementary slave clock.

number

[0074] If the slave latch 700 is transmissive, the data latch circuit 730 is open to receive a data signal (d) or (q) from the output of the data gating circuit 720. If the slave latch 700 is opaque, the data latch circuit 730 is closed to hold the data (q).

[0075] More specifically, the data latch circuit 730 includes a fifth FET M5, a sixth FET M6, a seventh FET M7, and an eighth FET M8 coupled in series between an upper voltage rail Vdd and a lower voltage rail Vss. The fifth FET M5 and the sixth FET M6 may be implemented as PMOS FETs. The seventh FET M7 and the eighth FET M8 may be implemented as NMOS FETs. The input of the data latch circuit 730 is at the node between the FETs M6 and M7 (e.g., their drains), which is the same node as the output of the data gating circuit 720. The gates of the FETs M5 and M8 are both coupled to the data output (q) of the slave latch 700, which is coupled to an input of a corresponding multiplexer (e.g., one of the multiplexers 440-0 to 440-3) and to an input terminal of the second transmission gate M10 of the multiplexer 710. The gates of FET M6 and FET M7 are coupled to the outputs of inverters 744 and 748, respectively, to generate the internal non-complementary slave clock sclk. i and internal complementary slave clock

number

[0076] In operation, the complementary write bit signal

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[0077] The previously stored data (q) is represented by the complementary write bit signal

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[0078] The data is the complementary slave clock.

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[0079] 8 illustrates a flow diagram of an exemplary method 800 of writing and masking data to a latch array according to one embodiment of the disclosure. The method 800 includes providing a deasserted write bit signal to a target slave latch in the set of slave latches (block 810). An example of a means for providing a deasserted write bit signal to a target slave latch in the set of slave latches includes any one of the second set of master latches 450-00 to 450-3 coupled to one of the slave latches 430-0 to 430-33, respectively, via a corresponding one of the set of write bit lines WB0 to WB3.

[0080] The method 800 further includes providing the first set of data signals, respectively, to the set of slave latches (block 820). An example of the means for providing the first set of data signals, respectively, to the set of slave latches includes a first set of master latches 430-00 through 430-3 coupled to a column of slave latches 420-0 through 430-30 through 420-03 through 430-33, respectively, via a set of bit lines BL0 through BL3. In addition, the method 800 includes providing a first slave clock, respectively, to the set of slave latches for writing data to one or more of the set of slave latches based on one or more of the first set of data signals (block 830). An embodiment of the means for providing a first slave clock to the set of slave latches, respectively, for writing data to one or more of the set of slave latches based on one or more of the first set of data signals includes a corresponding one of the set of clock gating circuits (CGCs) 410-0 to 410-3 coupled to a corresponding one of the rows of slave latches 430-00 to 430-03 to 430-30 to 430-33 via a corresponding one of the set of word lines WL0 to WL3, respectively.

[0081] Note that method 800 includes operating the target slave latch to retain the previously stored data in response to a deasserted write bit signal while the first slave clock is causing the writing of data to one or more of the sets of slave latches, respectively, based on one or more of the first set of data signals (block 840). Examples of means for operating the target slave latch to retain the previously stored data in response to a deasserted write bit signal while the first slave clock is causing the writing of data to one or more of the sets of slave latches, respectively, based on one or more of the first set of data signals include any one of slave latches 500, 600, and 700 described above.

[0082] Operating the target slave latch of method 800 may include gating the first slave clock from being applied to the data gating circuitry and the data latch circuitry in response to the deasserted write bit signal. One embodiment of the means for gating the first slave clock from being applied to the data gating circuitry and the data latch circuitry in response to the deasserted write bit signal includes the clock gating circuitry 530 of the slave latch 500.

[0083] Operating the target slave latch of method 800 may include maintaining the data gating circuit in a gated state and closing the data latch circuit in response to a deasserted write bit signal. One embodiment of the means for maintaining the data gating circuit in a gated state and closing the data latch circuit in response to a deasserted write bit signal includes a pair of FETs M9-M10 of data gating circuit 610 having gates coupled to the outputs of inverters 632 and 636, respectively, and a pair of FETs M6-M7 including gates coupled to the outputs of inverters 636 and 632, respectively.

[0084] Operating the target slave latch of method 800 may include feeding back previously stored data from a data output to a data input of the data latch circuit via a data gating circuit in response to a deasserted write bit signal and a first slave clock. One embodiment of a means for feeding back previously stored data from a data output to a data input of the data latch circuit via a data gating circuit in response to a deasserted write bit signal and a first slave clock includes a data latch circuit 730 having a data output (q) coupled to a data input (q) of a multiplexer 710 responsive to the write bit signal, the multiplexer 710 including a data output coupled to a data input of the data gating circuit 720, the data gating circuit 720 including a data output coupled to a data input of the data latch circuit 730.

[0085] Method 800 may further include providing an asserted write bit signal to a target slave latch. An embodiment of the means for providing an asserted write bit signal to the target slave latch includes any one of the second set of master latches 450-00 through 450-3 each coupled to one of the slave latches 430-0 through 430-33 via a corresponding one of the set of write bit lines WB0 through WB3.

[0086] Method 800 may further include providing a second set of data signals, respectively, to the set of slave latches. An example of the means for providing the second set of data signals, respectively, to the set of slave latches includes a first set of master latches 430-00 through 430-3 coupled to a string of slave latches 420-0 through 430-30 through 420-03 through 430-33, respectively, via a set of bit lines BL0 through BL3. Additionally, method 800 may include providing a second slave clock, respectively, to the set of slave latches for writing data to one or more of the set of slave latches based on one or more of the second set of data signals. An embodiment of the means for providing a second slave clock to the set of slave latches for writing data to one or more of the set of slave latches based on one or more of the second set of data signals, respectively, includes a corresponding one of the sets of clock gating circuits (CGCs) 410-0 to 410-3 coupled to a corresponding one of the rows of slave latches 430-00 to 430-03 to 430-30 to 430-33 via a corresponding one of the sets of word lines WL0 to WL3, respectively.

[0087] Additionally, method 800 may include operating the target slave latch in response to the asserted write bit signal and the second slave clock to store data based on a corresponding one of the second set of data signals. Examples of means for operating the target slave latch in response to the asserted write bit signal and the second slave clock to store data based on a corresponding one of the second set of data signals include any one of slave latches 500, 600, and 700 described above.

[0088] Operating the target slave latch to store data in method 800 may include communicating a second slave clock to the data gating circuit and the data latch circuit in response to an asserted write bit signal. One embodiment of the means for communicating a second slave clock to the data gating circuit and the data latch circuit in response to an asserted write bit signal includes the clock gating circuit 530 of the slave latch 500.

[0089] Operating the target slave latch to store data in method 800 may include setting the data gating circuit to an ungated state and setting the data latch circuit to an open state in response to an asserted write bit signal and a second slave clock. One embodiment of the means for setting the data gating circuit to an ungated state and setting the data latch circuit to an open state in response to an asserted write bit signal and a second slave clock includes FETs M9-M10 of data gating circuit 610 having gates respectively coupled to outputs of inverters 636 and 632, a pair of FETs M6-M7 including gates respectively coupled to outputs of inverters 632 and 636, and FETs M2-M3 of data gating circuit 610 having gates respectively coupled to outputs of inverters 638 and 634, and a pair of FETs M6-M7 including gates respectively coupled to outputs of inverters 634 and 638.

[0090] Operating the target slave latch to store the data of method 800 may include applying a corresponding one of the second set of data signals to a data gating circuit in response to an asserted write bit signal. One embodiment of the means for applying a corresponding one of the second set of data signals to the data gating circuit in response to an asserted write bit signal includes a multiplexer 710 including an input for receiving a data signal (d) and an output coupled to the data gating circuit 720 and responsive to the write bit signal.

[0091] 9 illustrates a block diagram of an exemplary wireless communication device 900 according to another aspect of the present disclosure. The wireless communication device 900 includes at least one antenna 960 (e.g., an antenna array), a transceiver 950 coupled to the at least one antenna 960, and an integrated circuit (IC) or system on chip (SOC) 910. The IC or SOC 910 includes a latch array 920 and one or more signal processing cores 930 coupled to the latch array 920. The latch array 920 may be implemented for each latch array 400 including any one of the slave latches 500, 600, and 700 described above. The one or more signal processing cores 930 are coupled to the transceiver 950.

[0092] According to a signal transmission application, the one or more signal processing cores 930 may generate a transmit baseband (BB) signal based on the data retrieved from the latch array 920. The one or more signal processing cores 930 provide the transmit baseband (BB) signal to a transceiver 950, which then generates a transmit radio frequency (RF) signal based on the transmit baseband (BB) signal. The transmit RF signal is provided to at least one antenna 960 for wireless transmission to one or more remote wireless devices.

[0093] According to a signal receiving application, the at least one antenna 960 is configured to wirelessly receive a received RF signal from one or more remote wireless devices. The transceiver 950 is configured to generate a received baseband (BB) signal in a second voltage domain based on the received RF signal. The one or more signal processing cores 930 may be configured to process the received baseband (BB) signal to generate data. The one or more signal processing cores 930 may store the data in the latch array 920.

[0094] The following provides a summary of aspects of the disclosure.

[0095] Aspect 1: A wireless communication device comprising: a latch array including a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs each coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive a master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs each coupled to the set of write bit lines; and an array of slave latches arranged in columns and rows, wherein the slave latches in a column of the array include a second set of data inputs coupled to the set of bit lines and the second set of write bit inputs each coupled to the set of write bit lines.

[0096] Aspect 2: A latch array as described in aspect 1, further comprising a set of clock gating circuits including a third set of clock inputs configured to receive a master clock and a set of clock outputs coupled to the set of word lines, wherein slave latches in a row of the array include a fourth set of clock inputs each coupled to the set of word lines.

[0097] Aspect 3: The latch array of aspect 2, wherein each slave latch of the array comprises: a clock gating circuit including one of the second set of write bit inputs coupled to one of the set of write bit lines, one of the fourth set of clock inputs coupled to one of the set of word lines, and a complementary clock output; a data gating circuit including one of the second set of data inputs coupled to one of the set of bit lines, a first set of complementary clock inputs each coupled to the complementary clock outputs of the clock gating circuit, and a first data output; and a data latch circuit including the second set of complementary clock inputs each coupled to the complementary clock outputs of the clock gating circuit, a data input coupled to the first data output of the data gating circuit, and a second data output.

[0098] Aspect 4: Each slave latch of the array includes a clock gating circuit including a NOR gate including a first input serving as one of a second set of write bit inputs coupled to one of the set of write bit lines, a second input serving as one of a fourth set of clock inputs coupled to one of the set of word lines, and an output, a first inverter including an input coupled to the output of the NOR gate, and an output, and a data gating circuit including a first field effect transistor (FET) including a first gate serving as one of the second set of data inputs coupled to one of the set of bit lines, a second FET including a second gate coupled to the output of the first inverter, a third FET including a third gate coupled to the output of the NOR gate, and a fourth FET including a fourth gate coupled to the first gate of the first FET, a data gating circuit including a fourth FET, the second FET, the third FET, and the fourth FET being coupled in series between the first voltage rail and the second voltage rail; a data latch circuit including a fifth FET having a fifth gate coupled to an output of the data latch circuit, a sixth FET having a sixth gate coupled to an output of the NOR gate, a seventh FET having a seventh gate coupled to an output of the first inverter, and a fifth gate of the fifth FET. 3. The latch array of embodiment 2 comprising: an eighth FET including an eighth gate coupled to the fifth FET, wherein the fifth FET, the sixth FET, the seventh FET, and the eighth FET are coupled in series between the first voltage rail and the second voltage rail; and a data latch circuit including a second inverter, the second inverter including an input coupled to a node between the sixth FET and the seventh FET and an output coupled to an output of the data latch circuit.

[0099] Aspect 5: The latch array of aspect 4, wherein the first FET, the second FET, the fifth FET, and the sixth FET are each p-channel metal-oxide-semiconductor field effect transistors (PMOS FETs), and the third FET, the fourth FET, the seventh FET, and the eighth FET are each n-channel metal-oxide-semiconductor field effect transistors (NMOS FETs).

[0100] Aspect 6: The latch array of aspect 2, wherein each slave latch of the array includes: a data gating circuit coupled to one of the second set of data inputs coupled to one of the sets of bit lines, one of the fourth set of clock inputs coupled to one of the sets of word lines, and one of the second set of write bit inputs coupled to one of the sets of write bit lines, the data gating circuit including a first data output; and a data latch circuit coupled to one of the fourth set of clock inputs and one of the second set of write bit inputs, the data latch circuit including a data input coupled to the first data output of the data gating circuit and a second data output.

[0101] Aspect 7: Each slave latch of the array is a signal buffer circuit comprising: a first inverter including an input section functioning as one of a fourth set of clock inputs coupled to one of the word lines, and an output section; a second inverter including an input section coupled to the output of the first inverter, and an output section; a third inverter including an input section functioning as one of a second set of write bit inputs coupled to one of the set of write bit lines, and an output section; an input section coupled to the output of the third inverter, and an output section; a fourth inverter; and a signal buffer circuit including a data gating circuit including a first field effect transistor (FET) including a first gate coupled to one of the second set of data inputs coupled to one of the set of bit lines, a second FET including a second gate coupled to an output of the second inverter, a third FET including a third gate coupled to an output of the fourth inverter, a fourth FET including a fourth gate coupled to the output of the third inverter, and a fifth gate coupled to the output of the first inverter. a data gating circuit including a sixth FET, the sixth FET including a sixth gate coupled to the first gate of the first FET, wherein the first FET, the second FET, the third FET, the fourth FET, the fifth FET, and the sixth FET are coupled in series between the first voltage rail and the second voltage rail; and a data latch circuit, the data latch circuit including a seventh gate coupled to an output of the data latch circuit, the seventh FET including a seventh gate coupled to an output of the first inverter and the third inverter, a first pair of column FETs, a second pair of parallel FETs including gates respectively coupled to the outputs of the second inverter and the fourth inverter; an eighth FET including an eighth gate coupled to a seventh gate of the seventh FET, wherein the seventh FET, the first pair of parallel FETs, the second pair of parallel FETs, and the eighth FET are coupled in series between a first voltage rail and a second voltage rail; an input coupled to a node between the first pair of parallel FETs and the second pair of parallel FETs; and an output coupled to the output of the data latch circuit.and a fifth inverter.

[0102] Example 8: The latch array of example 7, wherein the first parallel FET, the second parallel FET, the third parallel FET, the seventh parallel FET, and the first pair of parallel FETs each comprise p-channel metal-oxide-semiconductor field effect transistors (PMOS FETs), and the fourth parallel FET, the fifth parallel FET, the sixth parallel FET, the eighth parallel FET, and the second pair of parallel FETs each comprise n-channel metal-oxide-semiconductor field effect transistors (NMOS FETs).

[0103] Aspect 9: The latch array of aspect 2, wherein each slave latch of the array comprises: a multiplexer including one of the second set of data inputs coupled to one of the set of bit lines, one of the second set of write bit inputs coupled to one of the set of write bit lines, a first data input, and a first data output; a data gating circuit including a second data input coupled to the first data output of the multiplexer, and a second data output, wherein the data gating circuit is coupled to one of the fourth set of clock inputs coupled to one of the set of word lines; and a data latch circuit coupled to one of the fourth set of clock inputs, wherein the data latch circuit includes a third data input coupled to the second data output of the data gating circuit, and a third data output coupled to the first data input of the multiplexer.

[0104] Aspect 10: Each slave latch of the array includes a signal buffer circuit including a first inverter including an input serving as one of a fourth set of clock inputs coupled to one of the word lines and an output, a second inverter including an input coupled to the output of the first inverter and an output, a third inverter including an input serving as one of a second set of write bit inputs coupled to one of the set of write bit lines and an output, and a fourth inverter including an input coupled to the output of the third inverter and an output, and a multiplexer coupled to one of the second set of data inputs coupled to one of the set of bit lines. a first transmission gate including a first terminal coupled to the output of the multiplexer, a first set of complementary gates coupled to the outputs of the third inverter and the fourth inverter, respectively, and a second terminal; a second transmission gate including the third terminal, a second set of complementary gates coupled to the outputs of the third inverter and the fourth inverter, and a fourth terminal coupled to the second terminal to form the output; and a data gating circuit including a first field effect transistor (FET) including a first gate coupled to the output of the multiplexer, a second FET including a second gate coupled to the output of the second inverter, and a third gate coupled to the output of the first inverter.a data gating circuit including a third FET and a fourth FET including a fourth gate coupled to the first gate of the first FET, where the first FET, the second FET, the third FET, and the fourth FET are coupled in series between a first voltage rail and a second voltage rail; a data latch circuit including a fifth FET including a fifth gate coupled to an output of the data latch circuit, a sixth FET including a sixth gate coupled to an output of the first inverter, and a seventh FET including a seventh gate coupled to an output of the second inverter; 3. The latch array of aspect 2 comprising: an eighth FET including an eighth gate coupled to a fifth gate of the first FET, wherein the fifth FET, the sixth FET, the seventh FET, and the eighth FET are coupled in series to a node between the first voltage rail and the second voltage rail; and a data latch circuit comprising: a fifth inverter having an input coupled to a node between the sixth FET and the seventh FET and an output coupled to an output of the data latch circuit, wherein the output of the data latch circuit is coupled to a third terminal of the second transmission gate.

[0105] Example 11: The latch array of example 10, wherein the first FET, the second FET, the fifth FET, and the sixth FET each comprise p-channel metal-oxide-semiconductor field effect transistors (PMOS FETs), and the third FET, the fourth FET, the seventh FET, and the eighth FET each comprise n-channel metal-oxide-semiconductor field effect transistors (NMOS FETs).

[0106] Aspect 12: A latch array according to any one of aspects 2 to 11, wherein the set of clock gating circuits includes a set of enable inputs configured to receive a write address.

[0107] Aspect 13: A latch array as described in any one of aspects 1 to 12, further comprising a set of multiplexers including a set of inputs each coupled to a second set of data outputs of the column of slave latches, a set of selection inputs configured to receive a read address, and a third set of data outputs each configured to generate the second set of data.

[0108] Aspect 14: A method comprising: providing a deasserted write bit signal to a target slave latch among a set of slave latches; providing a first set of data signals to the set of slave latches, respectively; providing a first slave clock to the set of slave latches to write data to one or more of the set of slave latches based on one or more of the first set of data signals, respectively; and operating the target slave latch to retain previously stored data in response to the deasserted write bit signal while the first slave clock respectively causes the writing of data to one or more of the set of slave latches based on the one or more of the first set of data signals.

[0109] Aspect 15: The method of aspect 14, wherein the target slave latch includes a data gating circuit and a data latch circuit, and operating the target slave latch includes gating the first slave clock from being applied to the data gating circuit and the data latch circuit in response to a deasserted write bit signal.

[0110] Aspect 16: The method of aspect 14, wherein the target slave latch includes a data gating circuit and a data latch circuit, and operating the target slave latch includes maintaining the data gating circuit in a gated state and closing the data latch circuit in response to a deasserted write bit signal.

[0111] Aspect 17: The method of aspect 14, wherein the target slave latch includes a data gating circuit and a data latch circuit, and operating the target slave latch includes feeding back previously stored data from the data output to the data input of the data latch circuit via the data gating circuit in response to a deasserted write bit signal and a first slave clock.

[0112] Aspect 18: The method of any one of aspects 14-17, further comprising: providing an asserted write bit signal to a target slave latch; providing a second set of data signals to the set of slave latches, respectively; providing the second slave clock to the set of slave latches, respectively, in response to the asserted write bit signal and the second slave clock to write data to at least the target slave latches based on the corresponding one of the second set of data signals; and operating the target slave latches to store data based on the corresponding one of the second set of data signals in response to the asserted write bit signal and the second slave clock.

[0113] Aspect 19: The method of aspect 18, wherein the target slave latch includes a data gating circuit and a data latch circuit, and operating the target slave latch to store data includes communicating a second slave clock to the data gating circuit and the data latch circuit in response to an asserted write bit signal.

[0114] Aspect 20: The method of aspect 18, wherein the target slave latch includes a data gating circuit and a data latch circuit, and operating the target slave latch to store data includes setting the data gating circuit to a non-gated state and setting the data latch circuit to an open state in response to an asserted write bit signal and a second slave clock.

[0115] Aspect 21: The method of aspect 18, wherein the target slave latch includes a data gating circuit and a data latch circuit, and operating the target slave latch to store data includes communicating a corresponding one of the second set of data signals to the data gating circuit in response to an asserted write bit signal.

[0116] Aspect 22: An apparatus including: means for providing a deasserted write bit signal to a target slave latch in a set of slave latches; means for providing a first set of data signals, respectively, to the set of slave latches; means for providing a first slave clock, respectively, to the set of slave latches to write data to one or more of the set of slave latches based on one or more of the first set of data signals; and means for operating the target slave latch to retain previously stored data in response to the deasserted write bit signal while the first slave clock, respectively, causes the writing of data to one or more of the set of slave latches based on the one or more of the first set of data signals.

[0117] Aspect 23: The apparatus of aspect 22, wherein the target slave latch includes a data gating circuit and a data latch circuit, and the means for operating the target slave latch includes means for gating the first slave clock from being applied to the data gating circuit and the data latch circuit in response to a deasserted write bit signal.

[0118] Aspect 24: The apparatus of aspect 22, wherein the target slave latch includes a data gating circuit and a data latch circuit, and the means for operating the target slave latch includes means for maintaining the data gating circuit in a gated state and placing the data latch circuit in a closed state in response to a deasserted write bit signal.

[0119] Aspect 25: The apparatus of aspect 22, wherein the target slave latch includes a data gating circuit and a data latch circuit, and the means for operating the target slave latch includes means for feeding back previously stored data from the data output to the data input of the data latch circuit via the data gating circuit in response to a deasserted write bit signal and a first slave clock.

[0120] Aspect 26: The apparatus of any one of aspects 22-25, further including: means for providing an asserted write bit signal to the target slave; means for providing a second set of data signals to the set of slave latches, respectively; means for providing the second slave clock to the set of slave latches, respectively, in response to the asserted write bit signal and the second slave clock to write data to at least the target slave latches based on the corresponding one of the second set of data signals; and means for operating the target slave latches to store data based on the corresponding one of the second set of data signals in response to the asserted write bit signal and the second slave clock.

[0121] Aspect 27: The apparatus of aspect 26, wherein the target slave latch includes a data gating circuit and a data latch circuit, and the means for operating the target slave latch to store data includes communicating a second slave clock to the data gating circuit and the data latch circuit in response to an asserted write bit signal.

[0122] Aspect 28: The apparatus of aspect 26, wherein the target slave latch includes a data gating circuit and a data latch circuit, and the means for operating the target slave latch to store data includes means for setting the data gating circuit to a non-gated state and the data latch circuit to an open state in response to an asserted write bit signal and a second slave clock.

[0123] Aspect 29: The apparatus of aspect 26, wherein the target slave latch includes a data gating circuit and a data latch circuit, and the means for operating the target slave latch to store data includes means for communicating a corresponding one of the second set of data signals to the data gating circuit in response to an asserted write bit signal.

[0124] Aspect 30: A wireless communication device comprising: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; and a latch array coupled to the one or more signal processing cores, the latch array comprising: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to respectively receive a set of data, and a first set of data outputs respectively coupled to a set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to the set of write bit lines; and an array of slave latches arranged in columns and rows, the slave latches in a column of the array including a second set of data inputs coupled to the set of bit lines, and a second set of write bit inputs respectively coupled to the set of write bit lines.

[0125] The preceding description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. 1. A latch array comprising: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs respectively coupled to the set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; an array of slave latches arranged in columns and rows, the slave latches in the columns of the array including a second set of data inputs coupled to the set of bit lines and a second set of write bit inputs respectively coupled to the set of write bit lines.

2. 2. The latch array of claim 1, further comprising a set of clock gating circuitry including a third set of clock inputs configured to receive the master clock and a set of clock outputs coupled to a set of word lines, wherein the slave latches in the rows of the array include a fourth set of clock inputs each coupled to the set of word lines.

3. Each slave latch of the array a clock gating circuit including one of the second set of write bit inputs coupled to one of the sets of write bit lines, one of the fourth set of clock inputs coupled to one of the sets of word lines, and a complementary clock output; a data gating circuit including one of the second set of data inputs coupled to one of the sets of bit lines, a first set of complementary clock inputs respectively coupled to the complementary clock outputs of the clock gating circuit, and a first data output; a data latch circuit including a second set of complementary clock inputs respectively coupled to the complementary clock outputs of the clock gating circuit, a data input coupled to the first data output of the data gating circuit, and a second data output; The latch array of claim 2 , comprising:

4. Each slave latch of the array 1. A clock gating circuit comprising: a NOR gate including: a first input serving as one of the second set of write bit inputs coupled to one of the set of write bit lines; a second input serving as one of the fourth set of clock inputs coupled to one of the set of word lines; and an output; a first inverter including an input coupled to the output of the NOR gate and an output; A clock gating circuit comprising:

1. A data gating circuit comprising: a first field effect transistor (FET) including a first gate that serves as one of the second set of data inputs coupled to one of the set of bit lines; a second FET including a second gate coupled to the output of the first inverter; a third FET including a third gate coupled to the output of the NOR gate; a fourth FET including a fourth gate coupled to the first gate of the first FET, wherein the first FET, the second FET, the third FET, and the fourth FET are coupled in series between a first voltage rail and a second voltage rail; a data gating circuit comprising: A data latch circuit, a fifth FET including a fifth gate coupled to an output of the data latch circuit; a sixth FET including a sixth gate coupled to the output of the NOR gate; a seventh FET including a seventh gate coupled to the output of the first inverter; an eighth FET including an eighth gate coupled to the fifth gate of the fifth FET, wherein the fifth FET, the sixth FET, the seventh FET, and the eighth FET are coupled in series between the first voltage rail and the second voltage rail; a second inverter including an input coupled to a node between the sixth FET and the seventh FET and an output coupled to the output of the data latch circuit; A data latch circuit comprising: The latch array of claim 2 , comprising:

5. 5. The latch array of claim 4, wherein the first FET, the second FET, the fifth FET, and the sixth FET are each p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and the third FET, the fourth FET, the seventh FET, and the eighth FET are each n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

6. Each slave latch of the array a data gating circuit coupled to one of the second set of data inputs coupled to one of the set of bit lines, one of the fourth set of clock inputs coupled to one of the set of word lines, and one of the second set of write bit inputs coupled to one of the set of write bit lines, the data gating circuit including a first data output; a data latch circuit coupled to the one of the fourth set of clock inputs and the one of the second set of write bit inputs, the data latch circuit including a data input coupled to the first data output of the data gating circuit, and a second data output; The latch array of claim 2 , comprising:

7. Each slave latch of the array 1. A signal buffer circuit, comprising: a first inverter including an input serving as one of the fourth set of clock inputs coupled to one of the word lines, and an output; a second inverter including an input coupled to the output of the first inverter and an output; a third inverter including an input serving as one of the second set of write bit inputs coupled to one of the set of write bit lines, and an output; a fourth inverter including an input coupled to the output of the third inverter and an output; a signal buffer circuit comprising:

1. A data gating circuit comprising: a first field effect transistor (FET) including a first gate coupled to one of the second set of data inputs coupled to one of the set of bit lines; a second FET including a second gate coupled to the output of the second inverter; a third FET including a third gate coupled to the output of the fourth inverter; a fourth FET including a fourth gate coupled to the output of the third inverter; a fifth FET including a fifth gate coupled to the output of the first inverter; a sixth FET including a sixth gate coupled to the first gate of the first FET, wherein the first FET, the second FET, the third FET, the fourth FET, the fifth FET, and the sixth FET are coupled in series between a first voltage rail and a second voltage rail; a data gating circuit comprising: A data latch circuit, a seventh FET including a seventh gate coupled to an output of the data latch circuit; a first pair of parallel FETs including gates respectively coupled to the outputs of the first inverter and the third inverter; a second pair of parallel FETs including gates respectively coupled to the outputs of the second and fourth inverters; an eighth FET including an eighth gate coupled to the seventh gate of the seventh FET, wherein the seventh FET, the first pair of parallel FETs, the second pair of parallel FETs, and the eighth FET are coupled in series between the first voltage rail and the second voltage rail; and a fifth inverter having an input coupled to a node between the first pair of parallel FETs and the second pair of parallel FETs, and an output coupled to the output of the data latch circuit; A data latch circuit comprising: The latch array of claim 2 , comprising:

8. 8. The latch array of claim 7, wherein the first parallel FET, the second parallel FET, the third parallel FET, the seventh parallel FET, and the first pair of parallel FETs each comprise p-channel metal-oxide-semiconductor field effect transistors (PMOS FETs), and the fourth parallel FET, the fifth parallel FET, the sixth parallel FET, the eighth parallel FET, and the second pair of parallel FETs each comprise n-channel metal-oxide-semiconductor field effect transistors (NMOS FETs).

9. Each slave latch of the array a multiplexer including: one of the second set of data inputs coupled to one of the set of bit lines; one of the second set of write bit inputs coupled to one of the set of write bit lines; a first data input; and a first data output; a data gating circuit including a second data input coupled to the first data output of the multiplexer and a second data output, the data gating circuit coupled to one of the fourth set of clock inputs coupled to one of the set of word lines; a data latch circuit coupled to the one of the fourth set of clock inputs, the data latch circuit including a third data input coupled to the second data output of the data gating circuit and a third data output coupled to the first data input of the multiplexer; The latch array of claim 2 , comprising:

10. Each slave latch of the array 1. A signal buffer circuit, comprising: a first inverter including an input serving as one of the fourth set of clock inputs coupled to one of the word lines, and an output; a second inverter including an input coupled to the output of the first inverter and an output; a third inverter including an input serving as one of the second set of write bit inputs coupled to one of the set of write bit lines, and an output; a fourth inverter including an input coupled to the output of the third inverter and an output; a signal buffer circuit comprising: A multiplexer, a first transmission gate including a first terminal coupled to one of the second set of data inputs coupled to one of the set of bit lines, a first set of complementary gates coupled to the outputs of the third inverter and the fourth inverter, respectively, and a second terminal; a second transmission gate including a third terminal, a second set of complementary gates coupled to the outputs of the third inverter and the fourth inverter, respectively, and a fourth terminal coupled to the second terminal to form an output; a multiplexer comprising:

1. A data gating circuit comprising: a first field effect transistor (FET) including a first gate coupled to the output of the multiplexer; a second FET including a second gate coupled to the output of the second inverter; a third FET including a third gate coupled to the output of the first inverter; a fourth FET including a fourth gate coupled to the first gate of the first FET, wherein the first FET, the second FET, the third FET, and the fourth FET are coupled in series between a first voltage rail and a second voltage rail; a data gating circuit comprising: A data latch circuit, a fifth FET including a fifth gate coupled to an output of the data latch circuit; a sixth FET including a sixth gate coupled to the output of the first inverter; a seventh FET including a seventh gate coupled to the output of the second inverter; an eighth FET including an eighth gate coupled to the fifth gate of the fifth FET, wherein the fifth FET, the sixth FET, the seventh FET, and the eighth FET are coupled in series between the first voltage rail and the second voltage rail; a fifth inverter including an input coupled to a node between the sixth FET and the seventh FET and an output coupled to the output of the data latch circuit, the output of the data latch circuit being coupled to the third terminal of the second transmission gate; A data latch circuit comprising: The latch array of claim 2 , comprising:

11. 11. The latch array of claim 10, wherein the first FET, the second FET, the fifth FET, and the sixth FET each comprise p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and the third FET, the fourth FET, the seventh FET, and the eighth FET each comprise n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

12. 3. The latch array of claim 2, wherein the set of clock gating circuits includes a set of enable inputs configured to receive a write address.

13. 2. The latch array of claim 1, further comprising a set of multiplexers including a set of inputs respectively coupled to a second set of data outputs of the column of slave latches, a set of select inputs configured to receive a read address, and a third set of data outputs respectively configured to generate the second set of data.

14. 1. A method comprising: providing a deasserted write bit signal to a target slave latch in the set of slave latches; providing a first set of data signals to a set of said slave latches, respectively; providing first slave clocks to the set of slave latches to write data to one or more of the set of slave latches based on one or more of the first set of data signals, respectively; operating the target slave latch to retain previously stored data in response to the deasserted write bit signal while the first slave clock causes the writing of data to the one or more of the set of slave latches based on the one or more of the first set of data signals, respectively; A method comprising:

15. 15. The method of claim 14, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and operating the target slave latch comprises gating, in response to the deasserted write bit signal, the first slave clock from being applied to the data gating circuit and the data latch circuit.

16. 15. The method of claim 14, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and operating the target slave latch comprises maintaining the data gating circuit in a gated state and maintaining the data latch circuit in a closed state in response to the deasserted write bit signal.

17. 15. The method of claim 14, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and operating the target slave latch comprises, in response to the deasserted write bit signal and the first slave clock, feeding back the previously stored data from a data output to a data input of the data latch circuit via the data gating circuit.

18. providing an asserted write bit signal to the target slave latch; providing a second set of data signals to a set of slave latches, respectively; providing second slave clocks to the set of slave latches for writing data to at least the target slave latches respectively based on corresponding ones of the second set of data signals; operating the target slave latch in response to the asserted write bit signal and the second slave clock to store data based on the corresponding one of the second set of data signals; The method of claim 14 further comprising:

19. 20. The method of claim 18, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and wherein operating the target slave latch to store the data comprises communicating the second slave clock to the data gating circuit and the data latch circuit in response to the asserted write bit signal.

20. 20. The method of claim 18, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and wherein operating the target slave latch to store the data comprises setting the data gating circuit to a ungated state and setting the data latch circuit to an open state in response to the asserted write bit signal and the second slave clock.

21. 20. The method of claim 18, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and wherein operating the target slave latch to store the data comprises communicating the corresponding one of the second set of data signals to the data gating circuit in response to the asserted write bit signal.

22. An apparatus comprising: means for providing a deasserted write bit signal to a target slave latch in the set of slave latches; means for providing a first set of data signals to a set of said slave latches, respectively; means for providing a first slave clock to one or more of the set of slave latches for writing data to the set of slave latches based on one or more of the first set of data signals, respectively; means for operating the target slave latch to retain previously stored data in response to the deasserted write bit signal while the first slave clock causes the writing of data to the one or more of the set of slave latches based on the one or more of the first set of data signals, respectively; An apparatus comprising:

23. 23. The apparatus of claim 22, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and wherein the means for operating the target slave latch includes means for gating, in response to the deasserted write bit signal, the first slave clock from being applied to the data gating circuit and the data latch circuit.

24. 23. The apparatus of claim 22, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and wherein the means for operating the target slave latch includes means for maintaining the data gating circuit in a gated state and for placing the data latch circuit in a closed state in response to the deasserted write bit signal.

25. 23. The apparatus of claim 22, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and wherein the means for operating the target slave latch includes means for feeding back the previously stored data from a data output to a data input of the data latch circuit via the data gating circuit in response to the deasserted write bit signal and the first slave clock.

26. means for providing an asserted write bit signal to said target slave latch; means for providing a second set of data signals to said set of slave latches, respectively; means for providing a second slave clock to each of the set of slave latches for writing data to at least the target slave latches based on a corresponding one of the second set of data signals; means for operating the target slave latch in response to the asserted write bit signal and the second slave clock to store data based on the corresponding one of the second set of data signals; 23. The apparatus of claim 22, further comprising:

27. 27. The apparatus of claim 26, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and wherein the means for operating the target slave latch to store the data comprises communicating the second slave clock to the data gating circuit and the data latch circuit in response to the asserted write bit signal.

28. 27. The apparatus of claim 26, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and wherein the means for operating the target slave latch to store the data includes means for setting the data gating circuit to a ungated state and setting the data latch circuit to an open state in response to the asserted write bit signal and the second slave clock.

29. 27. The apparatus of claim 26, wherein the target slave latch comprises a data gating circuit and a data latch circuit, and wherein the means for operating the target slave latch to store the data includes means for communicating the corresponding one of the second set of data signals to the data gating circuit in response to the asserted write bit signal.

30. 1. A wireless communication device, comprising: At least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; a latch array coupled to the one or more signal processing cores, the latch array comprising: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a set of data, and a first set of data outputs respectively coupled to the set of bit lines; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write bit inputs configured to receive a set of write bit signals, and a set of write bit outputs respectively coupled to a set of write bit lines; an array of slave latches arranged in columns and rows, the slave latches in the columns of the array including a second set of data inputs coupled to the set of bit lines and a second set of write bit inputs respectively coupled to the set of write bit lines; a latch array comprising: A wireless communication device comprising:

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