Method for treating an optoelectronic device and an optoelectronic device - Patents.com

Abstract

The present invention relates to a method for processing an optoelectronic device providing a functional semiconductor stack (10) with a conductive layer and a hard mask layer on the conductive layer, both of which are structured and include a protective layer arranged on the sidewalls of the conductive layer. Two dry and wet etching processes are then performed to obtain an optoelectronic device. Parts of the hard mask layer on the conductive layer remain on the functional stack and become an integral part of the device.

Description

[Technical field]

[0001] The present invention relates to a method for processing an optoelectronic device and to an optoelectronic device.

[0002] Optoelectronic devices with a diameter of their light-emitting surface less than 70 μm and up to 1 μm are called μ-LEDs. Such μ-LEDs have a diameter of about 1 μm 2 ~about 100μm 2 and is configured to emit blue, red and green light. The processing of such LEDs in very small formats presents various challenges, for example in particular the processing of damaged side edges of the active area in order to stabilize and optimize the electro-optical performance of very small μ-LEDs. For this purpose, it has been proposed to use wet chemical etching processes to process the dry chemical side edges of the semiconductor layers, in particular the area of ​​the pn junction.

[0003] Another difficulty comes from placing a p-side mirror on the functional semiconductor stack to achieve reasonably good performance. For this, the mirror must cover most, if not all, of the p-side. In the prior art, mirror stacks, mainly containing Ag, are structured using lift-off techniques. However, such a process requires several lithographic steps that can lead to misalignment. Moreover, in the conventional approach, the mirror sidewalls often slope, reducing the overall performance.

[0004] The aim of the present application is to improve the above situation by reducing the lithography steps without compromising the quality or performance of the device. Summary of the Invention

[0005] For the structuring of the size and shape of the μ-LEDs, the inventors propose to use only a single photolithography step to structure the hard mask, which results in self-alignment with the underlying conductive layer. During the dry and wet etching processes, the hard mask also forms a protection. This approach allows the wet etching process with KOH to be performed only on a vertically limited part of the peripheral mesa of the pn junction.

[0006] In this process flow, the inventors propose to structure in a single step a hardmask and a conductive layer on the surface of a functional stack, which structuring results in the alignment of the sidewalls of the conductive layer and the hardmask stack.

[0007] In one aspect, a method for processing an optoelectronic device includes providing a functional semiconductor stack. The functional semiconductor stack includes an active region buried below a surface of the functional semiconductor stack. A conductive layer is disposed on the surface of the stack. In this regard, the conductive layer may include a variety of properties and / or functions, including but not limited to providing current distribution to upper layers of the functional stack. The conductive layer may include a transparent and / or highly reflective metal.

[0008] Then, a patterned hard mask stack is deposited on the conductive layer, the hard mask stack having at least a first mask layer. The patterned hard mask stack and the conductive layer are dry etched together, the patterned hard mask serves as an alignment for the conductive layer, providing a structured hard mask stack, and a portion of the functional semiconductor stack is exposed. In the next step, a first protective layer is deposited on at least the sidewall of the conductive layer, the first protective layer comprising the same etching properties as the first layer and being resistant to the wet etching process. In other words, the first layer of the structured hard mask stack may be sealed by the material of the first protective layer.

[0009] In a next step, a first anisotropic dry chemical etching process is performed to etch the structured hard mask stack and the part of the functional semiconductor stack not covered by the structured hard mask stack to a first depth that exposes the edge of the active area. A chlorine-containing gas may be used for this first dry etching process. The anisotropic etching does not etch the first protective layer on the sidewalls (of both the conductive layer and the hard mask stack) and still protects the sidewalls.

[0010] In the following steps, a wet chemical etching process is performed to treat and shape in particular the exposed surfaces of the functional semiconductor stack. During this wet etching process, the first protective layer protects the sidewalls of the conductive layer from being etched. Once the wet etching process is completed, which removes damage from the mesa sidewalls and in particular the edges of the active area, the exposed edges of the active area are covered with a second protective layer.

[0011] A second anisotropic dry chemical etch is then performed to remove parts of the hard mask stack and parts of the functional semiconductor stack not covered by the structured hard mask and the third material to a second depth, however, a small amount of material of the hard mask stack, in particular the first hard mask layer, remains on the surface of the conductive layer and forms an integral part of the optoelectronic device.

[0012] Finally, the second protective layer is removed, thereby exposing the first protective layer and again exposing the sidewall edges of the active area. The optoelectronic device is then further processed such that parts of the first mask layer (31) and the second protective layer remain on the sidewalls of the functional stack and the conductive layer, respectively.

[0013] The method according to the proposed principle combines the self-alignment possibility of the hard mask with the conductive material underneath, thereby eliminating the need for separate lithographic steps for patterning and structuring the conductive layer and the hard mask. The structured mask stack serves as a mask layer for various dry and wet etching processes to form the mesa structures.

[0014] In some embodiments, the step of providing a functional semiconductor comprises depositing a functional laminate and a conductive material on the surface of the functional laminate. If necessary, an annealing layer can be deposited, which is subsequently removed. In some examples, the annealing layer comprises ZnO. A conductive layer is deposited on the conductive material, particularly after removing the annealing layer on the conductive material, and the conductive layer is compatible with the dry etching process used to structure the patterned hard mask or is resistant to KOH.

[0015] In some other embodiments, depositing a patterned hardmask stack comprises depositing a SiN layer having a thickness in the range of greater than 500 nm, particularly in the range of 700 nm to 1500 nm, and particularly in the range of 1000 nm to 1300 nm, on the conductive layer. x The method includes depositing a first mask layer of SiO2. Optionally, depositing a second layer on the first mask layer, the second layer comprising SiO2 and being thinner than the first mask layer. Finally, applying and patterning a photoresist.

[0016] The first protective layer has a thickness at the sidewall in the range of 10 nm to 70 nm, in particular 20 nm to 40 nm, and is of the same material as the first layer. In some embodiments, the first protective layer encapsulates the first mask layer of the structured hard mask stack and at least partially covers the exposed portion of the functional semiconductor stack.

[0017] The first anisotropic dry etching process may result in sloping sidewalls in the functional stack and expose the edges of the active areas. The depth of the etching process is controllable and may be in the range of 300 nm to 1000 nm, in particular 400 nm to 600 nm.

[0018] In another embodiment, the wet chemical etching process includes etching with KOH. After the wet etching process is completed, the exposed and treated edges and sidewalls of the active area are covered by a thin second protective layer. The second protective layer may include Al2O3. In some examples, it is deposited by an atomic layer deposition process such as ALD or CVD with a thickness of less than 60 nm, particularly less than 40 nm. The second protective layer protects the sidewalls and edges of the active area from a subsequent dry etching process without damaging or interfering with the edges of the active area itself.

[0019] In some examples, the second anisotropic dry chemical etching step is a repeat of the first dry etching process using the same etchant. Alternatively, a different etchant or different process parameters can be used to control the etching process. The second anisotropic dry chemical etching may remove the structured hard mask stack and the first mask layer until only a small residual layer remains on the surface of the conductive layer. The second anisotropic dry chemical etching removes the second protective layer on top of the functional semiconductor stack and etches the functional semiconductor stack to a second depth.

[0020] In some examples, the second anisotropic dry chemical etch step produces a sloped surface portion of the functional stack that is not covered by the second protective layer, the slope being different from the slope of the sidewall treated by the wet etching process. In some embodiments, the second anisotropic dry chemical etch is performed until an undoped buffer layer of the functional stack is reached.

[0021] Finally, the remains of the second protective layer are removed, for example using an acid in which the second protective layer is soluble, this process re-exposing the first mask layer on top of the conductive layer and at the sidewalls of the conductive layer.

[0022] The method can be applied to the processing of μ-LEDs based on various material systems, including semiconductor materials such as GaN, InGaN, and InAlGaN, which have crystal orientations that are substantially inert to wet chemical etching processes for removing the hard mask.

[0023] The optoelectronic device can then be further processed to complete the device. In some embodiments, a third protective layer is deposited on the surface and walls sealing the remainder of the first mask layer, the conductive layer, and the active area of ​​the functional semiconductor stack. The third protective layer may comprise Al2O3 and is deposited by an ALD process. The thickness of the third protective layer ranges from 10 nm to about 100 nm, in particular from 35 nm to 65 nm. The third protective layer and the remainder of the first mask layer are then structured to expose a part of the conductive layer. A metal layer is filled into the recess so as to also cover the surface of the third protective layer. The metal layer forms a contact for the p-side of the optoelectronic device.

[0024] To process the n-side, the optoelectronic device may be encapsulated with a sacrificial layer. The sacrificial layer comprises SiO2 and has a thickness in the range of about 100 nm to 300 nm. An anchor is formed to support the optoelectronic device, the anchor extending through the sacrificial layer, the sacrificial layer comprising a recess. The device is then cast with a filler material, the filler material also filling the recess, thereby forming the anchor. The filler material may be partially removed to provide access to the sacrificial layer and the n-side surface of the optoelectronic device. After forming metal contacts to the n-side surface of the device, the sacrificial layer may be removed. The device is now resting on the anchor.

[0025] Some other aspects relate to an optoelectronic device comprising a functional stack. The functional stack comprises a first doped layer, a second doped layer and an active region located between the first doped layer and the second doped layer. A conductive layer is arranged on the surface of the second doped layer. The stack further comprises a structured non-conductive mask layer on the conductive layer and a structured protective layer on the non-conductive mask layer. A metal layer covers the structured protective layer, which is electrically connected to the conductive layer. According to the proposed principle, the structured protective layer extends to the sidewalls of the structured non-conductive mask layer of the active region, the sidewalls of the conductive layer and the sidewalls of the active region. In other words, the structured protective layer covers the sidewalls of the structured non-conductive mask layer, the sidewalls of the conductive layer and the sidewalls of the active region. Furthermore, the sidewalls of the non-conductive mask layer are aligned with the sidewalls of the conductive layer. There is no step or lateral displacement between the sidewalls.

[0026] The optoelectronic device according to the proposed principle intentionally uses a hard mask material used to align the conductive layer structure with the mesa structure, which is an integral part of the device. This differs from conventional approaches where the hard mask is usually removed before further processing of the device. In some examples, the sidewalls of the active region are also aligned with the sidewalls of the conductive layer. Note that "aligned" in this case means substantially linear and without steps or the like. The sidewalls of the conductive layer may be covered with a material having similar or identical properties to the non-conductive mask layer. In such a case, the sidewalls of the active region are linear with said material, which itself is substantially linear. Note that the above alignment is also referred to as flush.

[0027] In some examples, the second sidewall, which forms part of the first doped layer, is laterally displaced relative to the sidewall of the active region and extends along a portion of the first doped layer. It may also be inclined relative to the sidewall of the active region. More specifically, in some examples, the angle between the sidewall of the active region and the second sidewall is greater than 0°, in particular between 1° and 5°.

[0028] In some further embodiments, the material of the structured non-conductive mask layer is SiN x Similarly, the material covering the sidewalls of the conductive layer may also include SiN. x In some instances, the conductive layer comprises a laminate, one layer of which is a metal layer, particularly an Ag layer, and a second layer may comprise a transparent conductive oxide, particularly ITO, which has several properties that are useful during the manufacturing process.

[0029] The metal layer is located only on the top surface of the structured protective layer. The protective layer may have one or more recesses such that the metal filling the recesses extends through the non-conductive mask layer to the conductive layer. The structured protective layer may include Al2O3. [Brief description of the drawings]

[0030] Other aspects and embodiments consistent with the principles of the present teachings will become apparent in connection with the detailed description of the various embodiments and examples that are illustrated in the accompanying drawings. [Figure 1A] 1 shows the first steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 1B] 1 shows the first steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 1C] 1 shows the first steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 1D] 1 shows the first steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 2A] 4 illustrates further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 2B] 4 illustrates further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 2C] 4 illustrates further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 3A]5 shows some further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 3B] 5 shows some further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 4] 1 illustrates an alternative embodiment of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 5A] 5 shows some further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 5B] 5 shows some further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 5C] 5 shows some further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 5D] 5 shows some further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 5E] 5 shows some further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 5F] 5 shows some further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 5G] 5 shows some further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. [Figure 5H] 5 shows some further steps of a method for processing an optoelectronic device according to some aspects of the proposed principles. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The following embodiments and examples disclose various aspects and their combinations according to the proposed principles. The embodiments and examples are not necessarily drawn to scale. Similarly, different elements can be displayed enlarged or reduced to emphasize individual aspects. It goes without saying that each aspect of the embodiments and examples shown in the drawings may be combined with each other, unless otherwise stated, as long as it does not violate these principles. Some aspects show regular structures or shapes. It should be noted that in practice, slight differences and deviations from the ideal form may occur, but still do not contradict the inventive concept of the present invention.

[0032] In addition, the individual drawings and aspects are not necessarily shown to the correct size, and the ratio between the individual elements is not necessarily essentially correct. Some aspects are emphasized by showing them enlarged. However, with respect to each element in the drawings, the expressions "upper", "upper", "lower", "lower", "larger", "smaller", etc. are correct expressions in the drawings. Therefore, the relationship between each such element can be inferred based on the drawings.

[0033] 1A-1D show the first steps of a method for processing an optoelectronic device according to some embodiments of the proposed principle. The optoelectronic device, also called μ-LED, is configured to emit light of a specific wavelength, the wavelength itself depending on the substrate used. The optoelectronic device 1 comprises a functional semiconductor stack 10 having several differently doped layers and an active region 12. The functional semiconductor stack has been deposited on a growth substrate, not shown in the figures, which comprises one or more layer structures to prepare for the deposition of the various layers of the stack 10.

[0034] More specifically, the functional semiconductor stack 10 comprises a first doped layer 11, in particular an n-doped layer, deposited directly on a buffer layer structure or a growth substrate (not shown here), respectively. This n-doped first layer 11 may comprise a current distribution layer, a sacrificial layer or other suitable layer providing current injection into an active region 12 deposited on the first doped layer 11. The active region 12 comprises a quantum well or multiple quantum well structure having a band gap suitable for emitting light of the desired wavelength.

[0035] It should be noted that the active region 12 may also include a quantum well interdiffusion region in the portion close to the mesa structure that will be processed in the next step of the proposed method. On top of the active region 12, a second doped layer, in particular a p-doped layer 13, is provided. In this regard, the second doped layer 13, and also the first doped layer 11, may include a constant or variable doping profile to ensure proper current injection into the active region 12 and achieve the desired electrical properties.

[0036] A conductive layer 14 is provided on the top surface of the second doped layer 13. The conductive layer 14 includes a metallic mirror structure 14', for example a metal alloy including Ag and Zn. The metallic layer 14' is deposited to cover the entire top surface of the second layer 13, as shown in FIG. 1A. Its thickness may be in the range of 100 nm to 150 nm. A small layer of ZnO or other material in the range of about 50 nm is deposited on the Ag layer and baked. The ZnO layer may later be replaced by an ITO layer 15 as shown, so that the upper layer also has some etch-stop properties. Both layers 14' and 15 form the conductive layer 14. The conductive layer 14 serves as a contact layer as well as a reflective layer for the light generated in the active region 12.

[0037] After depositing each layer of the functional semiconductor laminate 10 including the conductive layer 14, a hard mask layer 31 is deposited on the surface of the conductive layer. The hard mask layer is made of SiN xand is about 1000 nm thick, the thickness being selected so that after various dry and wet chemical etching steps, a thin layer of about 70 nm to 150 nm, in particular a hard mask layer 31 of about 100 nm, remains on the surface of the conductive layer 14 and forms an integral part of the optoelectronic device. This silicon nitride layer 31 acts as a protection layer for the conductive layer 14 during the wet etching process with KOH. However, it is etched in the chlorine dry etching process, so it needs to be thicker as mentioned above.

[0038] 1B shows the result of depositing a hard mask layer 31 applied to the surface of conductive layer 14. In the next step, a photoresist layer 100 is applied on top of the hard mask layer and patterned to expose portions of the surface of layer 31.

[0039] After patterning the hard mask and layer 31, a first etching process, i.e. a dry etching process, is performed as shown in FIG. 1C. The etching process removes the hard mask layer 31 and also the conductive layer 14. In this example, the etching process removes the ITO layer 15, the AG layer 14' down to the surface of the functional semiconductor stack. During the etching process, the sidewalls of the mask layer 31 are aligned with the sidewalls of the conductive layer 14. This alignment is substantially maintained in subsequent steps and can be observed in the final optoelectronic device.

[0040] The etchant used in the dry etching process may include Cl in combination with an oxygen reducing agent to avoid oxidizing the exposed sidewalls of the AG layer 14'. In other examples, the dry chemical etching process may use CF3, CF4, CxHyFz compounds, or SF6 in combination with an inert gas (e.g., argon). The dry etching process may be anisotropic to avoid under-etching the conductive layer 14 beneath the hard mask layer 31.

[0041] In the next step shown in FIG. 1D, a first protective layer 21 is deposited on the top surface of the mask layer 31, on the sidewalls of the conductive layer 14, and on the sidewalls including the exposed surface of the functional semiconductor stack. The material of the first protective layer 21 is SiN, which is the same material used for the hard mask layer. x As mentioned above, SiN x The protective layer 21 is resistant to etching by KOH and prevents the conductive layer from being etched in a subsequent process. The thickness of the protective layer 21 is in the range of a few tens of nm, for example in the range of 20 nm to 70 nm, in particular in the range of about 25 nm to 45 nm. As part of the hard mask layer 31, the material covering the sidewalls of the conductive layer 14 remains on the sidewalls and becomes an integral part of the optoelectronic device.

[0042] 2A-2C illustrate the next steps of the method for processing an optoelectronic device according to the proposed principles.

[0043] A first anisotropic dry etching process is performed to obtain a shallow mesa structure, the result of which is shown in FIG. 2A. The anisotropic dry etching process includes chlorine gas and removes a part of the mask layer 31 and the protective layer 21 on the surface of the semiconductor stack, exposing a part of the semiconductor stack 10. The material of the functional semiconductor stack 10, including the layer 13, the active region 12 and a part of the first layer 11, is etched to obtain a shallow mesa structure 120. The sidewalls 121 of the shallow mesa structure are slightly inclined due to the shadow effect of the anisotropic dry etching process. The material of the protective layer 21 applied to the sidewalls of the hard mask layer 31 and the sidewalls of the conductive layer 14 remains.

[0044] The result of this first anisotropic dry etching process is that the side edges of active region 12 are exposed. The nature of the dry etching causes some damage to the crystalline structure of the side edges of active region 12, and also of regions 13 and 11, leaving a high density of non-radiative recombination centers in the crystalline structure. To remove most of these non-radiative recombination centers, a wet etching process is performed using KOH. The wet etching process exposes well-defined crystalline facets, preferably leading to substantially vertical sidewalls 121, so that the sidewalls are aligned with the sidewalls of hard mask layer 31 and the sidewalls of conductive layer 14. KOH is a crystalline silicon carbide (SiN x The etchant is an etchant that barely etches the conductive layer 14. Thus, the material of the first protective layer 21 on the sidewalls covering the conductive layer 14 is not etched, and the conductive layer is protected. Similarly, the mask layer 31 acts as a protective layer for the underlying layer 14 in the wet etching process. The resulting structure is shown in Figure 2B.

[0045] Then, after the wet etching process is finished, the exposed edges of the active area 12, as well as the first protective layer 21 and the hard mask layer 31 on the sidewalls, are covered by a second protective layer 22. The second protective layer 22 comprises Al2O3 and is deposited using an ALD process, with a thickness ranging from a few nm to 60 nm. The second protective layer 22 also extends onto the top surface of the previously etched functional semiconductor stack. The layer 22 protects the active area 12 against a subsequent anisotropic dry etching process used to etch deep mesa structures as shown in FIG. 3A.

[0046] The second anisotropic dry etching process, shown in FIG. 3A, removes further parts of the mask layer 31 down to a small layer 31'. For this purpose, the thickness of the mask layer 31 is adjusted to the etching rates of the first and second anisotropic etching processes to ensure that some material of the mask layer 31 remains on the surface. In addition, the material of the second protective layer 22 on the top surface of the functional stack 10 is removed and the functional stack is etched until the undoped buffer layer is reached. As a result, sloping sidewalls are generated in the first doped layer 11 of the functional stack. The slope of said sidewalls is in the range of several degrees depending on the etching solution and its process parameters. Due to the anisotropic etching process, the second protective layer 22 material on the sidewalls remains substantially intact and protects the surface of the functional stack in the areas 120 exposed by the first dry etching process.

[0047] In Fig. 3B, after the second anisotropic dry etching process, the second protective layer 22 is removed using a solution of H3PO4. The removal process causes a small lateral displacement in the first doped layer, the width d'' of which corresponds approximately to the thickness of the Al2O3 protective layer. The SiN x The area 130 has sloping sidewalls with an angle α in the range of several degrees.

[0048] According to the proposed method, optoelectronic devices can be processed with deep mesa structures without changing the pattern mask in the whole process. In particular, the proposed structured hard mask is aligned with respect to the conductive layer at the surface. The first protective layer provides sufficient protection against the dry chemical etching process, while at the same time allowing a very precise and selective etching process. An alternative method of processing optoelectronic devices apart from the single hard mask structure 30 is shown in FIG. 4.

[0049] This optoelectronic device has a functional stack 10 similar to the embodiment of the previously proposed method, the surface of which is covered with a conductive layer 14. In contrast to the previous embodiment, the hard mask structural layer 30 is made of SiN x and a first layer 31 made of SiNx The SiO2 layer 32 overlies the SiN layer. Although the SiO2 layer 32 is relatively thin, the etch rate of the SiO2 layer 32 during the first anisotropic etching process is x The etching rate of the material is smaller than that of the required SiN x Less material is required. Therefore, SiN x As with the material, the SiO2 layer is substantially removed during the first dry etching process, but at a lower etch rate.

[0050] 5A-5H show the next few steps in further processing of the device.

[0051] As shown in FIG. 5A, a third protective layer 33 is deposited over the surface of the device, so that the SiN x In some instances, ozone may be used in the deposition process, thus leaving the SiN x Preferably, the third protective layer 33 remains to cover the sidewalls of the conductive layer and prevent its oxidation. The thickness of the third protective layer 33 is in the range of about 40 nm to 100 nm. The resulting structure is then further processed as shown in FIG. 5B. The protective layer 33 is covered with a patterned photoresist layer. The third protective layer 33 is structured to form recesses in the layer 33 and in the hard mask layer 31, respectively, to expose parts of the conductive layer 14.

[0052] The recess and the top surface of the Al2O3 layer 33 are then covered with a metal layer 40 that forms a contact for the optoelectronic device (see FIG. 5C). The metal extends into the recess and is in electrical contact with the conductive layer 14. A sacrificial layer 50 is then placed over the entire surface of the optoelectronic device, as shown in FIG. 5D. The sacrificial layer may also comprise a material that is easy to remove later, such as SiO2. The sacrificial layer 50 is patterned to open small recesses to access the metal layer. As will become apparent, the recesses can have different shapes and can be located in different locations on the device. A support structure is then formed to support the optoelectronic device and hold it in place. In this example, the recesses are on the top surface, SiN xIt is formed above a recess that penetrates layer 31 .

[0053] In a next step, the device is encapsulated in a carrier material 55. The carrier material 55 comprises a polymer or plastic material. The carrier material 55 also fills the recesses in the sacrificial layer and forms the anchor elements 51. As shown in Fig. 5E, an additional support carrier 56 is placed on the carrier material 55. The additional support carrier 56 allows the growth substrate to be rebonded and removed.

[0054] FIG. 5F shows the next steps. First, the device is rotated to allow access to the n-doped side. If necessary, the surface is polished or otherwise smoothed or partially removed to allow access to the n-side of the functional semiconductor stack. A transparent metal n-contact 60, for example ITO, is deposited on top of the n-side face of layer 11 and patterned with a photoresist, not shown. The encapsulation material 55 can be partially removed to facilitate access to the sacrificial layer 50, shown in FIG. 5G. As shown, the recess in the sacrificial layer 50 is thus filled with the encapsulation material 55, supporting the optoelectronic device. In the final step shown in FIG. 5H, a release etch is performed to remove the sacrificial layer 50 from the sides and the underside of the device. The optoelectronic device is now only resting on the support structure. [Explanation of symbols]

[0055] 1 Optoelectronic devices 10. Functional semiconductor laminate 11 First doped layer 12 Active area 13 Second doped layer 14 Conductive layer 14' Ag layer 15 ITO layers 21 1st protective layer 22 Second protective layer 30 Hard mask stack 31 First hard mask layer 32 Second hard mask layer 33 Third protective layer 40 metal layer 50 Sacrificial Layer 51 Anchor 55 Plastic Materials 56 Support Carrier 100 Photoresist 120 Area 1 130 Area 2

Claims

1. 1. A method for treating an optoelectronic device, comprising the steps of: providing a functional semiconductor stack (10) having an active area (12), said active area (12) being spaced apart from a surface of said functional semiconductor stack (10), said surface having a conductive layer (14) deposited thereon; depositing a patterned hardmask stack (30) on the conductive layer (14), the hardmask stack (30) having at least a first mask layer (31); dry etching the patterned hardmask stack (30) and the conductive layer (14) to provide a structured hardmask stack (30') and to expose a portion of the functional semiconductor stack (10); depositing a first protective layer (21) on at least the sidewalls of said conductive layer (14), said first protective layer (21) having similar etching properties as said first layer (31) and being resistant to wet etching processes; a first anisotropic dry chemical etching of the structured hard mask stack (30') and of the portion of the functional semiconductor stack (10) not covered by the structured hard mask stack (30') to a first depth exposing an edge of the active area (12); carrying out a wet chemical etching process, in particular on the exposed surfaces of said functional semiconductor stack (10), while the side edges of said conductive layer (14) are protected by said first protective layer (21); covering the exposed edges of the active area (12) with a second protective layer (22); A second anisotropic dry chemical etching of the structured hardmask stack (30') and of further parts of the functional semiconductor stack (10) not covered by the structured hardmask (30') to a second depth; removing the second protective layer (22); further processing the optoelectronic device such that a part of the first mask layer (31) and the second protective layer remain on the sidewalls of the functional stack and the conductive layer, respectively; The method according to claim 1,

2. The step of providing a functional semiconductor includes: depositing a functional laminate; depositing a conductive material (14'), in particular Ag, on the surface of the functional laminate; Optionally, depositing an annealing layer, in particular ZnO, on top of said conductive material; depositing a conductive layer (15) on the conductive material (14'), which is highly compatible with the dry etching process used to structure the patterned hard mask or is highly resistant to KOH, in particular after removing the annealing layer on the conductive material (14'), The method of claim 1.

3. The step of depositing the patterned hardmask stack (30) comprises: SiN having a thickness in the range of more than 500 nm, in particular in the range of 700 nm to 1500 nm, in particular in the range of 1000 nm to 1300 nm. ｘ depositing said first mask layer (31) on said conductive layer; The first mask layer (31) is made of SiO ２ optionally depositing a second layer (32) thinner than said first mask layer (31); depositing a photoresist and patterning the photoresist. The method according to claim 1 or 2.

4. the first protective layer (21) has a thickness at the sidewall in the range of 10 nm to 70 nm, in particular in the range of 20 nm to 40 nm, and is of the same material as the first layer (31); 4. The method according to any one of claims 1 to 3.

5. The first protective layer (21) encapsulates the first mask layer (31) of the structured hard mask stack (30) and covers at least a portion of the exposed portion of the functional semiconductor stack. The method according to claim 3 or 4.

6. The first anisotropic dry chemical etching step produces sloped sidewalls in the functional laminate (10); 6. The method according to any one of claims 1 to 5.

7. The first depth is in the range of 300 nm to 1000 nm, in particular in the range of 400 nm to 600 nm; 7. The method according to any one of claims 1 to 6.

8. The steps of the wet chemical etching process include etching with KOH; 8. The method according to any one of claims 1 to 7.

9. The step of covering the exposed edges of the active area (12) comprises: The second protective layer (22), in particular Al, having a thickness in the range of less than 60 nm, in particular less than 40 nm, is deposited by an ALD process. ２ O ３ on said sidewalls.

9. The method according to any one of claims 1 to 8.

10. The second anisotropic dry chemical etching step comprises: The second anisotropic dry chemical etch has the same etchant as the first anisotropic dry chemical etch, and / or the second anisotropic dry chemical etch removes the second protective layer (22) on top of the functional semiconductor stack.

10. The method according to any one of claims 1 to 9.

11. The second anisotropic dry chemical etching step produces an inclined surface (130) portion of the functional laminate (10); 11. The method according to any one of claims 1 to 10.

12. A second anisotropic dry chemical etch is performed until an undoped buffer layer of the functional stack is reached and / or a second anisotropic dry chemical etch removes a portion of the first mask layer (31).

12. The method according to any one of claims 1 to 11.

13. The functional laminate (10) comprises: GaN, InGaN, and InAlGaN, Optionally, a crystal orientation of the semiconductor material is substantially inert to the wet chemical etching process.

13. The method according to any one of claims 1 to 12.

14. Further processing the optoelectronic device comprises: Using an ALD process, the third protective layer (33), in particular Al ２ O ３ on said sidewalls and said surface, said sidewalls and said surface encapsulating the remainder of said first mask layer (31), said conductive layer (14) and said active area (12) of said functional semiconductor stack; structuring the third protective layer (33) and the remainder of the first mask layer to expose a part of the conductive layer (14); and depositing a metal layer (40) on the third protective layer to electrically connect the conductive layers.

14. The method according to any one of claims 1 to 13.

15. Further processing the optoelectronic device comprises: encapsulating the optoelectronic device in a sacrificial layer; encapsulating the optoelectronic device with a filler material; forming an anchor (51) extending through the sacrificial layer by the filler material supporting the optoelectronic device; and removing the sacrificial layer.

15. The method according to any one of claims 1 to 14.

16. 1. An optoelectronic device, comprising: A first doped layer (11); A second doped layer (13); an active region (12) between the first doped layer and the second doped layer (13); a conductive layer (14) on the surface of said second doped layer (13); a structured non-conductive mask layer (31) on said conductive layer (14); a structured protective layer (33) on said non-conductive mask layer (31); a metal layer (40) on the structured protective layer (33), electrically connecting the conductive layer (14), the structured protective layer (33) extends over the sidewalls of the structured non-conductive mask layer (31), over the sidewalls of the conductive layer (14) and over the sidewalls of the active area (12); the sidewalls of the non-conductive mask layer (31) being substantially flush with the sidewalls of the conductive layer (14); Optoelectronic devices.

17. the sidewalls (120) of the active area are flush with the sidewalls of the conductive layer; 17. An optoelectronic device according to claim 16.

18. a second sidewall (130) laterally displaced relative to the sidewall (120) of the active region and extending along a portion of the first doped layer (11); An optoelectronic device according to claim 16 or 17.

19. The angle between the sidewall (120) of the active area and the second sidewall (130) is greater than 0°, in particular between 1° and 10°; An optoelectronic device according to any one of claims 16 to 18.

20. a layer of material between the sidewall of the conductive layer (14) and the protective layer; said material layer comprising the same material as said structured non-conductive mask layer (31); 20. An optoelectronic device according to any one of claims 16 to 19.

21. The material of the structured non-conductive mask layer (31) is SiN ｘ Including, An optoelectronic device according to any one of claims 16 to 20.

22. The conductive layer comprises a first metal layer, in particular Ag, and a transparent conductive oxide, in particular ITO; 22. An optoelectronic device according to claim 20 or 21.

23. 23. An optoelectronic device according to any one of claims 20 to 22, wherein the metal layer is positioned only on the top surface of the structured protective layer.

24. The structured protective layer (14) is made of Al ２ O ３ Including, 23. An optoelectronic device according to any one of claims 20 to 22.

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