Data transmission method and data transmission device

Abstract

An embodiment of this application provides a data transmission method and a data transmission device. The data transmission method includes the steps of generating a bit stream, the bit stream including data and a control word, the control word including a first field indicating start position information of the control word, a second field indicating end position information of the control word, and a third field used to carry link information indicating a wired serial link, and transmitting the bit stream on a wired serial link. The data transmission method can reduce the complexity of a control signal transmitted at a physical layer.

Description

[Technical field]

[0001] TECHNICAL FIELD Embodiments of this application relate to the field of communication networks, and in particular to a data transmission method and a data transmission device. [Background technology]

[0002] In communication network technology, communication devices usually communicate with each other over a data link, and a physical layer at a signal transmitting end transmits a bit stream over the link to a physical layer at a signal receiving end for signal exchange between the communication devices. The bit stream includes both an encoded data signal and a plurality of control signals indicating information such as a link configuration or a link status, so that the signal receiving end accurately decodes data from the bit stream. For example, the plurality of control signals include a control signal indicating a frame delimiter of a data packet and a control signal indicating a link bandwidth. The plurality of control signals are independent encoded segments. Moreover, the plurality of control signals are usually added to a specific position of the data signal for transmission.

[0003] However, with the continuous development of the operating rate at the physical layer and the more precise control on the link, more control signals need to be set to meet the requirements. As a result, the amount of control signals becomes large, which complicates the design at the physical layer in the communication device and increases the cost of the physical layer. Therefore, how to reduce the complexity of the control signals transmitted at the physical layer becomes a problem to be solved. Summary of the Invention

[0004] The data transmission method and data transmission device provided in this application can reduce the complexity of the control signal transmitted in the physical layer. To achieve the above objectives, the following technical solutions are used in this application:

[0005] According to a first aspect, an embodiment of the present application provides a data transmission method, which is applied at a transmitting end, and includes the steps of: generating a bit stream, the bit stream including data and a control word, the control word including a first field indicating start position information of the control word, a second field indicating end position information of the control word, and a third field used to carry link information indicating a wired serial link; and transmitting the bit stream over a wired serial link.

[0006] In this implementation, the transmitting end may be, for example, the interface controller shown in Figures 1, 4A and 4B and 5. The first field indicating the start position information of the control word may be, for example, the start field shown in Figure 2. The second field indicating the end position information of the control word may be, for example, the end field shown in Figure 2. The third field used to carry link information indicating a wired serial link may be, for example, the payload field shown in Figure 2.

[0007] In a conventional wired serial link, the coded segment is usually used to transmit data between two communication devices, realize link alignment, and transfer various information about the link, where one type of information is one coded segment. For example, information indicating link power consumption is a coded segment, and information indicating the status of each circuit in the link is a coded segment. In other words, there are multiple coded segments to realize link alignment. However, with the continuous development of the operating rate at the physical layer and more precise control on the link, more link information needs to be set to meet the requirements. As a result, the amount of link information becomes large, i.e., the number of coded segments becomes large, which complicates the design at the physical layer in the communication device and increases the design cost of the physical layer. The control word provided in this embodiment of this application is set in a structure including a first field, a second field, and a third field, and carries the link information in the third field. This realizes that one control word indicates multiple link information, reduces the complexity of the control signal transmitted at the physical layer, and simplifies the design at the physical layer. In addition, since the second field in the control word indicates the end position information of the control word, that is, the second field in the control word may limit the length of the control word. In addition, by flexibly adjusting the end position information of the control word, the amount of link information carried in the control word may be flexibly adjusted, providing flexibility of the control word.

[0008] Optionally, the end position information may be the length or end position of the control word, for example after a preset number of bits starting from the second field.

[0009] Optionally, the data is service data or training data.

[0010] In a possible implementation, the link information includes at least one of the following: the number of lanes for transmitting the first bitstream, the power consumption state of the hardware in the link, the operating state of the circuits in the link, or the gain of the codec used in the link.

[0011] In order to reduce the power consumption of the hardware in the link at the physical layer, the power consumption of each hardware in the link usually includes multiple types, such as low power consumption, medium power consumption, and high power consumption. For example, when the hardware such as a scrambler and a data distributor included in the link is in one of the following modes, namely, standby, sleep, or power off, the hardware in the link is in a low power consumption state. When a part of the hardware included in the link is in one of the following modes, namely, standby, sleep, or power off, and other parts of the hardware are in an operational state, the hardware in the link is in a medium power consumption state. When all components in the link are in an operational state, the hardware in the link is in a high power consumption state. For example, when the data transmitted is training data, this may indicate that the power consumption of each hardware in the link is low power consumption. When the data transmitted is service data, this may indicate that the power consumption of each hardware in the link is medium power consumption or high power consumption. The operational state of the circuit in the link may include, for example, a power on state or a power off state. For example, when the data to be transmitted is training data, the state of the codec circuit may be in a power-off state. When the data to be transmitted is service data, the state of the codec circuit may be in a power-on state. Therefore, the transmitting end may add information such as one of a plurality of power consumption states, information indicating an operating state of one of the circuits in the link, and information indicating the gain of the codec to the third field, and transmit the information to the receiving end.

[0012] In a possible implementation, the first and second fields instruct the receiving end to perform framing on the data.

[0013] In this possible implementation, the control word may be followed by the data content of the data. In other words, the first and second fields in the control word may be used as a frame header of the data frame. After identifying the first and second fields in the control word, the receiving end may determine the starting position of the data (i.e., the frame delimiter) and read the data from the bit stream. In this embodiment of the application, the first and second fields in the control word are used as the frame header of the data frame, so that the frame header of the data frame does not need to be further set. This can simplify the design of the bit stream.

[0014] In a possible implementation, there are multiple bit streams, there are multiple lanes on the wired serial link, the multiple bit streams correspond one-to-one to the multiple lanes, and the step of transmitting the bit streams on the wired serial link specifically includes the step of transmitting the corresponding multiple streams through the multiple lanes.

[0015] When there are multiple lanes on a wired serial link, one control word is set for each lane, so that the receiving end can accurately read data from the bit stream transmitted on each lane based on the control word in each lane, which improves the data reading accuracy of the receiving end.

[0016] In a possible implementation, the control word further comprises a fourth field indicating the lane number.

[0017] The fourth field may be, for example, the lane identifier field shown in FIG.

[0018] In this implementation, a fourth field in the control word indicating the lane number is set, so that the receiving end can adjust the sequence of data received from each lane according to each lane number, which improves the accuracy of the data received by the receiving end.

[0019] In a possible implementation, the first field includes multiple groups of identical fields, each group of fields including multiple bits, and the multiple groups of identical fields are used to compensate for the difference between the clock cycles of the sending end and the receiving end.

[0020] In this implementation, the transmitting end may encode the first field into a series of "0" and "1" signals, and then transmit the bit stream to the receiving end based on a local clock cycle over a wired serial link. After receiving the bit stream, the receiving end first recovers the clock cycle of the transmitting end from the first field, and then adds at least one group of fields to the multiple groups of identical fields or removes at least one group of fields from the multiple groups of identical fields based on an offset between the recovered clock cycle and the local cycle.

[0021] For example, a buffer queue may be disposed at the receiving end, and the receiving end writes the data carried in the first field into the buffer queue based on a clock cycle recovered from the first field. In addition, the receiving end may further read data from the buffer queue based on a local clock cycle. The two operations are performed simultaneously. When the receiving end detects that the writing rate of data into the buffer queue is greater than the reading rate of data from the buffer queue, this indicates that the clock cycle of the sending end is greater than the clock cycle of the receiving end. In this case, at least one group of fields is removed from the group of multiple identical fields included in the first field to ensure clock cycle synchronization between the sending end and the receiving end. When the receiving end detects that the writing rate of data into the buffer queue is less than the reading rate of data from the buffer queue, this indicates that the clock cycle of the sending end is less than the clock cycle of the receiving end. In this case, at least one group of fields from the group of multiple identical fields is added to the first field to realize clock cycle synchronization between the sending end and the receiving end.

[0022] In the prior art, since no structured control word is set, a dedicated sequence for compensating the difference between the clock cycle of the sending end and the clock cycle of the receiving end is usually set in the transmitted bit stream, and the sequence does not carry any useful data. In this embodiment of the present application, a group of multiple identical fields is set in the first field in the control word, so that the control word can achieve more functions. In other words, a dedicated sequence for compensating the difference between the clock cycle of the sending end and the clock cycle of the receiving end does not need to be further set in the bit stream. Compared with the prior art, the design in the physical layer can be simplified.

[0023] In a possible implementation, when the data is training data, generating the bit stream comprises appending a control word after the data to generate the bit stream.

[0024] According to a second aspect, an embodiment of the present application provides a data transmission method, which is applied at a receiving end, and includes the steps of: receiving a bit stream, the bit stream including data and a control word, the control word including a first field indicating start position information of the control word, a second field indicating end position information of the control word, and a third field used for carrying link information indicating a wired serial link; reading the control word from the bit stream based on the first field and the second field; and reading data from the bit stream based on the control word.

[0025] In this implementation, the receiving end may be, for example, the network interface card shown in Figure 1, Figure 4A and Figure 4B and Figure 5. The first field indicating the start position information of the control word may be, for example, the start field shown in Figure 2, the second field indicating the end position information of the control word may be, for example, the end field shown in Figure 2, and the third field used to carry link information indicating the wired serial link may be, for example, the payload field shown in Figure 2.

[0026] The control word provided in this embodiment of the application is set to a structure including a first field, a second field and a third field, and carries link information in the third field. This realizes that one control word indicates multiple link information, and can simplify the design in the physical layer. In addition, the second field in the control word indicates the end position information of the control word, that is, the second field in the control word may limit the length of the control word. In addition, by flexibly adjusting the end position information of the control word, the amount of link information carried in the control word may be flexibly adjusted, providing flexibility of the control word.

[0027] In a possible implementation, the method further comprises a step of adjusting at least one of the wired serial links based on link information, i.e., the power consumption state of the hardware in the link, the operating state of the circuitry in the link, or the gain of the codec used in the link.

[0028] In order to reduce the power consumption of the hardware in the link at the physical layer, the power consumption of each hardware in the link usually includes multiple types, such as low power consumption, medium power consumption, and high power consumption. For example, when the data to be transmitted is training data, this may indicate that the power consumption of each hardware in the link is low power consumption. When the data to be transmitted is service data, this may indicate that the power consumption of each hardware in the link is medium power consumption or high power consumption. The operating state of the circuit in the link may include, for example, a power-on state or a power-off state. For example, when the data to be transmitted is training data, the state of the codec circuit may be a power-off state. When the data to be transmitted is service data, the state of the codec circuit may be a power-on state. The receiving end adjusts the power consumption state of the hardware in the link to the power consumption state indicated by the third field, the operating state of one of the circuits in the link, and the gain of the codec based on one of the multiple power consumption states indicated by the third field, adjusts the operating state of the circuits in the link to the operating state indicated by the third field, and adjusts the gain of the codec to the gain indicated by the third field.

[0029] In a possible implementation, the step of reading data from the bit stream based on the control word includes the steps of determining a coding length of the control word based on the first field and the second field, identifying a frame start position of data from the bit stream based on the coding length of the control word, where the frame start position of data is located after the control word, and reading the data based on the frame start position of data.

[0030] In this possible implementation, the control word may be followed by the data content of the data. In other words, the first and second fields in the control word may be used as a frame header of the data frame. After identifying the first and second fields in the control word, the receiving end may determine the starting position of the data and read the data from the bit stream. In this embodiment of the application, the first and second fields in the control word are used as the frame header of the data frame, so that the frame header of the data frame does not need to be further set. This can simplify the design of the bit stream.

[0031] In a possible implementation, there are multiple bit streams, there are multiple lanes on the wired serial link, the multiple bit streams are received from the transmitting end through multiple corresponding lanes, the link information further includes a number of lanes for transmitting the multiple bit streams, and the control word further includes a fourth field indicating a lane number. Reading data from the bit stream based on the control word includes reading data from the bit stream received through the corresponding lane based on the number of lanes for transmitting the bit streams and the fourth field.

[0032] The fourth field may be, for example, the lane identifier field shown in FIG.

[0033] In a possible implementation, the method further includes removing data skew between the multiple lanes based on a sequence of the multiple received bit streams and a fourth field in each of the multiple control words in the multiple bit streams.

[0034] In a possible implementation, the first field includes a plurality of groups of identical fields, each group of fields including a plurality of bits. The method further includes performing one of the following operations based on a clock frequency offset between the receiving end and the transmitting end: deleting at least one group of fields from the plurality of groups of identical fields, or adding at least one group of fields to the plurality of groups of identical fields.

[0035] In this implementation, the transmitting end may encode the first field into a series of "0" and "1" signals, and then transmit the bit stream to the receiving end based on a local clock cycle over a wired serial link. After receiving the bit stream, the receiving end first recovers the clock cycle of the transmitting end from the first field, and then adds at least one group of fields to the multiple groups of identical fields or removes at least one group of fields from the multiple groups of identical fields based on an offset between the recovered clock cycle and the local cycle.

[0036] For example, a buffer queue may be disposed at the receiving end, and the receiving end writes the data carried in the first field into the buffer queue based on a clock cycle recovered from the first field. In addition, the receiving end may further read data from the buffer queue based on a local clock cycle. The two operations are performed simultaneously. When the receiving end detects that the writing rate of data into the buffer queue is greater than the reading rate of data from the buffer queue, this indicates that the clock cycle of the sending end is greater than the clock cycle of the receiving end. In this case, at least one group of fields is removed from the group of multiple identical fields included in the first field to ensure clock cycle synchronization between the sending end and the receiving end. When the receiving end detects that the writing rate of data into the buffer queue is less than the reading rate of data from the buffer queue, this indicates that the clock cycle of the sending end is less than the clock cycle of the receiving end. In this case, at least one group of fields from the group of multiple identical fields is added to the first field to realize clock cycle synchronization between the sending end and the receiving end.

[0037] In the prior art, since no structured control word is set, a dedicated sequence for compensating the difference between the clock cycle of the sending end and the clock cycle of the receiving end is usually set in the transmitted bit stream, and the sequence does not carry any useful data. In this embodiment of the present application, a group of multiple identical fields is set in the first field in the control word, so that the control word can achieve more functions. In other words, a dedicated sequence for compensating the difference between the clock cycle of the sending end and the clock cycle of the receiving end does not need to be further set in the bit stream. Compared with the prior art, the design in the physical layer can be simplified.

[0038] According to a third aspect, an embodiment of the present application provides a data transmission device. The data transmission device includes a processor and an interface. The processor is configured to generate a bit stream. The bit stream includes data and a control word, and the control word includes a first field indicating start position information of the control word, a second field indicating end position information of the control word, and a third field used to carry link information indicating a wired serial link. The interface transmits the bit stream over the wired serial link.

[0039] In a possible implementation, the link information includes at least one of the following: the number of lanes for transmitting the bitstream, the power consumption state of the hardware in the link, the operating state of the circuits in the link, or the gain of the codec used in the link.

[0040] In a possible implementation, the first and second fields instruct the receiving end to perform framing on the data.

[0041] In a possible implementation, there are multiple bit streams and there are multiple lanes on the wired serial link, with the multiple bit streams corresponding one-to-one to the multiple lanes, and the interface is specifically configured to transmit the corresponding multiple streams over the multiple lanes.

[0042] In a possible implementation, the control word further comprises a fourth field indicating the lane number.

[0043] In a possible implementation, the first field includes multiple groups of identical fields, each group of fields including multiple bits, and the multiple groups of identical fields are used to compensate for the difference between the clock cycles of the sending end and the receiving end.

[0044] According to a fourth aspect, an embodiment of the present application provides a data transmission device. The data transmission device includes a processor and an interface. The interface is configured to receive a bit stream. The bit stream includes data and a control word, and the control word includes a first field indicating start position information of the control word, a second field indicating end position information of the control word, and a third field used to carry link information indicating a wired serial link. The processor is configured to read the control word from the bit stream based on the first field and the second field, and read data from the bit stream based on the control word.

[0045] In a possible implementation, the processor is further configured to adjust at least one of the wired serial links based on link information, i.e., the power consumption state of hardware in the link, the operating state of circuits in the link, or the gain of a codec used in the link.

[0046] In a possible implementation, the processor is specifically configured to determine a coding length of the control word based on the first field and the second field, identify a frame start position of the data from the bit stream based on the coding length of the control word, the frame start position of the data being located after the control word, and read the data based on the frame start position of the data.

[0047] In a possible implementation, there are multiple bit streams, there are multiple lanes on the wired serial link, the multiple bit streams are received from the transmitting end through multiple corresponding lanes, the link information further includes a number of lanes for transmitting the multiple bit streams, and the control word further includes a fourth field indicating a lane number. The processor is specifically configured to read data from the bit stream received through the corresponding lane according to the number of lanes for transmitting the bit streams and the fourth field.

[0048] In a possible implementation, the processor is further configured to remove data skew between the multiple lanes based on a sequence of the multiple received bit streams and a fourth field in each of the multiple control words in the multiple bit streams.

[0049] In a possible implementation, the first field includes a plurality of groups of identical fields, each group of fields including a plurality of bits. The processor is further configured to perform one of the following operations based on a clock frequency offset between the data transmission device and the sending end: delete at least one group of fields from the plurality of groups of identical fields, or add at least one group of fields to the plurality of groups of identical fields.

[0050] According to a fifth aspect, an embodiment of the present application provides a computer-readable storage medium configured to store a computer program, which, when executed by a processor, realises the data transmission method in the first aspect or the data transmission method in the second aspect.

[0051] According to a sixth aspect, an embodiment of the present application provides a computer program product, which, when executed on a processor, realises the data transmission method in the first aspect or the data transmission method in the second aspect.

[0052] It should be understood that the technical solutions in the second to sixth aspects of this application are consistent with the technical solutions in the first aspect of this application, and the beneficial effects achieved by the aspects and corresponding feasible implementation manners are similar, and the details will not be described again. [Brief description of the drawings]

[0053] In order to more clearly describe the technical solutions in the embodiments of this application, the following briefly introduces the accompanying drawings for describing the embodiments of this application. The accompanying drawings in the following description merely illustrate some embodiments of this application, and it is obvious that those skilled in the art can still derive other drawings from these accompanying drawings without creative efforts. [Figure 1] FIG. 2 is a diagram of a hardware architecture of an electronic device according to an embodiment of the present application. [Diagram 2] FIG. 2 is a diagram of a frame structure of a control word according to an embodiment of the present application. [Figure 3A] FIG. 2 is a diagram of an eBCH codeword set according to an embodiment of the present application. [Figure 3B] FIG. 2 is a diagram of a coding structure of a lane identifier according to an embodiment of the present application. [Figure 4A] FIG. 2 is a diagram of a hardware architecture at the physical layer according to an embodiment of the present application. [Figure 4B] FIG. 2 is a diagram of a hardware architecture at the physical layer according to an embodiment of the present application. [Diagram 5] 1 is a flowchart of a data transmission method according to an embodiment of the present application. [Figure 6A] 4 is another flowchart of a data transmission method according to an embodiment of the present application. [Figure 6B] 4 is another flowchart of a data transmission method according to an embodiment of the present application. [Figure 7] FIG. 2 is a structural diagram of a data transmission device according to an embodiment of this application; [Figure 8] FIG. 2 is another structural diagram of a data transmission device according to an embodiment of this application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] The following clearly and completely describes the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. It is clear that the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art according to the embodiments of this application without creative efforts shall fall within the protection scope of this application.

[0055] The terms "first" or "second" and similar terms referred to herein do not denote any order, number or importance, but are merely used to distinguish between different components. Similarly, similar terms such as "one" or "a" also do not denote a number limitation, but denote at least one. Similar terms such as "coupled" are not limited to a direct physical or mechanical connection, but may include electrical connections that are equivalent to connections in the broadest sense, whether direct or indirect.

[0056] In the embodiments of this application, terms such as "example" or "for example" are used to provide an example, illustration, or explanation. Any embodiment or design manner described in the embodiments of this application as "example" or "for example" should not be described as being preferred or having more advantages than other embodiments or design manners. Strictly speaking, the use of terms such as "example", "for example", and the like is intended to present the related concept in a particular manner. In the description of the embodiments of this application, "plurality" means two or more, unless otherwise specified. For example, multiple lanes means two or more lanes.

[0057] The data transmission system provided in the embodiment of this application may include a transmitting end and a receiving end. Both the transmitting end and the receiving end may be electronic devices. For example, the electronic device may be a terminal device, for example, various types of portable devices such as mobile phones, PC computers, tablet computers, notebook computers, or wearable devices (for example, smart watches, AR devices, or VR devices). The electronic device may alternatively be a switch device, a router device, etc. In an application scenario, the transmitting end may be a terminal device, and the receiving end may be a router device. The terminal device communicates with the router device over a wired serial link and transmits a signal to the router device. In this application scenario, when the router device transmits a signal to the terminal device, the router device may alternatively be referred to as a transmitting end, and the terminal device may alternatively be referred to as a receiving end.

[0058] Moreover, the transmitting end and the receiving end may be a module, a chip, a circuit board, or a component with a chip or chipset, or a chipset disposed in the electronic device. The electronic device is, for example, the electronic device mentioned above. A network interface card may be disposed in the electronic device, so that the electronic device may access a network through the network interface card for communication. The network may be, for example, an Ethernet. In an application scenario, the transmitting end may be an interface controller integrated in the electronic device, and the receiving end may be a network interface card disposed in the electronic device. The interface controller may communicate with the network interface card over a wired serial link. The interface controller transmits a bit stream to the network interface card over the wired serial link, and the network interface card encapsulates the received bit stream into an Ethernet frame and transmits the Ethernet frame to the Ethernet. In this application scenario, after receiving the bit stream from the Ethernet, the network interface card needs to transmit the received bit stream to the interface controller. In this case, the interface controller is the transmitting end, and the network interface card is the receiving end. In the embodiment of this application, an example in which the transmitting end is an interface controller and the receiving end is a network interface card is used for explanation, but is not intended to limit the solution.

[0059] FIG. 1 is a diagram of a structure of an electronic device 100 according to an embodiment of this application. In FIG. 1, the electronic device 100 includes one or more processors. The one or more processors include, for example, an interface controller 10 and a central processing unit (CPU) 12. Optionally, the one or more processors may be integrated into one or more chips, and the one or more chips may be considered as a chipset. In an optional implementation manner, the interface controller 10 and the CPU 12 may be integrated into a system on chip (SOC) shown in FIG. 1, and devices or components such as a memory 13 and a direct memory access controller (DMAC) 14 may be further integrated into the SOC. Signals are transmitted between the interface controller 10, the CPU 12, the memory 13, and the DMAC 14 through a bus. The CPU 12 may execute software programs or software plug-ins, such as operating system software and application software. The memory 13 may store software programs or software plug-ins required for the execution of the CPU 12. Furthermore, the memory 13 may further store instructions and data necessary for execution by the CPU 12 , and the CPU 12 obtains the instructions and data from the memory 13 via the DMAC 14 .

[0060] As shown in FIG. 1, the electronic device 100 further includes a network interface card 11. The network interface card 11 may be located outside the SOC shown in FIG. The interface controller 10 includes an interface 101 and a processor 102. The network interface card 11 includes an interface 111 and a processor 112. The network interface card 11 is connected to the interface 101 in the interface controller 10 through the interface 111. In an optional implementation manner, the interface 101 and the interface 111 may be a serializer / deserializer (SerDes) interface. The interface 101 may be coupled to the interface 111 through various physical media (e.g., twisted pair or cable). Thus, the electronic device 100 accesses a network through the network interface card 11 and communicates with other devices (e.g., server devices or terminal devices) in the network for data exchange. In a possible implementation, the processor 102 and the processor 112 may separately include an encoder, a decoder, a control word generator, a link training state machine, and other components. In addition, the processor 102 and the processor 112 may optionally include a scrambler, a descrambler, and other components. For a more detailed structure of the interface controller 10 and the network interface card 11, please refer to the related description in Figures 4A and 4B.

[0061] In an embodiment of this application, the communication network model of the electronic device 100 may conform to the open systems interconnection reference model (OSI reference model) standard. The OSI reference model may specifically include an application layer, a transport layer, a data link layer, and a physical layer, and may further include more layers. This is not particularly limited in the embodiment of this application. The application layer may include application software running on the CPU 12, for example, a video playback application and an instant messaging application. The transport layer is used to describe the transport layer protocol specification of the system, including definition and arrangement of data types and structures, route control, bandwidth management, etc. The data link layer is used to encapsulate data packets provided by the transport layer into data frames and provide transparent transmission. The physical layer is used to define the link state, clock reference, data encoding, and circuits of the wired serial link required for data transmission and reception, and to provide a standard interface for the data link layer. The physical layer encodes the data frames to generate a bit stream and transmits the bit stream on the wired serial link. It should be noted that the interface controller 10 and the network interface card 11 provided in the embodiments of this application typically operate at the physical layer in the OSI standard.

[0062] In the execution process of the electronic device 100, the processor 102 in the interface controller 10 may obtain an original data packet (e.g., the CPU 12 may trigger the processor 102 to read the data packet from the memory 13). The processor 102 processes the obtained data packet (e.g., encapsulates the data packet into a data frame and performs Hamming coding), generates a bit stream, and outputs the bit stream to the network interface card 11 through the interface 101. The interface 111 in the network interface card 11 receives the bit stream, and the processor 112 in the network interface card 11 further processes the received bit stream (e.g., obtains a data frame through decoding, encapsulates the data frame into an Ethernet frame, and performs Manchester coding), and then transmits the data frame to the network. Similarly, after receiving a data frame from the network, the network interface card 11 may perform processing (e.g., performs Manchester decoding, removes the Ethernet frame, and performs Hamming coding), and then transmits the data frame to the interface controller 10 through the interface 111. After further processing the obtained data frames (e.g., performing decryption and decapsulation), the interface controller 10 generates data packets and stores the data packets in memory 13 or provides the data packets directly to the CPU 12.

[0063] In the embodiment of this application, in order to realize signal transmission with a low bit error rate, in addition to the data obtained by encoding the data frame, the bit stream transmitted by the interface controller 10 (i.e., the transmitting end) to the network interface card 11 (i.e., the receiving end) further includes a control word, as shown in FIG. 2. FIG. 2 shows a schematic diagram of the bit stream transmitted by the interface controller 10 to the network interface card 11. The control word indicates the link state, the clock reference, the data frame delimiter of the wired serial link and other information. Therefore, the physical layer of the receiving end determines the data frame delimiter, adjusts the clock reference, adjusts the link state, etc. based on the control word. The control word includes a start field indicating the start position information of the control word, an end field indicating the end position information of the control word, and a payload field used to carry instruction information. The instruction information carried by the payload field indicates the link information of the wired serial link.

[0064] In a conventional wired serial link, the coded segment is usually used to transmit data between two communication devices, realize link alignment, and transfer various information related to the link, where one type of information is one coded segment. For example, information indicating link power consumption is a coded segment, and information indicating the status of each circuit in the link is a coded segment. In other words, there are multiple coded segments to realize link alignment. However, with the continuous development of the operating rate at the physical layer and more precise control on the link, more link information needs to be set to meet the requirements. As a result, the amount of link information becomes large, i.e., the number of coded segments becomes large, which complicates the design at the physical layer in the communication device and increases the design cost of the physical layer. The control word provided in the embodiment of this application is set in a structure including a start field, an end field, and a payload field, and carries the link information in the payload field. This realizes that one control word indicates multiple link information, and can simplify the design at the physical layer. In addition, the end field in the control word indicates the end position information of the control word, i.e., the end field in the control word may limit the length of the control word. Furthermore, by flexibly adjusting the end position information of the control word, the amount of link information carried in the control word may be flexibly adjusted, providing flexibility for the control word.

[0065] It should be noted that in the bit stream shown in FIG. 2, the data is located to the left of the control word. In the process of transmitting the bit stream, the signal of the control word is transmitted first, and then the data signal is transmitted. In the implementation manner shown in FIG. 2, the data may be, for example, service data. Optionally, the data may be located to the right of the control word as an alternative. In the process of transmitting the bit stream, the data signal is transmitted first, and then the signal of the control word is transmitted. In this implementation manner, the data may be, for example, training data. Furthermore, since the data and the control word are coded as "0" and "1" signals in the physical layer, the control word may alternatively be set to any position of the data.

[0066] Fig. 2 further illustrates the frame structure of the control word. In Fig. 2, the control word includes a start field U_I indicating the start position information of the control word, an end field U_END indicating the end position information of the control word, and a payload field payload indicating link information of the wired serial link. The control word will be described in more detail below with reference to the frame structure of the control word illustrated in Fig. 2.

[0067] The start field U_I includes at least one group, i.e., multiple bits, of U_ID0-U_IDN. In other words, in the frame structure shown in FIG. 2, the first N+1 bits are the header of the control word, and the (N+1)-bit header may enable the network interface card 11 to identify the start field of the control word. In an optional realization manner of this embodiment of this application, the length of the start field U_I may vary within a preset range to ensure that the control word has a certain fault tolerance capability and compensate for the difference between the clock cycle of the sending end and the clock cycle of the receiving end. For example, the start field U_I may include multiple groups of repeated U_ID0-U_IDN, and the variable length of the start field U_I may be, for example, 8 bytes. Assume that N is 4 and U_ID0-U_IDN are 00101. The start field U_I may be 001010010100101, i.e., three groups of repeated code streams.

[0068] The interface controller 10 may encode the start field into a series of "0" and "1" signals and transmit the bit stream to the network interface card 11 based on a local clock cycle over a wired serial link. After receiving the bit stream, the network interface card 11 first recovers the clock cycle of the interface controller 10 from the start field, and then adds at least one group of fields to the group of multiple identical fields or removes at least one group of fields from the group of multiple identical fields based on an offset between the recovered clock cycle and the local cycle. Specifically, a buffer queue may be disposed in the network interface card 11, and the network interface card 11 writes data carried in the start field to the buffer queue based on the clock cycle recovered from the start field. Furthermore, the network interface card 11 may further read data from the buffer queue based on the local clock cycle. The two operations are performed simultaneously. When the network interface card 11 detects that the writing rate of data to the buffer queue is greater than the reading rate of data from the buffer queue, this indicates that the clock cycle of the interface controller 10 is greater than the clock cycle of the network interface card 11. In this case, one or more groups of U_ID0-U_IDN in the start field U_I are deleted to ensure clock cycle synchronization between the interface controller 10 and the network interface card 11. When the network interface card 11 detects that the rate at which data is written to the buffer queue is less than the rate at which data is read from the buffer queue, this indicates that the clock cycle of the interface controller 10 is less than the clock cycle of the network interface card 11.In this case, one or more groups of U_ID0 to U_IDN are added to the start field U_I to achieve clock cycle synchronization between the interface controller 10 and the network interface card 11.

[0069] The end field U_END indicates end position information of the control word. The end position information may be, for example, the length or end position of the control word. The end position may be, for example, a position after a preset number of bits starting from the end field U_END. Thus, after identifying the end field U_END from the control word, the network interface card 11 may count backward a preset number of bits from the end field to determine that the code stream of the control word has ended.

[0070] In this possible implementation, the control word may be followed by the data content. In other words, the start field and end field in the control word may be used as the frame header of the data frame. After identifying the start field and end field in the control word, the receiving end may determine the start position of the data (i.e., the frame delimiter) and read the data from the bit stream. In the embodiment of this application, the start field and end field in the control word are used as the frame header of the data frame, so that the frame header of the data frame does not need to be further set. This can simplify the design of the bit stream.

[0071] The payload field payload is used to carry link information. The link information may include, but is not limited to, one or more of the following: clock cycles for adding a control word to data, power consumption state of hardware in the link, operation state of circuits in the link, and output gain of codec circuits used in the link. For example, the power consumption state of hardware in the link includes, for example, three states: low power consumption, medium power consumption, and high power consumption. For example, when hardware such as a scrambler and a data distributor included in the link are in one of the following modes: standby, sleep, or power off, the hardware in the link is in a low power consumption state. When a part of the hardware included in the link is in one of the following modes: standby, sleep, or power off, and other parts of the hardware are in an operation state, the hardware in the link is in a medium power consumption state. When all components in the link are in an operation state, the hardware in the link is in a high power consumption state. For example, when the data transmitted is training data, this may indicate that the power consumption of each hardware in the link is low power consumption. When the data to be transmitted is service data, this may indicate that the power consumption of each hardware in the link is medium power consumption or high power consumption. The operating state of the circuit in the link may include, for example, a power-on state or a power-off state. For example, when the data to be transmitted is training data, the state of the codec circuit may be a power-off state. When the data to be transmitted is service data, the state of the codec circuit may be a power-on state. The gain of the codec in the link may include, for example, gain 1, gain 2, and gain 3.

[0072] In an optional implementation, the payload field may include two parts, namely a type field and a detail field. The type field indicates various types of link information, and the detail field indicates specific parameters corresponding to each type of link information. For example, the link information includes a power consumption state of the hardware in the link, an operating state of the circuit in the link, or a gain of the codec in the link. The type field indicates that the link information includes a power consumption state of the hardware in the link and a gain of the codec in the link. The detail field further indicates that the power consumption state of the hardware in the link is a medium power consumption state, and the gain of the codec in the link is a gain of 2. Therefore, the network interface card 11 may determine the link information and the parameters corresponding to the link information based on the type field and the detail field to adjust the link.

[0073] In this embodiment of the application, the wired serial link used to transmit the bit stream between the interface controller 10 and the network interface card 11 may include one lane, or may include multiple lanes based on the bandwidth of the wired serial link. In other words, the bit stream may be transmitted between the interface controller 10 and the network interface card 11 through one lane, or the bit stream may be transmitted through multiple lanes. When the interface controller 10 transmits the bit stream to the network interface card 11 through multiple lanes, in an optional implementation manner, in addition to data, the bit stream transmitted through each lane may further include a control word. In addition to the above fields, each control word may further include a lane identifier field Lane, which indicates a link number, as shown in FIG. 2. The network interface card 11 may realize lane reversal based on the lane identifier field Lane, and may eliminate data skew between data transmitted through the lanes. Furthermore, the interface controller 10 may transmit the bit stream to the network interface card 11 through a fixed number of lanes, or may transmit the bit stream to the network interface card 11 through a variable number of lanes. When the interface controller 10 transmits the bit stream to the network interface card 11 through a variable number of lanes, in an optional implementation manner, the link information carried in the payload field may further include a link bandwidth (i.e., the number of lanes for transmitting the bit stream). The network interface card 11 may receive the bit stream from a corresponding lane based on the link information.

[0074] In conclusion, it can be seen that in the control word, the start field, the end field and the payload field are set, and the lane identifier field is optionally set, so that the control word can indicate more information, which reduces the complexity of the control word transmitted at the physical layer.

[0075] Based on the above frame structure of the control word, in a possible implementation, in the embodiment of this application, the control word may be coded with an error correction coding scheme. The interface controller 10 transmits a correctable code. The network interface card 11 can automatically find errors and automatically correct errors in the code word transmission. The error correction coding may include, but is not limited to, forward error correction coding, Hamming coding, and extended Bose-Chaudhuri-Hocquenghem (eBCH) coding. The Hamming code is a linear code. For a code block with a length of m bits, there are n redundant bits, and the remaining bits are payload bits. Each redundant bit is obtained by performing an exclusive-or operation on several payload bits in a specific manner. The Hamming code coding can correct any single bit error. The eBCH code is also a linear code, and the eBCH coding can correct multiple bit errors in a code block. In the following, eBCH coding is used as an example to describe the control word coding method in detail by using a concrete example. In the embodiment of this application, an eBCH code set may be constructed first. For example, an eBCH code set may include 32 codes, and the structure of each code may be BCH(16,5,1), where 16 (bits) is the coding length, 5 (bits) is the payload length, and 1 (bit) is the check coding length. The Hamming distance between any two codes in the eBCH code set is 8. In other words, the number of different bits between any two codes is 8. The eBCH codeword set is shown in FIG. 3A.

[0076] From Figure 3A, it can be seen that the eBCH codeword set includes 32 codes, namely CW0 to CW31, and each code is 16 bits long. The number of different bits between any two codes is 8. Based on the eBCH code constructed in Figure 3A, the specific instances of the control words in this embodiment of this application are shown in Table 1. [Table 1]

[0077] From the control word instance shown in Table 1, it can be seen that one control word contains (4*N+27) bytes, i.e., byte 0 to byte (4*N+27). The number of bytes in the control word start field may range from 4 to 20. The codes of the control word start field are CW21 and CW28. In other words, the lower 16 bits of the control word start field are code CW28 shown in Table 1, and the upper 16 bits are code CW21 shown in Table 1. The codes of the control word end field are CW22 and CW8. In other words, the lower 16 bits of the control word end field are code CW22 shown in Table 1, and the upper 16 bits are code CW8 shown in Table 1.

[0078] The lane identifier field is shown in FIG. 3B. Assume that the maximum link bandwidth between the interface controller 10 and the network interface card 11 is 32 lanes, namely, lane 0 to lane 31 shown in FIG. 3B. In this case, the identifier of each lane may be represented by four codes, namely, 64 bits. The lane 2 shown in FIG. 3B is used as an example. From FIG. 3B, it can be seen that the lane 2 is represented by four codes, namely, CW3, CW9, CW3 and CW9. For the specific bits of CW3 and CW9, refer to Table 1. From FIG. 3B, it can be further seen that among the 64 bits, bits [0 to 15] are CW3, bits [16 to 31] are CW9, bits [32 to 47] are CW3 and bits [48 to 63] are CW9. For the detailed codes of other lanes, refer to FIG. 3A and FIG. 3B. Details will not be described.

[0079] It should be noted that Table 1, Table 2, Table 3, and the tables shown in FIGS. 3A and 3B may be pre-stored in the interface controller 10 and the network interface card 11 separately. [Table 2] [Table 3]

[0080] From Table 2, it can be seen that the link information includes four types of information, namely, forward error correction (FEC) encoder gain, link bandwidth, hardware power consumption, and control word appending period. Each type of information is represented by two codes (i.e., 32 bits). Table 2 shows that the codes of FEC gain are CW8 and CW10, that is, of the 32 bits representing FEC gain, the lower 16 bits are CW10, and the upper 16 bits are CW8. The FEC gain further includes four modes, namely, bypass FEC, FEC gain 1, FEC gain 2, and FEC gain 3, as shown in Table 3. It is assumed that the type field in the control word transmitted by the interface controller 10 to the network interface card 11 includes CW8 and CW10, and the detail field includes CW9 and CW10. After receiving the bit stream, the network interface card 11 obtains the type field and the detail field of the control word through analysis. Network interface card 11 finds from Table 2 that CW8 and CW10 indicate FEC gain. Then, network interface card 11 further compares CW3 and CW9 with the codes corresponding to the FEC gain in Table 3, and finds that the FEC gain is FEC gain 1. In this case, network interface card 11 may adjust the FEC gain to gain 1.

[0081] Table 2 shows that the codes of link bandwidth are CW10 and CW22, that is, of the 32 bits indicating link bandwidth, the lower 16 bits are CW10 and the upper 16 bits are CW22. The link bandwidth further includes seven modes shown in Table 3, namely X0, X1, X2, X4, X8, X16 and X32. Assume that in the type field in the control word transmitted by the interface controller 10 to the network interface card 11, the first 32 bits are CW8 and CW10, the last 32 bits are CW10 and CW22, and in the detail field, the first 32 bits are CW9 and CW10, and the last 32 bits are CW9 and CW21. After receiving the bit stream, the network interface card 11 finds through analysis that the first 32 bits of the type field in the control word indicate FEC gain and the last 32 bits indicate link bandwidth. Then, the network interface card 11 compares the first 32 bits of the detail field with the information corresponding to the FEC gain in Table 3, and compares the last 32 bits of the detail field with the information corresponding to the link bandwidth in Table 3, and finds that the FEC gain is FEC gain 1 and the link bandwidth is X1. In this case, the network interface card 11 may adjust the FEC gain to gain 1 and obtain data through one lane. It should be noted that the lanes used in each link bandwidth may further be pre-agreed between the physical layer of the interface controller 10 and the physical layer of the network interface card 11. For example, when one lane is used to transmit service data, it may be pre-agreed that the service data is transmitted through the lane whose lane identifier is lane 0. Alternatively, when four lanes are used to transmit service data, it may be pre-agreed that the service data is transmitted through the lanes whose lane identifiers are lane 0 to lane 3.It should be further noted that when the type field of the control word indicates link bandwidth information and the detail field is the code CW3 and the code CW9, this indicates that the transmission of service data by the interface controller 10 to the network interface card 11 is terminated and the data transmitted in the next period is training data. In other words, when the information indicating the link bandwidth in the control word is X0, this indicates that the transmission of service data is terminated and the data transmitted in the next period is training data. When the information indicating the link bandwidth in the control word is any one of the information other than X0, this indicates that the data transmitted by the interface controller 10 to the network interface card 11 is service data. Therefore, the code indicating the link bandwidth may further indicate a switch between service data and training data.

[0082] When the control word transmitted by the interface controller 10 to the network interface card 11 includes information indicating the power consumption of the hardware and the control word addition period, the analysis of the control word by the network interface card 11 and how it determines the link information that needs to be adjusted is similar to that of the FEC encoder gain and the link bandwidth, and the details will not be described again.

[0083] Based on the structure of the electronic device 100 shown in FIG. 1 and the frame structure of the control word shown in FIG. 2, FIG. 4A and FIG. 4B are diagrams of the hardware structure in the physical layer of the interface controller 10 according to an embodiment of this application. It should be noted that the hardware structure in the physical layer of the network interface card 11 may be the same as the hardware structure in the physical layer of the interface controller 10. In this embodiment of this application, the hardware in the physical layer of the interface controller 10 is used as an example for explanation. As shown in FIG. 4A and FIG. 4B, the physical layer of the interface controller 10 includes an encoder 101, a data distributor 102, a control word generator 103, a multiplexer 104, a link training state machine 105, a scrambler 106, a serializer / deserializer 107, a descrambler 108, a control word decoder 109, a data deskewer 1010 and a decoder 1011. It can be understood that the physical layer of the interface controller 10 may further include more circuits, modules or components, which is not particularly limited in this embodiment of this application. The components included in the physical layer of the interface controller 10 may be integrated into one or more chips. The components may be realized by using hardware circuits, or some components may be realized by using hardware driven by software. In a possible implementation, some components may be integrated into the same processor, which executes the functions corresponding to the components or modules. For example, the encoder 101 and the data distributor 102 may be integrated into the same processor, which realizes the data encoding and allocation functions. Furthermore, the physical layer of the network interface card 11 may have the same or similar components as the interface controller 10.4A and 4B, the physical layer of the network interface card 11 includes an encoder 111, a data distributor 112, a control word generator 113, a multiplexer 114, a link training state machine 115, a scrambler 116, a serializer / deserializer 117, a descrambler 118, a control word decoder 119, a data deskewer 1110 and a decoder 1111. Hereinafter, the components or functions of the physical layers of the interface controller 10 and the network interface card 11 will be described by using an example in which the physical layer of the interface controller 10 transmits a bit stream to the physical layer of the network interface card 11.

[0084] In the physical layer of the interface controller 10, the encoder 101 is configured to encode a data frame to be transmitted in the data link layer to generate encoded data. The encoding may be, for example, forward error encoding, error detection and retransmission encoding, or hybrid error correction encoding. The data distributor 102 is configured to divide the encoded data into a plurality of data streams (hereinafter referred to as service data), and allocate the plurality of data streams to a plurality of lanes, with one lane corresponding to one data. The link training state machine 105 is configured to generate link information and provide the generated link information to the control word generator 103. The control word generator 103 generates the control word based on the link information and the frame structure of the control word shown in FIG. 2. The link information may include, for example, a link power consumption state, a link output gain, and a link encoding mode. Furthermore, the link training state machine 105 is further configured to control the multiplexer 104 to selectively form a path between one of the plurality of input ends and an output end based on a current state (e.g., a service data transmission state, a link training state, or a link reset state) and a clock cycle. 4A and 4B show that the multiplexer 104 includes three inputs. One input is coupled to the data distributor 102, one input is configured to input training data, and the other input is coupled to the control word generator 103. In other words, the multiplexer 104 outputs one of the service data, the training data, or the control word to the scrambler 106 under the control of the link training state machine 105. It should be noted that the service data in this embodiment of the application may be data generated after data, such as audio data and video data input by a user by using an application program, is encapsulated and encoded in the application layer, the transport layer, the data link layer, and the physical layer. The training data is used to test and adjust multiple lanes in the link training phase.The scrambler 106 scrambles the received data stream or control word and provides the scrambled data stream to the serializer / deserializer 107. The serializer / deserializer 107 converts the received multiple parallel low-speed bit streams into high-speed serial bit streams and transmits the high-speed serial bit streams to the network interface card 11 through multiple lanes. It should be further noted that the number of lanes is the same as the number of transmitted bit streams, and each bit stream includes data and control words. Under the control of the link training state machine 105, the control words may be added at any position to the corresponding data. Preferably, the control words may be added before the data.

[0085] In the physical layer of the network interface card 11, the serializer / deserializer 117 receives a serial bit stream signal on a lane, converts the serial bit stream into multiple parallel bit streams, and provides the multiple parallel bit streams to the descrambler 118. The descrambler 118 descrambles the multiple parallel bit streams, and outputs the descrambled bit streams to the control word decoder 119. Based on the frame structure of the control word shown in FIG. 4A and FIG. 4B, the control word decoder 119 identifies a control word from each bit stream, and parses the control word to obtain indication information in the payload field. The indication information indicates link information. For example, the indication information indicates that the link enters an intermediate power consumption state and indicates that the link coding mode is a forward error coding mode. The control word decoder 119 provides the obtained indication information to the link training state machine 115, and provides data and a lane identifier corresponding to each data to the data deskewer 1110. The link training state machine 115 performs a corresponding action based on the indication information. For example, the link is set to a medium power consumption state and a coding mode (e.g., a forward error coding mode) is provided to the decoder 1111. The data deskew unit 1110 performs deskew on the data stream and provides the deskewed data stream to the decoder 1111. The decoder 1111 decodes the data stream based on the coding mode in a corresponding decoding mode and provides the decoded data to the data link layer of the network interface card 11.

[0086] Based on the architecture of the electronic device 100 shown in FIG. 1, the frame structure of the control word shown in FIG. 2, and the hardware architecture in the physical layer of the interface controller 10 (or the network interface card 11) shown in FIG. 4A and FIG. 4B, the embodiment of this application further provides a data transmission method. The data transmission method may be used in the electronic device 100 shown in FIG. 1. The data transmission method provided in the embodiment of this application is described below by using an example in which the interface controller 10 is the transmitting end and the network interface card 11 is the receiving end. In the data transmission method provided in the embodiment of this application, the transmitting end and the receiving end of the data transmission method may be realized by one or more components shown in FIG. 2. It should be noted that in this embodiment of this application, the interface controller 10 may transmit a control word to the network interface card 11 in any data transmission phase. For example, the control word may be added to the training data transmitted in the link training phase, the control word may be added to the service data transmitted in the service data transmission phase, or the control word may be added to the training data transmitted in the link reset phase. It should be further noted that the control word may be set before the service data, may be set at any position of the service data based on the clock cycle, may be set before the training data, or may be set after the training data, which is not particularly limited in this embodiment of this application. Figure 5 shows a procedure 500 of a data transmission method according to an embodiment of this application. The data transmission method includes the following steps:

[0087] Step 501: The interface controller 10 generates a bit stream, the bit stream including data and control words, the control words including a start field indicating start position information of the control word, an end field indicating end position information of the control word, and a payload field used to carry link information indicating a wired serial link. Step 502: The interface controller 10 transmits the bit stream on the wired serial link.

[0088] Step 503: The network interface card 11 reads a control word from the bit stream based on the start field and the end field.Step 504: Reads data from the bit stream based on the control word.

[0089] In this embodiment, the data may be, for example, either service data or training data. The control word may have, for example, a structure as shown in Fig. 2. The link information may include, but is not limited to, one or more of the following: clock cycles for adding the control word to the data, power consumption status of the hardware in the link, operating status of the circuits in the link, and output gain of the codec circuit used in the link.

[0090] In this implementation, the start and end fields of the control word may indicate the length of the control word. For example, after reading the start field, the network interface card 11 identifies that the bit stream includes a control word. After reading the end field, the network interface card 11 identifies that the position after a preset number of bits starting from the field is the end position of the control word. Furthermore, the control word may be followed by the data content of the data. In other words, the start and end fields of the control word may be used as a frame header of a data frame. After identifying the start and end fields in the control word, the receiving end may determine the start position of the data and read the data from the bit stream.

[0091] The control word provided in the embodiment of this application is set to a structure including a start field, an end field and a payload field, and carries link information in the payload field. This realizes that one control word indicates multiple link information, and can simplify the design in the physical layer. Furthermore, the end field in the control word indicates the end position information of the control word, that is, the end field in the control word may limit the length of the control word. Furthermore, by flexibly adjusting the end position information of the control word, the amount of link information carried in the control word may be flexibly adjusted, providing flexibility of the control word.

[0092] 6A and 6B, the following describes the data transmission method provided in the embodiment of this application by using a more specific scenario and example in which the bit stream includes training data and control words, and the bit stream includes service data and control words, and an example in which the interface controller 10 transmits data to the network interface card 11 on four lanes. Figures 6A and 6B show a procedure 600 of the data transmission method according to the embodiment of this application. The data transmission method includes the following steps:

[0093] Step 601: The interface controller 10 generates bit streams B0 to B3 by adding control words C0 to C3 to training data D0 to D3, respectively. This step is a link training phase. The link training phase is used to match the link state of the interface controller 10 with the link state of the network interface card 11. In this step, the interface controller 10 may assign the preset training data D0 to D3 to lane 0 to lane 3. The interface controller 10 may further generate the control words C0 to C3 based on the current link information (e.g., the link enters a medium power consumption state, each hardware circuit at the physical layer is in a power-on state, the gain of the link encoder at the physical layer is "1", and the link coding mode is forward error coding), the clock cycle for adding the control words to the training data, and the frame structure of the control words shown in FIG. 2. The lane identifier field of control word C0 indicates lane 0, the lane identifier field of control word C1 indicates lane 1, the lane identifier field of control word C2 indicates lane 2, and the lane identifier field of control word C3 indicates lane 3. Furthermore, the data carried in the start field, end field, and payload field in control word C0 to control word C3 may be the same. Then, interface controller 10 adds control word C0 to control word C3 to training data D0 to training data D3, respectively, to generate bit stream B0 to bit stream B3. Step 602: Interface controller 10 simultaneously transmits bit stream B0 to bit stream B3 to network interface card 11 through lane 0 to lane 3, respectively.

[0094] Step 603: The network interface card 11 identifies the control words C0 to C3 from the bit streams B0 to B3 based on the start field indicating the start position of the control words C0 to C3 and the end field indicating the end position of the control words C0 to C3, respectively. Step 604: The network interface card 11 adjusts the link alignment sequence based on the lane identifier carried in the lane identifier field in the control words C0 to C3. This step is used to align the link number with the data stream sequence. For example, the interface controller 10 transmits the bit streams B0-B1-B2-B3 through lane 0-lane 1-lane 2-lane 3, respectively, and the data stream received by the network interface card 11 from lane 0-lane 1-lane 2-lane 3 is actually B3-B2-B1-B0. In other words, the lane numbers in the interface controller 10 are completely reversed to the lane numbers in the network interface card 11. The network interface card 11 may re-mark the lane numbers in the network interface card 11 based on the lane identifier field in the control word to achieve alignment with the lane numbers in the interface controller 10. Step 605: The network interface card 11 adjusts the link state based on the link information indicated by the payload fields in the control words C0 to C3. For example, the link information indicates that the link enters a medium power consumption state, each hardware circuit in the physical layer is in a power-on state, and the gain of the link encoder in the physical layer is "1". Based on the link information, the network interface card 11 adjusts the power consumption state of the hardware circuits such as amplifiers and encoders in the link to a medium power consumption state, adjusts the gain of the link encoder to "1", etc. Step 606: The network interface card 11 aligns the data transmitted through the lanes based on the sequence of receiving the bit streams B0 to B3.

[0095] Step 607: The interface controller 10 adds the control word C4 to the control word C7 to the training data D4 to the training data D7, respectively, to generate bit streams B4 to B7, and the payload fields of the control word C4 to the control word C7 carry indication information indicating the transmission of service data in the next period. This step is in the link training phase. In step 601, after the interface controller 10 adds the link information to the payload fields and provides the payload fields to the network interface card 11, the interface controller 10 may further add indication information indicating the transmission of service data in the next period to the payload fields of the control word C4 to the control word C7. The payload fields of the control word C4 to the control word C7 may further include the link information described in step 601. Furthermore, the control word C4 to the control word C7 further include a start field, an end field and a lane identifier field. The interface controller 10 adds the control word C4 to the control word C7 to the training data D4 to the training data D7, respectively, to generate bit streams B4 to B7. Step 608: The interface controller 10 simultaneously transmits bit streams B4 to B7 to the network interface card 11 via lane 0 to lane 3, respectively.

[0096] Step 609: The interface controller 10 adds the control word C8 to the control word C111 to the service data D8 to the service data D111, respectively, to generate the bit stream B8 to the bit stream B111. In this step, the interface controller 10 may obtain a data frame at the data link layer. Based on a preset encoding format (e.g., a forward error encoding format), the interface controller 10 encodes the data frame to generate the service data D8 to D11. Then, the interface controller 10 may assign the service data D8 to D11 to lane 0 to lane 3. Then, the interface controller 10 generates the control word C8 to the control word C11 based on the current link information, the number of lanes used, the clock period for adding the control word to the training data, and the frame configuration of the control word shown in FIG. 2. The number of lanes used is carried in the payload field of the control word C8 to the control word C11. Finally, the interface controller 10 adds the control word C8 to the control word C111 to the training data D8 to the training data D111, respectively, to generate the bit stream B8 to the bit stream B111. In an optional implementation manner, the control word C8 to the control word C111 may be added to the preset positions of the service data D8 to the service data D111, respectively. The preset positions may be, for example, before the service data. Step 610: The interface controller 10 simultaneously transmits the bit stream B8 to the bit stream B111 to the network interface card 11 through lane 0 to lane 3, respectively.

[0097] Step 611: The network interface card 11 identifies the control words C8 to C111 from the bit streams B8 to B111, respectively, and reads the service data D8 to D111 from the bit streams B8 to B111 based on the start field indicating the start position of the control words C8 to C111 and the end field indicating the end position of the control words C8 to C111. In this step, the network interface card 11 may perform frame delimitation on the service data based on the position of the control word in the bit stream, that is, may determine the start position of the service data. In an optional implementation manner, the position of the service data in the bit stream is a preset position after the control word. For example, the second bit after the end bit of the control word is the start bit of the service data. After reading the end field of the control word, the network interface card 11 may determine the end bit of the control word, so that the network interface card 11 may read the service data from the second bit after the end bit of the control word. Step 612: The network interface card 11 decodes the read service data D8 to D111 according to the encoding format used by the interface controller 10 to obtain a decoded data frame.

[0098] It should be noted that the procedure 600 of the data transmission method is an example. It can be understood that the data transmission method provided in the embodiment of this application may include more or less procedures than the procedure 600. For example, before step 604 and after step 603, the network interface card 11 may further transmit information indicating that the link setting is completed to the interface controller 10. In another example, before step 604 and after step 603, the network interface card 11 may further transmit a bit stream to the interface controller 10. The bit stream includes training data and a control word added to the training data, and the control word indicates a link state of the physical layer of the network interface card 11.

[0099] To realize the above functions, it can be understood that the interface controller includes corresponding hardware and / or software modules for performing the functions. With reference to the steps of each example described in the embodiments disclosed in this specification, this application may be realized in the form of hardware, or in the form of a combination of hardware and computer software. Whether the functions are performed by hardware or by hardware driven by computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to realize the described functions for each specific application with reference to the embodiments. However, the implementation manner should not be considered to go beyond the scope of this application.

[0100] In an embodiment, the components included in the interface controller 10 shown in FIG. 1 may be divided into functional modules based on the above example of the method. For example, components corresponding to functions may be divided, or two or more components having functions may be integrated into one processing module. The integrated processing module may be realized in the form of hardware. In the embodiment, it should be noted that the division into modules is an example and is merely a logical division of functions. In the actual implementation manner, other division manners may be used. When the integrated module is used, FIG. 7 is a possible diagram of a data transmission device 700. As shown in FIG. 7, the data transmission device 700 may include a processing unit 701 and a sending unit 702. The above device may be further expanded. The processing unit 701 is configured to generate a bit stream. The bit stream includes data and a control word, and the control word includes a first field indicating a start position information of the control word, a second field indicating an end position information of the control word, and a third field used to carry link information indicating a wired serial link. The sending unit 702 is configured to send the bit stream on the wired serial link.

[0101] In a possible implementation, the link information includes at least one of the following: the number of lanes for transmitting the bitstream, the power consumption state of the hardware in the link, the operating state of the circuits in the link, or the gain of the codec used in the link.

[0102] In a possible implementation, the first and second fields instruct the receiving end to perform framing on the data.

[0103] In a possible implementation, there are multiple bit streams and there are multiple lanes on the wired serial link, and the multiple bit streams correspond one-to-one to the multiple lanes. The transmitting unit 702 is specifically configured to transmit the corresponding multiple streams over the multiple lanes.

[0104] In a possible implementation, the control word further comprises a fourth field indicating the lane number.

[0105] In a possible implementation, the first field includes multiple groups of identical fields, each group of fields including multiple bits, and the multiple groups of identical fields are used to compensate for the difference between the clock cycles of the sending end and the receiving end.

[0106] The data transmission device 700 provided in this embodiment is used in a data transmission method performed by the interface controller 10, and can achieve the same effect as the method or device of the above implementation manner. Specifically, the modules corresponding to FIG. 7 may be realized by software, hardware, or a combination thereof. For example, each module may be realized in the form of software, corresponding to the processor 102 and the interface 101 corresponding to the modules in FIG. 1, and configured to drive the corresponding components to operate. Alternatively, each module may include two parts, that is, a corresponding component and a corresponding driver software, that is, may be realized by using a combination of software and hardware. Therefore, it may be considered that the data transmission device 700 logically includes the interface controller 10 shown in FIG. 1 and FIG. 4A and FIG. 4B, and each module includes at least a driver software program of a corresponding function. Details will not be described in this embodiment.

[0107] In an embodiment, the components included in the interface card 11 shown in FIG. 1 may be divided into functional modules based on the above method examples. For example, components corresponding to functions may be divided, or two or more components having functions may be integrated into one processing module. The integrated processing module may be realized in the form of hardware. In the embodiment, it should be noted that the division into modules is an example and is merely a logical functional division. In the actual implementation manner, other division manners may be used. When an integrated module is used, FIG. 8 is a possible diagram of a data transmission device 800. As shown in FIG. 8, the data transmission device 800 may include a receiving unit 801 and a processing unit 802. The above device may be further expanded. The receiving unit 801 is configured to receive a bit stream, the bit stream including data and a control word, the control word including a first field indicating a start position information of the control word, a second field indicating an end position information of the control word, and a payload field used to carry link information indicating a wired serial link. The processing unit 802 is configured to read a control word from the bitstream based on the first field and the second field, and to read data from the bitstream based on the control word.

[0108] In a possible implementation, the processing unit 802 is further configured to adjust at least one of the wired serial links based on link information, i.e., the power consumption state of the hardware in the link, the operating state of the circuitry in the link, or the gain of the codec used in the link.

[0109] In a possible implementation, the processing unit 802 is specifically configured to determine a coding length of the control word based on the first field and the second field, identify a frame start position of data from the bit stream based on the coding length of the control word, where the frame start position of data is located after the control word, and read the data based on the frame start position of data.

[0110] In a possible implementation, there are multiple bit streams, there are multiple lanes on the wired serial link, the multiple bit streams are received from the transmitting end through multiple corresponding lanes, the link information further includes a number of lanes for transmitting the multiple bit streams, and the control word further includes a lane identifier field indicating a lane number. The processing unit 802 is specifically configured to read data from the bit stream received through the corresponding lane according to the number of lanes for transmitting the bit streams and the lane identifier field.

[0111] In a possible implementation, the processing unit 802 is further configured to remove data skew between the multiple lanes based on a sequence of the multiple received bit streams and a lane identifier field in each of the multiple control words in the multiple bit streams.

[0112] In a possible implementation, the first field includes multiple groups of identical fields, and each group of fields includes multiple bits. The processing unit 802 is further configured to perform one of the following operations based on a clock frequency offset between the data transmission device and the sending end: delete at least one group of fields from the multiple groups of identical fields, or add at least one group of fields to the multiple groups of identical fields.

[0113] The data transmission device 800 provided in this embodiment is used in a data transmission method performed by the network interface card 11, and can achieve the same effect as the method or device of the above implementation manner. Specifically, the modules corresponding to FIG. 8 may be realized by software, hardware, or a combination thereof. For example, each module may be realized in the form of software, corresponding to the interface 111 and the processor 112 corresponding to the modules in FIG. 1, and configured to drive the corresponding components to operate. Alternatively, each module may include two parts, that is, a corresponding component and a corresponding driver software, that is, may be realized by using a combination of software and hardware. Therefore, it may be considered that the data transmission device 500 logically includes the network interface card 11 shown in FIG. 1 and FIG. 4A and FIG. 4B, and each module includes at least a driver software program of a corresponding function. Details will not be described in this embodiment.

[0114] Those skilled in the art may recognize, with reference to the examples described in the embodiments disclosed in this specification, that the units and algorithm steps may be realized by electronic hardware or a combination of computer software and electronic hardware. Whether a function is performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to realize the described functions for each specific application. However, the implementation manner should not be considered to go beyond the scope of this application.

[0115] In some embodiments provided in this application, it should be understood that the disclosed systems and devices may be realized in other ways. For example, the above device embodiments are merely examples. For example, the division into units is merely a logical division of functions, and other division methods may be used in actual implementation. For example, multiple units or components may be combined or integrated into other systems, or some features may be ignored or not implemented. Furthermore, the shown or discussed mutual couplings or direct couplings or communication connections may be realized through some interfaces. Indirect couplings or communication connections between devices or units may be realized in electronic, mechanical, or other forms.

[0116] The units described as separate parts may or may not be physically separate, and the parts shown as units may or may not be physical units, may be located in one location, or may be distributed among multiple network units. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solutions of the embodiments.

[0117] Furthermore, the functional units in the embodiments of this application may be integrated into one processing unit, or each of the units may exist physically alone, or two or more units may be integrated into one unit.

[0118] When the function is realized in the form of a software functional unit and sold or used as an independent product, the function may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of this application may be essentially realized in the form of a software product, or a part of the technical solution may be realized in the form of a software product. The computer software product is stored in a storage medium and includes some instructions for instructing a computer device (which may be a personal computer, a server or a network device) to execute all or part of the steps of the method described in the embodiments of this application. The above storage medium or memory includes any medium that can store program code, such as a USB flash drive, a removable hard disk, a ROM, a RAM, a magnetic disk or an optical disk.

[0119] Finally, it should be noted that the above embodiments are intended to merely describe the technical solutions of this application, rather than limiting this application. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications may still be made to the technical solutions described in the above embodiments, or equivalent substitutions may be made to some or all of the technical features thereof, without departing from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for transmitting data over a wired serial link, applied at a transmitting end, comprising: generating a bit stream, the bit stream including data and a control word, the control word including a first field indicating start position information of the control word, a second field indicating end position information of the control word, and a third field used to carry link information indicating a wired serial link; transmitting said bit stream over said wired serial link; A data transmission method comprising:

2. 2. The data transmission method of claim 1, wherein the link information includes at least one of the following: a number of lanes for transmitting bit streams, a power consumption state of hardware in the link, an operating state of circuits in the link, or a gain of a codec used in the link.

3. The data transmission method according to claim 1 or 2, wherein the first field and the second field instruct a receiving end to perform frame delimitation on the data.

4. There are a plurality of bit streams and a plurality of lanes on the wired serial link, the plurality of bit streams corresponding one-to-one to the plurality of lanes; The step of transmitting the bit stream over the wired serial link comprises: The data transmission method according to claim 1 , specifically comprising the step of transmitting a corresponding number of streams over the plurality of lanes.

5. 5. The data transmission method according to claim 4, wherein the control word further comprises a fourth field indicating a lane number.

6. the first field includes a plurality of groups of identical fields, each group of fields including a plurality of bits; 6. The data transmission method according to claim 1, wherein the group of the same fields is used to compensate for a difference between a clock cycle of the sending end and a clock cycle of the receiving end.

7. the data being service data or training data; When the data is training data, the step of generating a bit stream comprises: A method for transmitting data according to any one of claims 1 to 6, comprising the step of appending said control word after said data to generate said bit stream.

8. 1. A method for transmitting data over a wired serial link, applied at a receiving end, comprising: receiving a bit stream, the bit stream including data and a control word, the control word including a first field indicating start position information of the control word, a second field indicating end position information of the control word, and a third field used to carry link information indicating a wired serial link; reading the control word from the bitstream based on the first field and the second field; reading the data from the bitstream based on the control word; A data transmission method comprising:

9. 9. The data transmission method according to claim 8, further comprising the step of adjusting at least one of the wired serial links based on the link information, i.e., a power consumption state of hardware in the link, an operating state of a circuit in the link, or a gain of a codec used in the link.

10. The step of reading the data from the bitstream based on the control word comprises: determining a coding length of the control word based on the first field and the second field; identifying a frame start position of said data from said bitstream based on said coding length of said control word; reading the data based on the frame start position of the data; 10. The data transmission method according to claim 8 or 9, comprising:

11. There are a plurality of bit streams, and there are a plurality of lanes on the wired serial link, and the plurality of bit streams are received from a transmitting end through a plurality of corresponding lanes, the link information further includes a number of lanes for transmitting the plurality of bit streams, and the control word further includes a fourth field indicating a lane number; The step of reading the data from the bitstream based on the control word comprises:

11. The data transmission method according to claim 8, further comprising the step of reading the data from the bit stream received through a corresponding lane based on the number of lanes for transmitting the plurality of bit streams and the fourth field.

12. 12. The data transmission method of claim 11, further comprising removing data skew between the plurality of lanes based on a sequence of the plurality of received bit streams and a fourth field in each of a plurality of control words in the plurality of bit streams.

13. the first field includes a plurality of groups of identical fields, each group of fields including a plurality of bits; 13. The data transmission method according to claim 8, further comprising the step of performing one of the following operations based on a clock frequency offset between the receiving end and the transmitting end: deleting at least one group of fields from the plurality of groups of identical fields, or adding at least one group of fields to the plurality of groups of identical fields.

14. A data transmission device including a processor and an interface, the processor is configured to generate a bit stream, the bit stream including data and a control word, the control word including a first field indicating start location information of the control word, a second field indicating end location information of the control word, and a third field used to carry link information indicating a wired serial link; The interface transmits the bit stream over the wired serial link.

15. The data transmission device of claim 14, wherein the link information includes at least one of the following: a number of lanes for transmitting a bit stream, a power consumption state of hardware in the link, an operating state of circuits in the link, or a gain of a codec used in the link.

16. 16. The data transmission device according to claim 14 or 15, wherein the first field and the second field instruct a receiving end to perform frame delimitation on the data.

17. There are a plurality of bit streams and a plurality of lanes on the wired serial link, the plurality of bit streams corresponding one-to-one to the plurality of lanes; The interface includes:

17. The data transmission device according to claim 14, specifically configured to transmit a corresponding number of streams over said multiple lanes.

18. 20. The data transmission device of claim 17, wherein the control word further includes a fourth field indicating a lane number.

19. the first field includes a plurality of groups of identical fields, each group of fields including a plurality of bits; 19. A data transmission device according to claim 14, wherein the group of a plurality of identical fields is used to compensate for a difference between a clock cycle at a sending end and a clock cycle at a receiving end.

20. A data transmission device including a processor and an interface, the interface is configured to receive a bit stream, the bit stream including data and a control word, the control word including a first field indicating start position information of the control word, a second field indicating end position information of the control word, and a third field used to carry link information indicating a wired serial link; The processor is configured to read the control word from the bit stream based on the first field and the second field, and to read the data from the bit stream based on the control word.

21. The data transmission device of claim 20, wherein the processor is further configured to adjust at least one of the wired serial links based on the link information, i.e., a power consumption state of hardware in the link, an operating state of circuits in the link, or a gain of a codec used in the link.

22. The processor, determining a coding length of the control word based on the first field and the second field; identifying a frame start position of the data from the bit stream based on the coding length of the control word; 22. A data transmission device as claimed in claim 20 or 21, specifically configured to read the data based on the frame start position of the data.

23. There are a plurality of bit streams, and there are a plurality of lanes on the wired serial link, and the plurality of bit streams are received from a transmitting end through a plurality of corresponding lanes, the link information further includes a number of lanes for transmitting the plurality of bit streams, and the control word further includes a fourth field indicating a lane number; The processor, 23. The data transmission device of claim 20, specifically configured to read the data from the bit stream received through a corresponding lane based on the number of lanes for transmitting the multiple bit streams and the fourth field.

24. The processor, 24. The data transmission device of claim 23, further configured to remove data skew between the plurality of lanes based on a sequence of the plurality of received bit streams and a fourth field in each of a plurality of control words in the plurality of bit streams.

25. the first field includes a plurality of groups of identical fields, each group of fields including a plurality of bits; The processor, 25. The data transmission device of claim 20, further configured to perform one of the following operations based on a clock frequency offset between the data transmission device and a sending end: deleting at least one group of fields from the plurality of groups of identical fields, or adding at least one group of fields to the plurality of groups of identical fields.

26. A computer-readable storage medium configured to store a computer program, comprising: A computer readable storage medium, the computer program causing a method according to any one of claims 1 to 7 or any one of claims 8 to 13 to be realized when the computer program is executed by a processor.

27. 1. A computer program product comprising: A computer program product, which, when executed on a processor, causes the method according to any one of claims 1 to 7 or the method according to any one of claims 8 to 13 to be implemented.

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