Micro LED, Micro LED Array Panel and Manufacturing Method Thereof

Abstract

The micro LED includes a first type of semiconductor layer (110), a first type of cap layer (114), a light emitting layer (130), a second type of cap layer (124), and a second type of semiconductor layer (120), where the first type of semiconductor layer (110) includes a mesa structure (111), a trench (112), and an ion implantation fence (113) separated from the mesa structure (111), where the trench (112) extends into at least a portion of the first type of cap layer (114) and is formed around the mesa structure (111), and the ion implantation fence (113) is formed around the trench (112). An electrical resistance of the ion implantation fence (113) is higher than an electrical resistance of the mesa structure (111), and the ion implantation fence (113) can absorb light from the mesa structure (111).

Description

[Technical field]

[0001] The present disclosure relates generally to light emitting diodes, and more particularly to micro light emitting diodes (LEDs), micro LED array panels, and methods for manufacturing the same. [Background technology]

[0002] Inorganic micropixel light-emitting diodes, also known as micro light-emitting diodes, micro LEDs or μ-LEDs, are gaining importance due to their use in a variety of applications including self-emissive microdisplays, visible light communications, and optogenetics. Micro LEDs exhibit higher output performance than conventional LEDs due to better strain relief, increased light extraction efficiency, and uniform current spreading. Micro LEDs also exhibit improved thermal effects, fast response speeds, wider operating temperature ranges, higher resolution, color gamut and contrast, as well as lower power consumption and can be operated at higher current densities compared to conventional LEDs.

[0003] Inorganic micro-LEDs are traditionally III-V epitaxial layers formed as multiple mesas. In traditional micro-LED structures, a space is formed between adjacent micro-LEDs to avoid carriers in the epitaxial layers from diffusing from one mesa to the adjacent mesa. However, the space formed between adjacent micro-LEDs can reduce the active light-emitting area and reduce the light extraction efficiency. If there is no space between adjacent micro-LEDs, the active light-emitting area will increase and carriers in the epitaxial layers will diffuse laterally toward the adjacent mesas, reducing the light-emitting efficiency of the micro-LEDs. In addition, if there is no space between adjacent mesas, crosstalk will occur between adjacent micro-LEDs, interfering with the operation of the LEDs.

[0004] However, smaller micro LEDs with higher current densities experience red shifts at high current densities, reduced maximum efficiency, and non-uniform emission, which are attributed to damage in the fabrication process, resulting in poor electrical injection. Furthermore, the peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) decrease significantly with decreasing chip size. The decrease in EQE is due to non-radiative recombination caused by etching damage, while the decrease in IQE is due to poor current injection and electron leakage current in micro LEDs.

[0005] The above discussion is merely intended to aid in understanding the technical problem overcome by the present disclosure, and is not an admission that the above is prior art. Summary of the Invention

[0006] An embodiment of the present disclosure provides a micro-LED, the micro-LED comprising: a first type semiconductor layer, a light emitting layer formed on the first type semiconductor layer, a first type cap layer formed on a bottom surface of the light emitting layer and between the first type semiconductor layer and the light emitting layer, the first type semiconductor layer including a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extending upward through the first type semiconductor layer and extending upward into at least a portion of the first type cap layer, the ion implantation fence formed around the trench, the trench formed around the mesa structure, and an electrical resistance of the ion implantation fence being higher than an electrical resistance of the mesa structure.

[0007] An embodiment of the present disclosure provides a method for manufacturing a micro LED, the method includes providing an epitaxial structure including, in top-down order, a first type of semiconductor layer, a first type of cap layer, a light emitting layer, a second type of cap layer, and a second type of semiconductor layer, patterning the first type of semiconductor layer to form a mesa structure, a trench, and a fence, depositing a bottom contact on the mesa structure, and performing an ion implantation process on the fence to form an ion-implanted fence.

[0008] An embodiment of the present disclosure provides a micro-LED, the micro-LED includes a first type of semiconductor layer, a first type of cap layer formed on the first type of semiconductor layer, a light emitting layer formed on the first type of cap layer, a second type of cap layer formed on the light emitting layer, a second type of semiconductor layer formed on the second type of cap layer, and an integrated circuit (IC) backplane formed on a bottom surface of the first type of semiconductor layer, the second type of semiconductor layer having a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extends downward through the second type of semiconductor layer and into at least a portion of the second type of cap layer, the ion implantation fence is formed around the trench, the trench is formed around the mesa structure, an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure, and a conductivity type of the first type of semiconductor layer is different from a conductivity type of the second type of semiconductor layer.

[0009] An embodiment of the present disclosure provides a method for manufacturing a micro LED, the method including: providing an epitaxial structure including, in top-down order, a first type of semiconductor layer, a first type of cap layer, a light emitting layer, a second type of cap layer, and a second type of semiconductor layer, bonding the epitaxial structure with an integrated circuit (IC) backplane, patterning the second type of semiconductor layer to form a mesa structure, a trench, and a fence, depositing a top contact on the mesa structure, performing an ion implantation process on the fence, and depositing a top conductive layer on a top surface of the second type of semiconductor layer, on the top contact, and in the trench.

[0010] An embodiment of the present disclosure provides a micro LED, the micro LED includes a first type of semiconductor layer, a first type of cap layer formed on the first type of semiconductor layer, a light emitting layer formed on the first type of cap layer, a second type of cap layer formed on the light emitting layer, and a second type of semiconductor layer formed on the second type of cap layer, the first type of semiconductor layer includes a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure, the first trench extends through the first type of semiconductor layer to the first type of cap layer. a first ion implantation fence formed around the first trench, the first trench being formed around the first mesa structure, an electrical resistance of the first ion implantation fence being higher than an electrical resistance of the first mesa structure; a second type of semiconductor layer including a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure, the second ion implantation fence being formed around the second trench, the second trench being formed around the second mesa structure; The second ion implantation fence has an electrical resistance higher than an electrical resistance of the second mesa structure, and the conductivity type of the first type of semiconductor layer is different from the conductivity type of the second type of semiconductor layer.

[0011] An embodiment of the present disclosure provides a method for manufacturing a micro LED, the method including step I including patterning a first type of semiconductor layer and implanting the first type of semiconductor layer with first ions, and step II including patterning a second type of semiconductor layer and implanting the second type of semiconductor layer with second ions.

[0012] An embodiment of the present disclosure provides a micro LED array panel, which includes a plurality of micro LEDs as described above.

[0013] Embodiments and various aspects of the present disclosure are set forth in the following detailed description and in the accompanying drawings, in which various features are not drawn to scale. [Brief description of the drawings]

[0014] [Figure 1A] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1B] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1C] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1D] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1E] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 1F] 1A-1D are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro LED according to some embodiments of the present disclosure. [Diagram 2] FIG. 2 is a structural diagram illustrating a bottom view of a first exemplary micro LED according to some embodiments of the present disclosure. [Diagram 3] FIG. 2 is a structural diagram illustrating a cross-sectional side view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. [Figure 4] FIG. 2 is a structural diagram illustrating a cross-sectional side view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. [Diagram 5] 1 is a flowchart of a method for manufacturing a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 6A] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 501 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6B]FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 502 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6C] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 503 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6D] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 504 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6E] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 505 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6F] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 506 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6G] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 507 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6H] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 508 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6I] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 509 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 6J] FIG. 6 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process at step 510 of the method shown in FIG. 5 according to some embodiments of the present disclosure. [Figure 7] FIG. 2 is a structural diagram illustrating a cross-sectional side view of adjacent micro LEDs of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 8] FIG. 8 is a structural diagram showing a bottom view of the side-by-side micro-LEDs of FIG. 7 according to some embodiments of the present disclosure. [Figure 9]FIG. 2 is a structural diagram illustrating a cross-sectional side view of adjacent micro LEDs of a first exemplary micro LED according to some embodiments of the present disclosure. [Figure 10A] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10B] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10C] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10D] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10E] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 10F] 1A-1C are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. [Figure 11] FIG. 1 is a structural diagram illustrating a top view of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 12A] FIG. 13 is a structural diagram illustrating a cross-sectional side view of another variation of the second exemplary micro LED according to some embodiments of the present disclosure. [Figure 12B] FIG. 13 is a structural diagram illustrating a cross-sectional side view of another variation of the second exemplary micro LED according to some embodiments of the present disclosure. [Figure 13] FIG. 1 is a structural diagram illustrating a cross-sectional side view of another variation of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 14] 1 shows a flowchart of a second exemplary method for fabricating a micro LED according to some embodiments of the present disclosure. [Figure 15A]FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1401 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15B] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1402 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15C] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1403 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15D] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1404 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15E] FIG. 15 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 1405 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 15F] FIG. 15 is a structural diagram illustrating a cross-sectional side view of a micro LED manufacturing process in step 1406 of the method shown in FIG. 14 according to some embodiments of the present disclosure. [Figure 16] FIG. 1C is a structural diagram showing a side cross-sectional view of adjacent micro LEDs of a second exemplary micro LED according to some embodiments of the present disclosure. [Figure 17] FIG. 17 is a structural diagram showing a top view of the side-by-side micro-LEDs of FIG. 16 according to some embodiments of the present disclosure. [Figure 18] FIG. 12C is a structural diagram showing a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 12B according to some embodiments of the present disclosure. [Figure 19A] 11A-11C are structural diagrams illustrating cross-sectional side views of different variations of a third exemplary micro-LED according to some embodiments of the present disclosure. [Figure 19B] 11A-11C are structural diagrams illustrating cross-sectional side views of different variations of a third exemplary micro-LED according to some embodiments of the present disclosure. [Figure 19C]11A-11C are structural diagrams illustrating cross-sectional side views of different variations of a third exemplary micro-LED according to some embodiments of the present disclosure. [Figure 19D] 11A-11C are structural diagrams illustrating cross-sectional side views of different variations of a third exemplary micro-LED according to some embodiments of the present disclosure. [Figure 19E] 11A-11C are structural diagrams illustrating cross-sectional side views of different variations of a third exemplary micro-LED according to some embodiments of the present disclosure. [Figure 19F] 11A-11C are structural diagrams illustrating cross-sectional side views of different variations of a third exemplary micro-LED according to some embodiments of the present disclosure. [Figure 20] FIG. 13 is a structural diagram illustrating a cross-sectional side view of another variation of the third exemplary micro LED according to some embodiments of the present disclosure. [Figure 21] 1 shows a flowchart of a third exemplary method for manufacturing a micro LED according to some embodiments of the present disclosure. [Figure 22A] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process at step 2110 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 22B] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process at step 2111 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 22C] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process at step 2112 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 22D] FIG. 22 is a structural diagram showing a cross-sectional side view of a micro LED manufacturing process in step 2113 of the method shown in FIG. 21 according to some embodiments of the present disclosure. [Figure 23A] FIG. 13 is a structural diagram illustrating a cross-sectional side view of another variation of the third exemplary micro LED according to some embodiments of the present disclosure. [Figure 23B] FIG. 13 is a structural diagram illustrating a side cross-sectional view of another variation of the third exemplary micro LED according to some embodiments of the present disclosure. [Figure 24] FIG. 23B is a structural diagram showing a cross-sectional side view of adjacent ones of the micro-LEDs of FIG. 23A according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which like numbers in different drawings represent the same or similar elements unless otherwise specified. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the present invention. Instead, these are merely examples of apparatus and methods consistent with aspects related to the present invention as set forth in the appended claims. Certain aspects of the present disclosure are described in more detail below. In the event of a conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall control.

[0016] The present disclosure provides a micro LED that can avoid non-radiative recombination on the sidewall of the mesa according to the structure of the semiconductor layer and the light emitting layer that are successively formed. Moreover, compared with conventional micro LEDs, the spacing between adjacent mesas can be significantly reduced by the ion implantation fence. Thus, the integration of micro LEDs in a chip is increased and the active light emitting efficiency is improved. Moreover, the micro LED provided by the present disclosure can also increase the active light emitting area and improve image quality.

[0017] EMBODIMENT 1 1A-1F are structural diagrams illustrating cross-sectional side views of different variations of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0018] 1A-1F, the micro LED includes a first type semiconductor layer 110, a first type cap layer 114, a light emitting layer 130, a second type cap layer 124, and a second type semiconductor layer 120. The light emitting layer 130 is formed on the first type cap layer 114 above the first type semiconductor layer 110, and the second type semiconductor layer 120 is formed on the second type cap layer 124 above the light emitting layer 130. The thickness of the first type semiconductor layer 110 is thicker than the thickness of the second type semiconductor layer 120.

[0019] The conductivity type of the first type semiconductor layer 110 is different from the conductivity type of the second type semiconductor layer 120. In some embodiments, the conductivity type of the second type semiconductor layer 120 is P-type and the conductivity type of the first type semiconductor layer 110 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 120 is P-type and the conductivity type of the first type semiconductor layer 110 is N-type. For example, the material of the first type semiconductor layer 110 can be selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 120 can be selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. The first-type cap layer 114 has the same conductivity type as the first-type semiconductor layer 110 , and the second-type cap layer 124 has the same conductivity type as the second-type semiconductor layer 120 .

[0020] The first type semiconductor layer 110 includes a mesa structure 111, a trench 112, and an ion implantation fence 113. The ion implantation fence 113 is separated from the mesa structure 111 by the trench 112. The trench 112 and the ion implantation fence 113 are formed in an annular shape around the mesa structure 111.

[0021] The ion implanted fence 113 includes a light absorbing material that absorbs light from the mesa structure 111. The conductivity type of the light absorbing material is the same as the conductivity type of the first type semiconductor layer 110. Preferably, the light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. Furthermore, the ion implanted fence 113 is formed by implanting ions into a fence formed from at least the first type semiconductor layer 110. Preferably, the type of ions implanted into the fence is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0022] Additionally, the width of the ion implantation fence 113 is less than or equal to 50% of the diameter of the mesa structure 111. In some embodiments, the width of the ion implantation fence 113 is less than or equal to 10% of the diameter of the mesa structure 111. Preferably, the width of the ion implantation fence 113 is less than or equal to 200 nm, the diameter of the mesa structure 111 is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer 110 is less than or equal to 300 nm.

[0023] In some embodiments, the width of trench 112 is less than or equal to 50% of the diameter of mesa structure 111. In some embodiments, the width of trench 112 is less than or equal to 10% of the diameter of mesa structure 111. Preferably, the width of first trench 112 is less than or equal to 200 nm.

[0024] In some embodiments, the top surface of the ion implantation fence 113 is lower than or aligned with the top surface of the first type semiconductor layer 110. Thus, the ion implantation fence 113 can contact the first type cap layer 114 but cannot contact the light emitting layer 130. The top surface of the ion implantation fence 113 can be formed anywhere within the first type semiconductor layer 110. As shown in FIG. 1A, the trench 112 extends through the first type semiconductor layer 110 and into the first type cap layer 114. The top surface of the trench 112 is higher than the top surface of the first type semiconductor layer 110. The top surface of the ion implantation fence 113 is lower than the top surface of the trench 112. FIG. 2 is a structural diagram illustrating a bottom view of the first exemplary micro LED shown in FIG. 1A according to some embodiments of the present disclosure. 2 shows a bottom view of a first type semiconductor layer 110 with an ion implantation fence 113 separated from a mesa structure 111 by a trench 112. The ion implantation fence 113 is formed around the trench, which is formed around the mesa structure 111. The trench extends up through the first type semiconductor layer 110 into the first type cap layer 114, such that the first type cap layer 114 is visible through the trench in the bottom view.

[0025] In some embodiments, the trench 112 extends upward through the first type semiconductor layer 110 and the first type cap layer 114 to the light emitting layer 130. In some embodiments, referring to FIG. 1B , the trench 112 extends upward through the first type semiconductor layer 110 and the first type cap layer 114 and further into the light emitting layer 130. In some embodiments, the trench 112 extends upward through the first type semiconductor layer 110, the first type cap layer 114, and the light emitting layer 130. Further, in some embodiments, the trench 112 extends upward through the first type semiconductor layer 110, the first type cap layer 114, and the light emitting layer 130 and further into the second type cap layer 124. Further, in some embodiments, referring to FIG. 1C , the trench 112 extends upward through the first type semiconductor layer 110, the first type cap layer 114, the light emitting layer 130 and the second type cap layer 124, and further extends upward into the second type semiconductor layer 120.

[0026] With reference to FIG. 1C, in some embodiments, the top surface of the ion implantation fence 113 is aligned with the top surface of the first type semiconductor layer 110.

[0027] Furthermore, the bottom surface of the ion implantation fence 113 can be formed at any position. Preferably, the bottom surface of the ion implantation fence 113 is aligned with the bottom surface of the first type semiconductor layer 110. With reference to FIG. 1D, in some embodiments, the bottom surface of the ion implantation fence 113 is higher than the bottom surface of the first type semiconductor layer 110. With reference to FIG. 1E, in some embodiments, the bottom surface of the ion implantation fence 113 is lower than the bottom surface of the first type semiconductor layer 110.

[0028] In some embodiments, the mesa structure 111 includes a stair structure 111a, as shown in Figure IF. In some embodiments, the mesa structure 111 can have one or more stair structures.

[0029] 3 is a structural diagram showing a side cross-sectional view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 3, the micro LED further includes a bottom isolation layer 140 filled in the trench 112. Preferably, the material of the bottom isolation layer 140 is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.

[0030] In this embodiment, an integrated circuit (IC) backplane 190 is formed below the first type semiconductor layer 110 and is electrically connected to the first type semiconductor layer 110 through a connection structure 150. As shown in FIG. 3, the connection structure 150 is a connection pillar.

[0031] The micro LED further includes a bottom contact 160. The bottom contact 160 is formed on the bottom of the first type semiconductor layer 110. The top surface of the connection structure 150 is connected to the bottom contact 160, and the bottom surface of the connection structure 150 is connected to the IC backplane 190.

[0032] Referring to FIG. 3 , in some embodiments, the micro LED further includes a top contact 180 and a top conductive layer 170. The top contact 180 is formed on the second type semiconductor layer 120. The top conductive layer 170 is formed on the second type semiconductor layer 120 and the top contact 180. The conductivity type of the top contact 180 is the same as the conductivity type of the second type semiconductor layer 120. For example, in some embodiments, the conductivity type of the second type semiconductor layer 120 is N-type and the conductivity type of the top contact 180 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 120 is P-type and the conductivity type of the top contact 180 is P-type. The top contact 180 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 180 is used to form an ohmic contact between the top conductive layer 170 and the second type semiconductor layer 120 to optimize the electrical properties of the micro LED. The diameter of the top contact 180 is about 20 to 50 nm, and the thickness of the top contact 180 is about 10 to 20 nm.

[0033] 4 is a structural diagram showing a cross-sectional side view of another variation of the first exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 4, the connection structure 150 is a metal bonding layer for bonding the micro LED with an IC backplane 190. Furthermore, the bottom contact 160 is a bottom contact layer in this variation.

[0034] Figure 5 shows a flowchart of a method 500 for fabricating a first exemplary micro LED, such as the micro LED shown in Figure 3, according to some embodiments of the present disclosure. The method 500 for fabricating a micro LED includes steps 501-510. Figures 6A-6J are structural diagrams showing cross-sectional side views of a micro LED fabrication process at each step (i.e., steps 501-510) corresponding to the method 500 shown in Figure 5, according to some embodiments of the present disclosure.

[0035] 5 and 6A-6J. In step 501, an epitaxial structure is provided. As shown in FIG. 6A, the epitaxial structure includes, from top to bottom, a first type semiconductor layer 610, a first type cap layer 614, a light emitting layer 630, a second type cap layer 624, and a second type semiconductor layer 620. The epitaxial structure is grown on a substrate 600. The substrate 600 can be GaN, GaAs, etc.

[0036] In step 502, referring to FIG. 6B, a first type semiconductor layer 610 is patterned to form mesa structures 611, trenches 613, and fences 613'.

[0037] Step 502 may further include sequentially etching the first type semiconductor layer 610, the first type cap layer 614, and the light emitting layer 630, and stopping the etch on the second type cap layer 624. As shown in Figure 6B, the bottom surface of the first trench 612 contacts and is located on the second type cap layer 624. The first type semiconductor layer 610 is etched by a conventional dry etching method, such as a plasma etching method, as would be understood by one of ordinary skill in the art.

[0038] In some embodiments, step 502 may include sequentially etching the first type semiconductor layer, the first type cap layer, and the light emitting layer, and stopping the etch in the light emitting layer. For example, referring back to FIG. 1B , the top surface of trench 121 contacts and is located within light emitting layer 130.

[0039] In some embodiments, step 502 may include sequentially etching the first type semiconductor layer, the first type cap layer, the light emitting layer, the second type cap layer, and the second type semiconductor layer, and stopping the etch in the second type semiconductor layer. For example, referring back to FIG. 1C , the top surface of trench 121 contacts and is located in second type semiconductor layer 120.

[0040] 1A , the first type semiconductor layer 110 is etched and the etch is stopped within the first type cap layer 114 to avoid etching the light emitting layer 130 during the patterning process. The bottom of the trench 112 does not reach the light emitting layer 130. The first type semiconductor layer 110 is etched by a conventional dry etching method, such as a plasma etching method, as would be understood by one of ordinary skill in the art.

[0041] In step 503, referring to FIG. 6C, a bottom contact 660 is deposited on the mesa structure 611.

[0042] Before the bottom contact 660 is deposited, a first protective mask (not shown) is used to protect the area where the bottom contact 660 is not to be formed. Then, the material of the bottom contact 660 is deposited on the first protective mask and on the first type of semiconductor layer 610 by a conventional deposition method such as physical vapor deposition or chemical vapor deposition. After the deposition process, the first protective mask is removed from the first type of semiconductor layer 610, and the material on the first protective mask is also removed together with the first protective mask to form the bottom contact 660 on the mesa structure 611.

[0043] In step 504, and with reference to Figure 6D, an ion implantation process is performed within fence 613'. The arrows indicate the direction of the ion implantation process.

[0044] As shown in FIG. 6D in conjunction with FIG. 6C, an ion implantation step implants ions into fence 613' (as shown in FIG. 6C) to form ion-implanted fence 613 (as shown in FIG. 6D). Prior to the ion implantation step, a second protective mask (not shown) is formed in the areas where ions are not to be implanted. Ions are then implanted into the exposed fence 613'. The second protective mask is then removed by conventional chemical etching methods, as will be understood by those skilled in the art. Preferably, the implantation energy is 0-500 Kev and the implantation dose is 1E10-9E17.

[0045] In step 505, referring to Figure 6E, a bottom isolation layer 640 is deposited over the substrate 600. That is, the bottom isolation layer 640 is deposited on the first type semiconductor layer 610. The first type semiconductor layer 610 and the bottom contact 660 are covered by the bottom isolation layer 640, and the trench 612 is filled by the bottom isolation layer 640. The bottom isolation layer 640 is deposited by conventional chemical vapor deposition.

[0046] As shown in FIG. 6E, a bottom isolation layer 640 is filled in the trench 612. Thus, the bottom isolation layer 640 is formed on the sidewalls and bottom of the trench 612. The bottom isolation layer 640 is also formed on the sidewalls of the first type semiconductor layer 610, the first mesa structure 611, the first type cap layer 614 and the light emitting layer 630 in the first trench 612, and on the surface of the second type cap layer 624 in the first trench 612. In some embodiments, referring back to FIG. 1A, the bottom isolation layer may be formed on the sidewalls of the mesa structure 111, the first type semiconductor layer 110, and the ion implantation fence 113, as well as on the surface of the first type cap layer 114 in the trench 112. 1B , a bottom isolation layer may be formed on the sidewalls of the mesa structure 111, the first type semiconductor layer 110, the ion implantation fence 113, and the first type cap layer 114 in the first trench 112, as well as on surfaces within the light emitting layer 130 in the first trench 112. In some embodiments, referring back to FIG. 1C , a bottom isolation layer may be formed on the sidewalls of the mesa structure 111, the ion implantation fence 113, the first type cap layer 114, the light emitting layer 130, and the second type cap layer 124 in the trench 112, as well as on surfaces within the second type semiconductor layer 120 in the trench 112.

[0047] In step 506, referring to Figure 6F, the bottom isolation layer 640 is patterned to expose the bottom contact 660. The bottom isolation layer 640 is etched by photo-etching and dry-etching methods.

[0048] In step 507, and referring to Figure 6G, a metal material 650' is deposited over the substrate 600. That is, the metal material 650' is deposited on the bottom isolation layer 640 and the bottom contact 660. The metal material is deposited by conventional physical vapor deposition.

[0049] In step 508, referring to Figure 6H, the top of the metal material is polished down to the top of the bottom isolation layer 640 to form connection structures 650, such as connection pillars. In some embodiments, the metal material is polished by a chemical mechanical polishing (CMP) process.

[0050] In step 509, referring to FIG. 6I, the connection pillars 650 are bonded to the IC backplane 690. The epitaxial structure is first turned upside down. Then, a metal bonding process bonds the connection pillars 650 to the contact pads of the IC backplane 690. The substrate 600 is then removed by conventional separation methods such as laser stripping or chemical etching. The arrows indicate the direction of removal of the substrate 600.

[0051] In step 510, referring to FIG. 6J, a top contact 680 and a top conductive layer 670 may be sequentially deposited on the second type semiconductor layer 620 by conventional deposition techniques.

[0052] Some embodiments of the present disclosure further provide a micro LED array panel, which includes a plurality of micro LEDs as described above, as shown in Figures 1A-1F, 3 and 4. These micro LEDs may be arranged in an array within the micro LED array panel.

[0053] 7 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the first exemplary micro LEDs according to some embodiments of the present disclosure. As shown in FIG. 7, the micro LED array panel includes a first type of semiconductor layer 710 formed continuously in the micro LED array panel, a first type of cap layer 714 formed continuously on the first type of semiconductor layer 710, a light emitting layer 730 formed continuously on the first type of cap layer 714, a second type of cap layer 724 formed continuously on the light emitting layer 730, and a second type of semiconductor layer 720 formed continuously on the second type of cap layer 724.

[0054] The conductivity type of the first type semiconductor layer 710 is different from the conductivity type of the second type semiconductor layer 720. For example, in some embodiments, the conductivity type of the first type semiconductor layer 710 is P-type and the conductivity type of the second type semiconductor layer 720 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 720 is P-type and the conductivity type of the first type semiconductor layer 710 is N-type. The thickness of the first type semiconductor layer 710 is greater than the thickness of the second type semiconductor layer 720. In some embodiments, the material of the first type semiconductor layer 710 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 720 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. The conductivity type of the first type cap layer 714 is the same as the conductivity type of the first type semiconductor layer 710, and the conductivity type of the second type cap layer 724 is the same as the conductivity type of the second type semiconductor layer 720.

[0055] The first type semiconductor layer 710 includes a plurality of mesa structures 711, a plurality of trenches 712, and a plurality of ion implantation fences 713 separated from the mesa structures 711 by the trenches 712. The top surface of the ion implantation fences 713 is aligned with the top surface of the first type semiconductor layer 710 or is lower than the top surface of the first type semiconductor layer 710. Therefore, the ion implantation fences 713 cannot reach the light emitting layer 730. The top of the ion implantation fences 713 can be formed at any position. Furthermore, the bottom surface of the ion implantation fences 713 can be formed at any position. The relationship between the top surface of the ion implantation fences 713, the top surface of the first type semiconductor layer 710, and the top surface of the trenches 712 can be confirmed in the micro LED shown in FIG. 1A to FIG. 1E, and will not be further described here. Additionally, the relationship between the bottom surface of the ion implantation fence 713 and the bottom surface of the first type semiconductor layer 710 can be seen in the micro LEDs shown in Figures 1E-1G and will not be described further herein. In another embodiment, the mesa structure can have one or more stair structures, as seen in the mesa structure shown in Figure 1H.

[0056] 8 is a structural diagram illustrating a bottom view of the adjacent micro LEDs of FIG. 7 according to some embodiments of the present disclosure. As shown in FIG. 8, ion implantation fences 713 are formed around the trenches 712 and between adjacent mesa structures 711. Furthermore, in each micro LED, the ion implantation fences 713 are formed around the trenches 712, and the trenches 712 are formed around the mesa structures 711. The electrical resistance of the ion implantation fences 713 is higher than the electrical resistance of the mesa structures 711. The trenches extend upward through the first type semiconductor layer 710 and the first type cap layer 714 such that the light emitting layer 730 is visible through the trenches in the bottom view.

[0057] In some embodiments, the spacing between adjacent sidewalls of adjacent ones of the mesa structures 711 can be adjusted. For example, in some embodiments, the spacing between adjacent sidewalls of the mesa structures 711 is 50% or less of the diameter of the mesa structures 711. In some embodiments, the spacing between adjacent sidewalls of the mesa structures 711 is 30% or less of the diameter of the mesa structures 711. Preferably, the spacing between adjacent sidewalls of the mesa structures 711 is 600 nm or less. Furthermore, in some embodiments, the width of the ion implantation fence 713 can be adjusted. For example, the width of the ion implantation fence 713 can be 50% or less of the diameter of the mesa structures 711. In some embodiments, the width of the ion implantation fence 713 can be 10% or less of the diameter of the mesa structures 711. Preferably, in a micro LED array panel, the width of the ion implantation fence 713 is 200 nm or less.

[0058] 9 is a structural diagram showing a side cross-sectional view of adjacent ones of the first exemplary micro LEDs in a micro LED array panel according to some embodiments of the present disclosure. As shown in FIG. 9, the micro LED array panel further includes a bottom isolation layer 940 formed on the first type semiconductor layer 910 and filled in the trench 912. Preferably, in some embodiments, the material of the bottom isolation layer 940 is one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2. Also, an IC backplane 990 is continuously formed below the first type semiconductor layer 910 and electrically connected with the first type semiconductor layer 910 through a connection structure 950. The micro LED array panel further includes a bottom contact 960 formed on the bottom of the first type semiconductor layer 910. Further details of the bottom isolation layer 940, IC backplane 990, bottom contacts 960, and connection structures 950 are shown in the micro-LEDs of Figures 3 and 4, which correspond to the isolation layer 140, IC backplane 190, bottom contacts 160, and connection structures 150, respectively, and will not be described further.

[0059] In this embodiment, the micro LED array panel further includes a top contact 980 and a top conductive layer 970. The top contact 980 is formed on the second type semiconductor layer 920. The top conductive layer 970 is formed on the second type semiconductor layer 920 and the top contact 980. The conductivity type of the top contact 980 is the same as the conductivity type of the second type semiconductor layer 920. For example, in some embodiments, the conductivity type of the second type semiconductor layer 920 is N-type and the conductivity type of the top contact 980 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 920 is P-type and the conductivity type of the top contact 980 is P-type. The top contact 980 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 980 is used to form an ohmic contact between the top conductive layer 970 and the second type semiconductor layer 920 to optimize the electrical properties of the micro LED. The diameter of the top contact 980 is about 20 to 50 nm, and the thickness of the top contact 980 is about 10 to 20 nm.

[0060] The micro LED array panel can be manufactured by a method 500 shown in FIG. 5, which will not be described further.

[0061] EMBODIMENT 2 10A-10F are structural diagrams illustrating cross-sectional side views of different variations of a second exemplary micro-LED according to some embodiments of the present disclosure. As shown in FIG. 10A, the micro-LED includes a first type of semiconductor layer 1010, a first type of cap layer 1014, a light-emitting layer 1030, a second type of cap layer 1024, and a second type of semiconductor layer 1020. The conductivity type of the first type of semiconductor 1010 is different from the conductivity type of the second type of semiconductor layer 1020. For example, the conductivity type of the first type of semiconductor 1010 is P-type, and the conductivity type of the second type of semiconductor layer 1020 is N-type. The thickness of the first type of semiconductor layer 1010 is thicker than the thickness of the second type of semiconductor layer 1020. The material of the first type semiconductor layer 1010 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer 1020 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. The conductivity type of the first type cap layer 1014 is the same as the conductivity type of the first type semiconductor layer 1010, and the conductivity type of the second type cap layer 1024 is the same as the conductivity type of the second type semiconductor layer 1020.

[0062] The second type semiconductor layer 1020 includes a mesa structure 1021, a trench 1022, and an ion implantation fence 1023 separated from the mesa structure 1021. The bottom surface of the ion implantation fence 1023 is aligned with or higher than the bottom surface of the second type semiconductor layer 1020. Therefore, the ion implantation fence 1023 can reach the second type cap layer 1024 but cannot reach the light emitting layer 1030. The bottom surface of the ion implantation fence 1023 can be formed at any position. Furthermore, the ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021. The electrical resistance of the ion implantation fence 1023 is higher than the electrical resistance of the mesa structure 1021.

[0063] The ion implantation fence 1023 includes a light absorbing material that absorbs light from the mesa structure 1021. The conductivity type of the light absorbing material is the same as the conductivity type of the second semiconductor layer 1020. Preferably, the light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN. Furthermore, the ion implantation fence 1023 is formed by implanting ions into at least the second type semiconductor layer 1020. Preferably, the ion type implanted into the second type semiconductor layer 1020 is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0064] Also, the width of the ion implantation fence 1023 can be adjusted. For example, in some embodiments, the width of the ion implantation fence 1023 is 50% or less of the diameter of the mesa structure 1021. In some embodiments, the width of the ion implantation fence 1023 is 10% or less of the diameter of the mesa structure 1021. Preferably, the width of the ion implantation fence 1023 is 200 nm or less. The diameter of the mesa structure 1021 is 2500 nm or less. The thickness of the second type semiconductor layer 1020 is 100 nm or less.

[0065] In some embodiments, the width of trench 1022 is less than or equal to 50% of the diameter of mesa structure 1021. In some embodiments, the width of trench 1022 is less than or equal to 10% of the diameter of mesa structure 1021. Preferably, the width of trench 1022 is less than or equal to 200 nm.

[0066] The depth of the trench 1022 is not limited. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and into the second type cap layer 1024. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and the second type cap layer 1024 to the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020 and the second type cap layer 1024 to the light emitting layer 1030. In some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020, the second type cap layer 1024, and the light emitting layer 1030. Further, in some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020, the second type cap layer 1024, and the light emitting layer 1030, and can extend down into the first type cap layer 1014. Further, in some embodiments, the trench 1022 can extend down through the second type semiconductor layer 1020, the second type cap layer 1024, the light emitting layer 1030, and the first type cap layer 1014, and can extend down into the first type semiconductor layer 1010.

[0067] In some embodiments, as shown in FIG. 10A, the trench 1022 extends down through the bottom surface of the second type semiconductor layer 1020 and into the second type cap layer 1024. The bottom surface of the trench 1022 is lower than the bottom of the second type semiconductor layer 1020. Also, the bottom surface of the second ion implantation fence 1023 is higher than the bottom surface of the second trench 1022. FIG. 11 is a structural diagram illustrating a top view of the second exemplary micro LED shown in FIG. 10A. FIG. 11 illustrates a top view of the second type semiconductor layer 1020 with the ion implantation fence 1023 separated from the mesa structure 1021 by the trench 1022. Here, the ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021. The trenches 1022 extend through the bottom surface of the second type semiconductor layer 1020 and down into the second type cap layer 1024 so that the second type cap layer 1024 is visible through the trenches 1022 in a top view.

[0068] 10B, the trench 1022 extends downward through the bottom surface of the second type semiconductor layer 1020 and the second type cap layer 1024. The bottom surface of the ion implantation fence 1023 is higher than the bottom surface of the second trench 1022. In some embodiments, the bottom surface of the ion implantation fence 1023 is aligned with the bottom surface of the second type semiconductor layer 1020, as shown in FIG.

[0069] Additionally, in some embodiments, the top surface of the ion implantation fence 1023 can be formed at any location. In some embodiments, the top surface of the ion implantation fence 1023 is higher than the top surface of the second type semiconductor layer 1020, as shown in FIG 10D. In some embodiments, the top surface of the ion implantation fence 1023 is lower than the top surface of the second type semiconductor layer 1020, as shown in FIG 10E.

[0070] In some embodiments, the mesa structure 1021 includes one stair structure 1021a, as shown in Figure 10F. In some embodiments, the mesa structure 1021 can have multiple stair structures.

[0071] 12A and 12B are structural diagrams showing side cross-sectional views of another variation of a second exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 12A, the micro LED further includes a bottom isolation layer 1040 formed under the first type semiconductor layer 1010. Preferably, the material of the bottom isolation layer 1040 is selected from one or more of SiO2, SiNx, or Al2O3. An integrated circuit (IC) backplane 1090 is formed under the first type semiconductor layer 1010 and electrically connected to the first type semiconductor layer 1010 through a connection structure 1050. The connection structure 1050 is a connection pillar. The micro LED further includes a bottom contact 1060 formed at the bottom of the first type semiconductor layer 1010. The top surface of the connection structure 1050 is connected to the bottom contact 1060, and the bottom of the connection structure 1050 is connected to the IC backplane 1090. In this embodiment, a bottom contact 1060 protrudes from the first type semiconductor layer 1010 as a bottom contact of the micro LED.

[0072] Further, in some embodiments, the micro LED further includes a top contact 1080 and a top conductive layer 1070. The top contact 1080 is formed on the second type semiconductor layer 1020. The top conductive layer 1070 is formed on the top surface of the second type semiconductor layer 1020 and on the top surface of the top contact 1080, and covers the sidewall of the second trench 1022. Preferably, a dielectric layer 1071 is formed on the sidewall and bottom surface of the trench 1022. The conductivity type of the top contact 1080 is the same as the conductivity type of the second type semiconductor layer 1020. For example, the conductivity type of the second type semiconductor layer 1020 is N-type, and the conductivity type of the top contact 1080 is N-type. The top contact 1080 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 1080 is used to form an ohmic contact between the top conductive layer 1070 and the second type semiconductor layer 1020 to optimize the electrical properties of the micro LED. The diameter of the top contact 1080 is about 20-50 nm, and the thickness of the top contact 1080 is about 10-20 nm.

[0073] 12B, the connection structure 1050 can be a metal bonding layer for bonding the micro-LEDs with an IC backplane 1090. Furthermore, in this embodiment, the bottom contact 1060 is a bottom contact layer.

[0074] 13 is a structural diagram illustrating a side cross-sectional view of another variation of a second exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 13, a dielectric layer 1071 may be filled in the second trench 1022. A conductive layer 1070 is formed over the entire substrate. In some embodiments, the dielectric layer 1071 may be formed on the top surface of the second type semiconductor layer 1020. In some embodiments, the dielectric layer may be a multi-layer structure, and the material of the first portion of the dielectric layer in the trench and the material of the second portion of the dielectric layer may be different.

[0075] Figure 14 shows a flowchart of a method 1400 for fabricating a second exemplary micro LED, such as the micro LED shown in Figure 13, according to some embodiments of the present disclosure. As shown in Figure 14, the method for fabricating a micro LED includes steps 1401-1406. Figures 15A-15F are structural diagrams illustrating cross-sectional side views of the micro LED fabrication process at each step (i.e., steps 1401-1406) of the method 1400 shown in Figure 14, according to some embodiments of the present disclosure.

[0076] 14 and 15A-15F. In step 1401, an epitaxial structure is provided. As shown in FIG. 15A, the epitaxial structure includes, from top to bottom, a first type semiconductor layer 1510, a first type cap layer 1514, a light emitting layer 1530, a second type cap layer 1524, and a second type semiconductor layer 1520. The epitaxial structure is grown on a substrate 1500. The substrate 1500 can be GaN, GaAs, etc.

[0077] Preferably, before turning the epitaxial structure upside down, a bottom contact layer 1560 used as a bottom contact is deposited on the top surface of the first type semiconductor layer 1510. Then, a metal bonding layer used as a connection structure 1550 is first deposited on the top surface of the bottom contact layer 1560.

[0078] In step 1402, referring to Fig. 15B, the epitaxial structure is bonded to an IC backplane 1590. The epitaxial structure is first turned upside down. Then, a metal bonding process is used to bond the connection structures 1550 to the contact pads of the IC backplane 1590. Finally, the substrate 1500 is removed by conventional separation methods such as laser stripping or chemical etching. The arrows indicate the direction of removal of the substrate 1500.

[0079] In step 1403, referring to FIG. 15C, a second type semiconductor layer 1520 is patterned to form mesa structures 1521, trenches 1522, and fences 1523'.

[0080] In some embodiments, step 1403 further includes etching the second type semiconductor layer and the second type cap layer, and stopping the etch at a top surface of light emitting layer 1030 to avoid etching the light emitting layer during the patterning process. As shown in FIG. 15C, the bottom surface of trench 1522 contacts light emitting layer 1530.

[0081] In some embodiments, step 1403 further includes sequentially etching the second type semiconductor layer and the light emitting layer, and stopping the etch in light emitting layer 1030. Referring back to FIG. 10B , a bottom surface of trench 1022 contacts and is located within light emitting layer 1030.

[0082] In some embodiments, step 1403 further includes sequentially etching the second type semiconductor layer, the light emitting layer, and the first type semiconductor layer, and stopping the etch in the first type semiconductor layer. Referring back to FIG. 10C, the bottom of trench 1022 contacts and is located within first type semiconductor layer 1010.

[0083] The second type semiconductor layer 1520 is etched by conventional dry etching techniques, such as plasma etching techniques, as would be understood by one of ordinary skill in the art.

[0084] In step 1404, referring to FIG. 15D, a top contact 1580 is deposited on the mesa structure 1521. Before the top contact 1580 is deposited, a first protective mask (not shown) is used to protect the area where the top contact 1580 is not to be formed. Then, the material of the top contact 1580 is deposited on the first protective mask and on the second type of semiconductor layer 1520 by a conventional deposition method such as physical vapor deposition or chemical vapor deposition. After the deposition step, the first protective mask is removed from the second type of semiconductor layer 1520, and the material on the first protective mask is also removed together with the first protective mask to form the top contact 1580 on the mesa structure 1521.

[0085] In step 1405, referring to FIG. 15E, an ion implantation process is performed in the fence 1523'. Referring also to FIG. 15D, the ion implantation process implants ions into the fence 1523' (as shown in FIG. 15D) to form the ion-implanted fence 1523 (as shown in FIG. 15E). The arrows indicate the direction of the ion implantation process. Prior to the ion implantation process, a second protective mask (not shown) is formed in the areas where ions are not to be implanted. Ions are then implanted into the exposed fence 1523' (as shown in FIG. 15D). The second protective mask is then removed by conventional chemical etching methods, as will be understood by those skilled in the art. Preferably, the implantation energy is between 0 and 500 KeV, and the implantation dose is between 1E10 and 9E17.

[0086] 15F, a top conductive layer 1570 is deposited on top of the second type semiconductor layer 1520 and on top contact 1580, and lines the sidewalls of trench 1522. Top conductive layer 1570 is deposited by conventional physical vapor deposition.

[0087] Prior to forming the top conductive layer 1570, a dielectric layer 1571 is formed on the sidewalls and bottom surface of the trench 1522. As shown in FIG. 15F, the dielectric layer 1571 is formed on the sidewalls of the second type semiconductor layer 1520, the mesa structure 1521, and the second type cap layer 1524 in the trench 1522, and on the surface of the light emitting layer 1530 in the trench 1522. In some embodiments, referring back to FIG. 10B, a dielectric layer may be formed on the sidewalls of the second type semiconductor layer 1020, the mesa structure 1021, and the light emitting layer 1030 in the trench 1022, and on the surface of the light emitting layer 1030 in the trench 1022. In some embodiments, referring back to FIG. 10C , a dielectric layer may be formed on the sidewalls of the mesa structure 1021, the second type cap layer 1024, the light emitting layer 1030, the first type cap layer 1014, and on the sidewalls and surface of the first type semiconductor layer 1010 in the trench 1022.

[0088] 15F, a top conductive layer 1570 is formed on the surface of the dielectric layer 1571 and covers the sidewalls and bottom of the trench 1522, the top surface of the second mesa structure 1521, and the top surface of the ion implantation fence 1523. Further, in some embodiments, referring back to FIG. 13, the dielectric layer 1071 may completely fill the second trench 1022. As can be appreciated by one skilled in the art, a microlens may further be formed on the top conductive layer.

[0089] Some embodiments of the present disclosure further provide a micro LED array panel, which includes a plurality of micro LEDs as described above, as shown in Figures 10A-10H, 12A, 12B and 13. These micro LEDs may be arranged in an array within the micro LED array panel.

[0090] 16 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the second exemplary micro LEDs according to some embodiments of the present disclosure. As shown in FIG. 16, the micro LED array panel includes a first type semiconductor layer 1610 formed continuously in the micro LED array panel, a first type cap layer 1614 formed continuously on the first type semiconductor layer 1610, a light emitting layer 1630 formed continuously on the first type semiconductor layer 1610, a second type cap layer 1624 formed continuously on the light emitting layer 1630, and a second type semiconductor layer 1620 formed continuously on the second type cap layer 1624.

[0091] The second type semiconductor layer 1620 includes a plurality of mesa structures 1621, a plurality of trenches 1622, and a plurality of ion implantation fences 1623 separated from the mesa structures 1621 by the trenches 1622. The bottom surfaces of the ion implantation fences 1623 are not lower than the bottom surface of the second type semiconductor layer 1620.

[0092] 17 is a structural diagram showing a top view of the side-by-side micro LEDs of FIG. 16 according to some embodiments of the present disclosure. In FIG. 17, the top view shows that an ion implantation fence 1623 is formed around the trench 1622 and between the adjacent mesa structures 1621. The electrical resistance of the ion implantation fence 1623 is higher than the electrical resistance of the mesa structures 1621. The ion implantation fence 1623 is formed around the trench 1622 and the trench 1622 is formed around the mesa structure 1621.

[0093] The variations in the relationship between the bottom surface of the ion implantation fence 1623, the bottom surface of the second type semiconductor layer 1620, and the bottom of the trench 1622 generally correspond to those shown for the micro LEDs of Figures 10A-10E and will not be described further herein. Furthermore, in some embodiments, the variations in the relationship between the top surface of the ion implantation fence 1623 and the top surface of the second type semiconductor layer 1620 generally correspond to those shown for the micro LEDs of Figures 10E-10G and will not be described further herein. In some embodiments, the mesa structure can have one or more staircase structures, as shown in Figure 10H.

[0094] In some embodiments, the spacing between adjacent sidewalls of adjacent ones of the mesa structures 1621 can be adjusted. For example, in some embodiments, the spacing between adjacent sidewalls of the mesa structures 1621 is 50% or less of the diameter of the mesa structures 1621. In some embodiments, the spacing between adjacent sidewalls of the mesa structures 1621 is 30% or less of the diameter of the mesa structures 1621. Preferably, the spacing between adjacent sidewalls of the mesa structures 1621 is 600 nm or less. Furthermore, in some embodiments, the width of the ion implantation fence 1623 can be adjusted. For example, the width of the ion implantation fence 1623 can be 50% or less of the diameter of the mesa structures 1621. In some embodiments, the width of the ion implantation fence 1623 can be 10% or less of the diameter of the mesa structures 1621. Preferably, in a micro LED array panel, the width of the ion implantation fence 1623 is 200 nm or less.

[0095] A bottom contact 1660 is formed on the bottom of the first type semiconductor layer 1610. The connection structure 1650 is a metal bonding layer for bonding the micro LED to an IC backplane 1690. Details of the bottom contact 1660, the connection structure 1650, and the IC backplane 1690 can be seen with reference to the above-described micro LEDs in Figures 12A and 12B.

[0096] Figure 18 is a structural diagram illustrating a side cross-sectional view of adjacent ones of the micro LEDs of Figure 12B in a micro LED array panel according to some embodiments of the present disclosure. As shown in Figure 18, the micro LED array panel further includes a top contact 1880, a dielectric layer 1871, and a top conductive layer 1870. Further details of the top contact 1880, the dielectric layer 1871, and the top conductive layer 1870 can also be understood with reference to Figures 10A-10F, Figures 12A and 12B, and the micro LEDs shown in Figure 13, which will not be described further herein.

[0097] Further, referring back to FIG. 18 , an IC backplane 1890 is formed below the first type semiconductor layer 1810 and electrically connected to the first type semiconductor layer 1810 via a connection structure 1850. The micro LED array panel further includes a bottom contact 1860 formed at the bottom of the first type semiconductor layer 1810. The connection structure 1850 may be a metal bonding layer for bonding the micro LEDs with the IC backplane 1890. Further, in some embodiments, the bottom contact 1860 is a bottom contact layer. Further details of the bottom isolation layer 1840, the IC backplane 1890, the bottom contact 1860, and the connection structure 1850 can be understood by also referring to FIG. 12B, which will not be further described here.

[0098] Further details regarding the characteristics of the micro LEDs and ion implanted fences in the micro LED array panel can also be understood by reference to the micro LEDs as shown in Figures 10A-10H, which will not be described further herein.

[0099] The micro LED array panel shown in FIG. 18 can be manufactured by the method for manufacturing the micro LEDs 1400 shown in FIG. 14, which will not be described further here.

[0100] EMBODIMENT 3 19A-19F are structural diagrams illustrating cross-sectional side views of different variations of a third exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 19A, in some embodiments, the micro LED includes at least a first type of semiconductor layer 1910, a first type of cap layer 1914, a light emitting layer 1930, a second type of cap layer 1924, and a second type of semiconductor layer 1920. The conductivity type of the first type of semiconductor layer 1910 is different from the conductivity type of the second type of semiconductor layer 1920. For example, in some embodiments, the conductivity type of the first type of semiconductor layer 1910 is P-type and the conductivity type of the second type of semiconductor layer 1920 is N-type. In some embodiments, the conductivity type of the second type of semiconductor layer 1920 is P-type and the conductivity type of the first type of semiconductor layer 1910 is N-type. The thickness of the first type of semiconductor layer 1910 is greater than the thickness of the second type of semiconductor layer 1920. The thickness of the first type semiconductor layer 1910 can be less than the thickness of the second type semiconductor layer 1920. In some embodiments, the material of the first type semiconductor layer 1910 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer 1920 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. The conductivity type of the first type cap layer 1914 is the same as the conductivity type of the first type semiconductor layer 1910, and the conductivity type of the second type cap layer 1924 is the same as the conductivity type of the second type semiconductor layer 1920.

[0101] The first type semiconductor layer 1910 includes a first mesa structure 1911, a first trench 1912, and a first ion implantation fence 1913 separated from the first mesa structure 1911. The second type semiconductor layer 1920 includes a second mesa structure 1921, a second trench 1922, and a second ion implantation fence 1923 separated from the second mesa structure 1921.

[0102] In combination with FIG. 1A, the first trench can extend upward through the top of the first type of semiconductor layer and into the first type of cap layer. In combination with FIG. 1B, the first trench can extend upward through the first type of semiconductor layer and the first type of cap layer to contact the light emitting layer. Furthermore, the first trench can extend into the light emitting layer. In some embodiments, the first trench can extend upward through the first type of semiconductor layer, the first type of cap layer, and the light emitting layer. Furthermore, the first trench can extend upward into the second type of cap layer. In some embodiments, in combination with FIG. 1C, the first trench can extend upward through the first type of semiconductor layer, the first type of cap layer, and the light emitting layer into the second type of cap layer. Furthermore, the first trench can extend upward into the second type of semiconductor layer. Additionally, the first trench can extend upward through the first type semiconductor layer, the first type cap layer, the light emitting layer, the second type cap layer, and the second type semiconductor layer.

[0103] In combination with FIG. 10A, the second trench can extend down through the second type of semiconductor layer and into the interior of the second type of cap layer. Furthermore, in combination with FIG. 10B, the second trench can extend down through the second type of semiconductor layer and through the second type of cap layer and can reach the light emitting layer. Furthermore, the second trench can extend into the interior of the light emitting layer. In some embodiments, the second trench can extend down through the second type of semiconductor layer, the second type of cap layer, and the light emitting layer. Furthermore, the second trench can extend down into the interior of the first type of cap layer. In some embodiments, in combination with FIG. 10C, the second trench can extend down through the second type of semiconductor layer, the second type of cap layer, the light emitting layer, and the first type of cap layer and can extend down into the interior of the first type of semiconductor layer. Additionally, the second trench can extend down through the second type semiconductor layer, the second type cap layer, the light emitting layer, the first type cap layer, and the first type semiconductor layer.

[0104] 19A-19D, the top of the first trench 1912 does not contact the bottom of the second trench 1922 in either the horizontal or vertical direction. A portion of the light emitting layer 1930 is configured between the top surface of the first trench 1912 and the bottom surface of the second trench 1922. Further, in some embodiments, with reference to FIGS. 19E and 19F, the top surface of the first trench 1912 is directly connected to the bottom of the second trench 1922 in the horizontal and vertical directions. In some embodiments, as shown in FIG. 19E, there is no light emitting layer between the top of the first trench 1912 and the bottom of the second trench 1922. That is, the first trench 1912 and the second trench 1922 are interconnected when the first trench 1912 and the second trench 1922 extend vertically through one another. The center of the first trench 1912 can be aligned with or offset from the center of the second trench 1922. In some embodiments, the first trench 1912 and the second trench 1922 are not aligned with each other in the vertical direction, as shown in Figures 19D and 19F. Furthermore, in some embodiments, the diameters from top to bottom of the first trench 1912 can be the same or different. The diameters from top to bottom of the second trench 1922 can be the same or different. The diameter of the first trench 1912 can be the same or different from the diameter of the second trench 1922.

[0105] In some embodiments, the center of the first mesa structure 1911 is aligned with the center of the second mesa structure 1921, the center of the first trench 1912 is aligned with the center of the second trench 1922, and the center of the first ion implantation fence 1913 is aligned with the center of the second ion implantation fence 1923.

[0106] The relationship between the top surface of the first ion implantation fence 1913, the top surface of the first trench 1912, and the top surface of the first type semiconductor layer 1910 is the same as that of the micro LED of the first embodiment shown in Figures 1A-1D, which will not be further described here. The relationship between the bottom of the first ion implantation fence 1913, the bottom of the first trench 1912, and the bottom of the first type semiconductor layer 1910 is the same as that of the micro LED of the first embodiment shown in Figures 1D-1G, which will not be further described here. Furthermore, in some embodiments, the first mesa structure 1911 can have one or more staircase structures, as shown in Figure 1H.

[0107] The relationship between the bottom of the second ion-implanted fence 1923, the bottom of the second trench 1922, and the bottom of the second type semiconductor layer 1920 is the same as that of the micro LED of the second embodiment shown in Figures 10A-10E, and will not be further described here. The relationship between the top surface of the second ion-implanted fence 1923, the top surface of the second trench 1922, and the top surface of the second type semiconductor layer 1920 is the same as that of the micro LED of the second embodiment shown in Figures 10E-10G, and will not be further described here. Furthermore, in some embodiments, the second mesa structure 1921 can have one or more staircase structures, as shown in Figure 10H.

[0108] FIG. 20 is a structural diagram showing a side cross-sectional view of another variation of the third exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 20, the micro LED further includes a bottom isolation layer 2040 filled in the first trench 2012. Preferably, the material of the bottom isolation layer 2040 is one or more of SiO2, SiNx, or Al2O3. The IC backplane 2090 is formed under the first type semiconductor layer 2010 and electrically connected with the first type semiconductor layer 2010 through a connection structure 2050. In this specification, the connection structure 2050 is a connection pillar. The micro LED further includes a bottom contact 2060 formed at the bottom of the first type semiconductor layer 2010. Further details of the bottom isolation layer 2040, the IC backplane 2090, the connection structure 2050, and the bottom contact 2060 can be known by referring to the description of the first embodiment, which will not be further described here.

[0109] The micro LED further includes a top contact 2080 and a top conductive layer 2070. The top contact 2080 is formed on the second type semiconductor layer 2020. The top conductive layer 2070 is formed on top of the second type semiconductor layer 2020 and the top contact 2080, and covers the sidewalls and bottom of the second trench 2022. Further details regarding the top contact 2080 and the top conductive layer 2070 can be known by referring to the description of the second embodiment, which will not be further described here.

[0110] Further details regarding the micro LED shown in FIG. 20, including the first ion-implanted fence 2013 and the second ion-implanted fence 2023, can be found by reference to the descriptions of embodiments 1 and 2, and will not be described further here.

[0111] 21 shows a flowchart of a third exemplary method 2100 for manufacturing a micro LED according to some embodiments of the present disclosure. The method 2100 includes at least step I and step II.

[0112] In step I, a first type of semiconductor layer is patterned, and then ions are implanted into the first type of semiconductor layer to form a first ion implantation fence.

[0113] In step II, after the second type of semiconductor layer is patterned, ions are implanted into the second type of semiconductor layer to form a second ion implantation fence.

[0114] Referring to FIG. 21, process I includes at least steps 2101-2109, and process II includes at least steps 2110-2113.

[0115] For process I, steps 2101-2109 are similar to steps 501-509 of method 500 shown in FIG. 5. The cross-sectional side views of the micro LEDs fabricated according to steps 2101-2109 are similar to those shown in FIG. 6A-6I. Please refer to FIG. 21 and FIG. 6A-6I. In step 2101, referring to FIG. 6A, an epitaxial structure is provided. The epitaxial structure includes, from top to bottom, a first type semiconductor layer 610, a first type cap layer 614, a light emitting layer 630, a second type cap layer 624 and a second type semiconductor layer 620. In step 2102, referring to FIG. 6B, the first type semiconductor layer 610 is patterned to form a mesa structure 611, a trench 612 and a fence 613'.

[0116] In step 2103, referring to FIG. 6C, a bottom contact 660 is deposited on the mesa structure 611.

[0117] In step 2104, with reference to FIG. 6D, an ion implantation process is performed within fence 613'.

[0118] In step 2105, referring to FIG. 6E, a bottom isolation layer 640 is deposited over the substrate 600.

[0119] A bottom isolation layer can be filled into the first trench. In some embodiments, the bottom isolation layer can be formed on the sidewalls of the first mesa structure, the first ion implantation fence, the first type of semiconductor layer, the first type of cap layer, the light emitting layer and the second type of semiconductor layer, the second mesa structure, the second type of cap layer, and the second type of ion implantation fence in the first trench, which depends on the depth of the first trench.

[0120] In step 2106, with reference to FIG. 6F, the bottom isolation layer 640 is patterned to expose the bottom contact 660.

[0121] In step 2107, referring to FIG. 6G, a metal material 650' is deposited over the substrate 600.

[0122] In step 2108, referring to FIG. 6H, the top of the metal material 650' is polished down to the top of the bottom isolation layer 640 to form the connecting pillars 650.

[0123] In step 2109, referring to FIG. 6I, the connection pillars 650 are bonded with the IC backplane 690 and the substructure 600 is removed.

[0124] 22A-22D are structural diagrams illustrating cross-sectional side views of a micro LED manufacturing process in steps 2110-2113 of the method 2100 shown in FIG. 21, according to some embodiments of the present disclosure. With reference to FIG. 21 and FIG. 22A-22D, in step 2110, with reference to FIG. 22A, a second type semiconductor layer 2220 is patterned to form mesa structures 2221, trenches 2222, and fences 2223′.

[0125] In step 2111, referring to FIG. 22B, a top contact 2280 is deposited on the mesa structure 2221.

[0126] In step 2112, with reference to Figure 22C, an ion implantation process is performed in fence 2223' to form ion implant fence 2223. The arrows in Figure 22B indicate the direction of the ion implantation process.

[0127] 22D , in step 2113, a top conductive layer 2270 is deposited on the top of the second type semiconductor layer 2220 and on the top contacts 2280 and in the trenches 2222. In some embodiments, the top conductive layer 2270 can be formed directly on the top of the second type semiconductor layer 2220 and on the top contacts 2280, as well as on the sidewalls and bottom of the trenches 2222.

[0128] 23A and 23B are structural diagrams illustrating side cross-sectional views of another variation of a third exemplary microLED according to some embodiments of the present disclosure. As shown in FIG. 23A, a bottom isolation layer 2340 is filled in the first trench 2312 and formed on the sidewalls of the first mesa structure 2311, the first ion-implanted fence 2313, the first type cap layer 2314, and the light emitting layer 2330 in the first trench 2312. Before forming the top conductive layer 2370, a dielectric layer 2371 is formed extending into the second trench 2322. The dielectric layer 2371 is formed on the sidewalls and bottom of the second trench 2322. Also, a dielectric layer 2371 is formed on the sidewalls of the second mesa structure 2321, the second type semiconductor layer 2320, the second ion implantation fence 2323, the second type cap layer 2324 and the light emitting layer 2330 within the second trench 2322. Then, an upper conductive layer 2370 extending into the second trench 2322 is formed on the surface of the dielectric layer 2371, on the second mesa structure 2321 and on the second ion implantation fence 2323.

[0129] In some embodiments, as shown in FIG. 23B, the bottom isolation layer 2340 is filled into the first trench 2312 and formed on the sidewalls of the first mesa structure 2311, the first ion implantation fence 2313, and the first type of semiconductor layer 2310. A top conductive layer 2370 can be formed extending into the second trench 2322. Additionally, a dielectric layer 2371 is formed extending into the second trench 2322. The dielectric layer 2371 is formed on the sidewalls of the second mesa structure 2321, the second type of semiconductor layer 2320, the second ion implantation fence 2323, the second type of cap layer 2324, the light emitting layer 2330, the first mesa structure 2311, the first type of cap layer 2314, the first ion implantation fence 2313, and the first type of semiconductor layer 2310 in the second trench 2322.

[0130] A bottom isolation layer 2340 is formed on the sidewalls and top of the first trench 2312, and a dielectric layer 2371 is formed on the sidewalls and bottom of the second trench 2322. The thickness of the bottom isolation layer extending into the first trench 2312 depends on the location of the bottom of the second trench 2322 and the location of the top of the first trench 2312. The thickness of the dielectric layer 2371 extending into the second trench 2322 depends on the location of the bottom of the second trench 2322 and the location of the top of the first trench 2312.

[0131] Top and bottom contacts may be formed on micro-LEDs according to some embodiments of the present disclosure and will not be described further herein.

[0132] Further details of step I can be known by referring to the description of steps 501 to 509 in embodiment 1. Further details of step II can be known by referring to the description of steps 1403 to 1406 in embodiment 2, which will not be further described here.

[0133] Some embodiments of the present disclosure further provide a micro LED array panel, which includes a plurality of micro LEDs as described above, as shown in Figures 19A-19E, 20, 23A and 23B, and which may be arranged in an array within the micro LED array panel.

[0134] 24 is a structural diagram showing a side cross-sectional view of adjacent ones of the micro LEDs of FIG. 23A in a micro LED array panel according to some embodiments of the present disclosure. As shown in FIG. 24, the micro LED array panel includes at least: The micro LED array panel includes a first type of semiconductor layer 2410 formed continuously in the micro LED array panel, a first type of cap layer 2414 formed continuously on the first type of semiconductor layer 2410, an emissive layer 2430 formed continuously on the first type of cap layer 2414, a second type of cap layer 2424 formed continuously on the emissive layer 2330, and a second type of semiconductor layer 2420 formed on the second type of cap layer 2324.

[0135] The first type semiconductor layer 2410 includes a plurality of first mesa structures 2411, a plurality of first trenches 2412, and a plurality of first ion implantation fences 2413 separated from the first mesa structures via the first trenches 2412. The top surface of the first ion implantation fences 2413 is lower than the top surface of the first type semiconductor layer 2410. Referring back to FIG. 8, the bottom view of the micro LED array panel without an IC backplane is similar to the bottom view shown in FIG. 8. The first ion implantation fences 2413 are formed around the first trenches 2412 and between adjacent first type mesa structures 2411. The electrical resistance of the first ion implantation fences 2413 is higher than the electrical resistance of the first mesa structures 2411. Additionally, a first ion implantation fence 2413 is formed around the first trench 2412 , which is formed around the first mesa structure 2411 .

[0136] The second type semiconductor layer 2420 includes a plurality of second mesa structures 2421, a plurality of second trenches 2422, and a plurality of second ion implantation fences 2423 separated from the second mesa structures 2421 via the second trenches 2422. The bottom surface of the second ion implantation fences 2423 is higher than the bottom surface of the second type semiconductor layer 2420. The top view of the micro LED array panel is similar to the top view shown in FIG. 17 in that the second ion implantation fences 2423 are formed around the second trenches 2422 and between adjacent second mesa structures 2421. The electrical resistance of the second ion implantation fences 2423 is higher than the electrical resistance of the second mesa structures 2421. A second ion implantation fence 2323 is formed around the second trench 2422 , which is formed around the second mesa structure 2421 .

[0137] In some embodiments, the spacing between adjacent sidewalls of the first mesa structure 2411 can be adjusted. For example, in some embodiments, the spacing between adjacent sidewalls of the first mesa structure 2411 is 50% or less of the diameter of the first mesa structure 2411. In some embodiments, the spacing between adjacent sidewalls of the first mesa structure 2411 is 30% or less of the diameter of the first mesa structure 2411. Preferably, the spacing between adjacent sidewalls of the first mesa structure 2411 is 600 nm or less. Furthermore, in some embodiments, the width of the first ion implantation fence 2413 can be adjusted. For example, in some embodiments, the width of the first ion implantation fence 2413 is 50% or less of the diameter of the first mesa structure 2411. In some embodiments, the width of the first ion implantation fence 2313 is 10% or less of the diameter of the first mesa structure 2311. Preferably, in some embodiments, in a micro LED array panel, the width of the first ion implantation fence 2413 is 200 nm or less. The spacing between adjacent sidewalls of the second mesa structure 2421 is 50% or less of the diameter of the second mesa structure 2421. In some embodiments, the spacing between adjacent sidewalls of the second mesa structure 2421 is 30% or less of the diameter of the second mesa structure 2421. Preferably, the spacing between adjacent sidewalls of the second mesa structure 2421 is 600 nm or less. Furthermore, the width of the second ion implantation fence 2423 is 50% or less of the diameter of the second mesa structure 2421. In some embodiments, the width of the second ion implantation fence 2423 is 10% or less of the diameter of the second mesa structure 2421. Preferably, in a micro LED array panel, the width of the second ion implantation fence 2423 is 200 nm or less.

[0138] The micro LED array panel further includes a bottom isolation layer 2440 filled in the first trench 2412. Preferably, in some embodiments, the material of the bottom isolation layer 2440 is one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2. Furthermore, an IC backplane 2490 is formed under the first type semiconductor layer 2410 and electrically connected with the first type semiconductor layer 2410 through a connection structure 2450. The micro LED array panel further includes a bottom contact 2460 formed at the bottom of the first type semiconductor layer 2410. The top surface of the connection structure 2450 is connected with the bottom contact 2460, and the bottom of the connection structure 2450 is connected with the IC backplane 2490. The bottom contact 2460 is a protruding contact. 4, the connection structure 2450 can be a metal bonding layer for bonding the micro-LEDs with an IC backplane 2490. Further, in some embodiments, the bottom contact 2460 is a bottom contact layer.

[0139] Referring back to FIG. 24 , the micro LED array panel further includes a top contact 2480 and a top conductive layer 2470. The top contact 2480 is formed on the second type semiconductor layer 2420. The top conductive layer 2470 is formed on the top of the second type semiconductor layer 2420 and the top contact 2480, covering the sidewall and bottom of the second trench 2422. The conductivity type of the top contact 2480 is the same as the conductivity type of the second type semiconductor layer 2420. For example, the conductivity type of the second type semiconductor layer 2420 is N-type, and the conductivity type of the top contact 2480 is N-type. The top contact 2480 is made of a metal or metal alloy, such as AuGe, AuGeNi, etc. The top contact 2480 is used to form an ohmic contact between the top conductive layer 2470 and the second type semiconductor layer 2420 to optimize the electrical properties of the micro LED. The diameter of the top contact 2480 is about 20-50 nm, and the thickness of the top contact 2480 is about 10-20 nm.

[0140] Additionally, a dielectric layer 2471 is formed on the sidewalls and bottom of the second trench 2422 underlying the upper conductive layer 2470 .

[0141] Further detailed characteristics of the micro LEDs in the micro LED array panel can be known by reference to the micro LEDs above, which will not be described further here.

[0142] The manufacturing method of the micro LED array panel at least includes: manufacturing the micro LEDs. The details of the manufacturing of the micro LEDs can be known by referring to the description of steps 501-509 in embodiment 1 and the description of steps 1403-1406 in embodiment 2, which will not be further described here.

[0143] In the first to third embodiments, a microlens may further be formed on or above the top surface of the second type semiconductor layer, such as on the top surface of the upper conductive layer, as can be understood by those skilled in the art.

[0144] The micro LEDs herein have a very small volume. The micro LEDs may be organic or inorganic LEDs. The micro LEDs may be applied to a micro LED array panel. The light emitting area of ​​the micro LED array panel is very small, for example 1 mm x 1 mm, 3 mm x 5 mm. In some embodiments, the light emitting area is the area of ​​the micro LED array in the micro LED array panel. The micro LED array panel includes one or more micro LED arrays forming a pixel array in which the micro LEDs are pixels, such as a 1600 x 1200, 680 x 480, or 1920 x 1080 pixel array. The diameter of the micro LEDs is in the range of about 200 nm to 2 μm. An IC backplane is formed on the back of the micro LED array and electrically connected to the micro LED array. The IC backplane receives signals such as image data from the outside via signal lines and controls whether or not the corresponding micro LEDs are made to emit light.

[0145] It should be noted that, as used herein, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another and do not require or imply an actual relationship or order between those entities or operations. Additionally, the words "comprising," "having," "containing," and "including," as well as other similar forms, are intended to have equivalent meanings and be open-ended, in that the item or items following any one of these words are not intended to be an exhaustive listing of such item or items, nor are they intended to be limited to only the item or items listed.

[0146] As used herein, unless otherwise stated, the term "or" includes all possible combinations unless impracticable. For example, if it is stated that a database can include A or B, the database can include A, or B, or A and B, unless otherwise stated or impracticable. As a second example, if it is stated that a database can include A, B, or C, the database can include A, or B, or C, or A and B, or A and B and C, unless otherwise stated or impracticable.

[0147] In the foregoing specification, the embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. Certain adaptations and modifications may be made to the described embodiments. Other embodiments may be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims. It is also intended that the order of steps depicted in the figures is for illustrative purposes only, and is not intended to be limited to the particular order of steps. Thus, one skilled in the art can appreciate that these steps may be performed in different orders while performing the same method.

[0148] In the drawings and specification, illustrative embodiments have been disclosed. However, many variations and modifications to these embodiments may be made. Thus, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A micro LED, a first type semiconductor layer; a first type cap layer formed on the first type semiconductor layer; a light-emitting layer formed on the first type of cap layer; Equipped with the first type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extending upwardly through the first type semiconductor layer and upwardly into at least a portion of the first type cap layer; The ion implantation fence is formed around the trench, the trench is formed around the mesa structure, and an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure.

2. 2. The micro-LED of claim 1 , wherein a top surface of the ion implanted fence is lower than or aligned with a top surface of the first type semiconductor layer.

3. 10. The micro-LED of claim 1, wherein a bottom surface of the ion implanted fence is aligned with, or is higher or lower than, a bottom surface of the first type semiconductor layer.

4. The micro-LED of claim 1 , wherein a top surface of the ion implanted fence is lower than a top surface of the trench.

5. The micro LED of claim 1 , wherein the trench extends upwardly through the first type cap layer.

6. The microLED of claim 5 , wherein the trench extends upwardly into at least a portion of the light emitting layer.

7. 10. The micro LED of claim 1, further comprising a second type cap layer formed on top of the light emitting layer and a second type semiconductor layer formed on the second type cap layer, the second type semiconductor layer having a different conductivity type than the first type semiconductor layer.

8. 8. The micro LED of claim 7, wherein the trench extends through the first type cap layer, the light emitting layer, and further upwardly into the second type cap layer.

9. 9. The micro LED of claim 8, wherein the trench extends upward through the second type cap layer and further into the second type semiconductor layer.

10. 10. The micro LED of claim 9, wherein the trench further extends upward through the second type semiconductor layer.

11. 10. The micro-LED of claim 1 , wherein the mesa structure comprises one or more stair structures.

12. 10. The micro LED of claim 1 , wherein the width of the trench is less than or equal to 50% of the width of the mesa structure.

13. 13. The micro-LED of claim 12, wherein the width of the trench is less than or equal to 200 nm.

14. 10. The micro-LED of claim 1, wherein the ion implanted fence comprises a light absorbing material, the light absorbing material being selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

15. 10. The micro LED of claim 1 , wherein a thickness of the first type semiconductor layer is greater than a thickness of the light emitting layer.

16. 10. The micro-LED of claim 1 further comprising a bottom isolation layer filled in said trench.

17. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 17. The micro-LED of claim 16, wherein the micro-LED is selected from one or more of:

18. 10. The micro LED of claim 1, wherein the ion implanted fence is formed by implanting ions into at least the first type semiconductor layer.

19. 20. The micro LED of claim 18, wherein the ions implanted in the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

20. 10. The micro-LED of claim 1 , wherein a width of the ion implanted fence is less than or equal to 50% of a diameter of the mesa structure.

21. 21. The microLED of claim 20, wherein the width of the ion implanted fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 100 nm.

22. 8. The micro LED of claim 7, wherein the material of the first type semiconductor layer is one or more of GaAs, GaP, AlInP, GaN, InGaN, AlGaN and the material of the second type semiconductor layer is one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN and AlGaN.

23. 10. The micro-LED of claim 1, further comprising an integrated circuit (IC) backplane formed below said first type semiconductor layer, and a connection structure electrically connecting said IC backplane with said first type semiconductor layer.

24. 24. The micro-LED of claim 23, wherein the connection structure is a connection pillar or a metal bonding layer.

25. 24. The micro-LED of claim 23, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

26. 26. A micro LED array panel comprising a plurality of micro LEDs according to any one of claims 1 to 25.

27. A method for manufacturing a micro LED, comprising: providing an epitaxial structure comprising, in top-to-bottom order, a first type of semiconductor layer, a first type of capping layer, a light emitting layer, a second type of capping layer, and a second type of semiconductor layer; patterning the first type semiconductor layer to form mesa structures, trenches, and fences; depositing a bottom contact on the mesa structure; performing an ion implantation process within the fence to form an ion implanted fence; A method comprising:

28. after patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence; depositing a bottom isolation layer over the first type semiconductor layer and the bottom contact; patterning the bottom isolation layer to expose the bottom contact; depositing a metallic material over the bottom isolation layer and the bottom contact; polishing the metal material to a top surface of the bottom isolation layer to form a connection structure; inverting the epitaxial structure and bonding the connection structure to an integrated circuit (IC) backplane; 28. The method of claim 27, further comprising:

29. When depositing the bottom isolation layer on the isolation layer and the bottom contact, the material of the bottom isolation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 29. The method of claim 28, wherein the at least one of the following is selected from one or more of:

30. 30. The method of claim 28, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.

31. Inverting the epitaxial structure and bonding the connection structure to the IC backplane includes: Removing the substrate.

31. The method of claim 30, further comprising:

32. After the epitaxial structure is turned upside down and the connection structure is bonded to the IC backplane, forming an upper contact and an upper conductive layer on an upper surface of the mesa structure; 31. The method of claim 30, further comprising:

33. patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence includes: Etching the first type semiconductor layer down to a surface of the light emitting layer.

28. The method of claim 27, further comprising:

34. patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence includes: sequentially etching the first type semiconductor layer and the light emitting layer; stopping the etching within the light emitting layer; 28. The method of claim 27, further comprising:

35. patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence includes: sequentially etching the first type semiconductor layer, the light emitting layer, and the second type semiconductor layer; stopping the etching in the second type semiconductor layer; 28. The method of claim 27, further comprising:

36. depositing the bottom contact on the mesa structure; forming a protective mask to protect areas where the bottom contact will not be deposited; depositing the bottom contact material over the protective mask and over the first type semiconductor layer; removing the protective mask from the first type semiconductor layer and removing the material above the protective mask to form the bottom contact on the mesa structure; 28. The method of claim 27, further comprising:

37. performing the ion implantation process within the fence to form the ion implanted fence; forming a protective mask over areas not to be implanted while leaving the fence exposed; implanting ions into the fence; removing said protective mask; 28. The method of claim 27, further comprising:

38. 38. The method of claim 37, wherein said ion implantation step in said fence to form said ion implanted fence is performed with an energy of between 0 and 500 KeV.

39. 38. The method of claim 37, wherein a dose of between 1E10 and 9E17 is implanted when performing the ion implantation step in the fence to form the ion implanted fence.

40. 38. The method of claim 37, wherein the ion implantation step in the fence to form the ion-implanted fence includes implanting ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F into the fence.

41. 38. The method of claim 37, wherein when performing the ion implantation step in the fence to form the ion implanted fence, the width of the ion implanted fence is less than or equal to 50% of a diameter of the mesa structure.

42. 38. The method of claim 37, wherein when performing the ion implantation step in the fence to form the ion implanted fence, the width of the ion implanted fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 300 nm.

43. 28. The method of claim 27, wherein when patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is less than or equal to 50% of a diameter of the mesa structure.

44. 28. The method of claim 27, wherein a conductivity type of the first type semiconductor layer is P-type and a conductivity type of the second type semiconductor layer is N-type, a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

45. 45. The method of claim 44, wherein the ion implanted fence comprises a light absorbing material.

46. 46. ​​The method of claim 45, wherein the light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

47. A micro LED, a first type semiconductor layer; a first type cap layer formed on the first type semiconductor layer; a light-emitting layer formed on the first type of capping layer; a second type of capping layer formed on the light-emitting layer; a second type semiconductor layer formed on the second type cap layer; an integrated circuit (IC) backplane formed on a bottom surface of the first type semiconductor layer; Equipped with the second type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extending downward through the second type semiconductor layer and extending downward into at least a portion of the second type cap layer; the ion implantation fence is formed around the trench, the trench is formed around the mesa structure, and an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure; The conductivity type of the first type semiconductor layer is different from the conductivity type of the second type semiconductor layer. Micro LED.

48. 48. The micro LED of claim 47, wherein a bottom surface of the ion implanted fence is elevated above or aligned with a bottom surface of the second type semiconductor layer.

49. 48. The micro LED of claim 47, wherein a top surface of the ion implanted fence is aligned with, or is higher or lower than, a top surface of the second type semiconductor layer.

50. 48. The micro LED of claim 47, wherein a bottom surface of the ion implanted fence is higher than a bottom surface of the trench.

51. 48. The micro LED of claim 47, wherein the trench extends downward through the second type cap layer.

52. 52. The microLED of claim 51 , wherein the trench extends further downward into at least a portion of the light emitting layer.

53. 53. The microLED of claim 52, wherein the trench extends further down through the light emitting layer into the first type cap layer, or the trench extends further down through the light emitting layer and the first type cap layer and into the first type semiconductor layer.

54. 54. The micro LED of claim 53, wherein the trench extends further down through the first type semiconductor layer.

55. 48. The micro LED of claim 47, wherein the mesa structure comprises one or more stair structures.

56. 48. The micro LED of claim 47, wherein the width of the trench is no more than 50% of the width of the mesa structure.

57. 57. The micro LED of claim 56, wherein the trench has a width of 200 nm or less.

58. 48. The microLED of claim 47, wherein the ion implanted fence comprises a light absorbing material, the light absorbing material being selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

59. 48. The micro LED of claim 47, wherein a thickness of the second type semiconductor layer is greater than a thickness of the light emitting layer.

60. 48. The micro-LED of claim 47, further comprising a bottom isolation layer formed between a bottom surface of the first type semiconductor layer and a top surface of the IC backplane.

61. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 61. The micro-LED of claim 60, wherein the micro-LED is selected from one or more of:

62. 48. The micro LED of claim 47, wherein the ion implanted fence is formed by implanting ions into at least the second type semiconductor layer.

63. 63. The micro LED of claim 62, wherein the ions implanted into the second type semiconductor layer are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

64. 48. The micro LED of claim 47, wherein a width of the ion implanted fence is no more than 50% of a diameter of the mesa structure.

65. 63. The microLED of claim 62, wherein the width of the ion implanted fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 300 nm.

66. 48. The micro LED of claim 47, wherein the material of the first type semiconductor layer is one or more of GaAs, GaP, AlInP, GaN, InGaN, AlGaN and the material of the second type semiconductor layer is one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, and AlGaN.

67. 48. The micro-LED of claim 47, further comprising a connection structure electrically connecting the IC backplane with the first type semiconductor layer.

68. 68. The micro LED of claim 67, wherein the connection structure is a connection pillar or a metal bonding layer.

69. 68. The micro-LED of claim 67, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of the connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

70. 70. A micro LED array panel comprising a plurality of micro LEDs according to any one of claims 47 to 69.

71. A method for manufacturing a micro LED, comprising: providing an epitaxial structure comprising, in top-to-bottom order, a first type of semiconductor layer, a first type of capping layer, a light emitting layer, a second type of capping layer, and a second type of semiconductor layer; bonding the epitaxial structure to an integrated circuit (IC) backplane; patterning the second type semiconductor layer to form mesa structures, trenches, and fences; depositing a top contact on the mesa structure; performing an ion implantation process within the fence; depositing a top conductive layer on the top surface of the second type semiconductor layer, on the top contact, and in the trench; A method comprising:

72. Providing the epitaxial structure includes: depositing a bottom contact layer on a top surface of the first type semiconductor layer; depositing a metal bonding layer on an upper surface of the bottom contact layer; 72. The method of claim 71, further comprising:

73. Bonding the epitaxial structure to the IC backplane comprises: turning the epitaxial structure upside down; bonding said metal bonding layer to a contact pad of said IC backplane; 73. The method of claim 72, further comprising:

74. 74. The method of claim 73, wherein in providing the epitaxial structure, the epitaxial structure is grown on a substrate.

75. Bonding the epitaxial structure to the IC backplane comprises: Removing the substrate.

75. The method of claim 74, further comprising:

76. patterning the second type semiconductor layer to form the mesa structure, the trench, and the fence includes: Etching the second type semiconductor layer down to a surface of the light emitting layer.

72. The method of claim 71, further comprising:

77. patterning the second type semiconductor layer to form the mesa structure, the trench, and the fence includes: sequentially etching the second type semiconductor layer and the light emitting layer; stopping the etching within the light emitting layer; 72. The method of claim 71, further comprising:

78. patterning the second type semiconductor layer to form the mesa structure, the trench, and the fence includes: sequentially etching the second type semiconductor layer, the light emitting layer, and the first type semiconductor layer; stopping the etching in the first type semiconductor layer; 72. The method of claim 71, further comprising:

79. depositing the top contact on the mesa structure; forming a protective mask to protect areas where the top contact will not be deposited; depositing the top contact material over the protective mask; removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask to form the top contact on the mesa structure; 72. The method of claim 71, further comprising:

80. performing the ion implantation step within the fence, forming a protective mask over areas not to be implanted while leaving the fence exposed; implanting ions into the fence; removing said protective mask; 72. The method of claim 71, further comprising:

81. 81. The method of claim 80, wherein the step of implanting ions into the fence is performed with an energy of between 0 and 500 KeV.

82. 81. The method of claim 80, wherein a dose of between 1E10 and 9E17 is implanted when performing the ion implantation step in the fence.

83. 81. The method of claim 80, wherein the ion implantation step in the fence comprises implanting the ion implantation fence with ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

84. 81. The method of claim 80, wherein a width of the ion implantation fence is less than or equal to 50% of a diameter of the mesa structure when performing the ion implantation step within the fence.

85. 81. The method of claim 80, wherein when performing the ion implantation step within the fence, the width of the ion implantation fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and the thickness of the second type semiconductor layer is less than or equal to 100 nm.

86. 72. The method of claim 71, wherein a conductivity type of the first type semiconductor layer is P-type and a conductivity type of the second type semiconductor layer is N-type, a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

87. 87. The method of claim 86, wherein the ion implanted fence comprises a light absorbing material.

88. 88. The method of claim 87, wherein the light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

89. A micro LED, a first type semiconductor layer; a first type cap layer formed on the first type semiconductor layer; a light-emitting layer formed on the first type of capping layer; a second type of capping layer formed on the light-emitting layer; a second type semiconductor layer formed on the second type cap layer; Equipped with the first type semiconductor layer comprises a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure, the first trench extending upwardly through the first type semiconductor layer and upwardly into at least a portion of the first type cap layer; the first ion implantation fence is formed around the first trench, the first trench is formed around the first mesa structure, and an electrical resistance of the first ion implantation fence is higher than an electrical resistance of the first mesa structure; the second type of semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure; the second ion implantation fence is formed around the second trench, the second trench is formed around the second mesa structure, and an electrical resistance of the second ion implantation fence is higher than an electrical resistance of the second mesa structure; The conductivity type of the first type semiconductor layer is different from the conductivity type of the second type semiconductor layer. Micro LED.

90. 90. The micro LED of claim 89, wherein a top surface of the first trench is not in contact with the bottom surface of the second trench, and a portion of the light emitting layer is disposed between the top surface of the first trench and the bottom surface of the second trench.

91. 91. The micro LED of claim 90, wherein a top surface of the first ion implanted fence is lower than or aligned with a top surface of the first type semiconductor layer and a bottom surface of the second ion implanted fence is higher than or aligned with a bottom surface of the second type semiconductor layer.

92. 90. The microLED of claim 89, wherein a bottom surface of the first ion implanted fence is aligned with a bottom surface of the first type semiconductor layer or is higher or lower than a bottom of the first type semiconductor layer and a top surface of the second ion implanted fence is aligned with a top surface of the second type semiconductor layer or is higher or lower than a top surface of the second type semiconductor layer.

93. 90. The micro LED of claim 89, wherein a top surface of the first ion implanted fence is lower than a top surface of the first trench.

94. 90. The micro LED of claim 89, wherein the second trench does not extend downward through the second type semiconductor layer.

95. 95. The microLED of claim 94, wherein the second trench extends down through the second type semiconductor layer and down into at least a portion of the second type cap layer, or extends down through the second type cap layer and down into at least a portion of the light emitting layer.

96. 96. The micro LED of claim 95, wherein a bottom surface of the second ion implanted fence is higher than a bottom surface of the second trench.

97. 90. The micro LED of claim 89, wherein a top surface of the first trench is directly connected to a bottom surface of the second trench without the light emitting layer being disposed between the first trench and the second trench.

98. 90. The micro LED of claim 89, wherein the first mesa structure comprises one or more stair structures and the second mesa structure comprises one or more stair structures.

99. 90. The micro LED of claim 89, wherein a width of the first trench is less than or equal to 50% of a width of the first mesa structure and / or a width of the second trench is less than or equal to 50% of a width of the second mesa structure.

100. 100. The micro LED of claim 99, wherein the width of the first trench is less than or equal to 200 nm and / or the width of the second trench is less than or equal to 200 nm.

101. 90. The microLED of claim 89, wherein the first ion-implanted fence comprises a first light absorbing material, the second ion-implanted fence comprises a second light absorbing material, the conductivity type of the first light absorbing material being the same as the conductivity type of the first type of semiconductor layer, and the conductivity type of the second light absorbing material being the same as the conductivity type of the second type of semiconductor layer.

102. 102. The micro LED of claim 101 , wherein the first light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and / or the second light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

103. 90. The micro LED of claim 89, wherein a thickness of the first type semiconductor layer is greater than a thickness of the light emitting layer, a thickness of the second type semiconductor layer is greater than the thickness of the light emitting layer, and the thickness of the first type semiconductor layer is greater than the thickness of the second type semiconductor layer.

104. 90. The micro LED of claim 89, further comprising a bottom isolation layer formed between a bottom surface of the first type semiconductor layer and a top surface of an IC backplane.

105. The material of the bottom separation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 105. The micro LED of claim 104, wherein the micro LED is selected from one or more of:

106. 90. The micro LED of claim 89, wherein the first ion implanted fence is formed by implanting ions into at least the first type of semiconductor layer and the second ion implanted fence is formed by implanting ions into at least the second type of semiconductor layer.

107. 107. The micro LED of claim 106, wherein the ions implanted into the first type semiconductor layer are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F, and the ions implanted into the second type semiconductor layer are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

108. 90. The micro LED of claim 89, wherein a width of the first ion implanted fence is no greater than 50% of a diameter of the first mesa structure and a width of the second ion implanted fence is no greater than 50% of a diameter of the second mesa structure.

109. the width of the first ion implantation fence is less than or equal to 200 nm, the diameter of the first mesa structure is less than or equal to 2500 nm, and the thickness of the first type semiconductor layer is less than or equal to 100 nm; the width of the second ion implantation fence is less than or equal to 200 nm, the diameter of the second mesa structure is less than or equal to 2500 nm, and the thickness of the second type semiconductor layer is less than or equal to 300 nm; 109. The micro LED of claim 108.

110. 90. The micro LED of claim 89, wherein a material of the first type semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and a material of the second type semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.

111. 90. The micro-LED of claim 89, further comprising an integrated circuit (IC) backplane formed beneath said first type semiconductor layer, and connection structures electrically connecting said IC backplane with said first type semiconductor layer.

112. 112. The micro LED of claim 111, wherein the connection structure is a connection pillar or a metal bonding layer.

113. 112. The micro-LED of claim 111, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, a top surface of a connection structure being connected to the bottom contact and a bottom surface of the connection structure being connected to the IC backplane.

114. 114. A micro LED array panel comprising a plurality of micro LEDs according to any one of claims 89 to 113.

115. A method for manufacturing a micro LED, comprising: Step I includes patterning a first type of semiconductor layer and implanting first ions into the first type of semiconductor layer; Step II includes patterning a second type of semiconductor layer and implanting second ions into the second type of semiconductor layer. A method comprising:

116. The step I comprises: providing an epitaxial structure comprising, in top-to-bottom order, a first type of semiconductor layer, a first type of capping layer, a light emitting layer, a second type of capping layer, and a second type of semiconductor layer; patterning the first type semiconductor layer to form mesa structures, trenches, and fences; depositing a bottom contact on the mesa structure; performing an ion implantation process within the fence to form an ion implanted fence; depositing a bottom isolation layer over the first type semiconductor layer and the bottom contact; patterning the bottom isolation layer to expose the bottom contact; depositing a metallic material over the bottom isolation layer and the bottom contact; polishing the metal material to a top surface of the bottom isolation layer to form a connection structure; inverting the epitaxial structure and bonding the connection structure to an integrated circuit (IC) backplane; 116. The method of claim 115, further comprising:

117. patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence includes: Etching the first type semiconductor layer down to a surface of the light emitting layer.

117. The method of claim 116, further comprising:

118. patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence includes: sequentially etching the first type semiconductor layer and the light emitting layer; stopping the etching within the light emitting layer; 117. The method of claim 116, further comprising:

119. patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence includes: sequentially etching the first type semiconductor layer, the light emitting layer, and the second type semiconductor layer; stopping the etching in the second type semiconductor layer; 117. The method of claim 116, further comprising:

120. depositing a bottom contact on the mesa structure; forming a protective mask to protect areas where the bottom contact is not to be deposited; depositing the bottom contact material over the protective mask and over the first type semiconductor layer; removing the protective mask from the first type semiconductor layer and removing the material above the protective mask to form the bottom contact on the mesa structure; 117. The method of claim 116, further comprising:

121. performing the ion implantation process within the fence to form the ion implanted fence; forming a protective mask over areas not to be implanted while leaving the fence exposed; implanting ions into the fence; removing said protective mask; 117. The method of claim 116, further comprising:

122. 122. The method of claim 121, wherein said ion implantation step in said fence to form said ion implanted fence comprises implanting at an energy between 0 and 500 KeV and implanting a dose between 1E10 and 9E17.

123. 122. The method of claim 121, comprising implanting ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F into the fence when performing the ion implantation step in the fence to form the ion implanted fence.

124. 122. The method of claim 121, wherein when performing the ion implantation step in the fence to form the ion implantation fence, a width of the ion implantation fence is less than or equal to 50% of a diameter of the mesa structure, the width of the ion implantation fence is less than or equal to 200 nm, the diameter of the mesa structure is less than or equal to 2500 nm, and a thickness of the first type semiconductor layer is less than or equal to 300 nm.

125. 117. The method of claim 116, wherein when patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is less than or equal to 50% of a diameter of the mesa structure.

126. the mesa structure, the trench, and the fence are a first mesa structure, a first trench, and a first fence, respectively; The step II comprises: patterning the second type semiconductor layer to form a second mesa structure, a second trench, and a second fence; depositing a top contact on the second mesa structure; performing an ion implantation process within the second fence; depositing a top conductive layer on a top surface of the second type semiconductor layer, on the top contact, and in the second trench; 116. The method of claim 115, further comprising:

127. patterning the second type semiconductor layer to form the second mesa structure, the second trench, and the second fence includes: Etching the second type semiconductor layer down to a surface of the light emitting layer.

127. The method of claim 126, further comprising:

128. patterning the second type semiconductor layer to form the second mesa structure, the second trench, and the second fence includes: sequentially etching the second type semiconductor layer and the light emitting layer; stopping the etching within the light emitting layer; 127. The method of claim 126, further comprising:

129. patterning the second type semiconductor layer to form the second mesa structure, the second trench, and the second fence includes: sequentially etching the second type semiconductor layer, the light emitting layer, and the first type semiconductor layer; stopping the etching in the first type semiconductor layer; 127. The method of claim 126, further comprising:

130. Depositing the top contact on the second mesa structure comprises: forming a protective mask to protect areas where the top contact will not be deposited; depositing the top contact material over the protective mask; removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask to form the top contact on the second mesa structure; 127. The method of claim 126, further comprising:

131. Performing the ion implantation step within the second fence includes: forming a protective mask over areas not to be implanted while leaving the second fence exposed; implanting the ions into the second fence; removing said protective mask; 127. The method of claim 126, further comprising:

132. 126. The method of claim 125, wherein the ion implantation step in the second fence is performed with an energy of 0 to 500 KeV and a dose of 1E10 to 9E17.

133. 126. The method of claim 125, wherein when performing the ion implantation step in the second fence, ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F are implanted in the second fence.

134. 126. The method of claim 125, wherein when performing the ion implantation step within the second fence, a width of the second ion implantation fence is less than or equal to 50% of a diameter of the second mesa structure, the width of the second ion implantation fence is less than or equal to 200 nm, the diameter of the second mesa structure is less than or equal to 2500 nm, and a thickness of the second type semiconductor layer is less than or equal to 100 nm.

135. providing the epitaxial structure, the epitaxial structure being grown on a substrate, and inverting the epitaxial structure to bond the connection structure to the IC backplane; Removing the substrate. Further comprising: The method of claim 116.

136. When depositing the bottom isolation layer on the first type semiconductor layer and the bottom contact, the material of the bottom isolation layer is SiO ２ , SiNx, Al ２ O ３ , AlN, HfO ２ , TiO ２ , or ZrO ２ 117. The method of claim 116, wherein the method is selected from one or more of:

137. 117. The method of claim 116, wherein the ion implanted fence comprises a light absorbing material.

138. 138. The method of claim 137, wherein the conductivity type of the light absorbing material is the same as the conductivity type of the first type semiconductor layer, and the light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

139. 117. The method of claim 116, wherein the conductivity type of the first type semiconductor layer is P-type and the conductivity type of the second type semiconductor layer is N-type, the material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

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