Optically active substrates for fabricating 3D capacitors and capacitor arrays

Abstract

The present invention provides a method of fabrication and a device made by preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide and cerium oxide, masking a design layout comprising one or more holes or posts to form one or more high surface area capacitance devices for monolithic system level integration on the glass substrate.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a PCT international application claiming the benefit of U.S. Application No. 17 / 584,543, filed January 26, 2022, the contents of which are incorporated by reference in their entirety herein.

[0002] Statement regarding federally funded research none.

[0003] The present invention relates to creating three-dimensional capacitor structures in photosensitive ceramic-in-glass substrates, and in particular to creating capacitors in combination with other passive components for electronic, microwave and radio frequency filters, surge protectors and memory devices. [Background technology]

[0004] Photosensitive glass structures have been proposed for many micromachining and microfabrication processes, such as integrated electronic elements combined with other element systems or subsystems. Traditional glass-on-silicon microfabrication is expensive and has low yields, while injection molding or embossing produces non-uniform shapes. Silicon microfabrication processes are based on expensive capital equipment, photolithography and reactive ion etching or ion beam milling tools, which typically cost more than $1 million each, and require ultra-clean high-productivity silicon fabrication facilities that cost millions to billions of dollars. Injection molding and embossing are less expensive ways to generate three-dimensional shapes, but they produce defects during transfer or have differences due to stochastic curing processes.

[0005] The present invention creates cost-effective glass-ceramic three-dimensional capacitor structures or three-dimensional capacitor array devices. Glass-ceramic substrates have demonstrated the ability to form such structures by processing both vertical and horizontal surfaces, either separately or simultaneously, to form two- or three-dimensional capacitance devices. Summary of the Invention [Means for solving the problem]

[0006] The present invention includes a method of fabricating a substrate with one or more two-dimensional or three-dimensional capacitor devices by preparing a photosensitive glass substrate having vias or posts, and further coating or filling it with one or more conductive layers, typically metal, a dielectric material, and a top conductive layer, typically a metal.

[0007] 1. A method of fabrication and a device made by the steps of preparing a photosensitive glass-ceramic composite substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide; masking a design layout comprising one or more two-dimensional or three-dimensional capacitor devices in the photosensitive glass substrate; exposing at least a portion of the photosensitive glass substrate to an activation energy source; exposing the photosensitive glass substrate to a heating step above its glass transition temperature for at least 10 minutes; cooling the photosensitive glass substrate to convert at least a portion of the exposed glass into a crystalline material to form a glass crystal substrate; and etching the glass crystal substrate with an etchant to form one or more angled channels or through holes which are then used to create a capacitance device.

[0008] The present invention provides a glass-ceramic capacitance device, comprising: a first glass crystal substrate comprising one or more conductive paths in the glass crystal substrate and a metal coating applied to the one or more conductive paths, the first glass crystal substrate comprising at least silica, lithium oxide, aluminum oxide and cerium oxide; a second glass crystal substrate comprising one or more second conductive paths in the second glass crystal substrate and a second metal coating applied to the one or more second conductive paths, the second glass crystal substrate comprising at least silica, lithium oxide, aluminum oxide and cerium oxide; a layer of dielectric material located between the first glass crystal substrate and the second glass crystal substrate; and one or more vias, posts, channels or combinations thereof connecting the first glass crystal substrate and the second glass crystal substrate. The first terminal may be connected to the first glass crystal substrate and the second terminal may be connected to the second glass crystal substrate. The glass-ceramic capacitance device can function as a voltage storage device. The metal coating, the second metal coating, or both may be Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al2O3, or mixtures and alloys thereof. The dielectric layer may be Ta2O5, Al2O3, or other vapor phase dielectrics including, but not limited to, Al2O3.

[0009] The present invention provides a method of making a capacitive device created in or on a photosensitive glass-ceramic, comprising the steps of: providing a photosensitive glass-ceramic substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide; masking a design layout on the photosensitive glass-ceramic substrate, the design layout including one or more structures for forming one or more conductive paths; exposing at least a portion of the photosensitive glass-ceramic substrate to an activation energy source; heating the photosensitive glass-ceramic substrate above its glass transition temperature for a heating step of at least 10 minutes; cooling the photosensitive glass-ceramic substrate to convert at least a portion of the exposed glass to a crystalline material to form a glass crystalline substrate; and etching the glass crystalline substrate. and optionally converting a portion of the glass crystal substrate adjacent the three-dimensional etched structures to a ceramic phase; rinsing the glass crystal substrate with a dilute glass etchant to form a high surface area texture in the glass region; coating the via or post channel with a first metal to form a bottom electrode; coating at least a portion of the structure with a dielectric medium; coating the via or post channel with a second metal to form a top electrode; removing at least a portion of the top and dielectric medium to provide an electrical contact or a freestanding device; and connecting the first metal, the second metal, or both to a circuit through surface or buried contacts.

[0010] The coating of the first metal, the second metal, or both uses atomic layer deposition (ALD). The glass-ceramic capacitance device functions as a voltage reservoir. The first metal, the second metal, or both include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al2O3, or mixtures and alloys thereof. The dielectric layer can be Ta2O5, Al2O3, or other vapor phase dielectrics.

[0011] In one embodiment, the present invention provides a method for fabricating a capacitive device in one or more three-dimensional structures etched into a single photosensitive glass-ceramic substrate, comprising the steps of: providing a photosensitive glass-ceramic substrate comprising silica, lithium oxide, aluminum oxide, and cerium oxide; masking a design layout on the photosensitive glass-ceramic substrate, the design layout including one or more structures for forming the one or more three-dimensional structures; exposing at least a portion of the photosensitive glass-ceramic substrate to an activation energy source; heating the photosensitive glass-ceramic substrate to a temperature above its glass transition temperature for at least 10 minutes; cooling the photosensitive glass-ceramic substrate to convert at least a portion of the exposed photosensitive glass-ceramic substrate to a crystalline material to form a glass crystal substrate; and etching the glass crystal substrate with an etchant to form a glass crystal. forming one or more three-dimensional etched structures in a glass crystal substrate, the etched glass crystal substrate and an unexposed portion of the photosensitive glass substrate having an anisotropic etch ratio of at least 30:1; rinsing an inner surface of each of the one or more three-dimensional etched structures with a dilute glass etchant to increase a surface area of ​​the inner surface to increase capacitance of the glass-ceramic capacitance device; coating at least a portion of the inner surface of each of the one or more three-dimensional etched structures with a first metal to form a bottom electrode; coating at least a portion of the bottom electrode with a dielectric medium; coating at least a portion of the dielectric medium with a second metal to form a top electrode; and removing at least a portion of the top electrode and the dielectric medium to provide an electrical contact configured to generate an electrical connection between the capacitance device and a circuit. In one aspect, the method further includes converting a portion of the glass crystal substrate adjacent to the one or more three-dimensional etched structures to a ceramic phase. In another embodiment, the coating with the first metal, the coating with the second metal, or both, is performed by atomic layer deposition (ALD).In another embodiment, the first metal, the second metal, or both, include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another embodiment, the dielectric layer includes Ta2O5, Al2O3, or another vapor phase dielectric, or a combination thereof.

[0012] In another embodiment, the invention includes a photosensitive glass-ceramic substrate including silica, lithium oxide, aluminum oxide, and cerium oxide, a glass crystal substrate, and one or more three-dimensional structures etched into the glass crystal substrate, where the glass crystal substrate and the non-glass crystal portion of the photosensitive glass substrate have an anisotropic etching ratio of at least 30:1, and each three-dimensional structure includes an inner surface having a high surface area texture; a first metal coating disposed on at least a portion of the inner surface of each three-dimensional structure as a bottom electrode; a dielectric coating disposed on at least a portion of the bottom electrode; a second metal coating disposed on at least a portion of the dielectric coating as a top electrode; and one or more surface contacts or one or more embedded contacts in electrical communication with the bottom electrode or top electrode and configured to be connected to a circuit. In one aspect, the device further includes a ceramic phase adjacent to the one or more three-dimensional etched structures. In another aspect, the first metal coating, the second metal coating, or both are disposed by atomic layer deposition (ALD). In another embodiment, the first metal, the second metal, or both, include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another embodiment, the dielectric layer includes Ta2O5, Al2O3, another vapor phase dielectric, or a combination thereof.

[0013] In another embodiment, the present invention provides a single photosensitive glass-ceramic substrate comprising silica, lithium oxide, aluminum oxide, and cerium oxide, a first glass crystal substrate, a second glass crystal substrate, and a three-dimensional structure etched into the first glass crystal substrate and the second glass crystal substrate, wherein the first glass crystal substrate and the second glass crystal substrate and the non-glass crystal portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1; a first metal coating disposed on the first glass crystal substrate; and a second metal coating disposed on the second glass crystal substrate. The capacitive device includes a coating, a layer of dielectric material disposed between the first and second glass crystal substrates, and one or more vias, one or more post channels, or a combination thereof, directly connecting the first and second glass crystal substrates, the one or more vias or one or more post channels being formed with a high surface area texture resulting in increased capacitance in the capacitive device. In one embodiment, the capacitive device further includes a ceramic phase adjacent the three-dimensional structure. In another embodiment, the first metal coating, the second metal coating, or both are disposed by atomic layer deposition (ALD). In another embodiment, the first metal, the second metal, or both include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another embodiment, the dielectric material comprises Ta2O5, Al2O3, another vapor phase dielectric, or a combination thereof. [Brief description of the drawings]

[0014] Further benefits and advantages of the present invention will become more apparent from the following description of various embodiments thereof, given by way of example with reference to the accompanying drawings, in which: [Figure 1] Through-hole vias are shown having a diameter of 65 μm and a center-to-center pitch of 72 μm. [Diagram 2]A blind via in a 1 mm thick substrate is shown, with a via depth of 440 μm, a top diameter of 41 μm and a bottom diameter of 19 μm. [Figure 3A] FIG. 1 shows a top view of a high surface area and high aspect ratio device in / on APEX® glass. [Figure 3B] FIG. 1 shows a top view of a high surface area and high aspect ratio device in / on APEX® glass. [Figure 4] FIG. 1 shows a side view of a filled through-hole via in / on APEX® glass. [Diagram 5] 1 shows an exploded view of a blind via with ADL capacitor structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Although the making and using of various embodiments of the invention are discussed in detail below, it should be understood that the invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention and do not delimit the scope of the invention.

[0016] To facilitate understanding of the present invention, certain terms are defined below. Terms defined herein have meanings commonly understood by those of ordinary skill in the art relevant to the present invention. Terms such as "a," "an," and "the" are not intended to refer to only a single entity, but include general classes of which a particular example may be used to illustrate. Although terminology herein is used to describe particular embodiments of the present invention, their use does not define the present invention, except as outlined in the claims.

[0017] To address these needs, the inventors have developed glass-ceramics (APEX® glass-ceramics) as novel packaging and substrate materials for semiconductors, RF electronics, microwave electronics, and optical imaging. APEX® glass-ceramics are processed using first generation semiconductor equipment in a simple three-step process, and the final material can be either formed into glass, formed into ceramic, or can contain regions of both glass and ceramic. APEX® glass-ceramics have several advantages over current materials, including ease of fabrication of high density vias, demonstrated microfluidic capabilities, microlenses or microlens arrays, high Young's modulus for a more rigid package, halogen-free fabrication, and economical manufacturing. Photoetchable glasses have several advantages for the fabrication of a wide variety of microsystem components. Microstructures have been produced relatively inexpensively in these glasses using conventional semiconductor processing equipment. In general, glasses have high temperature stability, good mechanical and electrical properties, and better chemical resistance than plastics and many metals. To our knowledge, the only commercially available photoetchable glass is FOTURAN®, made by Schott Corporation and imported into the United States exclusively by Invenios Inc. FOTURAN® comprises a lithium-aluminum-silicate glass containing trace amounts of silver ions plus other trace elements, specifically 75-85% by weight silicon oxide (SiO2), 7-11% by weight lithium oxide (Li2O), 3-6% by weight aluminum oxide (Al2O3), 1-2% by weight sodium oxide (Na2O), 0.2-0.5% by weight antimony trioxide (Sb2O3) or arsenic oxide (As2O3), 0.05-0.15% by weight silver oxide (Ag2O), and 0.01-0.04% by weight cerium oxide (CeO2). As used herein, the terms "APEX® glass-ceramic," "APEX® glass," or simply "APEX®" are used to refer to one embodiment of the glass-ceramic composition of the present invention.

[0018] When exposed to UV light within the absorption band of cerium oxide, the cerium oxide acts as a sensitizer, absorbing a photon and losing an electron, thereby reducing adjacent silver oxide to form silver atoms: e.g., Ce 3+ +Ag + =Ce 4+ +Ag 0

[0019] The silver atoms aggregate into silver nanoclusters during the firing process, inducing nucleation sites for crystallization of the surrounding glass. When exposed to UV light through a mask, only the exposed portions of the glass crystallize during the subsequent heat treatment.

[0020] This heat treatment should be carried out at a temperature near the glass transition temperature (e.g., above 465° C. in air for FOTURAN®). The crystalline phase is more soluble in etchants such as hydrofluoric acid (HF) than the unexposed glass-like amorphous regions. In particular, the crystalline regions of FOTURAN® etch about 20 times faster than the amorphous regions in 10% HF, allowing for a microstructure with a wall slope ratio of about 20:1 once the exposed regions are removed.

[0021] In general, glass-ceramic materials have had limited success in forming microstructures, plagued by problems of performance, uniformity, usability by others, and availability. In contrast to previous glass-ceramic materials that have provided etch aspect ratios of about 15:1, APEX® glass has an average etch aspect ratio of more than 50:1. This allows users to create smaller and deeper features. Furthermore, our manufacturing process allows for product yields of more than 90% (conventional glass yields are closer to 50%). Finally, in conventional glass-ceramics, only about 30% of the glass is converted to the ceramic state, whereas in APEX™ glass-ceramics, this conversion rate is closer to 70%.

[0022] The APEX® glass composition provides three primary mechanisms for its improved performance: (1) higher amounts of silver result in the formation of smaller ceramic crystals that etch faster at the grain boundaries, (2) reduced silica content (the main component etched by HF acid) reduces unwanted etching of unexposed material, and (3) a higher total weight percentage of alkali metal and boron oxide produces a much more homogeneous glass during manufacturing.

[0023] The ceramicization of glass is performed by applying approximately 20 J / cm2 to the entire glass substrate. 2 This is accomplished by exposing the mask to 310 nm light at 1000 nm. If glass spaces are to be created within the ceramic, the user exposes all of the material except where the glass is to remain glass. In one embodiment, the invention provides a quartz / chrome mask that includes various concentric circles with different diameters.

[0024] The present invention includes a method for fabricating inductive devices in or relating to glass-ceramic structural electrical microwave and radio frequency applications. The glass-ceramic substrate may be a photosensitive glass substrate having a wide number of compositional variations, including but not limited to: 60-76 wt.% silica; at least 3 wt.% K2O, with the combination of K2O and Na2O being 6 wt.% to 16 wt.%; 0.003-1 wt.% of at least one oxide selected from the group consisting of Ag2O and Au2O; 0.003-2 wt.% Cu2O; 0.75 wt.% to 7 wt.% B2O3 and 6-7 wt.% Al2O3, with the combination of B2O3 and Al2O3 not exceeding 13 wt.%; 8-15 wt.% Li2O; and 0.001-0.1 wt.% CeO2. This and other various compositions are commonly referred to as APEX® glass.

[0025] The exposed portion can be converted to a crystalline material by heating the glass substrate to a temperature near the glass transition temperature. When the glass substrate is etched in an etchant such as hydrofluoric acid, the anisotropic etch ratio of the exposed portion to the unexposed portion is at least 30:1 when the glass is exposed to a broad spectrum mid-UV (approximately 308-312 nm) flood lamp to provide a shaped glass structure with an aspect ratio of at least 30:1 and to create the inductive structures. The mask for the exposure can be a half-tone mask that provides a continuous gray scale to the exposure to form curved structures to create the inductive structures / devices. Digital masks can also be used in the flood exposure to provide the creation of the inductive structures / devices. The exposed glass is then baked, typically in a two-step process. It is heated at a temperature range between 420°C and 520°C for 10 minutes to 2 hours to aggregate the silver ions into silver nanoparticles, and heated at a temperature range between 520°C and 620°C for 10 minutes to 2 hours to form lithium oxide around the silver nanoparticles. The glass sheet is then etched, typically with an etchant of 5% to 10% by volume HF solution, with an etch ratio of exposed to unexposed portions of at least 30:1 when exposed with broad spectrum mid-UV flood light, and greater than 30:1 when exposed with a laser, to provide a shaped glass structure with an anisotropic etch ratio of at least 30:1.

[0026] The present invention includes one or more inductive structures created in a plurality of vias or posts of a glass-ceramic substrate, such a process using a photodefinable glass structure that includes at least one or more two-dimensional or three-dimensional capacitor devices. The capacitance device is formed by a via or a series of vias, which may be through-holes or blind vias, and an atomic layer deposition (ALD) process is used to deposit a bottom electrode, a dielectric, and a top electrode. The via may also be subjected to an additional low concentration rinse with an etchant such as dilute HF. The dilute HF patterns or textures the ceramic walls of the via. The texturing of the ceramic walls significantly increases the surface area of ​​the structure, which directly increases the capacitance of the device.

[0027] The capacitance device consists of a conductive layer that adheres well to the glass, a dielectric layer, a top conductive layer, and a final barrier layer. The APEX® glass dimensional structure is coated with a layer of TiN or other electrode material less than 2 microns, followed by a dielectric layer of Ta2O5, Al2O3, or other vapor phase dielectrics including but not limited to Al2O3 less than 2 microns. Al2O3 at 380°C using TMA and O3 - cycle time: 3.5 seconds. The Al2O3 layer is then heated to 300°C for 5 minutes in an oxygen atmosphere to fully oxidize the dielectric layer. A top electrode of TiN less than 2 microns is then deposited by ALD. The top and bottom electrodes need to be constructed from the same material to prevent the formation of space charges in the dielectric. Depending on the magnitude of the work function difference, the space charges may be greater than can be overcome with an external voltage without destroying the dielectric layer, rendering the capacitor unusable. Elimination of the work function problem can be achieved by creating an ohmic contact between the electrode and the dielectric. To increase the capacitance, additional metal and dielectric layers can be added.

[0028] Preferred embodiments. The preferred structure is to create a capacitor structure in which the vias or posts undergo a dilute HF clean to create a highly textured surface area coated TiW metallization for the bottom electrode, tantalum pentoxide for the dielectric, and TiW metallization for the top electrode. The TiW bottom electrode requires a two-step ALD process. Step 1 is to deposit Ti using a TiCl4 rate of 1.67 Å / cycle at a substrate temperature of 300° C.-400° C. and a cycle time of about 1.8 seconds. The second step is to deposit tungsten (W) using Si-H and WF mixed on the surface of the substrate before purging. The linear growth rate of W requires equal amounts of each reactant during the ALD cycle. A typical ALD growth for tungsten is a 6 Å cycle with a cycle time of 3.5 seconds and a substrate temperature of 177° C.-325° C. Alternating ALD cycles from W to Ti at the substrate temperature required to achieve deposition of both metals results in the formation of a TiW layer. The process is repeated until the TiW structure reaches 20 Å. Ta2O5 is then formed by ALD using TaCl5 precursor in the presence of atomic hydrogen. The tantalum film is deposited at substrate temperatures between 25 and 400 °C with an ALD cycle time of 1.8 seconds. After each ALD cycle, the tantalum film is exposed to O2 for 30 seconds while the substrate remains at 400 °C. This converts the tantalum metal film to Ta2O5. The device is completed by applying a TiW top electrode in the same manner as the bottom electrode. The very nature of the ALD process allows for a dense conformal coating.

[0029] In finishing the capacitor structure, it is necessary to etch down to the bottom electrode so that electrical connections can be made to both contacts of the capacitor. This is accomplished by coating the structure with a standard positive photoresist. The photoresist is exposed in a rectangle over a portion of the capacitor structure. The photoresist on the capacitor is then developed and removed to expose the top TiW photoresist electrode. The TiW electrode is etched with SF6 / He plasma using a Tegal 804 plasma etch system. The etch rate at 200W forward power is 200Å / min. This etch is preferential to the Ta2O5 layer, making it an effective etch stop. The Ta2O5 plasma etch uses an Ar / Cl (10% / 90%) mixture with a forward power of 300W at an etch rate of 1200Å / min. The Ar / Cl plasma does not attack / etch the TiW bottom electrode. This allows the top and bottom electrodes of the capacitor to be connected to the rest of the circuit by a wide number of standard thick and thin film processes.

[0030] A second embodiment uses through-hole vias that may have a ceramic phase etched with a dilute HF solution to create a textured high surface area on one or both sides to partially or completely remove the glass ceramic as a base substrate for the capacitance structure. A third embodiment uses posts on one or both sides of an APEX® glass substrate that may have a ceramic phase etched with dilute HF to create a high surface area capacitance structure.

[0031] In one embodiment, the present invention provides a method for fabricating a capacitive device in one or more three-dimensional structures etched into a single photosensitive glass-ceramic substrate, the method comprising the steps of: providing a photosensitive glass-ceramic substrate comprising silica, lithium oxide, aluminum oxide, and cerium oxide; masking a design layout on the photosensitive glass-ceramic substrate, the design layout including one or more structures for forming the one or more three-dimensional structures; exposing at least a portion of the photosensitive glass-ceramic substrate to an activation energy source; heating the photosensitive glass-ceramic substrate to a temperature above its glass transition temperature for at least 10 minutes; cooling the photosensitive glass-ceramic substrate to convert at least a portion of the exposed photosensitive glass-ceramic substrate to a crystalline material to form a glass crystal substrate; and etching the glass crystal substrate with an etchant to form the one or more three-dimensional structures in the glass crystal substrate. forming a three-dimensional etched structure on the photosensitive glass substrate, the etched glass crystal substrate and the unexposed portion of the photosensitive glass substrate having an anisotropic etch ratio of at least 30:1; rinsing an inner surface of each of the one or more three-dimensional etched structures with a dilute glass etchant to increase a surface area of ​​the inner surface to increase the capacitance of the glass-ceramic capacitance device; coating at least a portion of the inner surface of each of the one or more three-dimensional etched structures with a first metal to form a bottom electrode; coating at least a portion of the bottom electrode with a dielectric medium; coating at least a portion of the dielectric medium with a second metal to form a top electrode; and removing at least a portion of the top electrode and the dielectric medium to provide an electrical contact configured to generate an electrical connection between the capacitance device and a circuit. In one aspect, the method further includes converting a portion of the glass crystal substrate adjacent to the one or more three-dimensional etched structures to a ceramic phase. In another embodiment, the coating with the first metal, the coating with the second metal, or both, is performed by atomic layer deposition (ALD).In another embodiment, the first metal, the second metal, or both, include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another embodiment, the dielectric layer includes Ta2O5, Al2O3, or another vapor phase dielectric, or a combination thereof.

[0032] In another embodiment, the invention includes a photosensitive glass-ceramic substrate including silica, lithium oxide, aluminum oxide, and cerium oxide, a glass crystal substrate, and one or more three-dimensional structures etched into the glass crystal substrate, where the glass crystal substrate and the non-glass crystal portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1, and each three-dimensional structure includes an inner surface having a high surface area texture; a first metal coating disposed on at least a portion of the inner surface of each three-dimensional structure as a bottom electrode; a dielectric coating disposed on at least a portion of the bottom electrode; a second metal coating disposed on at least a portion of the dielectric coating as a top electrode; and one or more surface contacts or one or more embedded contacts in electrical communication with the bottom electrode or top electrode and configured to be connected to a circuit. In one aspect, the device further includes a ceramic phase adjacent to the one or more three-dimensional etched structures. In another aspect, the first metal coating, the second metal coating, or both are disposed by atomic layer deposition (ALD). In another embodiment, the first metal, the second metal, or both, include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another embodiment, the dielectric layer includes Ta2O5, Al2O3, another vapor phase dielectric, or a combination thereof.

[0033] In another embodiment, the present invention provides a single photosensitive glass-ceramic substrate comprising, consisting essentially of, or consisting of silica, lithium oxide, aluminum oxide, and cerium oxide, a first glass crystal substrate, a second glass crystal substrate, and three-dimensional structures etched into the first and second glass crystal substrates, wherein the first and second glass crystal substrates and the non-glass crystal portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1; a first metal coating disposed on the first glass crystal substrate; and a second metal coating disposed on the second glass crystal substrate. a second metal coating disposed on the first glass crystal substrate, a layer of dielectric material disposed between the first glass crystal substrate and the second glass crystal substrate, and one or more vias, one or more post channels, or a combination thereof, directly connecting the first glass crystal substrate and the second glass crystal substrate, the one or more vias or one or more post channels being formed with a high surface area texture resulting in increased capacitance in the capacitance device. In one aspect, the capacitance device further comprises a ceramic phase adjacent the three-dimensional structure. In another aspect, the first metal coating, the second metal coating, or both are disposed by atomic layer deposition (ALD). In another aspect, the first metal, the second metal, or both include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, Al2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another embodiment, the dielectric material comprises Ta2O5, Al2O3, another vapor phase dielectric, or a combination thereof.

[0034] It will be understood that the specific embodiments described herein are shown by way of example and not by way of limitation. The principal features of this invention can be employed in various embodiments without departing from the scope of the invention. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific procedures described herein. Such equivalents are considered to be within the scope of the invention and are covered by the claims.

[0035] All publications and patent applications mentioned in this specification are indicative of the level of skill of those skilled in the art to which this invention pertains. All publications and patent applications are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference.

[0036] The use of the word "a" or "an" in the claims and / or specification when used in conjunction with the term "comprising" can mean "one," but is also consistent with the meanings of "one or more," "at least one," and "one or more than one." While the present disclosure supports a definition that refers only to alternatives and "and / or," the use of the term "or" in the claims is used to mean "and / or" unless expressly indicated to refer only to alternatives or the alternatives are not mutually exclusive. Throughout this application, the term "about" is used to indicate that a value includes the inherent variation of error for the device, i.e., the method used to determine the value, or the variation that exists between study subjects.

[0037] As used in the specification and claim(s), the words "comprising" (and all forms of comprising, such as "comprise" and "comprises"), "having" (and all forms of having, such as "have" and "has"), "including" (and all forms of including, such as "includes" and "include"), or "containing" (and all forms of containing, such as "contains" and "contain") are inclusive or open-ended and do not exclude additional, unrecited elements or method steps. In any of the embodiments of the compositions and methods provided herein, "comprising" may be substituted with "consisting essentially of" or "consisting of." As used herein, the phrase "consisting essentially of" requires the specified integer(s) or steps, as well as those that do not materially affect the characteristics or function of the claimed invention. As used herein, the term "comprising" is used to indicate the presence of only a listed integer (e.g., feature, element, property, attribute, method / process step, or limitation) or group of integers (e.g., feature(s), element(s), property(s), attribute(s), method / process step(s), or limitation(s)).

[0038] As used herein, the term "or combinations thereof" refers to all permutations and combinations of the items listed preceding this term. For example, "A, B, C, or combinations thereof" is intended to include at least one of A, B, C, AB, AC, BC, or ABC, as well as BA, CA, CB, CBA, BCA, ACB, BAC, or CAB, if the order is important in the particular context. Continuing with this example, combinations including one or more repeats of an item or term, such as BB, AAA, AB, BBC, AAABCCCC, CBBAAA, CABABB, etc., are expressly included. One of ordinary skill in the art will understand that there is typically no limit to the number of items or terms in any combination, unless otherwise clear from the context.

[0039] As used herein, without limitation, approximation words such as "about", "substantial" or "substantially" refer to a state that, when so modified, is not necessarily understood to be absolute or complete, but is considered to be close enough to a person skilled in the art to ensure that the state is indicated as existing. The extent to which the description may vary depends on the extent to which changes can be made and the extent to which a person skilled in the art can still recognize that the modified feature still has the required properties and capabilities of the unmodified feature. Pursuant to the above discussion, generally, numerical values ​​herein modified with approximation words such as "about" may vary from the stated value by at least ±1, 2, 3, 4, 5, 6, 7, 10, 12 or 15%.

[0040] All of the devices and / or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. Although the devices and / or methods of the present invention have been described in terms of preferred embodiments, it will be apparent to those skilled in the art that changes can be applied to the compositions and / or methods, and to the steps or sequence of steps of the methods described herein, without departing from the concept, spirit and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope and concept of the invention as defined by the appended claims.

[0041] Furthermore, no limitations are intended to the details of construction or design shown herein, other than as described in the claims below. It is therefore apparent that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the present disclosure. Accordingly, the protection sought herein is as set forth in the claims below.

[0042] Modifications, additions, or omissions may be made to the systems and devices described herein without departing from the scope of the invention. Components of the systems and devices may be integrated or separate. Further, operations of the systems and devices may be performed by more, fewer, or other components. Methods may include more, fewer, or other steps. Further, steps may be performed in any suitable order.

[0043] To assist the Patent Office and any reader of any patent issued based on this application in interpreting the claims appended hereto, Applicants are advised that they do not intend to invoke paragraph 6 of 35 U.S.C. § 112 in any of the appended claims, as they exist as of the filing date of this application, unless the words "means for" or "step for" are expressly used in a particular claim.

[0044] For each claim, each dependent claim may depend on both the independent claim and each preceding dependent claim, so long as the preceding claim provides appropriate antecedent for a term or element of the claim.

Claims

1. 1. A method for fabricating capacitive devices in one or more three-dimensional structures etched into a single photosensitive glass-ceramic substrate, comprising: providing a photosensitive glass-ceramic substrate comprising silica, lithium oxide, aluminum oxide and cerium oxide; masking a design layout on the photosensitive glass-ceramic substrate, the design layout including one or more structures for forming one or more three-dimensional structures; exposing at least a portion of the photosensitive glass-ceramic substrate to an activation energy source; heating the photosensitive glass-ceramic substrate above its glass transition temperature for at least 10 minutes; cooling the photosensitive glass-ceramic substrate to convert at least a portion of the exposed photosensitive glass-ceramic substrate into a crystalline material to form a glass crystalline substrate; Etching the glass crystal substrate with an etching solution to form one or more three-dimensional etched structures in the glass crystal substrate, the etched glass crystal substrate and the unexposed portions of the photosensitive glass substrate having an anisotropic etching ratio of at least 30:1; rinsing an interior surface of each of the one or more three-dimensional etched structures with a dilute glass etchant to increase a surface area of ​​the interior surface and thereby increase capacitance of the glass-ceramic capacitance device; coating at least a portion of the interior surface of each of the one or more three-dimensional etched structures with a first metal to form a bottom electrode; coating at least a portion of the bottom electrode with a dielectric medium; coating at least a portion of the dielectric medium with a second metal to form a top electrode; removing at least a portion of the top electrode and the dielectric medium to provide an electrical contact configured to create an electrical connection between the capacitive device and a circuit; The method comprising:

2. The method of claim 1 , further comprising converting a portion of the glass crystalline substrate adjacent the one or more three-dimensional etched structures to a ceramic phase.

3. The method of claim 1 , wherein the coating with the first metal, the coating with the second metal, or both, is performed by atomic layer deposition (ALD).

4. The first metal, the second metal, or both are selected from the group consisting of Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, and Al. ２ O ３ , a mixture of two or more thereof, or an alloy of two or more thereof.

5. The dielectric layer is Ta ２ O ５ , Al ２ O ３ or another vapor phase dielectric, or a combination thereof.

6. Silica, lithium oxide, aluminum oxide and cerium oxide, Glass crystal substrate, One or more three-dimensional structures etched into the glass crystal substrate. wherein the glass crystal substrate and a non-glass crystal portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1, and each three-dimensional structure includes an inner surface having a high surface area texture. the photosensitive glass ceramic substrate; a first metallic coating disposed on at least a portion of the interior surface of each three-dimensional structure as a bottom electrode; a dielectric coating disposed on at least a portion of the bottom electrode; a second metallic coating disposed on at least a portion of the dielectric coating as a top electrode; one or more surface contacts or one or more recessed contacts in electrical communication with the lower electrode or the upper electrode and configured to be connected to a circuit; a capacitance device comprising:

7. The device of claim 6 , further comprising a ceramic phase adjacent the one or more three-dimensional etched structures.

8. The device of claim 6 , wherein the first metal coating, the second metal coating, or both are disposed by atomic layer deposition (ALD).

9. The first metal, the second metal, or both are selected from the group consisting of Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, and Al. ２ O ３ 7. The device of claim 6, comprising: a mixture of two or more thereof; or an alloy of two or more thereof.

10. The dielectric layer is Ta ２ O ５ , Al ２ O ３ 7. The device of claim 6, comprising a dielectric layer comprising a first dielectric layer, another vapor phase dielectric, or a combination thereof.

11. Silica, lithium oxide, aluminum oxide and cerium oxide, A first glass crystal substrate; A second glass crystal substrate; Three-dimensional structures etched into the first glass crystal substrate and the second glass crystal substrate. wherein the first glass crystal substrate and the second glass crystal substrate and a non-glass crystal portion of the photosensitive glass substrate have an anisotropic etching ratio of at least 30:

1. the single photosensitive glass-ceramic substrate; a first metal coating disposed on the first glass crystal substrate; a second metal coating disposed on the second glass crystal substrate; a layer of dielectric material disposed between the first and second glass crystal substrates; one or more vias, one or more post channels, or a combination thereof, directly connecting the first glass crystal substrate and the second glass crystal substrate, the one or more vias or the one or more post channels being formed with a high surface area texture that provides increased capacitance in a capacitive device; a capacitance device comprising:

12. The device of claim 11 , further comprising a ceramic phase adjacent the three-dimensional structure.

13. 12. The device of claim 11, wherein the first metal coating, the second metal coating, or both are disposed by atomic layer deposition (ALD).

14. The first metal, the second metal, or both are selected from the group consisting of Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, and Al. ２ O ３ , a mixture of two or more thereof, or an alloy of two or more thereof.

15. The dielectric material is Ta ２ O ５ , Al ２ O ３ 12. The device of claim 11, comprising a dielectric layer comprising a first insulating layer, a second insulating layer, another vapor phase dielectric, or a combination thereof.

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