Bias supply with resonant switching

Abstract

A bias source and a plasma processing system are disclosed. One bias source comprises an output node, a return node, and a power section coupled to the output node and the return node. A resonant switch section is coupled to the power section at a first node, a second node, and a third node, and the resonant switch section is configured to apply an asymmetric periodic voltage waveform to the return node at the output node by connecting and disconnecting current paths between the first node and the second node. The asymmetric periodic voltage waveform includes a first portion that starts from a first negative voltage and changes to a positive peak voltage, a second portion that changes from the positive peak voltage level to a third voltage level, and a fourth portion that includes a negative voltage ramp from the third voltage level to a fourth voltage level.

Description

[Technical field]

[0001] The present invention relates generally to power supplies, and more particularly to power supplies for applying voltages for plasma processing. [Background technology]

[0002] Many types of semiconductor devices are fabricated using plasma-based etching techniques. If it is a conductor being etched, a negative voltage with respect to ground can be applied to the conductive substrate such that across the surface of the substrate conductor, a substantially uniform negative voltage is created that attracts positively charged ions toward the conductor, so that the positive ions that impact the conductor have substantially the same energy.

[0003] However, if the substrate is a dielectric, a constant voltage is ineffective for applying a voltage across the surface of the substrate. However, an alternating current (AC) voltage (e.g., high frequency AC or radio frequency (RF)) can be applied to a conductive plate (or chuck) such that the AC field induces a voltage on the surface of the substrate. During the positive peak of the AC cycle, the substrate attracts electrons, which are light relative to the mass of the positive ions, and therefore many electrons will be attracted to the surface of the substrate during the positive peak of the cycle. As a result, the surface of the substrate becomes negatively charged, which causes ions to be attracted toward the negatively charged surface for the remainder of the AC cycle. Also, when ions collide with the surface of the substrate, the impact removes material from the surface of the substrate, resulting in etching.

[0004] In many instances, it is desirable to have a narrow (or specifically adjustable) ion energy distribution, but applying a sinusoidal waveform to a substrate induces a wide distribution of ion energy, which limits the ability of the plasma process to perform a desired etch profile. Known techniques for achieving a narrow ion energy distribution can be expensive, inefficient, difficult to control, and / or adversely affect plasma density. As a result, many of these known techniques have not been commercially adopted. Thus, systems and methods are needed to address the shortcomings of current technology and provide other new and innovative features. Summary of the Invention [Means for solving the problem]

[0005] The aspect may be characterized as a bias supply for applying a periodic voltage comprising an output node, a return node, and a resonant switch section. The resonant switch section comprises a first node, a second node, a third node, and a first current path between the first node and the second node comprising a series combination of a switch and a diode. The resonant switch section also comprises a second current path between the second node and the third node comprising a diode and an inductive element. The power section of the bias supply comprises a first voltage source coupled between the third node and the first node, and a second voltage source coupled to the return node. When the switch is closed, unidirectional currents in the first and second current paths cause application of a periodic voltage between the output node and the return node.

[0006] Another aspect may be characterized as a bias supply comprising an output node, a return node, and a power section coupled to the output node and the return node. The bias supply also comprises a first node, a second node, and a resonant switch section coupled to the power section at a third node, the resonant switch section configured to connect and disconnect a current path between the first node and the second node and cause application of an asymmetric periodic voltage waveform at the output node to the return node. Each cycle of the asymmetric periodic voltage waveform includes a first portion starting from a first negative voltage and changing to a positive peak voltage, a second portion changing from the positive peak voltage level to a third voltage level, and a fourth portion including a negative voltage ramp from the third voltage level to a fourth voltage level. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram depicting an exemplary plasma processing environment in which the bias sources disclosed herein may be utilized.

[0008] [Diagram 2] FIG. 2 is a schematic diagram depicting an exemplary bias supply.

[0009] [Diagram 3] FIG. 3 is a schematic diagram of a side electrical representation of a plasma processing chamber.

[0010] [Figure 4A] 4A, 4B, 4C, 4D, 4E, 4F, and 4G each depict an embodiment of the bias supply depicted in FIG. [Figure 4B] 4A, 4B, 4C, 4D, 4E, 4F, and 4G each depict an embodiment of the bias supply depicted in FIG. [Figure 4C] 4A, 4B, 4C, 4D, 4E, 4F, and 4G each depict an embodiment of the bias supply depicted in FIG. [Figure 4D] 4A, 4B, 4C, 4D, 4E, 4F, and 4G each depict an embodiment of the bias supply depicted in FIG. [Figure 4E] 4A, 4B, 4C, 4D, 4E, 4F, and 4G each depict an embodiment of the bias supply depicted in FIG. [Figure 4F] 4A, 4B, 4C, 4D, 4E, 4F, and 4G each depict an embodiment of the bias supply depicted in FIG. [Figure 4G] 4A, 4B, 4C, 4D, 4E, 4F, and 4G each depict an embodiment of the bias supply depicted in FIG.

[0011] [Figure 5A] 5A, 5B, and 5C are schematic diagrams each depicting an example of a resonant switch section. [Figure 5B] 5A, 5B, and 5C are schematic diagrams each depicting an example of a resonant switch section. [Figure 5C] 5A, 5B, and 5C are schematic diagrams each depicting an example of a resonant switch section.

[0012] [Figure 6A] FIG. 6A includes graphs depicting operational aspects of the bias supply disclosed herein in one exemplary mode of operation.

[0013] [Figure 6B] FIG. 6B includes graphs depicting operational aspects of the bias supply disclosed herein in another exemplary mode of operation.

[0014] [Figure 7] FIG. 7 is a block diagram depicting components that may be utilized to implement the control aspects disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Detailed Description The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0016] Preliminary Note: The flowcharts and block diagrams in the following figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, some blocks in these flowcharts or block diagrams may represent modules, partitions, or portions of code, which comprise one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially in parallel, or the blocks may sometimes be executed in reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system, or a combination of special-purpose hardware and computer instructions, that performs the specified functions or actions.

[0017] For purposes of this disclosure, a source generator is one whose energy is primarily directed to generating and sustaining a plasma, while a "bias source" is one whose energy is primarily directed to generating a surface potential to attract ions and electrons from the plasma.

[0018] Described herein are several embodiments of a novel bias source that can be used to apply a periodic voltage function to a substrate support in a plasma processing chamber. Referring initially to FIG. 1, shown is an exemplary plasma processing environment (e.g., a deposition or etching system) in which a bias source may be utilized. The plasma processing environment may include many pieces of equipment coupled directly and indirectly to a plasma processing chamber 101, which contains a volume containing a plasma 102 and a workpiece 103 (e.g., a wafer) and an electrode 104 (which may be embedded in a substrate support). The equipment may include vacuum handling and gas delivery equipment (not shown), one or more bias sources 108, one or more source generators 112, and one or more source matching networks 113. In many applications, power from a single source generator 112 is connected to one or more source electrodes 105. The source generator 112 may be higher frequency than a RF generator (e.g., 13.56 MHz to 120 MHz). Electrode 105 generally represents what may be implemented using an inductively coupled plasma (ICP) source, a dual frequency capacitively coupled plasma source (CCP) with a secondary upper electrode biased at another RF frequency, a helicon plasma source, a microwave plasma source, a magnetron, or other independently operated source of plasma energy.

[0019] 1, the source generator 112 and source matching network 113 may be replaced or augmented with a remote plasma source. Also, other variations of the system may include only a single bias source 108.

[0020] The following disclosure generally refers to plasma-based wafer processing, but implementations can include any substrate processing in a plasma chamber. In some cases, objects other than substrates can also be processed using the systems, methods, and apparatus disclosed herein. In other words, the present disclosure also applies to plasma processing of any object in a sub-atmospheric pressure plasma processing chamber to affect surface changes, sub-surface changes, deposition, or removal by physical or chemical means.

[0021] 2, shown is an exemplary bias supply 208 that may be utilized to implement the bias supply 108 described with reference to FIG. 1. The bias supply 208 generally represents a number of variations of the bias supply, further described herein with reference to FIGS. 4A, 4B, 4C, 4D, 4E, 4F, and 4G, for applying a periodic voltage function. Thus, reference to the bias supply 208 generally refers to the bias supply 208 depicted in FIG. 2, and bias supplies 408A-408G, further described herein. As shown, the bias supply 208 includes an output 210 (also referred to as an output node 210), a return node 212, a resonant switch section 220, and a power section 230, with the resonant switch section 220 coupled to the power section 230 at three nodes, namely, a first node 214, a second node 216, and a third node 218. In general, the bias source 208 functions to apply a periodic voltage function between an output node 210 and a return node 212. Current delivered to the load through the output node 210 is fed back to the bias source 208 through a return node 212, which may be common to the load.

[0022] In many implementations as further disclosed herein, the resonant switch section 220 is configured to allow a first current path between the first node 214 and the second node 216 to be periodically connected and disconnected, which results in application of a periodic voltage waveform between the output node 210 and the return node 212. For example, the resonant switch section 220 may comprise a controllable switch and one or more inductive elements arranged to provide a first current path between the first node 214 and the second node 216 and a second current path between the second node 216 and the third node 218. Additionally, the first current path and the second current path may be configured such that the current in the first and second current paths is unidirectional.

[0023] As described further herein, power section 230 may include a combination of one or more voltage sources and inductive elements. Although not depicted in FIG. 2 for clarity and simplicity, bias supply 208 may be coupled to, coupled to, and / or including a controller with resonant switch section 220 and / or power section 230. Details of the respective variations of resonant switch section 220 and power section 230 and the interoperation of resonant switch section 220 and power section 230 are also disclosed further herein, but first it is useful to understand the plasma load aspect.

[0024] 3, shown is a schematic diagram electrically depicting a side view of an exemplary plasma load within a plasma processing chamber 101. As shown, the plasma processing chamber 101 includes an input 310 (also referred to as an input node 310) to the plasma processing chamber 101 and a sheath voltage V at the surface of a workpiece 103 (also referred to as a substrate 103). s A node representing the chuck capacitance C Ch (including the capacitance of the chuck and workpiece 103). In addition, a return node 312 (which may be a connection to ground) is depicted. The plasma 102 in the processing chamber is represented by a sheath capacitance Cs , a diode, and a current source. The diode represents the nonlinear diode-like nature of the plasma sheath, which results in rectification of the applied AC field such that a direct current (DC) voltage drop appears between the workpiece 103 and the plasma 102.

[0025] 4A, 4B, 4C, 4D, 4E, 4F, and 4G, shown are bias supplies 408A, 408B, 408C, 408D, 408E, 408F, 408G, respectively, that may be utilized to realize bias supply 208, and thus bias supplies 408A-408G may be utilized as bias supply 108 depicted in FIG. 1. As shown, bias supplies 408A-408G each comprise a resonant switch section 220 in association with a variation of power section 230 that comprises one or more voltage sources and inductors arranged in various topologies. More specifically, in each of FIGs. 4A, 4B, 4C, 4D, 4E, 4F, and 4G, the depicted voltage sources, inductors, and interconnections between the voltage sources and inductors constitute a variation of power section 230.

[0026] As shown, the bias supplies are each configured to apply a periodic voltage and comprise an output node 210 and a return node 212, with the bias supplies each comprising a resonant switch section 220 coupled to power sections at a first node 214, a second node 216, and a third node 218. The power sections of each of the bias supplies 408A, 408B, 408C, 408D, 408E, 408F, 408G vary from others of the bias supplies, but each of the bias supplies 408A, 408B, 408C, 408D, 408E, 408F, 408G comprises a first voltage source 222 coupled between the third node 218 and the first node 214 and a second voltage source 224 coupled to the return node 212. As discussed further herein, the switching action of resonant switch section 220 results in the application of a periodic voltage between output node 210 and return node 212 .

[0027] 4A, a first inductor Lb is positioned between the second node 216 and the negative terminal of the second voltage source 224. In addition, an inductance Lext is positioned between the second node 216 and the output node 210. The inductance Lext may be a stray inductance or an inductor that is intentionally added.

[0028] 4B, 4C, 4D, and 4F, the first inductor Lb is positioned between the output node 210 and the second voltage source 224. Also, note that in the variation depicted in Figures 4B, 4C, 4D, and 4F, the second node 216 and the output node 210 are a common node such that the first inductor Lb is positioned between the second node 216 and the second voltage source 224. As shown in Figures 4B, 4C, 4D, and 4F, the first inductor Lb is coupled between the output node 210 and the negative terminal of the second voltage source 224.

[0029] In the variations of Figures 4B and 4C, the return node 212 is the connection point between the first inductor Lb and the second voltage source 224. In the variations depicted in Figures 4A, 4D, and 4E, the positive node of the second voltage source 224 is coupled to the return node 212, and in the variations depicted in Figures 4B and 4C, the negative terminal of the second voltage source 224 is coupled to the return node.

[0030] 4D and 4E depict variations comprising a third voltage source 226 in which the negative terminal of the third voltage source 226 is connected to the return node 212. In the variation of FIG. 4D, the positive terminal of the third voltage source 226 is connected to the third node 218 and the negative terminal of the first voltage source 226, and in the variation of FIG. 4E, the positive terminal of the third voltage source 226 is connected to the third node 218 and the negative terminal of the third voltage source 226 is coupled to the negative terminal of the first voltage source 222.

[0031] In the example bias supply 408D, the third voltage source 226 adds a DC compensation voltage, which may be used to adjust the chucking force applied by the electrostatic chuck in the plasma processing chamber 101. In some operating modes, the total voltage applied by the second voltage source 224 and the third voltage source 226 is set to a constant value, such that as the voltage applied by the third voltage source 226 is increased, the voltage applied by the second voltage source 224 is decreased.

[0032] 4F, shown is another exemplary bias supply 408F that may be used to implement the bias supply 208. As shown, a transformer 444 is used to apply power to the bias supply output node 210. The transformer 444 includes a primary winding (represented by Llp and Lp) and a secondary winding (represented by Lls and Ls). A first node 680 of the primary winding of the transformer 444 is coupled to the second node 216. A first node 682 of the secondary winding of the transformer 444 is coupled to the output node 210. Also, a second node 684 of the secondary winding of the transformer 444 is coupled to a secondary return node 612 on the secondary side of the transformer 444. A first voltage source 222 is coupled between the first node 214 and a third node 218 of the resonant switch section 220. The second voltage source 224 is coupled between a second node 686 of the primary winding of the transformer 444 and the return node 212 .

[0033] The bias supply 408G shown in FIG. offset 4G, except that the offset voltage source V is coupled between the second node 684 of the secondary winding of the transformer 444 and the secondary return node 612. More specifically, the offset voltage source V offset The positive terminal of is coupled to the secondary return node 612, and the negative terminal of the offset voltage source V offset is coupled to a second node 684 of the transformer 444.

[0034] 5A, 5B, and 5C, shown are variations of the resonant switch section 220. As shown, the resonant switch sections 520A, 520B, 520C include a first node 214, a second node 216, and a third node 218, and each variation includes a first current path (for current iS1) between the first node 214 and the second node 216. The first current path includes a series combination of a switch S1 and a diode D1. In addition, each variation of the resonant switch sections 520A, 520B, 520C includes a second current path (for current iD2) (between the first current path and the third node 218), which includes a second diode D2 and an inductive element L2. As shown, the resonant switch sections 520A, 520B, 520C also include driver controller circuitry 223 that is coupled to switch S1 via drive signal line 544.

[0035] It should be appreciated that diode D1 and diode D2 may each be realized by multiple diodes. For example, either diode D1 and / or diode D2 may be realized by multiple series-connected diodes (to improve voltage capability), or either diode D1 and / or diode D2 may be realized by multiple diodes arranged in parallel (to improve current capability).

[0036] In resonant switch section 520A, the first current path comprises a series combination of switch S1, inductive element L1, and diode D1 arranged between first node 214 and second node 216. It should be appreciated that the order in which switch S1, diode D1, and inductor L1 are positioned (between first node 214 and second node 216) may be varied (because switch S1, diode D1, and inductor L1 are arranged in series).

[0037] In resonant switch section 520B, the first current path comprises a switch S1 arranged in series with a diode D1, the series combination of switch S1 and diode D1 being coupled between the first node 214 and the fourth node 221. In addition, the second current path (for iD2) comprises a series combination of inductor L2 and diode D2 between the fourth node 221 and the third node 218. In addition, resonant switch section 520B comprises an inductor L3 between the fourth node 221 and the second node 216.

[0038] 5C, resonant switch section 520C is similar to resonant switch section 520B, except that a first current path comprises a series combination of switch S1, inductive element L1, and diode D1 arranged between first node 214 and fourth node 221. It should be appreciated that the order in which switch S1, diode D1, and inductor L1 are positioned (between first node 214 and fourth node 216) may be varied (because switch S1, diode D1, and inductor L1 are arranged in series).

[0039] In many implementations, switch S1 is realized by a field effect switch such as a metal oxide semiconductor field effect transistor (MOSFET), and in some implementations, switch S1 is realized by a silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) or a gallium nitride metal oxide semiconductor field effect transistor (GaN MOSFET). As another example, switch S1 may be realized by an insulated gate bipolar transistor (IGBT). In these implementations, driver controller circuitry 223 may include an electrical driver known in the art configured to apply a power signal to switch S1 via drive signal line 544 in response to a signal from the controller. It is also contemplated that the controller may be capable of applying a sufficient level of power such that a separate electrical driver may be omitted. It is also contemplated that drive signal line 544 may be an optical line for conveying an optical switching signal. Switch S1 may also switch in response to an optical signal and / or an optical signal converted to an electrical drive signal.

[0040] It should be appreciated that switch S1 generally represents one or more switches that can be opened and closed to connect and disconnect, respectively, the first current path between the first node 214 and the second node 216. For example, switch S1 may be realized by multiple switches arranged in series (for improved voltage capability). Or, switch S1 may be realized by multiple switches arranged in parallel (for improved current capability). In these variations, one skilled in the art will appreciate that each switch may be driven by a corresponding drive signal in a synchronous manner.

[0041] 6A and 6B, what is shown is an asymmetric periodic voltage V o6A is a graph depicting operational aspects of a variation of the bias supply 208 disclosed herein to achieve an asymmetric periodic voltage between the output node 210 and the return node 212 of the bias supply 208 during a complete cycle of. More specifically, FIG. 6A illustrates the voltage of the first voltage source 222 (V rail 6B depicts the operational aspects of the bias source 208 when the voltage of the first voltage source 222 (V rail 6A and 6B depict the operating profile of bias source 208 when sheath voltage V ) exceeds zero. Also depicted in FIGS. 6A and 6B is the sheath voltage V , which corresponds to an asymmetric periodic voltage. s As shown, the asymmetric periodic voltage is generally negative to attract ions to impinge on the surface of the workpiece and enable etching of the workpiece 103, as well as a sheath voltage V s Achieve this.

[0042] As shown in FIG. 6A, when the switch S1 is closed at time t0, a current path (comprising the switch S1 and the diode D1) connects the first node 214 to the second node 216, and the unidirectional current iS1 starts to increase from zero current at time t0, causing an asymmetric periodic voltage V o (with respect to the return node 212) begins to move (over a first portion 651 of the periodic voltage waveform) from a first negative voltage 652 to a positive peak voltage 656. As shown, the current iS1 increases to a peak value 654 and then decreases to zero at time t1 when switch S1 is opened.

[0043] As depicted, when switch S1 is opened, the current iS1 through the first current path drops to zero and the asymmetric periodic voltage drops from a positive peak voltage 656. As shown, when switch S1 is opened (during the second portion 653 of the asymmetric waveform), a unidirectional current iD2 begins to flow through the second current path through the second diode D2, reaches a peak, and then drops to zero current flow at time t1-time t2. As shown, the rise and fall of the unidirectional current iD2 occurs while the asymmetric periodic voltage changes from the positive peak voltage 656 to a third negative voltage level 658 (during the second portion 653). As depicted, during time t0-t2, a first portion 651 of the asymmetric cyclic voltage causes the sheath voltage to approach a positive voltage to repel positive charge (which accumulates on the workpiece surface while the workpiece surface is held at a negative voltage), and a second portion 653 of the asymmetric cyclic voltage causes the sheath voltage to be at a desired negative voltage (or range of voltages) to achieve an ion flux that achieves a desired ion energy 670.

[0044] As depicted, the unidirectional current iD2 rises and then falls back to the zero current level, followed by an asymmetric periodic voltage V o becomes more negative (as a negative voltage ramp) during a fourth portion 661 until switch S1 is closed again at time t3. As depicted, a compensation iLb produced by the second voltage source 224 may be provided during the asymmetric periodic voltage cycle to compensate for the ion current in the plasma chamber 101. For example, without the compensation current iLb, the sheath voltage V s may gradually change and become more positive during the fourth portion of the asymmetric periodic voltage, which would create a wider distribution of ion energies, which may not be desirable. However, in some variations, the compensation current iLb may be intentionally set to overcompensate or undercompensate the ion current in the plasma chamber 101, creating a wider distribution of ion energies. In the mode of operation depicted in FIGS. 6A and 6B, the compensation current iLb is set to a value greater than the value of the asymmetric periodic voltage V oDuring the fourth portion 661 of the s to provide.

[0045] As shown in FIG. 6B, at time t1, when the switch S1 is opened, the voltage V from the first voltage source 222 is increased so that the current iD2 is non-zero. rail When iD2 exceeds zero, the operating profile of the bias source 208 changes from the voltage V from the first voltage source 222 to the voltage V from the first voltage source 222 except that the current iD2 increases in a ramp-like manner while the switch S1 remains closed. rail The operational profile of bias source 208 is similar when V is less than zero.

[0046] The methods described in connection with the embodiments disclosed herein may be embodied directly in hardware, in processor executable code encoded in a non-transitory tangible processor-readable storage medium, or in a combination of the two. With reference to FIG. 7, for example, what is shown is a block diagram depicting physical components that may be utilized to realize the control aspects disclosed herein. As shown, in this embodiment, a display 1312 and a non-volatile memory 1320 are coupled to a bus 1322, which is also coupled to a random access memory ("RAM") 1324, a processing portion (including N processing components) 1326, a field programmable gate array (FPGA) 1327, and a transceiver component 1328, including N transceivers. Although the components depicted in FIG. 7 represent physical components, FIG. 7 is not intended to be a detailed hardware diagram, and thus many of the components depicted in FIG. 7 may be realized by a general structure or distributed among additional physical components. Additionally, it is contemplated that other existing and yet to be developed physical components and architectures may also be utilized to implement the functional components described with reference to FIG.

[0047] The display 1312 generally operates to provide a user interface for a user, and in some implementations the display is realized by a touch screen display. In general, the non-volatile memory 1320 is a non-transient memory that functions to store (e.g., persistently store) data and processor executable code (including executable code associated with steps that effect the methods described herein). In some embodiments, for example, the non-volatile memory 1320 includes boot loader code, operating system code, file system code, and non-transient processor executable code to facilitate execution of a method of biasing a substrate using a single controlled switch.

[0048] In many implementations, the non-volatile memory 1320 is realized by a flash memory (e.g., NAND or ONENAND memory), although it is contemplated that other memory types may be utilized as well. While it may be possible to execute code from the non-volatile memory 1320, executable code in the non-volatile memory is typically loaded into RAM 1324 and executed by one or more of the N processing components in the processing portion 1326.

[0049] The N processing components, in conjunction with the RAM 1324, generally operate to execute instructions stored in the non-volatile memory 1320 to enable execution of the algorithms and functions disclosed herein. It should be appreciated that while several algorithms are disclosed herein, some of these algorithms are not represented in the flow charts. Processor executable code for effecting the methods described herein may be stored persistently in the non-volatile memory 1320 and executed by the N processing components in conjunction with the RAM 1324. As one skilled in the art would appreciate, the processing portion 1326 may include a video processor, a digital signal processor (DSP), a microcontroller, a graphics processing unit (GPU), or other hardware processing components or a combination of hardware and software processing components (e.g., an FPGA or FPGAs including digital logic processing portions).

[0050] Additionally or alternatively, non-transient FPGA configuration instructions may be persistently stored in non-volatile memory 1320 and accessed (e.g., during boot-up) to configure a field programmable gate array (FPGA) to implement the algorithms disclosed herein.

[0051] The input component 1330 may receive signals (e.g., signals indicative of the current and voltage obtained at the output of the disclosed bias supply). In addition, the input component 1330 may receive phase information and / or synchronization signals between the bias supply 108 and the source generator 112 indicative of one or more aspects of the environment in the plasma processing chamber 101 and / or the synchronized control between the source generator and the single switch bias supply. The signals received at the input component may include, for example, from synchronization signals, power control signals for various generators and power supply units, or control signals from a user interface. Those skilled in the art will readily appreciate that any of a variety of types of sensors, such as, but not limited to, directional couplers and voltage-current (VI) sensors, may be used to sample power parameters such as voltage and current, and signals indicative of the power parameters may be generated in the analog domain and converted to the digital domain.

[0052] The output components may generally operate to provide one or more analog or digital signals to effect the opening or closing of switch S1. The output components may also control the voltage sources described herein.

[0053] The depicted transceiver component 1328 includes N transceiver chains that may be used to communicate with external devices over wireless or wired networks. Each of the N transceiver chains may represent a transceiver associated with a particular communication scheme (e.g., Wifi, Ethernet, Profibus, etc.).

[0054] As will be appreciated by those skilled in the art, aspects of the present disclosure may be embodied as a system, method, or computer program product. Thus, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which may all generally be referred to herein as a "circuit," "module," or "system." Additionally, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

[0055] As used herein, the recitation of "at least one of A, B, or C" is intended to mean "any of A, B, C, or any combination of A, B, and C." The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus for applying a periodic voltage, the apparatus comprising: a switch coupled to the first node and the second node; a first voltage source coupled to the first node and a third node; a second voltage source coupled to the second node and a third node; a controller configured to close the switch to connect and disconnect a current path between the first node and the second node to cause application of an asymmetric periodic voltage waveform at the second node relative to the third node; Equipped with 11. The apparatus of claim 10, wherein each cycle of the asymmetric periodic voltage waveform includes a first portion starting from a first negative voltage and changing to a positive peak voltage, a second portion changing from the positive peak voltage to a third voltage level, and a fourth portion including a negative voltage ramp from the third voltage level to a fourth voltage level.

2. The device described in claim 1, wherein connecting the current path between the first node and the second node causes the first portion of the asymmetric periodic voltage waveform to start from a first negative voltage and change to the positive peak voltage.

3. The device described in claim 2, wherein disconnecting the current path causes the second portion of the asymmetric periodic voltage waveform to change from the positive peak voltage level to the third voltage level.

4. The device described in claim 1, wherein the second voltage source is in series with an inductive element, and the second voltage source and the inductive element are coupled between the second node and the third node.

5. The device described in claim 4, wherein the switch is arranged in series with a first diode and a first inductor, and the switch, first diode, and first inductor are coupled between the first node and the second node.

6. The device described in claim 5, wherein a second inductor is arranged in series with a second diode, and the second inductor and the second diode are coupled between the second node and the third node.

7. The device described in claim 6, wherein the second voltage source is arranged in series with a third inductor (Lb), and the second voltage source and the third inductor are arranged between the second node and the third node.

8. The device of claim 1, wherein the switch includes a plurality of switches arranged in series.

9. The device of claim 1, wherein the switch includes a plurality of switches arranged in parallel.

10. A method, comprising: applying a first voltage between the first node and a third node; applying a second voltage between the second node and a third node; connecting and disconnecting a current path between the first node and the second node to cause application of an asymmetric periodic voltage waveform at the second node, each cycle of the asymmetric periodic voltage waveform including a first portion starting from a first negative voltage and changing to a positive peak voltage, a second portion changing from the positive peak voltage to a third voltage level, and a fourth portion including a negative voltage ramp from the third voltage level to a fourth voltage level; A method comprising:

11. The method of claim 10, wherein the connecting and disconnecting causes a unidirectional current through the current path between the first node and the second node.

12. The method of claim 11, wherein the connecting and disconnecting causes a unidirectional current through a second current path between the second node and the third node.

13. 1. An apparatus for applying a periodic voltage, the apparatus comprising: an output node; A return node; a switch and a first diode arranged in series in a first current path between a first node and a second node; a second current path between the second node and a third node, the second current path comprising a second diode; and a first voltage source coupled between the first node and the third node; a second voltage source coupled to the return node; Equipped with The apparatus, wherein closing the switch induces unidirectional current in the first current path and the second current path, causing the application of the periodic voltage between the output node and the return node.

14. The first current path is configured such that the unidirectional current in the first path flows through the switch at time t ０ The current increases from zero to a peak value at time t １ and the voltage between the output node and the return node decreases back to zero at time t ０ From the negative voltage at the time t １ 14. The apparatus of claim 13, configured to increase the amplitude of the signal to a peak value at

15. 14. The apparatus of claim 13, wherein the first current path comprises a series combination of the switch, a first inductive element, and the first diode coupled between the first node and the second node.

16. 14. The apparatus of claim 13, wherein the first current path comprises two inductive elements coupled together at the second node.

17. The apparatus of claim 13, comprising a series combination of the second voltage source and an inductive element coupled between the output node and the return node.

18. 14. The apparatus of claim 13, wherein the second voltage source is coupled between the second node and the return node.

19. 14. The apparatus of claim 13, wherein the negative terminal of the second voltage source is coupled to the negative terminal of the first voltage source.

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