Skew Matching at Die-to-Die Interfaces

Abstract

A semiconductor package for skew matching at a die-to-die interface comprises a first die, a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die, and a plurality of connection paths of substantially the same length, each connection path of the plurality of connection paths coupling a respective connection point of the first plurality of connection points to a corresponding connection point of the second plurality of connection points.

Description

[Background technology]

[0001] A die-to-die interface communicatively couples the die to enable data transfer between the die. Data is transferred using multiple simultaneously active connection paths. As an example, a byte is transferred between the die by simultaneously sending each bit value of the byte across multiple connection paths. If the connection paths vary in length, the portions of data (e.g., each bit) that are transmitted simultaneously will arrive at different times. This varying data arrival time is known as "skew." [Brief description of the drawings]

[0002] [Figure 1] 1 is a block diagram of an example semiconductor package for skew matching at die-to-die interfaces in accordance with some embodiments. [Diagram 2] FIG. 2 illustrates an example layout for input / output connection points for skew matching at die-to-die interfaces, according to some embodiments. [Diagram 3] FIG. 2 is a block diagram of an example computer for skew matching at die-to-die interfaces in accordance with some embodiments. [Figure 4] 4 is a flowchart of an exemplary method for skew alignment at a die-to-die interface in accordance with some embodiments. [Diagram 5] 5 is a flowchart of another exemplary method for skew alignment at a die-to-die interface, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0003] Existing solutions to address skew include training the receiving die to sample the received data at the correct time or to reconstruct the received datagram to account for the skew in the data transmission. These approaches require additional overhead and complex logic.

[0004] To that end, the present specification describes various embodiments for skew matching at die-to-die interfaces. In some embodiments, a semiconductor package for skew matching at die-to-die interfaces includes a first die and a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. The semiconductor package also includes a plurality of connection paths of substantially equal length, the paths coupling each connection point of the first plurality of connection points to a corresponding connection point of the second plurality of connection points.

[0005] In some embodiments of the semiconductor package, the layout of the first plurality of connection points corresponds to a 180 degree rotation of the layout of the second plurality of connection points after alignment of the first die and the second die. In some embodiments, the transmit block of the first die is linearly aligned with the receive block of the second die, and the transmit block of the second die is linearly aligned with the receive block of the first die. In some embodiments, the semiconductor package further includes a clock coupled to the first die and the second die. In some embodiments, each of the first plurality of connection points and the second plurality of connection points includes a first subset of connection points for data transfer and a second subset of connection points for the clock. In some embodiments, each of the first die and the second die provides a respective source synchronous clock signal along with a respective data signal. In some embodiments, the respective source synchronous clock signals are in quadrature with the respective data signals.

[0006] This specification also describes various embodiments of methods for skew matching at die-to-die interfaces, including aligning a first die with a second die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die, and coupling each connection point of the first plurality of connection points to a corresponding connection point of the second plurality of connection points using a plurality of connection paths of substantially the same length.

[0007] In some embodiments of the method, the layout of the first plurality of connection points corresponds to a 180 degree rotation of the layout of the second plurality of connection points after alignment of the first die with the second die. In some embodiments, after aligning the first die with the second die, the transmit block of the first die is linearly aligned with the receive block of the second die, and the transmit block of the second die is linearly aligned with the receive block of the first die. In some embodiments, the method further includes coupling a clock to the first die and the second die. In some embodiments, each of the first plurality of connection points and the second plurality of connection points includes a first subset of connection points for data transfer and a second subset of connection points for the clock. In some embodiments, each of the first die and the second die provides a respective source synchronous clock signal along with a respective data signal. In some embodiments, the respective source synchronous clock signals are in quadrature with the respective data signals.

[0008] Also described herein are various embodiments of an apparatus for skew alignment at a die-to-die interface. Such an apparatus includes a computer memory and a semiconductor package operably coupled to the computer memory. The semiconductor package includes a first die and a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. The semiconductor package also includes a plurality of connection paths of substantially equal length, the connection paths coupling each connection point of the first plurality of connection points to a corresponding connection point of the second plurality of connection points.

[0009] In some embodiments of the apparatus, the layout of the first plurality of connection points corresponds to a 180 degree rotation of the layout of the second plurality of connection points after alignment of the first die with the second die. In some embodiments, the transmit block of the first die is linearly aligned with the receive block of the second die, and the transmit block of the second die is linearly aligned with the receive block of the first die. In some embodiments, the apparatus further includes a clock coupled to the first die and the second die. In some embodiments, each of the first plurality of connection points and the second plurality of connection points includes a first subset of connection points for data transfer and a second subset of connection points for the clock. In some embodiments, each of the first die and the second die provides a respective source synchronous clock signal along with a respective data signal.

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the provided invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description includes embodiments in which the first and second features are formed in direct contact, and also includes embodiments in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," "back," "front," "top," "bottom," and the like are used herein to facilitate descriptions that describe the relationship of one element or feature to another element(s) or feature(s), as shown in the figures. Similarly, terms such as "front" and "back" or "top" and "back" are used herein to more easily identify various components and to identify those components as being on opposite sides of another component, for example. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures.

[0011] 1 is a block diagram of a non-limiting exemplary package 100. The exemplary package 100 may be implemented in a variety of computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, and the like. The package 100 is a semiconductor package, such as a processor. Such a processor may be implemented, for example, in a computer as a central processing unit (CPU), as a processor or core on a parallel accelerator, such as a graphics processing unit (GPU), machine learning accelerators, and links, or implemented in other ways, as can be understood by one of ordinary skill in the art.

[0012] The package 100 includes a die 102a and a die 102b. The die 102a, 102b are portions of semiconductor material, such as silicon, on which functional circuits are fabricated. In some embodiments, the die 102a, 102b are system-on-chip (SoC) dies, chiplets, or other functional semiconductor dies, as may be appreciated. In some embodiments, the package 100 includes a substrate, such as a printed circuit board (PCB), to which the die 102a, 102b are coupled. In some embodiments, the die 102a, 102b are housed or encapsulated within an encapsulant or other molding material. In some embodiments, the die 102a, 102b are mounted on or bonded to a carrier wafer or other structural support component.

[0013] Each of the dies 102a, 102b includes a number of input / output (I / O) connection points. Each I / O connection point is an area of ​​a conductive surface where a signal (e.g., data signal, clock signal) is provided to or from the die 102a, 102b. By way of example, the I / O connection points include pins, bumps, or other components, as may be understood. In the exemplary package 100, each of the dies 102a, 102b includes a respective transmit (Tx) block 104a, 104b and receive (Rx) block 106a, 106b. Each Tx block 104a, 104b of a given die 102a, 102b includes a number of I / O connection points that are assigned or dedicated to transmitting signals to the Rx block 106a, 106b of the other die 102a, 102b. Conversely, each Rx block 106a, 106b of a given die 102a, 102b includes a number of I / O connection points that are assigned or dedicated to receiving signals (e.g., data signals, clock signals) from the Tx blocks 104a, 104b of the other die 102a, 102b.

[0014] The dies 102a, 102b are communicatively coupled by an interface 108. In the exemplary package 100, the interface 108 couples the dies 102a, 102b by coupling the Tx blocks 104a, 104b of each die 102a, 102b to the Rx blocks 106a, 106b of the other die 102a, 102b. The interface 108 includes multiple connection paths. Each connection path in the interface 108 couples an I / O connection point of the die 102a, 102b (e.g., from the Tx blocks 104a, 104b) to another I / O connection point of the other die 102a, 102b (from the Rx blocks 106a, 106b). By way of example, the connection paths include conductive traces, wires, pins, vias, or other connection paths that may be understood.

[0015] In some embodiments, the interface 108 includes a bridge die. The bridge die is a die of semiconductor material (e.g., silicon) on which the connection paths are fabricated. In some embodiments, the interface 108 includes conductive traces (e.g., fan-out traces or other traces, as may be understood) contained or fabricated in one or more redistribution layers. Such redistribution layers include a continuous layer of dielectric material, such as polyamide, in which the conductive traces and other conductive materials (e.g., pads, plates, vias, etc.) are contained to form conductive connection paths between the dies 102a, 102b.

[0016] In existing solutions for die-to-die communication, the dies 102a, 102b are aligned and the connection paths of the interface 108 are formed such that pairs of I / O connection points located closer together are coupled using shorter connection paths within the interface 108, while pairs of I / O connection points located further away are coupled using longer connection paths (e.g., using a "clamshell" or other pattern of conductive traces). Thus, conductive paths of different lengths within the interface 108 are used to couple the dies 102a, 102b.

[0017] During data transmission between the dies 102a, 102b, multiple signals are transmitted simultaneously between the dies 102a, 102b using multiple connection paths in the interface 108. As an example, a frame or other datagram is transmitted between the dies 102a, 102b over multiple connection paths. Due to different lengths of the connection paths, signals transmitted simultaneously from one die 102a, 102b arrive at the other die 102a, 102b at different times, resulting in "skew" in the signals and data. Existing solutions to address these concerns require training the Rx blocks 106a, 106b samplers to sample the received signals at the correct times to reconstruct the received data or to align data received at different times with the correct datagram.

[0018] Instead, to address these concerns, the dies 102a, 102b are aligned within the package 100 such that each pair of I / O connection points are substantially equidistant. In other words, each I / O connection point of the first die 102 is located substantially the same distance from its corresponding I / O connection point in the second die 102b. Each pair of I / O connection points is connected using a connection path in the interface 108 that is substantially the same length. Because each connection path has approximately the same length and the same conductive characteristics, simultaneous transmission of multiple signals from one die 102a, 102b is received at the other die 102a, 102b substantially simultaneously.

[0019] To facilitate the formation of equal length connection paths in the interface 108, in some embodiments, the layout of the I / O connection points in the first die 102a (e.g., in the Tx block 104a and the Rx block 106a) corresponds to a 180 degree rotation of the layout of the I / O connection points in the second die 102b (e.g., in the Tx block 104b and the Rx block 106b). In other words, the layout of the I / O connection points in the first die 102a is flipped once across each of the X and Y axes to define the layout of the I / O connection points in the second die 102b.

[0020] Consider the example of Figure 2, which shows an exemplary layout of I / O connection points for die-to-die communication. Figure 2 shows a die 102a arranged side-by-side with a die 102b. Each die 102a, 102b includes multiple I / O connection points 202 grouped into respective Tx blocks 104a, 104b and Rx blocks 106a, 106b. The Tx block 104a of the die 102a is linearly aligned with the Rx block 106b of the die 102b, and the Tx block 104b of the die 102b is linearly aligned with the Rx block 106a of the die 102a.

[0021] Each I / O connection point 202 includes the labels “Tx1”-“Tx21”, “Rx1”-“Rx21”, “Tx1′-Tx21′” and “Rx1′-Rx21′”. As shown, the I / O connection points of die 102b reflect a 180 degree rotation of the I / O connection points of die 102a. As an example, I / O connection point 202 “Tx1” is located at the top left corner of Tx block 104a. Matching I / O connection point 202 “Tx1′” is located at the bottom right corner of Tx block 104b. As another example, I / O connection point 202 “Rx7” is located at the bottom left corner of Rx block 106a. Matching I / O connection point 202 “Rx7′” is located at the top right corner of Rx block 106b. 2, the dies 102a, 102b are constructed to have a matching layout of I / O connection points 202, and one die 102a, 102b is rotated 180 degrees for placement (e.g., within the package 100) to align pairs of I / O connection points 202.

[0022] Assume that some transmit I / O connection points 202 of a die 102a, 102b are connected via an interface 108 (not shown) to receive I / O connection points 202 in the other die 102a, 102b that are labeled with the same number. In the example of Fig. 2, connection paths 204 are used to couple I / O connection points 202 "Tx6" to "Rx6", "Tx7" to "Rx7", "Tx3'" to "Rx3'", and "Tx2'" to "Rx2'". As shown, due to their relative placement, each pair of coupled I / O connection points 202 are substantially the same distance apart and therefore can be coupled using connection paths 204 of substantially the same length.

[0023] Those skilled in the art will appreciate that the exemplary layout of FIG. 2 is merely exemplary and that other layouts and configurations of the dies 102a, 102b, I / O connection points 202, and connection paths 204 are contemplated within the scope of the present disclosure.

[0024] Returning to FIG. 1, in some embodiments, the package 100 also includes a clock 110. The clock 110 generates a signal oscillating at a particular frequency to drive the timing of data transmission by the Tx blocks 104a, 104b and the sampling of data by the Rx blocks 106a, 106b. In some embodiments, to further prevent skew across die-to-die data transmission, a clock signal is provided from the clock to the Tx blocks 104a, 104b to drive the timing of transmission by the Tx blocks 104a, 104b. In some embodiments, instead of the clock 110 providing a clock signal directly to the Rx blocks 106a, 106b, the Tx blocks 104a, 104b provide a clock signal to their respective Rx blocks 106a, 106b via the interface 108. Such a clock signal provided from the Tx blocks 104a, 104b to the Rx blocks 104a, 104b is considered a "transfer" or "source synchronous" clock signal. The Rx blocks 106a, 106b then sample the received signal using the received clock signal. In other words, in some embodiments, each Tx block 104a, 104b and Rx block 106a, 106b includes a subset of I / O connection points for data transfer and a subset of I / O connection points for the clock.

[0025] In some embodiments, each Tx block 104a, 104b transmits a clock signal that is orthogonal to the data signal. In other words, the clock signal is shifted 90 degrees with respect to the transmitted data signal. The clock signal is transmitted at the interface 108 using a connection path of the same length relative to the connection path used to transmit the data signal. Thus, skew of the clock signal is avoided since both the data signal and the clock signal are transmitted over a connection path of substantially the same length. Although FIG. 1 does not show a direct connection between the clock 110 and the Tx blocks 104a, 104b, this is for clarity, and those skilled in the art will understand that in some embodiments, the clock 110 provides a clock signal directly to the Tx blocks 104a, 104b, which are then forwarded by the Tx blocks 104a, 104b to the Rx blocks 106a, 106b. In some embodiments, the connection paths from the clock 110 to the Tx blocks 104a, 104b are substantially the same length to further avoid skew of the clock signal.

[0026] In some embodiments, the package 100 of FIG. 1 is implemented in a computer 300. For example, the package 100 is implemented as at least one processor 302. In addition to the at least one processor 302, the computer 300 of FIG. 3 includes random access memory (RAM) 304 that is connected to the processor 302 and other components of the computer 300 via a high speed memory bus 306 and a bus adapter 308. An operating system 310 is stored in the RAM 304. Although the operating system 310 in the example of FIG. 3 is shown in the RAM 304, many components of such software are typically also stored in non-volatile memory, such as data storage 312, e.g., a disk drive or the like.

[0027] 3 includes a disk drive adapter 316 coupled to processor 302 and other components of computer 300 via expansion bus 318 and bus adapter 308. Disk drive adapter 316 connects non-volatile data storage to computer 300 in the form of data storage 312. Such disk drive adapters include Integrated Drive Electronics ("IDE") adapters, Small Computer System Interface ("SCSI") adapters, and others as would occur to one of ordinary skill in the art. In some embodiments, the non-volatile computer memory is implemented as an optical disk drive, an electrically erasable programmable read-only memory (also known as "EEPROM" or "flash" memory), a RAM drive, or the like, as would occur to one of ordinary skill in the art.

[0028] The example computer 300 of Figure 3 includes one or more input / output ("I / O") adapters 320. I / O adapters provide user-oriented input / output through software drivers and computer hardware for controlling output to a display device, such as a computer display screen, and user input from user input devices 322, such as a keyboard and mouse. The example computer 300 of Figure 3 includes a video adapter 324, which is an example of an I / O adapter specifically designed for graphics output to a display device 326, such as a display screen or computer monitor. Video adapter 324 is connected to processor 302 via a high-speed video bus 328, bus adapter 308, and frontside bus 330, which is also a high-speed bus.

[0029] The example computer 300 of Figure 3 includes a communications adapter 332 for data communications with other computers and with a data communications network. Such data communications may occur serially through an RS-232 connection, through an external bus such as a Universal Serial Bus ("USB"), through a data communications network such as an IP data communications network, and / or in other manners as would occur to one skilled in the art. The communications adapter 332 provides the hardware level of data communications at which one computer sends data communications directly to another computer or over a data communications network. Such communications adapters 332 include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

[0030] For further explanation, FIG. 4 shows a flow chart illustrating an exemplary method for skew alignment at a die-to-die interface, comprising aligning 402 a first die 102a with a second die 102b such that each connection point of a first plurality of connection points of the first die 102a is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die 102b. The first and second plurality of connection points include, for example, I / O connection points 202. The connection points provide access points to the die 102a, 102b for transmitting or receiving signals, including data signals and clock signals. In some embodiments, the connection points are grouped in the die 102a, 102b into blocks of connection points for transmitting signals (e.g., Tx blocks 104a, 104b) and blocks of connection points for receiving signals (e.g., Rx blocks 106a, 106b).

[0031] In some embodiments, the first die 102a is aligned with the second die 102b during manufacturing of the semiconductor package (e.g., package 100). For example, the first die 102a and the second die 102b are placed on a carrier or other mechanical support and then encapsulated using an encapsulant or molding compound. In some embodiments, the Tx block 104a of the first die 102a is linearly aligned with the Rx block 106b of the second die 102b, and the Tx block 104b of the second die 102b is linearly aligned with the Rx block 106a of the first die 102a.

[0032] In some embodiments, the layout of the first plurality of connection points corresponds to a 180 degree rotation of the layout of the second plurality of connection points after alignment of the first die 102a and the second die 102b. In other words, the first die 102a and the second die 102b have matching connection point layouts. With a 180 degree rotation of either die 102a, 102b, the Tx block 104a and the Rx block 106a of the first die 102a are linearly aligned with the Tx block 104b and the Rx block 106b of the second die 102b. Thus, the pairs of connection points across the joined dies 102a, 102b are substantially equidistant after alignment.

[0033] The method of FIG. 4 includes coupling 404 each connection point of the first plurality of connection points to a corresponding connection point of the second plurality of connection points using a plurality of connection paths of substantially the same length. In some embodiments, the plurality of connection paths are included in an interface 108 that couples the first die 102a and the second die 102b. The interface 108 includes a plurality of connection paths. Each connection path in the interface 108 couples an I / O connection point of the die 102a, 102b (e.g., from the Tx blocks 104a, 104b) to another I / O connection point of the other die 102a, 102b (from the Rx blocks 106a, 106b). By way of example, the connection paths include conductive traces, wires, pins, vias, or other connection paths that may be understood.

[0034] In some embodiments, the interface 108 includes a bridge die. The bridge die is a die of semiconductor material (e.g., silicon) on which the connection paths are fabricated. In some embodiments, the interface 108 includes conductive traces (e.g., fan-out traces or other traces, as may be understood) contained or fabricated in one or more redistribution layers. Such redistribution layers include a continuous layer of dielectric material, such as polyamide, in which the conductive traces and other conductive materials (e.g., pads, plates, vias, etc.) are contained to form conductive connection paths between the dies 102a, 102b.

[0035] Since each connection path has approximately the same length and the same conductive characteristics, the simultaneous transmission of multiple signals from one die 102a, 102b is received at the other die 102a, 102b substantially simultaneously. Thus, the skew in data transfer between the first die 102a and the second die 102b is improved without the need for phase training or alignment or frame training or alignment.

[0036] For further explanation, Figure 5 shows a flowchart illustrating an example method for skew matching at die-to-die interfaces according to some embodiments of the present disclosure. The method of Figure 5 is similar to Figure 4 in that it includes aligning 402 a first die 102a with a second die 102b such that each connection point of a first plurality of connection points of the first die 102a is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die 102b, and coupling 404 each connection point of the first plurality of connection points to a corresponding connection point of the second plurality of connection points using a plurality of connection paths of substantially the same length.

[0037] The method of FIG. 5 differs from FIG. 4 in that it includes coupling 502 a clock 110 to the first die 102a and the second die 102b. The clock 110 generates a signal that oscillates at a particular frequency to drive the timing of data transmission by the Tx blocks 104a, 104b and the sampling of data by the Rx blocks 106a, 106b. In some embodiments, to further prevent skew across die-to-die data transmission, a clock signal is provided from the clock to the Tx blocks 104a, 104b to drive the timing of transmission by the Tx blocks 104a, 104b. In some embodiments, instead of the clock 110 providing a clock signal directly to the Rx blocks 106a, 106b, the Tx blocks 104a, 104b provide a clock signal to their respective Rx blocks 106a, 106b via the interface 108. Such a clock signal provided from the Tx block 104a, 104b to the Rx block 104a, 104b is considered a "transported" or "source synchronous" clock signal. The Rx block 106a, 106b then samples the received signal using the received clock signal. In other words, in some embodiments, each Tx block 104a, 104b and Rx block 106a, 106b includes a subset of I / O connection points for data transfer and a subset of I / O connection points for the clock.

[0038] In some embodiments, each Tx block 104a, 104b transmits a clock signal that is orthogonal to the data signal. In other words, the clock signal is shifted 90 degrees with respect to the transmitted data signal. The clock signal is transmitted at the interface 108 using a connection path of the same length relative to the connection path used to transmit the data signal. Thus, skew of the clock signal is avoided since both the data signal and the clock signal are transmitted over a connection path of substantially the same length. Although FIG. 1 does not show a direct connection between the clock 110 and the Tx blocks 104a, 104b, this is for clarity, and those skilled in the art will understand that in some embodiments, the clock 110 provides a clock signal directly to the Tx blocks 104a, 104b, which are then forwarded by the Tx blocks 104a, 104b to the Rx blocks 106a, 106b. In some embodiments, the connection paths from the clock 110 to the Tx blocks 104a, 104b are substantially the same length to further avoid skew of the clock signal.

[0039] In light of the above discussion, the reader will recognize many advantages of skew alignment in die-to-die interfaces including, for example, improved performance of a computing system by correcting skew in die-to-die communications without phase-matching frame training.

[0040] Exemplary embodiments of the present disclosure are described primarily in the context of a computer system that functions well for skew alignment at die-to-die interfaces. However, a reader of ordinary skill in the art will recognize that the present disclosure may be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium may be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tapes, and others as would occur to one of ordinary skill in the art. A person of ordinary skill in the art will readily recognize that any computer system with suitable programming means is capable of executing the steps of the method of the present disclosure embodied in a computer program product. A person of ordinary skill in the art will also recognize that while some of the exemplary embodiments described herein are directed to software that is installed and executed on computer hardware, alternative embodiments implemented as firmware or as hardware are nevertheless well within the scope of the present disclosure.

[0041] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the present disclosure.

[0042] A computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media includes, for example, portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves having instructions recorded thereon, and any suitable combination thereof. As used herein, a computer-readable storage medium should not be construed as being electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), such as radio waves or other freely propagating electromagnetic waves, or a transitory signal per se, such as an electrical signal transmitted through a wire.

[0043] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transmits the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing / processing device.

[0044] The computer readable program instructions for carrying out the operations of the present disclosure can be either assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions can be executed completely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or completely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to individualize the electronic circuitry to implement aspects of the present disclosure.

[0045] Aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer readable program instructions.

[0046] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to manufacture a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, generate means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions may be stored on a computer readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner such that the computer readable storage medium having instructions stored thereon comprises an article of manufacture including instructions that perform aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0047] The computer readable program instructions may be loaded into a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to generate a computer-implemented process such that the instructions executing on the computer, other programmable apparatus or other device perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0048] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions described in the blocks may occur out of the order described in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flow diagrams, as well as combinations of blocks in the block diagrams and / or flow diagrams, may be executed by a dedicated hardware-based system that performs the specified functions or acts, or executes a combination of dedicated hardware and computer instructions.

[0049] It will be understood from the above written description that modifications and variations can be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. 1. A semiconductor package for skew alignment at a die-to-die interface, comprising: A first die; and a second die aligned with the first die such that each connection point of the first plurality of connection points of the first die is equidistant to a corresponding connection point of the second plurality of connection points of the second die; a plurality of connection paths of the same length, each connection path of the plurality of connection paths coupling a respective connection point of the first plurality of connection points to a corresponding connection point of the second plurality of connection points; Semiconductor package.

2. a layout of the first plurality of connection points differs from a layout of the second plurality of connection points; 2. The semiconductor package of claim 1.

3. the transmit blocks of the first die are linearly aligned with the receive blocks of the second die, and the transmit blocks of the second die are linearly aligned with the receive blocks of the first die; 2. The semiconductor package of claim 1.

4. a clock coupled to the first die and the second die; 2. The semiconductor package of claim 1.

5. each of the first plurality of connection points and the second plurality of connection points comprises a first subset of connection points for data transfer and a second subset of connection points for a clock; 5. The semiconductor package of claim 4.

6. each of the first die and the second die providing a respective source synchronous clock signal along with a respective data signal; 6. The semiconductor package of claim 5.

7. said respective source synchronous clock signals being in quadrature with said respective data signals; 7. The semiconductor package of claim 6.

8. 1. A method for skew alignment at a die-to-die interface, comprising: aligning the first die with the second die such that each connection point of a first plurality of connection points of the first die is equidistant to a corresponding connection point of a second plurality of connection points of the second die; and coupling each connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points using connection paths, each of the connection paths having the same length. method.

9. a layout of the first plurality of connection points differs from a layout of the second plurality of connection points; 9. The method of claim 8.

10. after aligning the first die with the second die, a transmit block of the first die is linearly aligned with a receive block of the second die, and a transmit block of the second die is linearly aligned with a receive block of the first die; 9. The method of claim 8.

11. coupling a clock to the first die and to the second die; 10. The method of claim 9.

12. each of the first plurality of connection points and the second plurality of connection points comprises a first subset of connection points for data transfer and a second subset of connection points for a clock; 12. The method of claim 11.

13. and coupling the clock to the first die and the second die includes configuring the first die and the second die to provide a respective source synchronous clock signal along with a respective data signal.

13. The method of claim 12.

14. said respective source synchronous clock signals being in quadrature with said respective data signals; 14. The method of claim 13.

15. 1. An apparatus for skew alignment at a die-to-die interface, comprising: Computer memory; a semiconductor package operably coupled to the computer memory; The semiconductor package includes: A first die; and a second die aligned with the first die such that each connection point of the first plurality of connection points of the first die is equidistant to a corresponding connection point of the second plurality of connection points of the second die; a plurality of connection paths of the same length, each connection path of the plurality of connection paths coupling a respective connection point of the first plurality of connection points to a corresponding connection point of the second plurality of connection points; Device.

16. a layout of the first plurality of connection points differs from a layout of the second plurality of connection points; 16. The apparatus of claim 15.

17. the transmit blocks of the first die are linearly aligned with the receive blocks of the second die, and the transmit blocks of the second die are linearly aligned with the receive blocks of the first die; 16. The apparatus of claim 15.

18. the semiconductor package comprising a clock coupled to the first die and the second die; 16. The apparatus of claim 15.

19. each of the first plurality of connection points and the second plurality of connection points comprises a first subset of connection points for data transfer and a second subset of connection points for a clock; 20. The apparatus of claim 18.

20. each of the first die and the second die providing a respective source synchronous clock signal along with a respective data signal; 20. The apparatus of claim 19.

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