Semiconductor structure having embedded power interconnects - Patents.com

Abstract

An embodiment of the present invention provides a semiconductor structure including a substrate layer and a buried power wiring (BPR) embedded in the substrate layer, the BPR being separated from the substrate layer by an extended deep shallow trench isolation (STI) region. In one embodiment, the extended deep STI region has a first width near a top of the extended deep STI region and a second width near a middle portion of the extended deep STI region, the second width being greater than the first width. Methods of fabricating the above semiconductor structure are also provided.

Description

[Technical field]

[0001] This application relates to the fabrication of semiconductor integrated circuits, and more particularly to a semiconductor structure for landing nanoTSVs on buried power interconnects and a method for fabricating the same. [Background technology]

[0002] As the need for semiconductor circuit size continues to decrease, it becomes increasingly difficult to physically align semiconductor devices within and / or across various integration levels. One such example is the integration of buried power wiring within a semiconductor substrate.

[0003] At current transistor node levels, the critical dimensions (CD) of buried power lines are becoming extremely small. In the process of forming a through nano-silicon via to land on the buried power line, poor or insufficient CD or overlay control can short the through nano-silicon via to the substrate that typically immediately surrounds the buried power line. Summary of the Invention

[0004] According to one aspect of the invention, a semiconductor structure is provided that includes a substrate layer and a buried power interconnect (BPR) embedded in the substrate layer, the BPR being separated from the substrate layer by an extended deep shallow trench isolation (STI) region. According to one embodiment, the extended deep STI region has a first width near a top of the extended deep STI region and a second width near a middle portion of the extended deep STI region, the second width being greater than the first width.

[0005] Preferably, the present invention provides a semiconductor structure further comprising a nano through silicon via (nTSV), wherein a bottom portion of the nTSV contacts a bottom portion of the BPR, and wherein the bottom portion of the nTSV is completely surrounded by the extended deep STI region.

[0006] Preferably, the present invention provides a semiconductor structure, in which an nTSV is buried in a substrate layer, and the sidewalls of the TSV are completely surrounded by and separated from the substrate layer by an extended deep STI region.

[0007] According to another aspect of the invention, a method of forming a semiconductor structure is provided. In one embodiment, the method includes providing a semiconductor substrate, forming a first recess in the semiconductor substrate, increasing the depth and laterally increasing the width of the first recess to form an extended deep STI region, filling the extended deep STI region with a dielectric material, and forming at least one buried power interconnect (BPR) within the dielectric material in the extended deep STI region.

[0008] Preferably, the present invention provides a method further comprising: inverting the semiconductor substrate; and forming a nano through silicon via (nTSV) through at least a portion of the semiconductor substrate, wherein the nTSV contacts at least one BPR.

[0009] Preferably, the present invention provides a method, wherein forming the nTSV further includes thinning a semiconductor substrate to create a substrate layer, and depositing an interlevel dielectric (ILD) layer on top of the substrate layer.

[0010] Preferably, the present invention provides a method, wherein forming the nTSV further comprises forming an nTSV opening through the ILD layer and the substrate layer to expose a bottom portion of at least one BPR by a patterning process, and filling the nTSV opening with one or more conductive materials to form the nTSV.

[0011] According to another aspect of the present invention, there is provided a semiconductor structure comprising a substrate layer and a plurality of buried power wirings (BPRs) embedded in a plurality of laterally-extending deep shallow trench isolation (STI) regions within the substrate layer, the plurality of BPRs being respectively separated from the substrate layer by the plurality of laterally-extending deep STI regions.

[0012] The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0013] [Figure 1] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Diagram 2] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Diagram 3] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 4] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Diagram 5] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 6] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 7] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 8] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 9] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 10] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 11] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 12] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 13] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 14] 1A-1C are demonstrative illustrations of cross-sectional views of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to an embodiment of the present invention. [Figure 15] 1 is a demonstrative illustration of a flow chart of a method for fabricating a semiconductor structure in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] It will be understood that for simplicity and clarity, elements illustrated in the figures have not necessarily been drawn to scale. Further, where applicable, in various functional block diagrams, two connected devices and / or elements are not necessarily illustrated as being connected. In some other instances, the grouping of certain elements in the functional block diagrams is merely for illustrative purposes and may not necessarily imply that they are in or embodied in a single physical entity.

[0015] In the following detailed description and in the accompanying drawings, it should be understood that the various layers, structures, and regions shown in the drawings are both demonstrative and schematic illustrations that are not drawn to scale. In addition, for ease of illustration, one or more layers, structures, and regions of a type that are commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This is not intended to suggest that the layers, structures, and regions that are not explicitly shown are omitted from the actual semiconductor structure. Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is emphasized that the description provided herein is not intended to be inclusive of all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, have been purposefully not described herein for economy of description.

[0016] Furthermore, the same or similar reference numbers are used throughout the drawings to indicate the same or similar features, elements, or structures, and therefore, detailed descriptions of the same or similar features, elements, or structures may not be repeated for each of the drawings. It is to be understood that the terms "about" or "substantially" as used herein with respect to thickness, width, percentage, range, etc., are meant to indicate closeness or approximation, but not exactness. For example, as used herein, the terms "about" or "substantially" suggest that there is a small tolerance range, such as 1% or less from the stated amount. Similarly, the terms "on", "over", or "on Top of" as used herein to describe the positional relationship between two layers or structures are intended to be understood broadly and should not be interpreted as excluding the presence of one or more intervening layers or structures.

[0017] 1 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method for fabricating a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 1 shows a semiconductor structure 01 including a semiconductor substrate 100 and a plurality of sets of fins on top of the semiconductor substrate 100. The semiconductor substrate 100 can be a bulk silicon (Si) substrate, a bulk germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SiGeOI) substrate, or any other suitable substrate.

[0018] A plurality of sets of fins may include multiple sets of fins, and in the present application, a set of fins may include one or more fins. For example, a set of fins may be configured to form a certain type of field effect transistor (FET), such as a p-type FET or an n-type FET. Hereinafter, a set of fins may be referred to as a fin set, a set of fins configured to form a p-type FET may be referred to as a PFET fin set, and a set of fins configured to form an n-type FET may be referred to as an NFET fin set.

[0019] 1, the semiconductor structure 01 may include a first fin set 210, a second fin set 220, a third fin set 230, and a fourth fin set 240. According to one embodiment, the first fin set 210 may be an NFET fin set, the second fin set 220 may be a PFET fin set, the third fin set 230 may be a PFET fin set, and the fourth fin set 240 may be an NFET fin set. Although not shown in FIG. 1, it is further contemplated herein that there may be an NFET fin set to the left of the first fin set 210, and similarly, an NFET fin set to the right of the fourth fin set 240.

[0020] FIG. 2 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method for fabricating a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 2 shows the semiconductor structure 02 after forming a fin protection liner 310, such as an oxide liner, covering the first, second, third, and fourth fin sets 210, 220, 230, and 240. In one embodiment, the liner 310 may be a conformal liner, and the gaps between the fins in the fin sets may be filled by the liner 310. The embodiment also applies a mask layer 320, such as an organic planarization layer (OPL), to cover and protect the spaces between the fin sets for the different types of FETs, while the spaces between the fin sets for the same type of FETs are left open or uncovered. For example, the present embodiment may include applying a mask layer 320 to cover and protect the spaces between the first fin set 210 and the second fin set 220 and the spaces between the third fin set 230 and the fourth fin set 240, and the spaces between the second fin set 220 and the third fin set 230, the spaces to the left of the first fin set 210, and the spaces to the right of the fourth fin set 240 may be left uncovered. The present embodiment further includes etching the semiconductor substrate 100 to form a first recess 330. The first recess 330 may be etched to a depth of approximately 20-80 nm so that a sufficient area directly under the fin set may be reserved for the formation and functioning of transistors and is not affected by a later process of forming buried power wiring. The first recess 330 may have a first width W1.

[0021] 3 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 3 shows a semiconductor structure 03, and an embodiment of the method includes forming an additional liner 340 adjacent to a sidewall of a first recess 330, thereby protecting the sidewall of the first recess 330 from a subsequent etching process. The liner 340 may be, for example, a low-temperature silicon nitride (SiN) liner. However, the embodiment of the present invention is not limited in this respect, and liners of other materials may be used as well.

[0022] 4 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 4 shows a semiconductor structure 04, and an embodiment of the method includes performing further etching on the semiconductor substrate 100 to increase the depth and increase the width of the first recess 330 to form enlarged openings 410, 420, 430 for forming enlarged deep STI regions at a later stage. For example, performing etching can include not only etching the semiconductor substrate 100 deeply, but also increasing the width of the horizontal etching from a first width W1 of the first recess 330 to a second width W2 of the enlarged openings 410, 420, 430 (but less than the thickness of the liner 340) so that the enlarged deep STI regions are later formed, where W2 is greater than W1. In one embodiment, an anisotropic dry etch may be performed using, for example, HBr, Cl2, He, followed by an isotropic wet etch using tetramethylammonium hydroxide (TMAH) to form the openings, where the enlarged openings 410, 420, and 430 may be sigma-shaped, diamond-shaped, or hexagonal-shaped depending on the type of etchant used and the crystal orientation of the semiconductor substrate 100. The increasing width in the horizontal direction may extend beyond the liner 340 into the regions below the fin sets, such as below the second fin set 220 and the third fin set 230. The enlarged openings 410, 420, and 430 may have a second width W2 near a middle portion of the opening that is greater than a first width W1 near the top of the opening near the top of the semiconductor substrate 100.

[0023] 5 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method of fabricating a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 5 shows a semiconductor structure 05, and an embodiment of the method includes selectively removing a liner 340 covering a sidewall of a first recess 330, removing a mask layer 320 between the first fin set 210 and the second fin set 220 and between the third fin set 230 and the fourth fin set 240, and removing the liner 310 covering the first, second, third, and fourth fin sets 210, 220, 230, and 240 based on the etch selectivity of the respective materials to the etchant used. The embodiment further includes thereafter filling the enlarged openings 410, 420, and 430 with a dielectric material, such as, for example, a flowable oxide, to form enlarged deep STI regions 510, 520, and 530. The flowable oxide may be deposited through a chemical vapor deposition (CVD) process followed by a steam anneal process to fill the reentrant features of the openings. In doing so, the extended deep STI regions 510, 520, 530 may have a first width W1 near their tops and a second width W2 near their middle portions, the second width W2 being greater than the first width W1.

[0024] It is noted that in addition to flowable oxide, other suitable dielectric materials may be used as well in forming the extended deep STI regions 510, 520, 530. This dielectric material may fill the enlarged openings 410, 420, and 430, the spaces between the sidewalls of the first recess 330 that were previously covered by the liner 340, and the spaces between and above the first set of fins 210, the second set of fins 220, the third set of fins 230, and the fourth set of fins 240. An embodiment then applies a chemical mechanical polishing (CMP) process to remove excess dielectric material above the fins, for example, down to the top of the fin hardmask.

[0025] 6 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method of fabricating a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 6 shows a semiconductor structure 06, where one embodiment of the method includes forming a buried power wiring trench, filling the buried power wiring trench with metal, recessing the buried power wiring metal, overfilling the recess with a dielectric, planarizing the dielectric, and recessing the dielectric to expose the fin while the buried power wiring is still covered by the dielectric.

[0026] More specifically, a lithographic patterning process may be used to form buried power wiring trenches within the extended deep STI regions 510, 520, and 530, and then the trenches may be filled (with a thin adherent metal liner, such as TiN) with one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), or copper (Cu), or a combination thereof, to form the buried power wiring 611, 621, and 631. According to an embodiment of the invention, the trenches (for forming the buried power wiring) may be formed entirely within the extended deep STI regions 510, 520, 530, and no trenches open directly into the semiconductor substrate 100. Then, a dielectric liner, for example, a SiN liner, may be optionally formed first within the trenches before the openings are entirely filled with one or more conductive materials to form the buried power wiring. For example, liners 612, 622, 632 may be formed to line the bottom and sidewalls of the trenches, and then a metal such as W, Co, Ru, or Cu, or a combination thereof, along with a thin adherent metal liner such as TiN, may be filled into the remaining trenches to form buried power interconnects 611, 621, and 631. However, liners 612, 622, and 632 may not be necessary because buried power interconnects 611, 621, and 631 are now surrounded by the dielectric material of extended deep STI regions 510, 520, 530. After metal fill, the metal may be recessed, followed by dielectric overfill, dielectric planarization, and dielectric recession to expose the active fins for further device fabrication.

[0027] 7 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method of fabricating a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 7 shows a semiconductor structure 07, and an embodiment of the method includes forming a gate (not shown) and source / drain regions 711, forming transistors such as NFETs and PFETs using multiple fin sets after forming buried power wiring 611, 621, and 631, forming one or more multiple sets of fins, forming one or more via-BPR contacts (VBPR) 712, and forming a source / drain contact layer 720, which may be a middle-of-line (MOL) layer. One or more BEOL layers, such as back-end-of-line (BEOL) layers 730 / 740 and 750 / 760, may then be formed on top of the MOL layer 720.

[0028] 8 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method for fabricating a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 8 shows a semiconductor structure 08, where an embodiment of the method includes forming an additional BEOL layer 770 on top of a BEOL layer 760, and then substrate bonding a carrier wafer 810 to the top of the BEOL layer 770. The carrier wafer 810 can be bonded to the semiconductor structure 08 for easy handling, so that the semiconductor substrate 100 can be turned upside down for further processing from the bottom of the semiconductor substrate 100.

[0029] FIG. 9 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method of fabricating a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 9 illustrates a semiconductor structure 09 that is an inverted version of the semiconductor structure 08 illustrated in FIG. 8. After inverting the semiconductor structure 08, an embodiment of the method includes thinning the semiconductor substrate 100 by a thickness 910, such as by a grinding, CMP, or other etching process, to form a substrate layer 101. In an embodiment as illustrated in FIG. 9, the thinning process may not expose the top surfaces of the extended deep STI regions 510, 520, and 530. However, an embodiment of the present invention may include thinning the semiconductor substrate 100 to expose the top surfaces of, or even the interiors of, the extended deep STI regions 510, 520, and 530, as described in more detail below with reference to FIG. 12.

[0030] FIG. 10 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method of fabricating a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 10 shows a semiconductor structure 10, where an embodiment of the method includes depositing an interlevel dielectric (ILD) layer 1001 on top of a thinned semiconductor substrate, also referred to herein as substrate layer 101. The embodiment then includes performing lithographic patterning to form openings, such as openings 1010 and 1020, to form through silicon vias (TSVs). The TSVs may have different sizes in diameter, and in one embodiment, the diameter of the TSVs may be in the range of 15 to 120 nanometers. Such TSVs may be referred to as nanoTSVs (nTSVs). An embodiment of the present invention may generally form openings 1010 and 1020 to form TSVs, and further in one embodiment, to form nTSVs.

[0031] According to one embodiment of the invention, at least the bottom and lower portions of openings 1010 and 1020 may be formed entirely within extended deep STI regions 510 and 520. However, embodiments of the invention are not limited in this respect, and in one embodiment, sidewalls of openings 1310 and 1320 may be entirely surrounded by extended deep STI regions 510 and 520, as described in more detail below with reference to Figure 13. In Figure 10, it is assumed, by way of non-limiting example, that no openings (for TSV formation) are formed in extended deep STI region 530.

[0032] FIG. 11 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 11 shows a semiconductor structure 11, and an embodiment of the method includes forming liners 1112 and 1122 of a dielectric material, such as SiN, lining the openings 1010 and 1020. At the bottom of the openings 1010 and 1020, horizontal portions of the liner material of the liners 1112 and 1122 can then be removed by anisotropic etching to expose the bottom portions of the BPRs 611 and 621 for contact purposes. Then, a conductive material, such as W, Co, Ru, or Cu, can be used to fill the openings 1010 and 1020 to form the TSVs, in particular the nTSVs 1111 and 1121. The bottom portions of the nTSVs 1111 and 1112 are at least partially in direct contact with the bottom portions of the BPRs 612 and 622.

[0033] It should be noted that because at least the bottom portions of openings 1010 and 1020 are formed entirely within extended deep STI regions 510 and 520, the misalignment between, for example, BPR 621 and nTSV 1121 may expose a portion 1123 of the bottom portion of nTSV 1121 to extended deep STI region 520. Because extended deep STI region 520 is made of a dielectric material such as a flowable oxide, the misaligned portion 1123 of the bottom portion of nTSV 1121 is still separated from substrate layer 101.

[0034] FIG. 12 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method of manufacturing a semiconductor structure according to another embodiment of the present invention. More specifically, FIG. 12 shows the semiconductor structure 12 after the step shown in FIG. 8. More specifically, one embodiment of the method includes inverting the semiconductor structure 08 of FIG. 08 and performing a thinning process on the semiconductor structure 100 to remove a thickness 1210 that is relatively thicker than the thickness 910 shown in FIG. 9, resulting in a thinner substrate layer 101. Removing the thickness 1210 of the semiconductor substrate 100 ensures that the nTSV formed in the subsequent process to contact the BPR is entirely surrounded by the extended deep STI region embedded in the substrate layer 101.

[0035] 13 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method of fabricating a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 13 shows a semiconductor structure 13, in which an embodiment of the method includes forming an ILD layer 1301 on top of a substrate layer 101 and lithographically patterning one or more openings 1310 and 1320 for forming TSVs, such as nTSVs. Note that openings 1310 and 1320 are generally surrounded by extended deep STI regions 510 and 520 for at least the portions that are within substrate layer 101.

[0036] 14 is a demonstrative illustration of a cross-sectional view of a semiconductor structure during a process of a method for fabricating a semiconductor structure according to an embodiment of the present invention. More specifically, FIG. 14 shows a semiconductor structure 14, and an embodiment of the method includes performing metallization by filling the openings 1310 and 1320 with one or more conductive materials, such as W, Co, Ru, or Cu, or a combination thereof, to form TSVs, such as nTSVs 1410 and 1420. In contrast to the nTSVs 1111 and 1121 shown in FIG. 11, since the openings 1310 and 1320 are embedded in the substrate layer 101 but are separated and isolated from the substrate layer 101 by the extended deep STI regions 510 and 520, no dielectric liner, such as a SiN liner, is required to prevent the nTSVs 1410 and 1420 from contacting or shorting to the substrate layer 101. For example, according to an embodiment of the present invention, when nTSV 1420 is misaligned with BPR 621, as in the illustrative example shown in Figure 14, the bottom of nTSV 1420 is covered by extended deep STI region 520. Meanwhile, sidewall 1421 of nTSV 1420 is similarly completely surrounded by extended deep STI region 520, thereby preventing shorting or contact with substrate layer 101.

[0037] 15 is a demonstrative illustration of a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present invention. This embodiment includes (1510) forming a first recess in a semiconductor substrate between semiconductor device regions, such as between two NFET regions or two PFET regions, (1520) increasing the depth and width of the first recess to form an enlarged opening, and then filling the enlarged opening with a dielectric material to form an enlarged deep STI region, (1530) forming a buried power wiring in the enlarged deep STI region buried in the semiconductor substrate, (1540) forming transistors, such as NFETs and PFETs, forming mating MOL layers and BEOL layers on top of the transistors, and substrate bonding a carrier wafer on top of the BEOL layers.

[0038] An embodiment of the invention further includes (1550) flipping the semiconductor substrate upside down and thinning the thickness of the semiconductor substrate to form a substrate layer by the thinning process, in one embodiment exposing an extended deep STI region, and (1560) forming a nano-through silicon via (nTSV) opening in the extended deep STI region, with at least a bottom portion of the opening being surrounded by the extended deep STI region. This nTSV formation process may be performed by first depositing an interlevel dielectric (ILD) layer on top of the substrate layer, planarizing the ILD layer, and patterning the nTSV opening through a lithographic patterning and etching process. In one embodiment, the sidewalls of the nTSV opening are not completely surrounded by the extended deep STI region, and the embodiment may include (1570) lining the nTSV opening with a dielectric liner. An embodiment of the invention may further include (1580) metallizing the nTSV opening with a conductive material to contact a buried power interconnect.

[0039] It should be understood that the exemplary methods discussed herein for making or fabricating strained superlattices can be readily incorporated into other semiconductor process flows, semiconductor devices, and integrated circuits having various analog and digital or mixed signal circuits. In particular, integrated circuit dies can be fabricated with various devices such as field effect transistors, bipolar transistors, metal oxide semiconductor transistors, diodes, capacitors, inductors, and the like. Integrated circuits according to the present invention can be used in applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for implementing the present invention can include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., mobile phones), solid state media storage devices, functional circuits, and the like. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the present invention provided herein, one skilled in the art will be able to conceive other implementations and applications of the techniques of the present invention.

[0040] Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various other changes and modifications may be made by those skilled in the art without departing from the scope of the appended claims.

[0041] It should be understood that the various layers, structures, or regions described above, or combinations thereof, are not necessarily drawn to scale. Additionally, for ease of illustration, one or more layers, structures, and regions of the type commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure or drawing. This is not intended to imply that the layers, structures, or regions not explicitly shown have been omitted from the actual semiconductor structure.

[0042] It should be further understood that the embodiments discussed herein are not limited to the specific processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is emphasized that the descriptions provided herein are not intended to be inclusive of all of the processing steps that may be used to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, have been purposely not described herein for economy of description.

[0043] The terms "about" or "substantially" as used herein with respect to thicknesses, widths, percentages, ranges, etc., are meant to indicate closeness or approximation, but not exactness. For example, as used herein, the terms "about" or "substantially" suggest that a small tolerance exists, such as 1% or less from the recited amount, by way of example only. Also, in the figures, the illustrated scale of one layer, structure, or region, or combination thereof, relative to another layer, structure, or region, or combination thereof, is not necessarily intended to represent the actual scale.

[0044] Semiconductor devices and methods for forming same according to the techniques described above may be used in a variety of applications, hardware, or electronic systems or combinations thereof, including, but not limited to, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., mobile phones and smart phones), solid state media storage devices, functional circuits, etc. Given the teachings provided herein, those skilled in the art will be able to conceive other implementations and applications of embodiments of the present invention.

[0045] In some embodiments, the techniques described above are used in connection with the manufacture of semiconductor integrated circuit devices, illustratively including, by way of non-limiting example, CMOS devices, MOSFET devices, or FinFET devices or combinations thereof, or other types of semiconductor integrated circuit devices incorporating or otherwise utilizing CMOS, MOSFET, or FinFET technology, or both.

[0046] Thus, at least a portion of one or more semiconductor structures described herein may be embodied in an integrated circuit. The resulting integrated circuit chips may be distributed by manufacturers in raw wafer form (i.e., a single wafer having multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips may be implemented in a single-chip package (such as a plastic carrier or other higher level carrier having leads that are secured to a motherboard), or in a multi-chip package (e.g., a ceramic carrier having either surface interconnects or embedded interconnects or both). In either case, the chips may be integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of an intermediate product such as a motherboard, or a final product. The final product may be any product that includes the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products having displays, keyboards or other input devices, and a central processor.

[0047] Although the description of various embodiments of the present invention has been presented for illustrative purposes, the description is not intended to be exhaustive or limited to the disclosed embodiments. Many changes and modifications will become apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable other skilled in the art to understand the embodiments disclosed herein.

[0048] While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will occur to those skilled in the art. Such modifications, variations, or alternative embodiments or combinations thereof can be made without departing from the scope of the invention, and all are thereby considered to be within the scope of the invention. It is therefore to be understood that the appended claims are intended to cover all such modifications and variations that are within the scope of the invention.

Claims

1. A substrate layer; a buried power interconnect (BPR) buried in an extended deep shallow trench isolation (STI) region within the substrate layer; Equipped with The BPR is separated from the substrate layer by the extended deep STI region.

2. 2. The semiconductor structure of claim 1 , further comprising a nano through silicon via (nTSV), a bottom portion of said nTSV contacting a bottom portion of said BPR, and a bottom portion of said nTSV being completely surrounded by said extended deep STI region.

3. 3. The semiconductor structure of claim 2 wherein said nTSV is embedded in said substrate layer, sidewalls of said nTSV being completely surrounded by and separated from said substrate layer by said extended deep STI region.

4. 3. The semiconductor structure of claim 2 wherein said nTSV comprises a conductive material in direct contact with said extended deep STI region at a sidewall of said nTSV.

5. 3. The semiconductor structure of claim 2 , wherein said nTSV is misaligned with said BPR, a first portion of said bottom portion of said nTSV contacts said bottom portion of said BPR, and a second portion of said bottom portion of said nTSV is covered by said extended deep STI region.

6. 2. The semiconductor structure of claim 1 , wherein said extended deep STI region has a first width near a top of said extended deep STI region and a second width near a middle portion of said extended deep STI region, said second width being greater than said first width.

7. 1. A method for forming a semiconductor structure, comprising: Providing a semiconductor substrate; forming a first recess in the semiconductor substrate; increasing a depth and laterally increasing a width of the first recess to form an extended deep STI region; filling the extended deep STI region with a dielectric material; forming at least one buried power interconnect (BPR) within the dielectric material in the extended deep STI region; A method comprising:

8. 8. The method of claim 7, further comprising: inverting the semiconductor substrate; and forming a nano through silicon via (nTSV) through at least a portion of the semiconductor substrate, the nTSV contacting the at least one BPR.

9. 10. The method of claim 8, wherein forming the nTSV further comprises thinning the semiconductor substrate to create a substrate layer; and depositing an interlevel dielectric (ILD) layer on top of the substrate layer.

10. 10. The method of claim 9, wherein forming the nTSV further comprises forming an nTSV opening through the ILD layer and the substrate layer to expose a bottom portion of the at least one BPR by a patterning process, and filling the nTSV opening with one or more conductive materials to form the nTSV.

11. 8. The method of claim 7, wherein laterally increasing a width of the first recess comprises wet etching the first recess to form an extended deep STI region, the extended deep STI region having a sigma or hexagonal shape and having a first width near a top of the extended deep STI region and a second width near a middle portion of the extended deep STI region, the second width being greater than the first width.

12. 8. The method of claim 7, further comprising forming a plurality of fin sets on an upper portion of the semiconductor substrate, the fin set including a fin set for a p-type field effect transistor (FET) and a fin set for an n-type FET, prior to forming the first recess in the semiconductor substrate, the first recess being formed between two fin sets for the same type of FET.

13. 13. The method of claim 12, further comprising forming the p-type FET and the n-type FET, and forming a via-BPR contact to connect the at least one BPR to at least one of the p-type FET and the n-type FET.

14. 14. The method of claim 13, further comprising forming a middle-of-the-line (MOL) layer over the pFET and nFET, forming a back-end-of-the-line (BEOL) layer over the MOL layer, and substrate bonding a carrier wafer on top of the BEOL layer.

15. A substrate layer; a plurality of buried power interconnects (BPRs) embedded within a plurality of laterally-extending deep shallow trench isolation (STI) regions within the substrate layer, the plurality of BPRs being respectively isolated from the substrate layer by the plurality of laterally-extending deep STI regions; 1. A semiconductor structure comprising:

16. 16. The semiconductor structure of claim 15, further comprising a plurality of through silicon vias (TSVs) formed in said substrate layer, bottom portions of said TSVs contacting a bottom portion of said BPR, said bottom portions of said TSVs being completely surrounded by said laterally extended deep STI region.

17. 17. The semiconductor structure of claim 16, wherein said plurality of TSVs are embedded in said substrate layer, sidewalls of said plurality of TSVs being completely surrounded by and separated from said substrate layer by said laterally-extending deep STI regions.

18. 20. The semiconductor structure of claim 17, wherein said laterally-extending deep STI region comprises a flowable oxide, said plurality of TSVs comprises one or more metal elements of W, Co, Ru, and Cu, and said flowable oxide of said laterally-extending deep STI region directly contacts said metal elements of said plurality of TSVs at sidewalls of said laterally-extending deep STI region.

19. 17. The semiconductor structure of claim 16, wherein at least one of said TSVs is misaligned with at least one of said BPRs, a first portion of a bottom portion of said at least one of said TSVs contacts a bottom portion of said at least one of said BPRs, and a second portion of said bottom portion of said at least one of said TSVs is covered by one of said laterally extended deep STI regions.

20. 16. The semiconductor structure of claim 15, wherein said laterally expanded deep STI region has a first width near a top of said laterally expanded deep STI region and a second width near a middle portion of said laterally expanded deep STI region, said second width being greater than said first width.

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