Semiconductor chip with highly reliable patterned metallization and method for manufacturing same - Patents.com

Abstract

The present disclosure relates to a semiconductor chip having an aluminum layer with a texture of at least a portion of a surface that receives an additional deposit of either copper or epoxy resin, the texture forming a peak on the portion of the surface that occupies 20% to 80% of the portion of the surface.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This description relates to a top interconnection for an electronic device and a method for fabricating the top interconnection. [Background technology]

[0002] Interconnection technologies for power electronic devices typically include so-called "top interconnects" that function to electrically connect the semiconductor device to a metallic leadframe.

[0003] State of the art interconnect technology for the top interconnect may include aluminum based interconnects, and may comprise the following, as presented in the example of FIG. A metallization layer of aluminum (Al) or its alloys (with less than 5% Cu and / or less than 5% Si), usually between 2 μm and 10 μm thick. This layer is generally delivered together with the chip by the semiconductor chip manufacturer and is deposited on areas of the top surface of the semiconductor chip. The current state-of-the-art processes for selectively depositing a metal layer on some areas of a silicon chip are photolithographic processes based on subtractive or additive transfer. In the subtractive transfer process: First, a continuous thin film of metal of uniform thickness is deposited using a deposition technique, usually a physical vapor deposition technique such as sputtering or evaporation. · An etch resist layer is then deposited over the metal surface except where no metal layer is desired. This is usually done using a photolithography process. Finally, the exposed metal surfaces are removed using wet etching and the etch resist layer is stripped. In the additive transfer process: First, one or two etch resist layers are selectively deposited on surfaces where no metal layer is required. A uniform layer of metal is then deposited over both the etch resist layer and the final metallization surface. Finally, the etch resist layer is removed, resulting in the metal layer being peeled off from the unwanted surfaces. o Aluminum wire (or ribbon) connected between the aluminum metallization and the lead frame. This interconnection is usually made by the power module manufacturer during assembly of the power module. The current state of the art process for connecting aluminum wire and forming a bond with the aluminum metallization is the so-called "ultrasonic bonding" process, where the wire is attached to the metallization using ultrasonic energy and pressure to promote deformation and interdiffusion of the metallization and wire in the solid state (not melted). It is noted that a more reliable bond is usually formed when in contact with a flatter aluminum surface.

[0004] Aluminum-based interconnects are the standard technology currently used in the industry. However, it would be beneficial to transition from aluminum to copper interconnect technology for several reasons: Copper wire bonding is seen as the next generation top interconnect packaging solution that offers the opportunity to achieve reliable bonds at higher maximum operating temperatures. Several manufacturers have demonstrated that Cu-based interconnects offer significantly improved reliability (typically a 10x increase in interconnect life) compared to aluminum-based interconnects due to more stable wire bonds; o Better match with higher bandgap chip materials (SiC and GaN) that can operate at higher temperatures; o It has a higher current carrying capacity and is therefore compatible with high current density devices (Si-based devices or high bandgap semiconductor devices); Higher short circuit protection during turn-off events in high frequency Pulse Width Modulation (PWM) operation. Compared to traditional aluminum-based metallization, the higher thermal capacity of Cu, combined with the thicker metallization thickness, can provide a higher thermal buffer to prevent chip overheating during high frequency thermal events, thus enhancing the short circuit reliability of the package. o It is compatible with standard PCB technology, thus allowing the incorporation of power electronic dies into PCB boards with the added benefits of lower parasitic capacitance and lower thermal impedance.

[0005] On the other hand, a state-of-the-art copper-based interconnect, in a first embodiment as presented in the example of FIG. o A diffusion barrier that prevents copper from diffusing into the semiconductor device and reacting with and altering its electronic performance. This diffusion barrier can be a thin layer of tantalum (Ta) or tantalum nitride (TaN), titanium (Ti) or titanium nitride (TiN) W deposited by sputtering or chemical vapor deposition. The diffusion barrier layer is usually deposited by the chip manufacturer. These diffusion barrier layers do not exist in aluminum and therefore require non-standard special processes performed by the chip manufacturer. Currently, such chips are not widely available to module manufacturers. o A copper metallization layer, usually with a thickness greater than 10 μm, deposited by an electrolytic process (electroplating). o Thick (>250μm) copper wires connected to the metallization layers using ultrasonic wedge bonding.

[0006] Other state of the art copper based interconnects, as shown in the example of FIG. o A standard aluminium metallisation layer, deposited for example by sputtering, so that in this case standard chips can be used by the module manufacturer; o Ag sintered layer deposited by pressure-based or pressure-less process between chip and copper layer; ○ Copper foil attached to the Ag sintered layer during the sintering process; o Thick (>250μm) copper wires connected to the metallization layers using ultrasonic wedge bonding.

[0007] Therefore, from the above description of the current state of the art, it is clear that copper wire bonding technology is superior to aluminum wire bonding technology in several aspects. However, both current state of the art solutions have the following problems: In the solution shown in Figure 2, the deposition of a thin diffusion barrier on top of the semiconductor chip is a non-standard process that is not currently widely used in the industry, and such chips with copper metallization are not widely available to power module manufacturers. In the solution shown in Figure 2, the deposition of a thin diffusion barrier on top of the semiconductor chip is an additional manufacturing step that requires a lot of cost, and this process is very critical because the diffusion barrier requires high cleanliness and homogeneity to function effectively. - In the solution shown in Fig. 3, where standard Al-metallization is used in the copper-based top interconnect, failure of the aluminum layer and therefore delamination between the semiconductor and the Ag sintered layer limits the module's lifespan. This failure occurs due to crack propagation in the aluminum top metallization layer. This is shown in Fig. 3 between the Si IGBT layer and the Ag sintered layer in the top layer. Moreover, in the solution shown in Figure 3, an Ag layer is used to connect the aluminum metallization with the copper layer. The choice of the Ag layer is primarily driven by the reliability of Ag sintered interconnects and the availability of this technology. However, the introduction of this connection adds a process step that usually requires a heat treatment step that is expensive, time and energy consuming in the product manufacturing.

[0008] Therefore, to overcome the above mentioned limitations, it is desirable to directly connect a copper layer onto an aluminum layer. However, it is difficult to create a reliable Cu-Al interface because the adhesive strength of Cu on Al can be insufficient. Adhesive failure of Al-Cu bonds is due to several factors that can be classified as either external or internal: External factors: Thermomechanical stresses generated at the Al-Cu interface are the driving force for adhesive failure of the bond. Temperature changes during product manufacturing and use generate stresses at the joints due to different thermal expansion coefficients of materials present in the layer stack assembly. In semiconductor interconnect material layer geometries where the metallization layers are thin compared to the semiconductor die thickness, the stresses are strongest at the edge of the die and are mostly shear in nature (commonly referred to as "Mode II loading"); Internal factors: · Native oxide layer: Both aluminum and copper easily form an oxide layer when exposed to air. This can prevent the formation of strong metallic bonds on the atomic scale, resulting in a significant decrease in the adhesive strength. For this reason, for example, during the production of Al-Cu joints by chemical or electrochemical methods (electroless or electroplating), the oxide layer is often removed and the surface is protected from further oxidation by the deposition of a nanometer-scale layer (the so-called "passivation layer") or is covered by a barrier layer, usually less than 2 μm thick. Reaction between Al and Cu during high temperature exposure. Cu and Al form intermetallic phases that are mechanically weaker and more susceptible to oxidation and corrosion. In addition, the reaction is accompanied by volume changes that can generate cracks even in the absence of thermomechanical stresses, or can generate voids ("Kirkendall voiding"). For this reason, a thin non-reactive interface coating layer (typically less than 2 μm) is also beneficial.

[0009] Despite the use of an interface coating or passivation layer, the adhesion strength between Al and Cu may not be sufficient to provide a bond with reliability at least comparable to the current state of the art. The first problem addressed by the present disclosure is thus the insufficient adhesion strength between Al and Cu, which prevents the creation of reliable Al-Cu bonds.

[0010] Moreover, in conventional power modules, the power semiconductor chips are usually protected from the environment by an encapsulant, which is usually poured in as a heated liquid at the end of the packaging process and further solidified after cooling. The functions of the encapsulant are as follows: -Protects the chip and its interconnects from dust, oxidation and corrosion. -Prevents electrical breakdown between electrically connected elements separated by high voltage differences.

[0011] Therefore, the required properties of the encapsulant are high dielectric value and low moisture absorption and diffusion rate. In addition, the thermomechanical properties of these materials should be such that no additional thermomechanical stresses are applied to critical packaging elements such as the top aluminum interconnects.

[0012] State-of-the-art encapsulants can be divided into: - Silicone gel type materials, which generally provide a sufficiently high breakdown voltage and can be used under a wide temperature range (generally -50℃~200℃). These materials have flexible mechanical properties, so that the effects of thermo-mechanical stresses on the assembly can be neglected; -Epoxy-based potting materials that generally offer better insulation values ​​than silicon gel materials. Therefore, these resins are seen as the next generation insulation materials for high voltage power modules. However, due to their higher elastic limit and high thermal expansion coefficient, stresses can be generated at the interface between the semiconductor die and the encapsulation material.

[0013] It may be desirable to use epoxy-based encapsulants to protect electronic assemblies against dust, corrosion, and moisture, as they may be more suitable than silicone gels in harsh environments and high voltage applications. However, their higher elastic strength and hardness, combined with a high coefficient of thermal expansion, may create stresses at the interface between the semiconductor device and the epoxy, which may result in delamination due to adhesive failure.

[0014] This second problem, related to insufficient adhesive strength between Al and epoxy-based encapsulation materials, prevents the creation of a reliable bond between the metallization and the epoxy. Failure can occur during processing or product use due to (cyclical) temperature exposure (e.g., during solder reflow, power cycling) and when thermal (or hygrothermal) stresses overwhelm the adhesive strength of the bond. The incorporation of vapor pressure into the initially small interface pores can increase the interface stresses, which can result in the failure of the encapsulation material (the "pop-corn" effect). The final result of the presence of a low-insulating gas layer can be the destruction of the power electronic system through electrical breakdown at high voltages. Summary of the Invention [Problem to be solved by the invention]

[0015] The present description aims to improve the situation caused by at least the two problems presented above. [Means for solving the problem]

[0016] For that purpose, the present description proposes a semiconductor chip having an aluminum layer, which has a texture of at least a portion of a surface that receives an additional deposit, said texture forming a peak on said portion of said surface occupying 20% ​​to 80% of said portion of said surface.

[0017] As presented in the following embodiment examples, such a textured structure forms an interlocking structure with the additional stack, and the shear bond strength between the aluminum layer and the additional stack assembled thereto is increased, thereby improving the reliability of the assembly.

[0018] In one embodiment, the aluminum layer is a metallization layer having an average thickness T typically between 2 μm and 15 μm.

[0019] In one embodiment, the aluminum layer has an average thickness T and the texture has a length L that represents the average distance between first adjacent peaks of the texture and is related to said average thickness T by L<10*T.

[0020] In one embodiment, the aluminum layer has an average thickness T and the texture exhibits an average depth D of said peaks and has a depth D related to said average thickness T by D>0.2*T.

[0021] In one embodiment, the peaks may form a periodic sinusoidal shape in at least one profile section of the texture structure (as shown in FIG. 7, commented below).

[0022] In one embodiment, the peaks have bulges on their tops (as shown in FIG. 9, commented below).

[0023] The aforementioned semiconductor chip can be, for example, a power semiconductor chip.

[0024] In at least this type of application, the additional deposit may include copper and may include an epoxy resin.

[0025] Furthermore, the surface of the aluminum layer may comprise at least one additional portion that is separate from the portion comprising the texture and that may be configured for electrical connection of the aluminum layer (as shown in FIG. 10, commented on below).

[0026] The present disclosure also provides a method for manufacturing a semiconductor chip having an aluminum layer, comprising: depositing said aluminum layer; forming a texturing on at least a portion of a top surface of the aluminum layer; forming an additional deposit on at least the portion; and Including, The texture is directed to a method of forming a peak on the portion that occupies 20% to 80% of the portion.

[0027] In one embodiment, forming the tissue structure comprises: spatially selectively depositing a mask over the portion, the mask avoiding etching effects on an aluminum layer underlying the mask; Etching the portion; and Removing the mask; and / or in combination or alternatively to the above: spatially selectively depositing a mask over the portion, the mask avoiding deposition of aluminum thereon; depositing aluminum over the portion; Removing the mask; may include.

[0028] Alternatively or in combination, forming the texture may include using a machine tool to deform a top surface of the portion to create the peaks.

[0029] In one embodiment, forming the textured structure can further include applying a press tool to the tops of the peaks to form bulges thereon.

[0030] Further details are provided in the remainder of this specification with reference to the accompanying drawings. [Brief description of the drawings]

[0031] [Figure 1] FIG. 1 shows an aluminum-based upper interconnection of a semiconductor chip according to the current state of the art. [Diagram 2] FIG. 1 shows a first type of copper-based top interconnect (Solution "A") according to the current state of the art. [Diagram 3] FIG. 2 shows a second type of copper-based top interconnect (solution "B") according to the current state of the art. [Figure 4] FIG. 1 illustrates the problem arising due to insufficient adhesive strength at the Cu-Al interface (top) and the proposed solution for the mixed cohesive / adhesive failure mode (bottom) in an example embodiment. [Diagram 5] FIG. 1 illustrates the problem arising due to insufficient adhesive strength of Cu-encapsulated polymer (top) and the proposed solution for mixed cohesive / adhesive failure mode (bottom) in an example embodiment. [Figure 6] More specifically, a cross-sectional view of an example of a structured aluminum metallization having columnar structures with stress risers. [Figure 7] More specifically, FIG. 1 is a cross-sectional view of an example of a structured aluminum metallization having a periodic sinusoidal shape in at least one direction. [Figure 8] FIG. 1 is a top view of an example of a structured aluminum metallization showing the percentage area where the black regions are exposed to structuring. [Figure 9] 1A is a diagram showing an example of an overhang structure formed by applying pressure in the direction of vector P. FIG. [Figure 10] FIG. 2 shows an example of a portion of an aluminum layer surface that is removed to create electrical contacts connecting the aluminum layers. [Figure 11] FIG. 2 shows a comparison between a semiconductor chip (Si chip or SiC chip) with an aluminum layer according to the prior art (left) and the same semiconductor chip with a structured aluminum layer according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] This embodiment makes it possible to avoid the above-mentioned problem of insufficient adhesion strength at the Cu-Al interface by providing a particular geometry of a non-planar structured interface between the Al metallization and the Cu metallization.

[0033] In the following, "Al-Cu interface" refers to the joint between the aluminum metallization of the semiconductor die and the copper layer fixed to this metallization. Although additional thin layers may be present at the interface between the Al and Cu layers (e.g., for the purpose of oxide removal during manufacture or corrosion / oxidation prevention during product use), in the following these layers are considered to be part of the joint since their thickness is small compared to the thickness of the aluminum or copper metallization (usually less than 2 μm for each layer).

[0034] In addition, this embodiment makes it possible to avoid the problem of insufficient adhesive strength of the Al-potting interface mentioned above by using a non-flat structured aluminum metallization surface.

[0035] The effect of employing a structured metallization surface is to create an interlocking structure between the aluminum metallization and the material (whether that be below) assembled to the aluminum metallization. - Copper layers used for high reliability copper-based interconnects, or Polymers used as encapsulation materials (e.g. epoxy-based resins).

[0036] The interlocking structure is particularly effective in avoiding adhesive failure in cases where shear stresses dominate at or near the interface, which is typically the case at semiconductor die packaging material interfaces.More reliable bonds are created when using structured interfaces because the strength of the interface is increased due to the presence of the interlocking structure, which allows additional plastic or viscoelastic energy dissipation on the bulk of the material away from the interface, as shown in Figure 4 (for a Cu-Al interface embodiment) and Figure 5 (for a Cu-encapsulating polymer embodiment) presented below. - In the absence of an interlocking structure (top of Fig. 4), the Al-Cu interface or the Al-polymer interface undergoes adhesive failure due to insufficient adhesive strength of the assembly: the crack propagates mostly at the interface. - When an interlocking structure is present (Fig. 5, bottom), the interface fails in a mixed adhesive / cohesive mode: the crack propagates both at the interface and in the bulk of the assembly, thereby producing a more reliable bond since the physical bond is stronger in the bulk than at the interface.

[0037] The same effect can be seen in FIG. 5 for the Al-polymer encapsulation.

[0038] In that case, it can be noted that the texturing of the aluminum layer can be implemented in some situations, such as when a copper layer or a resin layer is deposited adjacent to the structured surface of the aluminum layer, although of course such texturing can also be implemented in other situations (e.g. when depositing a silver layer).

[0039] The present disclosure can therefore be directed to a semiconductor chip having an aluminum layer, the layer being provided with a surface texture for receiving an additional deposit, whether a resin layer or a copper layer etc. More particularly, the texture forms a peak on the surface, occupying 20% ​​to 80% of the surface.

[0040] In other words, the exposed area fraction A, which indicates the area formed by higher spots (or "peaks") of the structure, is preferably in the range of 20% < A < 80%, more preferably in the range of 30% < A < 70%, and still more preferably in the range of 40% < A < 60%, that is, for example, about 50%.

[0041] More specifically, the semiconductor chip described above can be a power semiconductor chip.

[0042] More specifically, the aluminum layer can be a metallization layer.

[0043] In an example of an embodiment where the aluminum layer has an average thickness T, the structure can have a length L that indicates the average distance between neighboring peaks of the structure related to the average layer thickness by L < 10 * T.

[0044] In an example of an embodiment where the aluminum layer has an average thickness T, the structure can have a depth D that indicates the average depth of the structure, and the characteristic depth is related to the average metallization thickness by D > 0.2 * T.

[0045] Therefore, the shear adhesion strength between the metallization and the material assembled to the metallization is increased, thereby improving the reliability of the assembly.

[0046] Examples are shown below.

[0047] By "aluminum" hereinafter is meant aluminum material in which small amounts of impurities have been dissolved or precipitated. For example, aluminum can have a purity of 6N (99.9999% pure) or 3N (99.9%), with the remaining elements intentionally or unintentionally present in the material to adjust its mechanical properties, electrical properties, or its properties against electromigration. In another example, impurities are intentionally added to the material to improve its mechanical properties, electrical properties, or its properties against electromigration. For example, less than 1% silicon and / or less than 1% copper are added to increase the hardness or strength of the material and / or to reduce electromigration.

[0048] In one example embodiment, the aforementioned "at least a portion of the metallization" is the entire surface of the metallization. In the following embodiments where some portions of the metallization layer are to be connected (e.g., through wire bonds), such portions may be unstructured.

[0049] In one example embodiment, the structure has the following characteristics: the average metallization thickness T is in the range from 2 μm to 15 μm, preferably in the range from 3 μm to 8 μm, for example 5 μm; the characteristic length L is of the same order of magnitude as the metallization thickness, for example L=3*T, or preferably L=2*T, or for example L=T, for example L=5 μm. The characteristic depth D is a large portion of the metallization thickness, for example more than 20% of the metallization thickness, preferably more than 50% of the metallization thickness, for example 3 μm. The area proportion A is between 30% and 70%, or between 40% and 60%, or even 50%.

[0050] In this example, if the aluminum metallization is subsequently attached to a nearby material that forms an interface with insufficient adhesive strength, the shear stress applied to this interface will be distributed toward the bulk of the aluminum metallization and the bulk of the nearby material, thereby advantageously reducing the risk of adhesive failure between these two materials.

[0051] Dimension D may be repeatable or may exhibit significant variation across the metallization surface depending on the manufacturing process. For example, dimension D may vary regularly or randomly between 5% of the metallization thickness and 50% of the metallization thickness.

[0052] Exemplary structures may consist of discrete hills arranged in a square or ridge pattern (examples of Figures 6 and 7), may also consist of hills arranged in a hexagonal pattern, or in any periodic arrangement. Alternatively, the structures may consist of isolated hills or ridges separated by a varying distance L, i.e., randomly distributed, e.g., the structures may not be periodic. For example, the distance L may vary between 0.1D and 10D, preferably between 0.5D and 2D, where D is the average depth.

[0053] Structural characterization (D, L and T measurements) can be performed using the following measurement tools and methods: - profilometers for measuring the height of a profile (2D) or a surface (3D), such as mechanical or optical profilometers, and - Cross-sectional surveying through the semiconductor die and metallization using standard microsection sample preparation techniques (cutting, mirror polishing) and subsequent observation using a microscope, possibly combined with image analysis tools to extract the profile of the semiconductor-metallization interface.

[0054] The profiles should be analyzed using the following data processing methods. -Measurement of T, where T is the distance between the semiconductor-aluminum interface and the average height of the aluminum metallization using microsection microscope images. For regular surface structures where L and D can be determined unambiguously, measurements can be made directly from the surface profile without the need for statistical analysis tools. -For structures with large statistical variations in structure size, The measurement of D can be done using the mean arithmetic average of the profile: average roughness Ra (for 2D measurements) or Sa (for 3D measurements) using the formula D=2*Ra or D=2*Sa respectively (ISO4287:1997). The length L can be measured using the average width parameters PSm, RSm, WSm (ISO 4287:1997). The areal proportion A can be measured using the Rpk parameter according to ISO 13565-2 or by the Spk parameter according to ISO 13565-3. The values ​​of the Rpk and Spk parameters are determined at the areal material ratio value of A.

[0055] In one embodiment, the structure is protected from stress risers. In other words, its shape is chosen to minimize the presence of stress risers. By stress riser, we mean the presence of sharp corners in the structure that act as centers of stress concentration in the metallization and the materials deposited thereon. The stress σ at a sharp corner of radius R is R It is generally accepted that is inversely proportional to the square root of the radius R and is related to the remote stress intensity σ by the following equation:

number

[0056] Thus, for example, referring to the right hand portion of Figure 6, the stress near the corners of radii R1 and R2 increases as R1 and R2 decrease, and cohesive failure may then initiate at these points. Thus, in an advantageous embodiment, one may choose to maximize the radius of curvature of the structure, as presented in the example shown in Figure 7, where the maximum radius is close to D. For example, the cross section of the structure preferably provides an interface that approximates a sine wave with period 2D and amplitude D.

[0057] A profile taken along a single direction can have a periodic shape (as shown in the right-hand portion of FIG. 8 ), or further, a profile taken along two perpendicular directions of the structured surface can have periodic hill shapes surrounded by valley shapes (as shown in the left-hand portion of FIG. 8 ).

[0058] The present description can also be directed to a method for structuring an aluminum metallization layer, which method comprises, for example: - patterning the wafer using standard metallization techniques using subtractive or additive transfer processes, with a view to obtaining, at defined locations on the semiconductor chip, a continuous layer of aluminum with a thickness T+D; and -Selectively removing thickness in two directions in defined areas of an aluminum layer using a subtractive transfer process.

[0059] Advantageously, therefore, this structure can be added to a standard semiconductor chip having standard aluminum metallization, and module manufacturers can easily implement the process for any standard aluminum metallization.

[0060] The subtractive transfer process may include a lithography process and may, for example, follow the following steps. First, a continuous thin film of uniform thickness of metal is deposited using a deposition method such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or (electro) plating. o An etch resist layer is then deposited over the metal surface except where no metal layer is desired, this is usually done by using a photolithography process. o Finally, the exposed metal surfaces are removed using a wet etch and the etch resist layer is stripped.

[0061] PVD processes can include evaporation and RF sputtering processes.

[0062] Instead of etching, mechanical processes such as grinding, sandblasting, chemically aided mechanical polishing (CMP), etc. using large (i.e. larger than the usual current state of the art) particle sizes can be performed to obtain the non-rectangular structures presented in FIG. 6 or FIG. 7.

[0063] Another alternative form of etching is a heterogeneous chemical process, such as heterogeneous etching due to the randomness of the etching process (such as a pitting process).

[0064] Alternatively or in combination with the above, a plasma etching process can be used to remove some of the aluminum.

[0065] Alternatively or in combination with the above, aluminum can be added using a screen printing process only to the elevated locations of the structure, and the structure can then be exposed to a heat treatment to provide a structure with mechanical strength comparable to that of bulk aluminum.

[0066] More generally, an aluminum metallization layer can be structured by selectively adding a thickness of aluminum in defined areas of an initially deposited aluminum layer (usually using an additive transfer process). An example of an additive transfer process can consist of: Selectively depositing at least one etch resist layer on surfaces on which the aluminum layer is not to be deposited. A uniform layer of aluminum is then deposited over both the etch resist layer and the final metallization surface. Finally, the etch resist layer is removed, resulting in the aluminum layer being peeled off from the unwanted surfaces.

[0067] An additional step of applying pressure to the upper exposed areas of the structured aluminum layer can be performed to plastically deform the structures and form nubs with negative slope at their tops.

[0068] This embodiment can advantageously improve the tensile strength and shear bond strength of the structure.

[0069] An example is shown in Figure 9, which can consist of taking a structure with square or wave-shaped ridges as presented in Figures 6 or 7, bringing a pressure forming tool into contact with the top of the exposed areas, and then applying pressure using a flat tool to plastically deform the final overhang structure. The peaks of the structure will eventually exhibit a bulge shape at their tops as shown in Figure 9.

[0070] In one example, the tool can be controlled in a displacement mode to ensure that the structure is only partially deformed and to avoid forming a flat metallization or creating closed porosity in the metallization. For example, the tool displacement can be limited by the presence of a stopper (shown on the side of FIG. 9).

[0071] In addition to improving adhesion strength in shear mode, such an overhang structure can improve adhesion strength in tensile mode when the metallization contacts a second material, i.e., when force is applied in a direction outward from the plane of the metallization surface.

[0072] Only parts of the metallization layer can be structured, for example no structure should be applied to the areas of the layer where wires are to be connected.

[0073] Thus, advantageously, the metallization improves the reliability of the interconnections with adjacent layers, without compromising the reliability of the interconnections with the wires.

[0074] In Figure 10 below, the area where the aluminum wire bonds will be connected (e.g., using an ultrasonic bonding process) is flat and unstructured. Higher wire bond reliability is generally associated with bonding on smooth surfaces, so if it is known in advance that the wires will be attached using an ultrasonic bonding process, it is beneficial to exclude structures in areas slightly larger than the wire bond surface, for example areas of dimensions 1000 μm x 2000 μm or 400 μm x 1000 μm.

[0075] The present disclosure is also directed to a power electronic module that includes one or several semiconductor chips, where at least one of the semiconductor chip(s) is encapsulated using an epoxy-based encapsulant.

[0076] Therefore, this structure improves the bonding between the semiconductor chip and the epoxy encapsulant, and the reliability of the bond between the aluminum and the epoxy compound is improved.

[0077] For example, epoxy-based encapsulants have good wetting properties with aluminum metallization, and during the encapsulation process, the epoxy-based encapsulant forms a conformal interface with the aluminum metallization structure by infiltrating into the structure. The wetting properties of the encapsulant in association with the aluminum metallization structure can be measured using a sessile drop technique, where an epoxy resin is placed in a liquid state in contact with the aluminum metallization, and parameters such as the Young angle are measured in the liquid state or after solidification as less than 90 degrees, preferably less than 60 degrees, and preferably less than 30 degrees. The Young angle is typically defined as the angle formed by the epoxy-gas surface and the metallization-epoxy surface.

[0078] An epoxy-based encapsulant is a material in which a large volume fraction of the material, e.g., more than 20% or more than 50%, is made up of epoxy resin, and the other components of the material are additive particles that give the material suitable properties, such as a coefficient of thermal expansion in the range 5 ppm / K to 30 ppm / K, or a thermal conductivity better than that of pure epoxy resin. For example, aluminum oxide particles are mixed with epoxy resin in a volume fraction of more than 40% or more than 70%.

[0079] During the encapsulation process, a pressure difference can be applied between the liquid encapsulant of the power module and one or several cavities, each of which is - a substrate for the semiconductor chip (usually consisting of one or several ceramic insulating plates combined with possibly metallic connecting leads fixed to copper plates); a case or lid made of a hard polymeric material, possibly having power and control terminals for connecting the semiconductor chip to external circuitry; A volume is formed between the

[0080] Therefore, the epoxy-based encapsulant can fill the structure better, the process yield is higher, and the reliability of the bond between the aluminum and the epoxy compound is improved.

[0081] When the challenge of creating a conformal interface between aluminum metallization and epoxy encapsulant cannot be overcome solely by using an epoxy resin with good wetting properties (e.g., due to unacceptably high viscosity and therefore unacceptably long processing times), the application of a pressure differential can be used to create an essentially pore-free and gas-free aluminum-epoxy interface.

[0082] The volume to be encapsulated may be essentially sealed except for an epoxy resin inlet and a vent hole to allow gas to escape during processing. An epoxy encapsulant is filled into said volume and a pressure differential is applied to the epoxy inlet of the volume compared to atmospheric pressure, for example +1 bar, or 10 bar, or +100 bar.

[0083] The encapsulated volume can be essentially sealed except for the epoxy resin input and a purge hole to pump out gases before or during processing. The gas is first pumped out of the cavity to reach a sufficiently low pressure, e.g., 100 mbar, or 10 mbar, or 1 mbar, and then the epoxy encapsulant is filled into the volume.

[0084] Alternatively, in another example, several cycles of under pressure / filling events are applied, with the filling being performed with an epoxy encapsulant pressure of +0 bar (i.e. atmospheric pressure) or at a pressure higher than atmospheric pressure as described in the example above.

[0085] Standard compression molding processes can also be used to apply pressure to the epoxy encapsulant.

[0086] The copper metallization layer may be in contact with the structured aluminum metallization layer.

[0087] The copper-metal semiconductor interconnect stack has higher reliability against thermo-mechanical fatigue due to the presence of the interlocking structures, and the copper metal cannot diffuse into the semiconductor due to the diffusion barrier properties of the aluminum metallization layer.

[0088] The minimum aluminum metallization thickness TD / 2 may be greater than 2 μm thick, preferably greater than 3 μm thick, and preferably greater than 5 μm thick, so that the aluminum metallization has a minimum thickness sufficient to act as a diffusion barrier against copper diffusion.

[0089] A thin interfacial layer (<2 μm) may be present between the copper layer and the structured aluminum metallization to provide one or some of the following properties: corrosion or reaction barrier between aluminum and copper, or oxidation resistance at the interface, good wetting properties between aluminum and copper during the copper deposition process. For example, such a diffusion barrier may be Ti, TiN, Ta, TaN, Au, Ni, Pd, Ag, or any conductive metal, and may be deposited using state-of-the-art deposition processes, such as PVD, CVD, electroplating, electroless plating, etc.

[0090] The average copper layer thickness can be from 5 μm to 50 μm, preferably from 10 μm to 30 μm.

[0091] The reliability of the assembly can be increased by a factor of 2, preferably by a factor of 10 (reliability is assessed using standard test procedures such as AQG324).

[0092] Copper-metal-semiconductor interconnects can be deposited using a plating process that includes at least some of the following steps. -1 / preparing a structured aluminum metallization layer, then -2 / Clean the surface with degreaser, then -3 / Chemically attack the aluminum surface using acid, then -4 / Activate the surface using one or several zincate bath treatments, then -5 / Optionally, deposit one or several thin layers (<2 μm) using electroplating or electroless plating, then -6 / Depositing a copper layer using an electroplating or electroless plating process alone or using an electroplating or electroless plating process in combination with a subsequent PVD or CVD process, then optionally -7 / Planarize the copper surface using a mechanical or chemical-mechanical polishing process.

[0093] For example, in step 2, the surface is cleaned using a degreaser such as isopropanol and / or acetone and / or ethanol, followed by rinsing in demineralized water.

[0094] For example, in step 3, the surface is eroded using a solution containing nitric acid and / or chloric acid, and / or sodium difluoride and / or sulfuric acid and / or chromic acid, and / or hydrofluoric acid to remove a surface layer less than 1 μm, preferably less than 100 nm, to expose an aluminium surface free of oxides and foreign elements.

[0095] For example, in step 6, a thin seed layer of copper (<2 μm) can be deposited using PVD or CVD techniques, and the remainder of the copper metallization material is deposited using plating techniques (which are typically cheaper).

[0096] For example, in step 7, the non-planar copper surface is planarized using state of the art chemical mechanical polishing, for example by mounting the bottom of the semiconductor on a first rotating surface and / or contacting the copper layer with a second polishing rotating surface parallel to the first surface, and removing excess copper material by mechanical polishing, optionally assisted by chemical action.

[0097] The resulting structure is shown in FIG.

[0098] The embodiments presented above can be applied in technical fields that require high adhesive strength between aluminum and other materials such as polymeric materials or copper.

[0099] A common problem in component assembly is poor adhesion strength between aluminum and such materials, typically epoxy resins, for example. The main reason is the rapid oxidation of aluminum and the poor adhesion strength between oxidized and oxide-free aluminum. The above embodiment allows achieving improved adhesion strength between aluminum and for example epoxy, despite the presence of an oxide layer, thus opening up the possibility of assembling aluminum parts using epoxy-based adhesives. Such application areas can be epoxy coatings for corrosion protection of aluminum, thermally efficient aluminum heat sink assembly (for example in power modules), general electronic packaging, PCB assembly to aluminum, etc.

[0100] Other embodiments of structuring the aluminum surface prior to bonding can be implemented. For example, structuring tools appropriate to the relevant technical field can be used. For example, structuring a bulky aluminum surface (e.g., from a heat sink) using machining techniques can be more time- and cost-effective than using lithography techniques.

[0101] The embodiments may further be adapted to technical fields where low-cost yet reliable interconnects between copper and electronic devices are needed and where copper may harm semiconductor devices (mainly Si and SiC devices). In general, copper may be preferred over aluminum to benefit from its higher electrical conductivity and lower thermal expansion coefficient. For example, such applications may be in the fields of solar cells (currently using screen-printed aluminum back metallization), Si and / or SiC power modules (for rail transport, factory automation, automobiles, industrial drives, embedded drives, charging stations, solar inverters, etc.), general electronic devices, etc.

Claims

1. 1. A semiconductor chip having an aluminum layer, the aluminum layer having a texture of at least a portion of a surface that receives additional deposition, the texture forming a peak on the portion of the surface that occupies 20% to 80% of the portion of the surface.

2. 2. The semiconductor chip of claim 1, wherein the aluminum layer is a metallization layer having an average thickness T between 2 μm and 15 μm.

3. 3. The semiconductor chip of claim 1, wherein the aluminum layer has an average thickness T, and the texture has a length L that indicates an average distance between first adjacent peaks of the texture and that is related to the average thickness T by L<10*T.

4. 4. The semiconductor chip according to claim 1, wherein the aluminum layer has an average thickness T and the texture exhibits an average depth D of the peaks and has a depth D related to the average thickness T by D>0.2*T.

5. The semiconductor chip of any one of claims 1 to 4, wherein the peaks form a periodic sinusoidal shape in at least one profile section of the texture.

6. The semiconductor chip according to any one of claims 1 to 5, wherein the peaks have bulges at their tops.

7. The semiconductor chip according to any one of claims 1 to 6, wherein the semiconductor chip is a power semiconductor chip.

8. The semiconductor chip of any one of claims 1 to 7, wherein the surface of the aluminum layer comprises at least one additional portion separate from the portion comprising the texture and configured for electrical connection of the aluminum layer.

9. The semiconductor chip according to any one of claims 1 to 8, wherein the additional deposit comprises copper.

10. The semiconductor chip of any one of claims 1 to 8, wherein the additional deposit comprises an epoxy resin.

11. 1. A method for manufacturing a semiconductor chip having an aluminum layer, comprising: depositing said aluminum layer; forming a texturing on at least a portion of a top surface of the aluminum layer; forming an additional deposit on at least the portion; and Including, The method, wherein the texture forms a peak on the portion that occupies between 20% and 80% of the portion.

12. forming the tissue structure spatially selectively depositing a mask over the portion, the mask avoiding etching effects on the aluminum layer underlying the mask; Etching the portion; and removing the mask; and The method of claim 11 , comprising:

13. forming the tissue structure spatially selectively depositing a mask over the portion, the mask preventing deposition of aluminum thereon; depositing aluminum over the portion; removing the mask; and The method of claim 11 or 12, comprising:

14. The method of any one of claims 11 to 13, wherein forming the textured structure comprises deforming the top surface of the portion using a machine tool to create the peaks.

15. The method of any one of claims 11 to 14, wherein forming the textured structure further comprises applying a press tool to the tops of the peaks to form bulges in the tops.

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