Tailoring thin film growth using wafer bow.

Abstract

A processing chamber and method for tailoring thin film growth on a wafer using a plasma enhanced chemical vapor deposition (PECVD) process are described. A first portion of a film is deposited on a wafer on a pedestal in the processing chamber during a first deposition phase. A second portion of a film is deposited on the wafer during a second deposition phase. The wafer is unclamped from the pedestal prior to the first and / or second deposition phases and remains unclamped during the first and / or second deposition phases. The wafer has a non-zero wafer bow during the unclamped deposition phases to provide a radially non-uniform film thickness profile on the wafer.

Description

Claiming priority

[0001] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 305,179, filed January 31, 2022, the entirety of which is incorporated herein by reference. [Technical field]

[0002] The subject matter disclosed herein generally relates to methods, systems, and machine-readable storage media for film growth tuning with non-zero wafer bow. [Background technology]

[0003] Semiconductor substrate processing systems are used to process semiconductor substrates by techniques including etching, deposition (such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), pulsed deposited layer (PDL), plasma enhanced pulsed deposited layer (PEPDL), electron beam evaporation, and sputtering, among others), resist removal, planarization, and cleaning. One type of semiconductor substrate processing equipment is a plasma processing equipment that includes a vacuum processing chamber with an upper electrode and a lower electrode. Radio frequency (RF) power is applied between the electrodes to excite process gases into a plasma for processing (e.g., layer deposition) on a substrate (also referred to herein as a wafer) in the chamber.

[0004] During plasma processing, the wafer may be clamped to a chuck to provide a flat surface for the plasma, for example, during thin film deposition. Typically, electrostatics are used to clamp the wafer, and electrostatic chucks (ESCs) are used to reduce wafer bow (i.e., height distance between the center and edge of the wafer) during thin film deposition. In traditional semiconductor process flows, high wafer bow (e.g., >300-600 μm) may be observed before, during, or even after thin film deposition. High wafer bow can cause non-uniform thin film deposition due to wafer-to-wafer, station-to-station, and batch-to-batch non-uniformity variability. In general, the use of ESCs has not proven successful in eliminating wafer bow and variability in thin film deposition. Also, ESCs are relatively expensive components, so some process chambers do not have ESC clamping capabilities.

[0005] The Background Art set forth herein is intended to present the contents of the present disclosure generally. Please note that the information set forth in this section is presented to provide those of skill in the art with the content of the subject matter disclosed below, and is not to be considered admitted prior art. In particular, the inventions of the currently named inventors are not admitted expressly or impliedly as prior art to the present disclosure to the extent that they are described in this Background Art section and in a manner of description that is not prior art at the time of filing. Summary of the Invention

[0006] Methods, systems, and computer programs are presented for film growth tuning using non-zero wafer bow. Some embodiments tailor film growth during PECVD by creating or controlling wafer bow. Some embodiments tailor film growth and control wafer bow by splitting wafer deposition into two or more stages.

[0007] An example includes forming a film (thin film) on the wafer up to about a few microns thick, although thicker films may be formed in other examples. If the processing chamber includes an ESC or other clamping mechanism, the first deposition stage includes depositing a predetermined ratio of the desired thin film thickness on a wafer clamped to a chuck or pedestal (i.e., clamped before deposition and remaining clamped during deposition in the first deposition stage). The wafer on the pedestal is then unclamped, and the remaining portion of the thin film is deposited while the wafer is on the pedestal (but unclamped) in the second deposition stage. Alternatively, the unclamped deposition stage may occur before the clamped deposition stage, or may be unclamped during any deposition stage. A multi-stage deposition process including clamped and unclamped stages forms a different thin film thickness profile on the wafer than a single clamped deposition stage. The thin film distribution ratio of the clamped and unclamped deposition stages may adjust the final thin film thickness profile. The selected distribution of thin film thicknesses deposited in each stage will allow the desired total film thickness and / or configuration to be formed accordingly.

[0008] Non-zero wafer bow can be generated (i.e., created) or modified using one or more of the methods described herein. For example, in a deposition chamber without a clamping mechanism such as an ESC, deposition of a portion of the thin film in a first deposition stage on a wafer that initially has a neutral bow (i.e., zero bow value) will apply sufficient force to the wafer to result in non-zero wafer bow. This effect may be considered "pseudo clamping." Non-zero wafer bow can be generated or modified by lifting the wafer off the pedestal for a period of time, evacuating the process chamber with an inert plasma, reigniting the plasma, moving the wafer relative to the pedestal, or changing the position of the wafer relative to the pedestal. Once non-zero wafer bow occurs, the remaining portion of the thin film will be deposited in a second deposition stage without clamping the wafer. Thus, the remaining portion of the thin film in the second deposition stage will result in a non-flat wafer with the desired non-zero wafer bow, forming a different thickness distribution on the wafer than in the first deposition stage. As a result, the final thickness distribution will be different from the thin film deposition using a single stage. As described above, the film thickness distribution ratio formed in each of the first and second stages can be adjusted to tailor the final film thickness profile on the wafer, thereby achieving a more uniform deposition on the wafer than conventional single-step deposition, where wafer bow can vary and the wafer bow variation rate (i.e., wafer bow change rate) can result in non-uniform thickness profiles from wafer to wafer, station to station, and batch to batch. [Brief description of the drawings]

[0009] Each of the accompanying drawings merely depicts an exemplary embodiment of the present disclosure and is not to be considered as limiting its scope.

[0010] [Figure 1] A processing chamber, such as a deposition chamber, for manufacturing a substrate, according to some exemplary embodiments.

[0011] [Diagram 2] 1 illustrates an aspect of a process flow for tailoring thin film growth using wafer bow, according to one embodiment.

[0012] [Diagram 3] 1 is a flow chart including operations in a method for modulating thin film growth, according to one embodiment.

[0013] [Figure 4] FIG. 1 is a block diagram illustrating an example of a machine upon which one or more exemplary method embodiments may be implemented or upon which one or more exemplary embodiments may be controlled. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Exemplary methods, systems, and computer programs are directed to methods, systems, and machine-readable storage media for thin film growth adjustment using wafer bow. Some embodiments adjust thin film growth during PECVD by controlling wafer bow. For convenience, in the embodiments disclosed herein, thin films are also simply referred to as "films." Unless otherwise specified, components and functions are optional and may be combined or sub-divided, and operations may be reordered or combined or sub-divided. In the following description, some specific details are set forth for the purpose of explanation in order to provide a thorough understanding of exemplary embodiments. However, it will be apparent to one skilled in the art that the present subject matter may be practiced without these specific details.

[0015] As mentioned above, deposition on a wafer introduces strain due to either or both lattice mismatch between the deposited layer and the underlying layer, or mismatch in the thermal expansion coefficient of the layer deposited on the wafer or the wafer itself. This strain will cause an inherent non-zero warpage structure due to the presence of different materials, and will worsen as the temperature changes (e.g., from process temperature to room temperature). Changing the clamping state of the wafer (i.e., clamped or unclamped) during thin film deposition may be used to adjust the growth. For example, unclamping of the wafer in an intermediate growth state (i.e., a first portion of the layer is deposited in a first deposition stage while the wafer is clamped, and a second portion is deposited in a second deposition stage while the wafer is unclamped) will introduce an inherent non-zero warpage in the wafer provided in the latter deposition stage (rather than a wafer that is made flat by clamping), which will change the deposition characteristics across the wafer due to changes in the plasma vicinity. The change in deposition characteristics will result in a reduction of the strain. That is, deposition in the unclamped stage will produce a different thickness distribution on the wafer than deposition in the clamped stage. As a result, the final film thickness distribution is more uniform than a wafer stack formed in a single deposition step.

[0016] Wafer bow may be determined using non-contact techniques such as optical measurement of the wafer surface. Optical measurements can provide the desired sensitivity to bows that are approximately 1000 times smaller than the wafer diameter (bows up to a few hundred microns for wafer diameters up to about a few hundred mm). In some cases, the wafer profile may be measured by laser scanning across the surface of the wafer at an angle from the surface of the wafer. The deflection of the laser is measured to determine the curvature of the wafer, and the bow of the wafer may be calculated from the curvature. Alternatively, an optical beam may be illuminated at the center of the wafer to determine the nominal height, and then re-illuminated at the edge of the wafer (or a series of positions along the wafer until the edge of the wafer is reached) to determine the height at the edge (or each position). This optical measurement may be used to calculate the bow, and then the radius of curvature of the wafer may be determined. Bow may be calculated in-situ during and / or before or after thin film deposition.

[0017] As used herein, the terms "wafer" and "substrate" are used interchangeably. Wafer or substrate refers to a support on which elements of a semiconductor device are fabricated or attached. Substrates (e.g., substrate 106 in FIG. 1) may include, for example, wafers (e.g., wafers with diameters of 100 mm, 150 mm, 200 mm, 300 mm, 450 mm, or more) composed of elemental semiconductors (e.g., silicon (Si) or germanium (Ge)) or compound semiconductors (e.g., binary compound semiconductors such as silicon germanium (SiGe), gallium arsenide (GaAs), or gallium nitride (GaN), ternary compound semiconductors such as indium gallium arsenide (InGaAs), indium gallium phosphide (InGaP), or indium aluminum arsenide (InAlAs), or quaternary (or higher) compound semiconductors). Other substrates also include dielectric materials (on which semiconductor materials are applied), such as, for example, quartz or sapphire. Substrates may be blanket wafers or patterned substrates. A blanket substrate is a substrate that includes a low surface (or substantially planar) top surface. A patterned substrate is a substrate that includes a high surface (or structured) top surface. The structured top surface of the substrate may include different high surface area structures, such as 3D NAND memory holes or other structures.

[0018] A general description of a process chamber using the disclosed method of thin film growth conditioning is provided with reference to FIG. 1. FIG. 1 illustrates a process chamber 100 (e.g., a deposition chamber or an etch chamber) for fabricating a substrate, according to one embodiment. In some examples, the process chamber 100 may also be referred to as a vacuum chamber. Exciting an electric field between two electrodes is one way to obtain a radio frequency (RF) gas discharge in the process chamber. When an oscillating voltage is applied between the electrodes, the resulting discharge is called a capacitively coupled plasma (CCP) discharge.

[0019] A plasma 102 is generated in the processing region 130 of the processing chamber 100 using one or more process gases to produce various chemically reactive by-products generated by dissociation of various molecules caused by collisions with electrons and neutrons. The plasma may be used to deposit semiconductor thin films using PECVD or to etch various materials such as oxides or nitrides. PECVD may be used to deposit semiconductors on a substrate at lower temperatures (typically about 250° C. to about 350° C.) than standard CVD (typically about 600° C. to about 800° C.), thereby reducing deleterious thermal effects on the substrate, such as thermally enhanced diffusion between existing layers of the wafer. PECVD may be used to deposit doped or undoped insulating or semiconductor films such as silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), and amorphous silicon (α-Si), among others. For example, silane (SiH4) may be combined with an oxygen source gas to form silicon dioxide, or with a nitrogen gas source to form silicon nitride.

[0020] PECVD may be used for etching, where the reaction of neutral gas molecules and their dissociated byproducts with molecules on the surface to be etched produces volatile molecules that may be exhausted. When a plasma is generated, positive ions are accelerated from the plasma across a space charge sheath that separates the plasma from the chamber walls to impact the substrate surface with sufficient energy to remove material from the substrate surface. The process of using energetic, chemically reactive ions to selectively and isotropically remove material from the substrate surface is called reactive ion etching (RIE). In some examples, the process chamber 100 may be used in conjunction with a PECVD or PEALD deposition process. In one embodiment, fluorocarbon gases such as CF4 and C4F8 are used in the dielectric etching process for their isotropic and selective etching capabilities, although the principles described herein may also be applied to other plasma generating gases. Fluorocarbon gases are readily dissociated into chemically reactive byproducts, including small molecules and atomic radicals. These chemically reactive byproducts etch the dielectric material.

[0021] Whether used for deposition or etching, the controller 116 manages the operation of the process chamber 100 by controlling different elements in the chamber 100 (e.g., RF generator 118, gas source 122, and gas pump 120). The process chamber 100 represents a process chamber comprising an upper (or top) electrode 104 and a lower (or bottom) electrode 108. The upper electrode 104 may be grounded or connected to an RF generator (not shown), and the lower electrode 108 is connected to the RF generator 118 via a matching network 114. The RF generator 118 provides an RF signal between the upper electrode 104 and the lower electrode 108 to generate RF power at one or more (e.g., two or three) different RF frequencies. At least one of the multiple RF frequencies may be turned on or off depending on the desired configuration of the process chamber 100 for a particular operation. In the embodiment shown in FIG. 1, the RF generator 118 is configured to provide frequencies such as 400 kHz, 2 MHz, 27 MHz, and 60 MHz, although other frequencies are possible.

[0022] The processing chamber 100 includes a gas showerhead at the top electrode 104 for injecting process gases provided by a gas source 122 into the processing chamber 100, and a perforated confinement ring 112 through which gases can be exhausted from the processing chamber 100 by a gas pump 120. In some exemplary embodiments, the gas pump 120 is a turbomolecular pump, although other types of gas pumps may be used.

[0023] When substrate 106 is present in process chamber 100, a silicon focus ring 110 is placed adjacent to substrate 106 to provide a uniform RF field at the bottom of plasma 102 for uniform deposition (or etching) on ​​the surface of substrate 106. The embodiment of FIG. 1 shows a triode reactor configuration in which upper electrode 104 is surrounded by a symmetric RF ground electrode 124. Insulator 126 is a dielectric that insulates ground electrode 124 from upper electrode 104. Other embodiments of process chamber 100 are possible, including inductively coupled plasma (ICP) embodiments, without changing the scope of the disclosed embodiments.

[0024] Each frequency generated by the RF generator 118 may be selected for a particular purpose in the substrate fabrication process. In the example of FIG. 1, RF power is provided at 400 kHz, 2 MHz, 27 MHz, and 60 MHz, with the 400 kHz or 2 MHz RF power providing control of ion energy and the 27 MHz and 60 MHz power providing control of plasma density and dissociation patterns of chemical reactions. This configuration of being able to turn each RF power on or off allows for certain processes with very low ion energy on the substrate and certain processes (e.g., soft etching of low-k materials) where ion energy needs to be low (e.g., less than 700 eV or 200 eV).

[0025] In another embodiment, 60 MHz RF power is used on the top electrode 104 to obtain ultra-low energy and ultra-high density. This configuration allows for chamber cleaning with high density plasma while minimizing sputtering on the ESC surfaces when the substrate 106 is not inside the process chamber 100. Since the ESC surfaces are exposed when the substrate 106 is not present and any ion energy on the surfaces should be avoided, the bottom 2 MHz and 27 MHz power sources may be turned off during cleaning.

[0026] In an exemplary embodiment, the process chamber 100 further includes a sensor 128 that can be disposed between the matching network 114 of the RF generator 118 and the lower electrode 108. The sensor 128 can include a voltage-current (or VI) sensor configured to generate a plurality of signals (e.g., sensed data) indicative of at least one signal characteristic of the RF signal generated by the RF generator 118 at the corresponding plurality of time instances. For example, the VI sensor can generate a plurality of signals indicative of one or more of the following signal characteristics of the RF signal: voltage, current, phase, power supply, and impedance. In some examples, the plurality of signals generated by the sensor 128 at the corresponding plurality of time instances can be stored (e.g., in the controller 116 or an on-chip memory of the sensor 128) and later retrieved (e.g., by the controller 116) for subsequent processing. In other aspects, the plurality of signals generated by the sensor 128 at the corresponding plurality of time instances can be automatically communicated to the controller 116 when generated.

[0027] Previously, film thickness distribution on a wafer could only be tuned by adjusting traditional "process knobs" such as pressure, electrode gap, gas flow, RF power, temperature, etc. Some disclosed embodiments provide a way to tune thin film growth using non-zero wafer bow (i.e., other than or in addition to using traditional process knobs). Some disclosed embodiments enable an efficient and cost-effective solution for chambers without ESC clamping hardware. Some disclosed embodiments use existing ESC clamping hardware, but rather than holding the wafer clamped throughout the entire deposition, these embodiments include a two- or multi-step deposition approach to tune the thin film thickness distribution on the wafer by controlling the wafer bow. Some disclosed embodiments do not include clamps, but include a two- or multi-step deposition to tune the thin film thickness distribution on the wafer in an effort to achieve more uniform film growth by controlling the wafer bow.

[0028] Reference is now made to Figure 2 of the accompanying drawings, which illustrates, from left to right, a sequence of steps in a process flow (or method) 202 for using wafer bow to tailor thin film growth. Some exemplary methods have the ability to tailor or control film thickness growth, i.e., control film thickness in a desired manner or to a desired extent or magnitude. The deposited film can be formed to a desired material thickness.

[0029] As used herein, the terms "chuck" and "pedestal" are used interchangeably. In some embodiments, the chuck or pedestal includes a clamp, and other embodiments do not include a chuck clamp or pedestal clamp. In some embodiments, the clamp includes a physical clamping mechanism (e.g., a vacuum applied to a wafer through-hole in the top surface of the chuck or platen on which the wafer is placed). In other embodiments, a non-physical mechanism (e.g., an electromagnetic or electrostatic clamping mechanism) may be used. In either case, the clamping mechanism can keep the wafer such that it remains essentially flat (i.e., secured to the top chuck surface or platen during wafer processing). Controlling the use of the clamping mechanism during deposition may cause the wafer to have a controllably induced non-zero wafer bow. For example, the non-zero wafer bow may be controllably induced in the wafer by depositing at least a first portion of the film on the wafer clamped to the chuck in a first deposition stage, and then unclamping or releasing the wafer from the chuck at a predetermined time after the first deposition stage (e.g., immediately after the first deposition stage). In a second deposition step, a second portion of the film is deposited on the unclamped wafer on the chuck.

[0030] In some embodiments, the non-zero wafer bow may be controllably induced in-situ (i.e., while the wafer is on the chuck (during one or more of the deposition steps)). Alternatively, or in addition, the non-zero wafer bow may be controllably induced in the wafer before the wafer is clamped to the chuck or before the wafer is introduced into a processing chamber in which the chuck is located. The shape of the induced non-zero wafer bow may or may not be controlled to meet a desired non-zero wafer bow specification (i.e., no specific wafer bow specification is set for a given process step). In some embodiments, the induced non-zero wafer bow occurs "automatically" or "naturally" upon de-clamping, while in other embodiments the non-zero wafer bow is "forced" into the wafer, where the wafer may be exposed to a deformation force. That is, non-zero wafer bow may be induced mechanically by thin film growth and / or by physical changes in wafer position on the pedestal (and / or changes to parameters such as the temperature of the processing chamber from stage to stage), and at least a portion of the non-zero wafer bow may thus be induced by each technique. In some embodiments, the wafer has an inherent non-zero wafer bow shape or value prior to deposition due to existing layers on the wafer.

[0031] In some embodiments, the wafer bow may be positive, negative, or zero (i.e., may have a positive, negative, or zero value). A zero wafer bow value corresponds to a flat wafer. For example, a concave (negative) wafer bow in a dome-shaped wafer has a negative bow value. In some embodiments, the reverse situation, where the wafer edge is relatively high and the wafer center is relatively low (e.g., a bowl-shaped wafer with a convex (positive) wafer bow), exhibits a positive bow value. In some embodiments, a wafer has a positive, negative, or zero intrinsic bow value.

[0032] Referring again to FIG. 2, in the illustrated embodiment, assume that it is desired to form a thin film 204 of a predetermined thickness (e.g., 2000 nm) on a wafer 206 using PECVD in a processing chamber. For example, the processing chamber may include or be comprised of the processing chamber 100 of FIG. 1. In the figure, for clarity of illustration, only a pedestal 208 (or chuck) and a showerhead 210 are shown. During the pre-deposition stage 212 and the subsequent stages in the formation of the thin film 204, the wafer 206 is supported on the pedestal 208. In the illustrated embodiment, the pedestal 208 includes a clamping mechanism. As such, the pedestal 208 may include an ESC to apply an electrostatic force to clamp the wafer 206 flatly to the pedestal 208. Although the embodiment is described for a thin film 204 having a tuned thickness of 2000 nm, other film thicknesses are possible, and the 2000 nm film thickness is merely an example. Exemplary thin film thicknesses may be, for example, from about 1000 nm to about 3400 nm. In some instances, the thin film thickness may be affected by the film stress level.

[0033] In a first deposition phase 214, a first deposition occurs on the wafer 206. In some embodiments, the first deposition phase 214 may be performed while the wafer 206 is either clamped or unclamped to the pedestal 208. In other embodiments, the wafer 206 is clamped to the pedestal 208 during the first deposition phase 214.

[0034] In a first deposition stage 214, some film material (or some percentage of the total 2000 nm film) is deposited using plasma to form a first portion 216 of the thin film 204. For illustrative purposes, the first portion 216 of the thin film 204 has a thickness of "x" nm when formed (where "x" is less than 2000 nm, i.e., less than the total adjusted thickness of the final thin film 204). The thickness of the first portion 216 of the thin film 204 may be substantially uniform across the wafer 206 (e.g., within a few percent across the wafer 206). Exemplary percentage thicknesses of the first portion 216 are described below. After formation of the first portion 216, deposition is stopped by turning off the gas source to inactivate the plasma and / or removing voltage from the electrodes.

[0035] At this point, a transition phase 218 is entered with the temperature within the chamber remaining the same as that used in the first deposition phase 214. In some embodiments, the intersection of the first deposition phase 214 and the transition phase 218 is the end of deposition in the first deposition phase 214. In some embodiments, deposition ends whether the wafer 206 is clamped or unclamped.

[0036] During the transition phase, after the wafer 206 is no longer clamped, the flat shape imposed by the clamps is relaxed and the wafer 206 can be adjusted to be concave or convex depending on the inherent non-zero bow between the deposited layers and the underlying layers on the wafer 206 and / or can be induced by applying other forces to the wafer 206. In the illustrated embodiment, the wafer 206 is assumed to be dome-shaped, i.e., to have a negative bow value.

[0037] In some embodiments, actuating the lift pins 220 to remove the wafer 206 from the pedestal 208 can loosen the wafer and cause a non-zero wafer bow. In some embodiments, the lift pins 220 include sapphire pins that, upon actuation, move upward to protrude above the pedestal 208. In some embodiments, the lift pins 220 penetrate the pedestal platen and are forced upward by a mechanism located below the pedestal platen (or pedestal 208) to lift the wafer 206 a predetermined distance from the pedestal 208. In some embodiments, a particular wafer lift distance may not determine a desired non-zero wafer bow, but is sufficient to allow for the formation of an inherent non-zero wafer bow by a raised unclamped wafer. In some embodiments, the wafer lift distance may cause a non-zero wafer bow by application of an external force (provided by the pins) to the wafer 206. In some embodiments, the lift distance is about 1 millimeter, or other distance that does not cause the wafer 206 to face another chamber hardware component. In some embodiments, the amount of wafer bow depends on the presence of free clearance of the wafer 206 from the pedestal 208. In some embodiments, this free clearance mitigates the inherent wafer bow introduced in the first deposition stage 214, e.g., having a maximum wafer bow of about 500 μm. Positive or negative wafer bow may be formed.

[0038] After the new wafer bow shape is formed during the transition phase 218, the second deposition phase 222 begins. In some embodiments, regardless of whether the first deposition phase 214 was performed with or without a wafer clamp, the second deposition phase 222 is performed without a clamp. Thus, for a pedestal including an ESC, no electrostatic clamping force is applied during the second deposition phase 222 (irrespective of whether an electrostatic clamping force was applied during the first deposition phase 214). The second deposition phase 222 occurs with the wafer 206 in a relaxed shape, even with a bow having a positive or negative value or an inherent bow value as a result of the first deposition phase 214. In some embodiments, this wafer shape may assume a natural or rest shape resulting from the first deposition phase 214. During the second deposition phase 222, a second portion 224 or a remaining portion of the thin film 204 of a predetermined thickness is formed. In this embodiment, the second portion 224 of the thin film 204 has a nominal thickness of 2000 nm (total thickness) minus "x" nm (deposited in the first deposition stage 214).

[0039] In some embodiments, the first deposition phase 214 and the second deposition phase 222 are "repeatable" (i.e., can be consistently repeated) or at least provide consistent results, allowing for repeatable and uniform adjustment of the overall thickness and profile of the thin film 204.

[0040] Because the wafer 206 has a non-zero bow value (typically tens to hundreds of microns) during the second deposition phase 222, the distance of the wafer 206 from the plasma may change during deposition, which may change the deposition rate due to comparative differences in plasma density, electric field, and temperature across the wafer 206 (temperature may vary with contact with the pedestal 208 and proximity to the plasma). This results in a variation in the thickness profile of the thin film 204 across the wafer 206 at the end of the second deposition phase 222. The thickness variation between the center and edge of the wafer 206 may be, at most, about a few percent (e.g., 7%) of the total film thickness, which may be small enough to have little effect on the properties of the thin film 204. The thickness may be determined based on the process time of depositing a flat (i.e., clamped) wafer of nominal thickness. In some embodiments, the ratio of the thickness of the film deposited in the first deposition stage 214 to the thickness of the film deposited in the second deposition stage 222 may be determined based on the maximum allowable thickness variation (or profile variation) across the wafer 206 when the thickness variations caused by the first deposition stage 214 and the second deposition stage 222 are known. In some embodiments, the bow shape of the wafer 206 on the pedestal 208 affects the relative deposition rate across the wafer 206 in a radial direction. In some embodiments, the deposition rate is continuous across the wafer 206 as a function of radius from the center of the wafer 206. That is, the total thickness of the thin film 204 is continuous across the wafer 206 in a radial direction and is the same for all points having the same radius from the center of the wafer 206.

[0041] In some embodiments, the center of the wafer 206 is at the origin of the wafer 206 at a 150 millimeter radius for a standard 300 millimeter wafer, or at zero radius centered on its edge. A two (or more) step deposition method that results in wafer bowing can thus address the problems caused by the conventional single deposition method described above. In some embodiments involving two (or multiple) step deposition, it has been found that the deposition rate between the center and edge of the wafer changes with changes in the shape or curvature of the wafer. Some embodiments modify the deposition thickness profile as a function of radius.

[0042] Some embodiments use at least two different partial profiles resulting from a first deposition stage 214 and a second deposition stage 222 with a deposition rate profile or thickness profile different from the first deposition stage 214. These deposition process differences can result in a desired or beneficial final film thickness or profile. The final film thickness or profile is the result of a combination of the two deposition stages. In some embodiments, deposition effectiveness is increased to tailor film thickness and profile by allowing wafer shape to mitigate and modify bowing. In some embodiments, the deposition rate at the center of the wafer is increased relative to the deposition rate at the edge of the wafer. Some embodiments result in a uniform thickness profile that is repeatable throughout by depositing the material that forms the film in two or more stages rather than a single stage. In some embodiments, the bow shape formed after the first deposition stage is repeatable and serves as a consistent basis for tailoring film thickness in the second deposition stage. Within normal wafer-to-wafer, station-to-station, and hardware setup variations, wafer bowing and film tailoring are repeatable.

[0043] In some embodiments, the thickness ratio of the first portion 216 of the film based on the total thickness of the thin film 204 is between 10% and 90%. In some embodiments, the thickness ratio of the first portion 216 of the film based on the total thickness of the thin film 204 is between 30% and 70%. In some embodiments, the thickness ratio of the first portion 216 of the film based on the total thickness of the thin film 204 is 50% ± 2%. In some embodiments, the film thickness ratio in the first and second stages can adjust the final thickness profile. In some cases, the wafer bow can be changed during a single deposition step, and the wafer bow variation rate (i.e., the rate of change of the wafer bow) can result in a non-uniform thickness profile from wafer to wafer, station to station, and batch to batch. Uniform deposition on the wafer can be achieved, or at least targeted, by selectively allocating the film thickness ratio in the first and second deposition steps.

[0044] Some examples include a method of forming a film on a wafer. An example is shown in FIG. 3. In some embodiments, not all of the operations in method 300 may be performed and / or other operations may be present. Referring to FIG. 3, a method 300 of regulating film growth on a wafer includes placing a wafer on a pedestal in a processing chamber in operation 302, depositing a first portion of a film on the wafer during a first deposition phase in operation 304, and depositing a second portion of a film on the wafer during a second deposition phase in operation 306. The wafer is unclamped from the pedestal prior to and / or during the first and / or second deposition phases and remains unclamped during and / or during the first and / or second deposition phases. During the second deposition phase, the wafer has a non-zero wafer bow.

[0045] In some embodiments, the second portion of the film is a remainder of the film, and the first and second portions of the film define a total thickness of the film.

[0046] In some embodiments, the method 300 further includes clamping the wafer to a pedestal during the first deposition stage.

[0047] In some embodiments, the method 300 further includes unclamping the wafer from the pedestal after the first deposition step.

[0048] In some embodiments, the non-zero wafer bow is induced by performing a first deposition step, hi some embodiments, the non-zero wafer bow is induced by forming a first portion of the thin film on the wafer.

[0049] In some embodiments, the wafer is unclamped during the first deposition step.

[0050] In some embodiments, the wafer is unclamped during the second deposition step.

[0051] In some embodiments, the wafer is unclamped during the first and second deposition stages.

[0052] In some embodiments, the wafer is clamped during a first deposition stage and unclamped during a second deposition stage.

[0053] In some embodiments, a thickness ratio of the first portion of the thin film based on a total thickness of the thin film is between 10% and 90%. In some embodiments, a thickness ratio of the first portion of the thin film based on a total thickness of the thin film is between 30% and 70%. In some embodiments, a thickness ratio of the first portion of the thin film based on a total thickness of the thin film is between 48% and 52%.

[0054] In some embodiments, the method 300 further includes adjusting a thickness ratio of the first portion of the thin film or a thickness ratio of the second portion of the thin film to adjust an overall thickness or profile of the thin film.

[0055] In some embodiments, the method 300 further includes forming a first predetermined profile of the first portion of the thin film during the first deposition stage.

[0056] In some embodiments, the method 300 further includes forming a second predetermined profile of a second portion of the thin film during a second deposition stage.

[0057] In some embodiments, the method 300 further includes forming a first predetermined profile of a first portion of the thin film during the first deposition stage and forming a second predetermined profile of a second portion of the thin film during the second deposition stage, the first and second profiles being different.

[0058] In some embodiments, the thickness of the first portion of the thin film is uniform across a diameter of the wafer.

[0059] In some embodiments, the thickness of the second portion of the thin film is uniform across a diameter of the wafer.

[0060] In some embodiments, the thickness of a first portion of the thin film is uniform across a diameter of the wafer, the thickness of a second portion of the thin film is uniform across a diameter of the wafer, and the thicknesses of the first and second portions are different from each other.

[0061] FIG. 4 is a block diagram illustrating an example of a machine 400 that may perform or control one or more exemplary process embodiments described herein. In another embodiment, the machine 400 may operate as a stand-alone device or may be connected (e.g., networked) to other machines. In various examples, some of the components shown in FIG. 4 may be absent and / or other components may be present. In a networked arrangement, the machine 400 may operate as a server machine, a client machine, or both in a server-client network environment. In one example, the machine 400 may function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Moreover, while only one machine 400 is depicted, the term "machine" may also be construed to include a group of machines that individually or cooperatively execute a set (or sets) of instructions to perform one or more methods described herein. Thus, for example, instructions may be programmed or provided to various machines that operate a PECVD chamber to provide the methods described herein.

[0062] The embodiments described herein may include or be performed by logic, several components, or mechanisms. Circuitry is circuitry implemented in a tangible object that includes hardware (e.g., simple circuits, gates, logic). The components of the circuitry may change over time and with underlying hardware variability. Circuitry includes components that, alone or in combination, can perform a particular operation when operated. In one embodiment, the hardware of the circuitry may be designed (e.g., word-wired) to perform a particular operation invariably. In one embodiment, the hardware of the circuitry may include variably connected physical components (e.g., execution units, transistors, simple circuits) that include computer-readable media that are physically modified (e.g., magnetically, electrically, by variable placement of invariable mass particles) to encode instructions for a particular operation. When connecting the physical components, the basic electrical properties of the hardware components change (e.g., from insulator to conductor or vice versa). The instructions enable the embedded hardware (e.g., execution units or loading mechanisms) to form the components of the circuitry into the hardware through variable connections to perform some of the particular operations when operated. Accordingly, the computer-readable medium is communicatively connected to other components of the circuitry when the device is operating. In some embodiments, any physical component may be used for more than one member of more than one circuitry. For example, during operation, an execution unit may be used at one time for a first circuit of a first circuitry and at a different time for use again by a second circuit of the first circuitry or a third circuit of the second circuitry.

[0063] The machine (e.g., a computer system) 400 may include a hardware processor 402 (e.g., a central processing unit (CPU), a hardware processor core, or a combination thereof), a graphics processing unit (GPU) 403, a main memory 404, and a static memory 406, some or all of which may communicate with each other through an interlink (e.g., a bus) 408. The machine 400 may further include a display device 410, an alphanumeric input device 412 (e.g., a keyboard), and a user interface (UI) navigation device 414 (e.g., a mouse). In one embodiment, the display device 410, the alphanumeric input device 412, and the UI navigation device 414 may be touch screen displays. The machine 400 may further include a mass storage device (e.g., a drive unit) 416, a signal generator 418 (e.g., a speaker), a network interface device 420, and one or more sensors 421 (such as a global positioning system (GPS) sensor, a compass, an accelerometer, or another sensor). The machine 400 may include an output controller 428 (such as a serial connection (e.g., Universal Serial Bus (USB)), parallel connection, or other wired or wireless connection (e.g., infrared (IR), near field communication (NFC))) to communicate with or control one or more peripheral devices (e.g., printer, card reader).

[0064] In the exemplary embodiment, the hardware processor 402 is capable of performing the functions of the controller 116 described herein.

[0065] The mass storage device 416 may include a machine-readable medium 422 having stored thereon one or more sets of data structures or instructions 424 (e.g., software) that embody or are used in one or more of the techniques and functions described herein. The instructions 424 may reside, completely or at least partially, within the main memory 404, the static memory 406, the hardware processor 402, or the GPU 403 during its execution by the machine 400. In an embodiment, one or any combination of the hardware processor 402, the GPU 403, the main memory 404, the static memory 406, and the mass storage device 416 may constitute a machine-readable medium. The instructions 424 may enable the machine 400 to perform the operations described herein, such as controlling components in a deposition chamber.

[0066] Although the machine-readable medium 422 is depicted as a single medium, the term “machine-readable medium” may include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store one or more instructions 424.

[0067] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions 424 for execution by the machine 400, causing the machine 400 to perform any one or more techniques of the present disclosure, or any medium capable of storing, encoding, or carrying data structures used in or related to such instructions 424. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. In one embodiment, a high-capacity machine-readable medium comprises a machine-readable medium 422 that includes a plurality of particles having an unchanging (e.g., stationary) mass. Thus, the high-capacity machine-readable medium is not a transitory propagating signal. Examples of high-capacity machine-readable media may include non-volatile memory (semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)), flash memory devices, magnetic disks (internal hard disks and removable disks, magneto-optical disks, CD-ROM and DVD-ROM disks, etc.)).

[0068] The instructions 424 may further be transmitted or received through the network interface device 420 over a communications network 426 using a transmission medium.

[0069] The implementation of the techniques described above may be performed by hardware and software in any number of specifications, configurations, or example arrangements. It should be understood that functional units or capabilities described herein may be referred to or denoted as components or modules to more specifically emphasize their implementation independence. Such components may be embodied in any number of software or hardware forms. For example, a component or module may be implemented as a hardware circuit including customized very large scale integrated (VLSI) circuits or gate arrays, off-the-shelf semiconductors (such as logic chips, transistors, or other discrete components). A component or module may be implemented in a programmable hardware device (such as a field programmable gate array, programmable array logic, programmable logic device, etc.). A component or module may be implemented in software for execution by various types of processors. A particular component or module of executable code may include one or more physical or logical blocks of computer instructions that may be organized as an object, procedure, or function, for example. Nonetheless, the executable files for a particular component or module need not be physically located together, but may comprise separate instructions stored in different locations which, when logically combined, comprise the component or module and achieve a predetermined purpose for the component or module.

[0070] In fact, an executable code component or module may be a single instruction or many instructions, and may be distributed across several memory devices or processing systems in several different code segments in different programs. In particular, some aspects of the described process (e.g., rewriting the code and analyzing the code) may be performed on a processing system (e.g., a computer in a data center) different from the processing system (e.g., a computer embedded in a sensor or robot) on which the code is deployed. Similarly, operational data may be identified and described in components or modules herein, and may be embodied in any suitable form and organized into any suitable type of data structure. The operational data may be collected as a single data set or distributed in different locations, including different storage devices, and may exist, at least in part, as mere electronic signals on a system or network. The components or modules may be passive or active parts or modules that include agents operable to perform a desired function.

[0071] Application example (Please note that "application example x to y" refers to any one or more of application examples x to y.)

[0072] Application example 1 is a method of modulating film growth on a wafer, the method including depositing a first portion of a film on a wafer disposed on a pedestal in a processing chamber during a first deposition phase, and depositing a second portion of the film on the wafer during a second deposition phase, where the wafer is unclamped from the pedestal prior to and / or during the first and / or second deposition phase, and remains unclamped during and / or during the first and / or second deposition phase.

[0073] In application example 2, the subject matter of application example 1 includes clamping the wafer to the pedestal prior to the first deposition step, and the wafer remaining clamped to the pedestal during the first deposition step.

[0074] In application example 3, the subject matter of application example 2 includes the wafer having a non-zero wafer bow during the second deposition phase.

[0075] In application example 4, the subject matter of application example 3 includes where non-zero wafer bow is introduced by deposition of the first portion of the film on the wafer.

[0076] In application example 5, the subject matter of applications 3-4 includes mechanically adjusting the position of the wafer on the pedestal to effect at least a portion of the non-zero wafer bow.

[0077] In application example 6, the subject matter of applications 2-5 includes clamping the wafer to the pedestal using an electrostatic chuck (ESC) during the first deposition phase.

[0078] In application example 7, the subject matter of applications examples 1-6 includes the wafer having non-zero wafer bow during at least one of the first deposition stage and the second deposition stage.

[0079] In application example 8, the subject matter of applications examples 1-7 includes unclamping the wafer prior to the first deposition step and keeping the wafer unclamped for the duration of the first deposition step.

[0080] In an example 9, the subject matter of example 8 includes the wafer remaining unclamped during the second deposition step.

[0081] In application example 10, the subject matter of applications 8-9 includes the wafer being clamped prior to the second deposition step and remaining clamped for the duration of the second deposition step.

[0082] In Application Example 11, the subject matter of Application Examples 1 to 10 includes determining a ratio of a thickness of a first portion of the film to a thickness of a second portion of the film based on an amount of wafer warp of the wafer obtained after the wafer is unclamped.

[0083] In Application Example 12, the subject matter of Application Examples 1 to 11 includes determining a ratio of a thickness of a first portion of the film to a thickness of a second portion of the film based on a predetermined thickness profile of the wafer after the second deposition stage.

[0084] In application example 13, the subject matter of applications examples 1-12 includes maintaining a constant temperature within the chamber during the first deposition stage and the second deposition stage.

[0085] In an embodiment 14, the subject matter of embodiments 1-13 includes repeating the first deposition step and / or the second deposition step to form a film.

[0086] In application example 15, the subject matter of application examples 1-14 includes forming a first predetermined profile of a first portion of the film during a first deposition phase and forming a second predetermined profile of a second portion of the film during a second deposition phase, the first predetermined profile and the second predetermined profile being different.

[0087] In Application Example 16, the subject matter of Application Examples 1 to 15 includes the fact that the thickness of at least one of the first portion and the second portion of the film is constant in the radial direction of the wafer.

[0088] In application example 17, the subject matter of applications examples 1-16 includes the plasma chamber being a plasma enhanced chemical vapor deposition (PECVD) chamber.

[0089] In application example 18, the subject matter of applications 1 to 17 includes the fact that the film is a semiconductor film.

[0090] In Application Example 19, the subject matter of Application Examples 1 to 18 includes the fact that the film is an insulating film.

[0091] In Application Example 20, the subject matter of Application Examples 1 to 19 includes the following: a thickness of a first portion of the film is constant in the radial direction of the wafer, a thickness of a second portion of the film is constant in the radial direction of the wafer, and the thicknesses of the first portion and the second portion are different from each other.

[0092] Application example 21 is a method of modulating film growth on a wafer, the method including clamping the wafer to a pedestal in a plasma-enhanced chemical vapor deposition (PECVD) chamber, depositing a first portion of an insulating film on the clamped wafer during a first deposition phase, unclamping the wafer after the first deposition phase, and depositing a second portion of the insulating film on the unclamped wafer during a second deposition phase.

[0093] In application example 22, the subject matter of application example 21 includes the wafer having a non-zero wafer bow during the second deposition stage, the non-zero wafer bow being caused by deposition of a first portion of the insulating film on the wafer.

[0094] In application example 23, the subject matter of application examples 21-22 further includes determining a ratio of a thickness of the first portion of the insulating film to a thickness of the second portion of the insulating film based on a predetermined thickness profile of the wafer after the second deposition stage.

[0095] Application example 24 is at least one machine-readable medium including instructions that, when executed by a processing circuit configuration, cause the processing circuit configuration to perform operations to implement any of applications 1-23.

[0096] Application Example 25 is an apparatus including means for carrying out any one of Application Examples 1 to 23.

[0097] Application Example 26 is a system for implementing any one of Application Examples 1 to 23.

[0098] Application Example 27 is a method for carrying out any one of Application Examples 1 to 23.

[0099] Throughout this specification, examples may include components, operations, or structures described as one example. Although individual operations of one or more methods are illustrated and described as separate operations, one or more individual operations may be performed simultaneously, and the operations need not be performed in the order illustrated. Structures and functions presented as separate components for example configurations may be implemented as combined structures or parts. Similarly, structures and functions presented as single parts may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter of this specification.

[0100] The embodiments described herein are described in sufficient detail to enable those skilled in the art to practice the teachings of the present disclosure. Other embodiments may be used and derived such that structural and logical substitutions and changes may be made without departing from the scope of the present disclosure. Thus, the detailed description should not be taken in a limiting sense, and the scope of the various embodiments is defined only by the appended claims, together with the full scope of equivalents to which they are entitled.

[0101] The claims may not recite all of the features disclosed herein, because embodiments feature a subset of the features. Moreover, embodiments may include fewer features than are disclosed in a particular example. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

[0102] The term "or" as used herein may be interpreted in either an inclusive or exclusive sense. Also, multiple examples may be provided for a resource, operation, or structure described herein as an example. Moreover, the boundaries between various resources, operations, modules, engines, and data stores are somewhat arbitrary, and specific operations are described in specific example configurations. Other allocations of functionality are contemplated and may fall within the scope of various embodiments of the disclosure. In general, structures and functions presented as separate resources in an example configuration may be used as combined structures or resources. Similarly, structures and functions presented as a single resource may be used as separate resources. These and other variations, modifications, additions, and improvements fall within the scope of the embodiments of the disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative and not restrictive.

Claims

1. 1. A method for modulating film growth on a wafer, comprising: depositing a first portion of a film on a wafer disposed on a pedestal within a processing chamber during a first deposition phase; depositing a second portion of the film on the wafer during a second deposition phase, wherein the wafer is unclamped from the pedestal prior to and / or during the first and / or second deposition phase and remains unclamped during and / or during the first and / or second deposition phase.

2. 10. The method of claim 1 further comprising:

11. The method of claim 10, further comprising clamping the wafer to the pedestal prior to the first deposition step, the wafer remaining clamped to the pedestal during the first deposition step.

3. 3. The method of claim 2, The method, wherein the wafer has a non-zero wafer bow during the second deposition stage.

4. 4. The method of claim 3, The method, wherein the non-zero wafer bow is caused by deposition of the first portion of the film on the wafer.

5. 4. The method of claim 3 further comprising: mechanically adjusting a position of the wafer on the pedestal to generate at least a portion of the non-zero wafer bow.

6. 3. The method of claim 2 further comprising: clamping the wafer to the pedestal using an electrostatic chuck (ESC) during the first deposition stage.

7. 2. The method of claim 1 , The method, wherein during at least one of the first deposition stage and the second deposition stage, the wafer has a non-zero wafer bow.

8. 2. The method of claim 1 , The method, wherein the wafer is unclamped prior to the first deposition step and remains unclamped during the first deposition step.

9. 9. The method of claim 8, The method wherein the wafer remains unclamped during the second deposition step.

10. 9. The method of claim 8, A method wherein the wafer is clamped prior to the second deposition step and remains clamped during the second deposition step.

11. 10. The method of claim 1 further comprising: determining a ratio of a thickness of the first portion of the film to a thickness of the second portion of the film based on an amount of wafer bow of the wafer obtained after the wafer is unclamped.

12. 10. The method of claim 1 further comprising: determining a ratio of a thickness of the first portion of the film to a thickness of the second portion of the film based on a predetermined thickness profile of the wafer after the second deposition stage.

13. 10. The method of claim 1 further comprising: maintaining a constant temperature within the chamber during the first and second deposition stages.

14. 10. The method of claim 1 further comprising: repeating at least one of the first and second deposition steps to form the film.

15. 10. The method of claim 1 further comprising: forming a first predetermined profile of the first portion of the film during the first deposition phase; forming a second predetermined profile of the second portion of the film during the second deposition stage, the first predetermined profile and the second predetermined profile being different.

16. 2. The method of claim 1 , A method according to claim 1, wherein a thickness of at least one of the first and second portions of the film is constant in a radial direction of the wafer.

17. 2. The method of claim 1 , a thickness of the first portion of the film is constant in a radial direction of the wafer; a thickness of the second portion of the membrane is constant in the radial direction of the wafer; The method, wherein the thickness of the first portion and the thickness of the second portion are different from one another.

18. 1. A method for modulating film growth on a wafer, comprising: Clamping the wafer to a pedestal in a plasma enhanced chemical vapor deposition (PECVD) chamber; depositing a first portion of an insulating film on the clamped wafer during a first deposition stage; unclamping the wafer after the first deposition step; depositing a second portion of the insulating film on the unclamped wafer during a second deposition phase; A method comprising:

19. 20. The method of claim 18, The method of claim 1, wherein the wafer has a non-zero wafer bow during the second deposition stage, the non-zero wafer bow being caused by deposition of the first portion of the insulating film on the wafer.

20. 20. The method of claim 18 further comprising: determining a ratio of a thickness of the first portion of the insulating film to a thickness of the second portion of the insulating film based on a predetermined thickness profile of the wafer after the second deposition stage.

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