MEMORY DEVICE HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING SAME - Patent application

Abstract

A three-dimensional memory device having vertical transistors and a method for forming the same are disclosed. In one example, the memory device includes an array of memory cells each including a vertical transistor. Along a first direction, one of the vertical transistors is disposed between two of the isolation structures in a plan view. Each of the isolation structures includes a protrusion, and the isolation structure and the corresponding protrusion are integral. The memory device also includes a plurality of bit lines including at least one conductive layer. At least one conductive layer is disposed between two protrusions of two isolation structures and in contact with one of the vertical transistors to couple one of the bit lines with one of the vertical transistors.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Application No. 63 / 340,686, filed May 11, 2022, which is incorporated herein by reference in its entirety.

[0002] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to methods for forming memory devices having vertical transistors, memory devices, and memory systems thereof. [Background technology]

[0003] The scalability of planar memory cells to smaller sizes depends on improvements in process technology, circuit design, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become increasingly difficult and expensive. As a result, the memory density of planar memory cells reaches upper limits.

[0004] To address the memory density limitations of planar memory cells, three-dimensional (3D) memory architectures have been introduced. Thus, the introduction of 3D memory architectures has provided a promising solution to the limitations of planar memory cells. Summary of the Invention [Means for solving the problem]

[0005] SUMMARY OF THE DISCLOSURE Disclosed herein are embodiments of 3D memory devices and methods for forming the same.

[0006] In some embodiments, the memory device may include an array of memory cells each including a vertical transistor. Along a first direction, one of the vertical transistors may be disposed between two of the isolation structures in a plan view. Each of the isolation structures may include a protrusion, and the isolation structure and the corresponding protrusion may be integral. The memory device may include a plurality of bit lines including at least one conductive layer. The at least one conductive layer may be disposed between two protrusions of two isolation structures and in contact with one of the vertical transistors to couple one of the bit lines with one of the vertical transistors.

[0007] In some implementations, the plan view is based on a first plane along the first direction, a projection of the at least one conductive layer disposed between the two protrusions onto a second plane that is substantially free of overlap with a projection of each of the two isolation structures onto the second plane, and the second plane is orthogonal to the first plane.

[0008] In some implementations, the memory device may further include a plurality of word lines extending in a first direction and configured to connect the gates of the vertical transistors, wherein a depth of one of the word lines is less than a depth of one of the isolation structures.

[0009] In some implementations, the memory device may further include a plurality of storage units, one of which is coupled to a corresponding one of the vertical transistors on the opposite side of the bit line.

[0010] In some implementations, one of the storage units may include a capacitor.

[0011] In some implementations, the capacitor is disposed in one or more interlayer dielectric (IDL) layers on opposite sides of the bitline.

[0012] In some implementations, the array of memory cells is disposed in the main memory area. The memory device may further include a capacitor contact disposed in a peripheral area outside the main memory area and electrically connected to the capacitor in the main memory area, the capacitor contact extending along a third direction in which the vertical transistor extends and including a seam portion, and a sidewall of the capacitor contact including an offset shape at the seam portion.

[0013] In some implementations, a surface of the at least one conductive layer of the bit line is substantially flush with surfaces of the two protrusions of the two isolation structures.

[0014] In some implementations, the at least one conductive layer may include a contact layer disposed between the two protrusions and contacting one of the vertical transistors, and a metal layer disposed between the two protrusions and in contact with the contact layer.

[0015] In some implementations, the contact layer may include a silicide and the metal layer may include tungsten.

[0016] In some implementations, the at least one conductive layer may include an interconnect layer disposed between the two protrusions and in contact with one of the vertical transistors.

[0017] In some implementations, the interconnect layer is disposed in the main memory area and configured to connect to one of the vertical transistors, and the sacrificial layer is disposed in a peripheral area outside the main memory area, and a surface of the interconnect layer in the main memory area is substantially coplanar with a surface of the sacrificial layer in the peripheral area.

[0018] In some implementations, an oxide pad layer is disposed in the peripheral area and beneath the sacrificial layer.

[0019] In some implementations, the interconnect layer may include polysilicon.

[0020] In some implementations, the surface of the interconnect layer is substantially coplanar with the surfaces of the two protrusions of the two physical structures.

[0021] In some implementations, the bitlines may further include a metal layer disposed in one or more interlevel dielectric (ILD) layers adjacent and in contact with the interconnect layer.

[0022] In some implementations, the interconnect layer extends continuously adjacent one of the vertical transistors in a second direction orthogonal to the first direction.

[0023] In some implementations, the metal layer may include metal points disposed in the interconnect layer.

[0024] In some implementations, the interconnect layers are separated in a second direction that is orthogonal to the first direction, and the metal layers can include metal traces connecting the interconnect layers.

[0025] In some implementations, the array of memory cells is arranged in a first semiconductor structure, and the memory device may further include a second semiconductor structure bonded to the first semiconductor structure and including peripheral circuitry, the peripheral circuitry coupled to the array of memory cells through bit lines and configured to control it.

[0026] In some further aspects, a memory system is provided. The memory system may include a memory device, the memory device includes a first semiconductor structure configured to store data and including a peripheral circuit, a second semiconductor structure bonded to the first semiconductor structure, and including an array of memory cells each including a vertical transistor, along a first direction, one of the vertical transistors being disposed between two of the isolation structures in a plan view, each of the isolation structures including a protrusion, and the isolation structure and the corresponding protrusion being integral, and a plurality of bit lines including at least one conductive layer, the at least one conductive layer being disposed between two protrusions of the two isolation structures and in contact with one of the vertical transistors to couple one of the bit lines with one of the vertical transistors, and the memory cells are coupled to the peripheral circuit through the bit lines. The memory system may further include a memory controller coupled to the memory device and configured to control the memory cells through the peripheral circuit.

[0027] In some further aspects, a method of forming a memory device is provided, which may include forming a plurality of isolation structures, forming an array of memory cells each including a vertical transistor, one of the vertical transistors being disposed in a plan view between two of the isolation structures along a first direction perpendicular to a second direction along which the isolation structures extend, forming a plurality of protrusions on one of the isolation structures each, and forming a plurality of bit lines including at least one conductive layer, the at least one conductive layer being disposed in a recess between two protrusions of the two isolation structures and in contact with one of the vertical transistors to couple one of the bit lines with one of the vertical transistors.

[0028] In some implementations, the method may further include forming a plurality of capacitors in one or more inter-layer dielectric (IDL) layers, one of the capacitors being connected to a corresponding one of the vertical transistors on an opposite side of the bit line.

[0029] In some implementations, the array of memory cells and the capacitors are arranged in the main memory area, and the method may further include forming a capacitor contact in a peripheral area outside the main memory area and electrically connected to one of the capacitors connected to one of the vertical transistors in the main memory area, the capacitor contact extending along a third direction in which the vertical transistors extend and including a seam portion, and a sidewall of the capacitor contact including an offset shape at the seam portion.

[0030] In some implementations, forming the plurality of isolation structures may include preparing a substrate including a device layer, a handle layer, and a buried oxide (BOX) layer between the device layer and the handle layer; removing first portions of the device layer and the handle layer to form a plurality of first trenches along a second direction, at least through the BOX layer; and filling each of the plurality of first trenches with a first dielectric material to form an isolation structure in the substrate.

[0031] In some implementations, the method may further include removing a second portion of the device layer to form a plurality of second trenches along the first direction, and forming the memory cells may include forming vertical transistors corresponding to the second trenches, and the method may further include forming a plurality of word lines each corresponding to one of the second trenches and configured to connect gates of the vertical transistors in a row of the array of memory cells.

[0032] In some implementations, the depth of one of the second trenches is less than the depth of one of the first trenches.

[0033] In some implementations, the step of forming the protrusions may include bonding the substrate to a carrier substrate on the front side of the substrate and removing a remaining handle layer of the substrate to expose the BOX layer and the isolation structures, one end of each of the isolation structures forming a protrusion and a recess being formed between the two protrusions of the two isolation structures.

[0034] In some implementations, the recess is a third trench extending along the second direction.

[0035] In some implementations, the step of forming the plurality of bit lines may include removing a portion of the BOX layer in the third trench that contacts one of the vertical transistors, and depositing at least one conductive layer in the third trench, wherein a surface of the at least one conductive layer is substantially flush with surfaces of the two protrusions of the isolation structure.

[0036] In some implementations, the at least one conductive layer may include a contact layer disposed in the third trench and in contact with one of the vertical transistors, and a metal layer disposed in the third trench in contact with the contact layer.

[0037] In some implementations, the contact layer may include a silicide and the metal layer may include tungsten.

[0038] In some implementations, forming the plurality of isolation structures may include preparing a transfer substrate including a silicon substrate, a cut layer in the silicon substrate, and an oxide pad layer on the silicon substrate; forming a sacrificial layer on the oxide pad layer; removing portions of the oxide pad layer and the sacrificial layer in the device layer of the transfer substrate to form a plurality of fourth trenches along the second direction; filling each of the plurality of fourth trenches with a second dielectric material to form an isolation structure; splitting the device layer from the transfer substrate along the cut layer; bonding a front side of the device layer to a carrier substrate to form a first semiconductor structure; and removing a back side of the device layer to expose the isolation structures.

[0039] In some implementations, the portion of the oxide pad layer and the sacrificial layer that is removed is a first portion of the oxide pad layer and the sacrificial layer where the array of memory cells is located in the main memory area, and a second portion of the oxide pad layer and the sacrificial layer remains in a peripheral area outside the main memory area.

[0040] In some implementations, the method may further include implanting ions into the transfer substrate to a depth to form a cutting layer in the transfer substrate.

[0041] In some implementations, the method may further include removing portions of the first semiconductor structure to form a plurality of fifth trenches along the first direction, and forming the memory cells may include forming vertical transistors corresponding to the fifth trenches, and the method may further include forming a plurality of word lines each corresponding to one of the fifth trenches and configured to connect gates of the vertical transistors in a row of the array of memory cells.

[0042] In some implementations, the step of forming the protrusions may include bonding a front side of the first semiconductor structure to a base substrate to form a second semiconductor structure; removing a portion of the second semiconductor structure to expose a sacrificial layer; and using a mask, removing a portion of the sacrificial layer and the oxide pad layer to expose the vertical transistor and the isolation structures, where one end of each of the isolation structures forms a protrusion and a recess is formed between the two protrusions of the two isolation structures.

[0043] In some implementations, the depth of one of the fifth trenches is less than the depth of one of the isolation structures.

[0044] In some implementations, the recess is a sixth trench extending along the second direction.

[0045] In some implementations, the step of forming the plurality of bit lines may further include depositing an interconnect layer in the sixth trench in contact with one of the vertical transistors, wherein a surface of the interconnect layer is substantially flush with surfaces of the two protrusions of the isolation structure and the at least one conductive layer includes the interconnect layer, and forming a metal layer in contact with the interconnect layer in one or more interlayer dielectric (ILD) layers.

[0046] In some implementations, the interconnect layer may include polysilicon and the metal layer may include tungsten.

[0047] In some implementations, the metal layer may include metal points on the interconnect layer.

[0048] In some implementations, the depth of one of the fifth trenches is approximately equal to the depth of one of the isolation structures.

[0049] In some implementations, the step of forming the multiple bit lines may include depositing an interconnect layer in the recess and in contact with one of the vertical transistors, wherein a surface of the interconnect layer is substantially flush with surfaces of the two protrusions of the isolation structure and the at least one conductive layer includes the interconnect layer, and forming a metal layer in one or more interlayer dielectric (ILD) layers and in contact with the interconnect layer.

[0050] In some implementations, the interconnect layer may include polysilicon and the metal layer may include tungsten.

[0051] In some implementations, the interconnect layers are separated in the second direction and the metal layer may include metal traces connecting the interconnect layers.

[0052] In some implementations, forming the plurality of isolation structures may include preparing a transfer substrate including a cut layer in a silicon substrate, a device layer including an oxide pad layer on the silicon substrate, and a sacrificial layer on the oxide pad layer; splitting the device layer from the transfer substrate along the cut layer; bonding a front side of the device layer to a carrier substrate to form a third semiconductor structure; removing a portion of the third semiconductor structure to form a plurality of seventh trenches along the second direction; and filling each of the plurality of seventh trenches with a third dielectric material to form an isolation structure.

[0053] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0054] [Figure 1] FIG. 1 illustrates distortion of memory cells in a memory device leading to failure of the memory device along the bit line direction. [Figure 2A]1 is a schematic diagram of a cross-section of a 3D memory device according to some embodiments of the present disclosure. [Figure 2B] 1 is a schematic diagram of a cross section of another 3D memory device in accordance with some embodiments of the present disclosure. [Diagram 3] FIG. 1 is a schematic diagram of an example system having a memory device in accordance with some aspects of the present disclosure. [Figure 4] FIG. 2 is a schematic diagram of an exemplary memory device including peripheral circuitry and an array of memory cells each having a vertical transistor, in accordance with some aspects of the disclosure. [Diagram 5] FIG. 1 is a schematic circuit diagram of an exemplary memory device including peripheral circuitry and an array of dynamic random access memory (DRAM) cells in accordance with some aspects of the disclosure. [Figure 6] 1 is a plan view of an exemplary array of memory cells each including a vertical transistor in a memory device according to some aspects of the disclosure. [Figure 7] FIG. 1 is a perspective view that illustrates a schematic diagram of an exemplary 3D memory device including protrusions for forming self-aligned bitlines, in accordance with some aspects of the present disclosure. [Figure 8] 1 is a flowchart of an exemplary method for forming a 3D memory device having self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 9A] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 9B] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 9C] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 9D] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 9E] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 9F] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 10] 1 is a flowchart of an exemplary method for forming an isolation structure in a 3D memory device according to some aspects of the disclosure. [Figure 11A] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 11B] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 11C] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 11D] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 11E] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 11F] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 11G] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 11H] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 11I] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 11J] 1A-1C are schematic diagrams of an example fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 12A] 1A-1C are schematic diagrams of another exemplary fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 12B] 1A-1C are schematic diagrams of another exemplary fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 12C] 1A-1C are schematic diagrams of another exemplary fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 12D] 1A-1C are schematic diagrams of another exemplary fabrication process for forming a 3D memory device with self-aligned bitlines in accordance with some aspects of the present disclosure. [Figure 13] 1 is a flowchart of another example method for forming an isolation structure in a 3D memory device in accordance with some aspects of the present disclosure. [Figure 14A] 1A-1C are schematic diagrams of yet another exemplary fabrication process for forming isolation structures in a 3D memory device in accordance with some aspects of the present disclosure. [Figure 14B] 1A-1C are schematic diagrams of yet another exemplary fabrication process for forming isolation structures in a 3D memory device in accordance with some aspects of the present disclosure. [Figure 14C] 1A-1C are schematic diagrams of yet another exemplary fabrication process for forming isolation structures in a 3D memory device in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0055] Embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0056] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements may be used without departing from the scope of the present disclosure. The present disclosure may also be utilized in various other applications. The functional and structural features as described in the present disclosure may be combined, coordinated, and modified with one another in ways not specifically shown in the drawings, such that such combinations, coordination, and modifications are within the scope of the present disclosure.

[0057] In general, terms may be understood at least in part from their usage in context. For example, the terms "at least one" and "one or more" may be used herein to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey a singular use or to convey a plural use, depending at least in part on the context. In addition, the terms "based on" and "according to" may be understood as not necessarily intended to convey an exclusive set of factors, but may instead allow for the presence of additional factors, again not necessarily expressly described, depending at least in part on the context.

[0058] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure should be interpreted in the broadest possible manner, such that "on" not only means "directly on" something, but can also include the meaning of "on" something with an intermediate thing or layer in between, and such that "on" or "covering" not only means "on" or "covering" something, but can also include the meaning of "on" or "covering" something without an intermediate thing or layer in between (i.e., directly on something).

[0059] Additionally, spatial relationship terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or thing to another element or thing as depicted in the figures. The spatial relationship terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein may be interpreted accordingly.

[0060] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself may be patterned. Materials added onto the substrate may be patterned or left unpatterned. Additionally, substrates may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, substrates may be made from non-conductive materials, such as glass, plastic, or sapphire wafers.

[0061] As used herein, the term "layer" refers to a portion of material that includes a region of thickness. A layer may extend over the entirety of an underlying or overlapping structure, or may have an extent that is less than the extent of the underlying or overlapping structure. Additionally, a layer may be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal surfaces between the top and bottom surfaces of a continuous structure, or on the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers within, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0062] Transistors serve as the primary switch or selection device in memory cells of some memory devices, including DRAM. However, planar transistors commonly utilized in current memory cells have a horizontal structure featuring a buried wordline in a substrate and a bitline above it. This design results in a lateral arrangement of the transistor's source and drain, which can increase the transistor's footprint. In addition, the planar transistor design complicates the layout of interconnected structures, which limits the pitch of the wordline and bitline, increasing fabrication complexity and reducing manufacturing yields.

[0063] Furthermore, in some memory device architectures, such as DRAM, the drains of memory cells are usually brought out using a backside process to form a series of bitlines. However, the wafer bonding process can pose significant challenges to backside lithography alignment. Conventional implantation techniques are constrained by performance requirements and cannot be directly applied to bitline formation. For example, the drains at the backside need to be activated using highly doped polysilicon at high temperatures to connect with metal to form the bitlines. This results in stringent lithography alignment requirements. Moreover, the wafer bonding process can increase the complexity of lithography alignment, as it can cause wafer deformation, leading to additional overlay residues. Stress from the front layer can cause some pattern distortion and misalignment from the lithography mask. As a result, the effective process window for lithography alignment is reduced.

[0064] As shown in FIG. 1, when the strain exceeds a certain level, the drain of the memory cell may be misaligned from the metal for bit line pick-up. The term "bit line pick-up" herein may refer to the process of locating and aligning the drain of the memory device to interface with the metal. This misalignment may lead to failure along the bit line direction. Moreover, the degree of strain of memory cells at different positions may be different, causing the contact area between the memory cell and the metal to vary. As a result, different resistor-capacitor (RC) delays may result from the memory cells, which greatly affects the uniformity of the performance of the memory device.

[0065] To address one or more of the aforementioned problems, the present disclosure introduces an approach in which vertical transistors replace traditional planar transistors as switch and selection devices in 3D memory cell arrays. Compared with planar transistors, vertically arranged transistors (i.e., drain and source overlap in plan view) can reduce the area of ​​the transistor and simplify the layout of the interconnect structure, thereby lowering the fabrication complexity and improving the yield. The vertical structure of the transistor also allows the bit line and the storage unit (such as a capacitor) to be arranged on opposite sides of the transistor in the vertical direction (e.g., one above the transistor and the other below the transistor), thereby increasing the process margin of the bit line and reducing the coupling capacitance between the bit line and the storage unit.

[0066] Moreover, to address the problem of pattern misalignment, the present disclosure provides a protrusion in the 3D memory device that allows the self-alignment of the bit line. In the memory device, a recess can be formed between two of the protrusions and above the vertical transistor. By utilizing the recess, the position of the bit line can be easily located and formed accordingly. This approach eliminates the need for a lithography process for bit line pick-up, thereby increasing the effective process window. Furthermore, this approach eliminates the problem of insufficient bit line pick-up overlay window brought about by the bonding process. Finally, the proposed approach can simplify the process flow, reduce the cost, and eliminate the need for an additional lithography mask.

[0067] Several implementations of the present disclosure will now be described with reference to the accompanying drawing illustrations, including FIGS. 2A-14C.

[0068] According to some aspects of the present disclosure, memory cells including a memory cell array having vertical transistors may be introduced. The memory cell array and the peripheral circuits of the memory cell array may be formed on different wafers and bonded together face-to-face. Thus, the thermal budget for fabricating the memory cell array does not affect the fabrication of the peripheral circuits. The stacked memory cell array and the peripheral circuits may also reduce the chip size compared to a side-by-side arrangement, thereby improving the array efficiency. In some implementations, more than one memory cell array may be stacked on top of each other using bonding techniques to further increase the array efficiency. In some implementations, the word lines and bit lines may be placed close to the bonding boundary, and they may be coupled to the peripheral circuits through a large number (e.g., millions) of parallel bonding contacts that span the bonding boundary, which may establish a direct, short-distance (e.g., micron-level) electrical connection between the memory cell array and the peripheral circuits, and increase the throughput and input / output (I / O) speed of the memory device.

[0069] 2A shows a schematic diagram of a cross section of a 3D memory device 200 according to some embodiments of the disclosure. The 3D memory device 200 may represent an example of a bonded chip. The components of the 3D memory device 200 (e.g., a memory cell array and peripheral circuits) may be formed separately on different substrates and then combined to form a bonded chip. The 3D memory device 200 may include a first semiconductor structure 202 that includes the peripheral circuits of the memory cell array. In some implementations, the 3D memory device 200 may also include a second semiconductor structure 204 that includes the memory cell array.

[0070] The peripheral circuits (also referred to as "control and sensing circuits") may include any suitable digital, analog, and / or mixed-signal circuits used to facilitate the operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., row decoder and column decoder), a sense amplifier, a driver (e.g., word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., subcircuit) of the functional circuits mentioned above, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) of the circuit. According to some implementations, the peripheral circuits in the first semiconductor structure 202 may use complementary metal oxide semiconductor (CMOS) technology, which may be implemented, for example, in a logic process (e.g., technology nodes of 90 nm, 65 nm, 60 nm, 45 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.).

[0071] As shown in FIG. 2A, the 3D memory device 200 may include a first semiconductor structure 204 including an array of memory cells (memory cell array) that can use transistors as switches and selection devices. In some implementations, the memory cell array may include an array of DRAM cells. For ease of explanation, in this disclosure, a DRAM cell array is used as an example to describe the memory cell array. However, it may be understood that the memory cell array is not limited to a DRAM cell array, but may include any other suitable type of memory cell that can use transistors as switches and selection devices, such as a phase change memory (PCM) cell array, a static random access memory (SRAM) cell array, a ferroelectric random access memory (FRAM®) cell memory, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, or any combination thereof, to name a few.

[0072] The second semiconductor structure 204 may be a DRAM device in which memory cells are provided in the form of an array of DRAM cells. In some implementations, each DRAM cell includes a capacitor for storing a bit of data as a positive or negative charge, as well as one or more transistors (also known as pass transistors) that control (e.g., switch and select) access to it. In some implementations, each DRAM cell is a one-transistor-one-capacitor (1T1C) cell. Because the transistor always leaks a small amount of charge, the capacitor slowly discharges and loses the stored information. Therefore, according to some implementations, the DRAM cell must be refreshed to retain the data, for example by peripheral circuitry in the first semiconductor structure 202.

[0073] 2A, the 3D memory device 200 further includes a bonding boundary 206 vertically (vertically, e.g., in the z-direction of FIG. 2A) between the first semiconductor structure 202 and the second semiconductor structure 204. As described in more detail below, the first semiconductor structure 202 and the second semiconductor structure 204 may be fabricated separately (and in some implementations in parallel) such that the thermal budget for fabricating one of the first semiconductor structure 202 and the second semiconductor structure 204 does not limit the process for fabricating the other of the first semiconductor structure 202 and the second semiconductor structure 204. Moreover, a large number of interconnects (e.g., bonding contacts) can be formed through the bonding boundary 206 to establish direct, short-distance (e.g., micron-level) electrical connections between the first semiconductor structure 202 and the second semiconductor structure 204, rather than a long-distance (e.g., millimeter or centimeter-level) chip-to-chip data bus on a circuit board such as a printed circuit board (PCB), thereby eliminating chip interface delays and achieving high-speed I / O throughput with low power consumption. Data movement between a memory cell array in the second semiconductor structure 204 and peripheral circuits in the first semiconductor structure 202 can be performed through interconnects (e.g., bonding contacts) across the bonding boundary 206. By vertically integrating the first semiconductor structure 202 and the second semiconductor structure 204, the chip size can be reduced and memory cell density can be increased.

[0074] It may be understood that the relative positions of the stacked first semiconductor structure 202 and second semiconductor structure 204 are not limited. Thus, FIG. 2B shows a schematic diagram of a cross section of another exemplary 3D memory device 201 according to some implementations. Unlike the 3D memory device 200 of FIG. 2A, in which the second semiconductor structure 204 including the memory cell array is on the first semiconductor structure 202 including the peripheral circuit, in the 3D memory device 201 of FIG. 2B, the first semiconductor structure 202 including the peripheral circuit is on the second semiconductor structure 204 including the memory cell array. Nevertheless, according to some implementations, a bonding boundary 206 is formed vertically between the first semiconductor structure 202 and the second semiconductor structure 204 in the 3D memory device 201, and the first semiconductor structure 202 and the second semiconductor structure 204 are joined vertically through bonding (e.g., hybrid bonding). Hybrid bonding, also known as "metal / dielectric hybrid bonding," is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as a solder or adhesive) that can simultaneously obtain metal-metal (e.g., copper-to-copper) and dielectric-to-dielectric (e.g., silicon oxide-to-silicon oxide) bonding. Data transfer between the memory cell array in the second semiconductor structure 204 and the peripheral circuitry in the first semiconductor structure 202 can be performed through interconnects (e.g., bonding contacts) that span the bonding boundary 206.

[0075] It should be noted that x, y, and z axes are included in Figures 2A and 2B to further illustrate the spatial relationships of the components of the 3D memory devices 200 and 201. The substrate of the 3D memory device may include two elongated surfaces extending laterally in the xy plane: a top surface on the front side of the wafer on which the semiconductor devices may be formed, and a bottom surface on the back side opposite the front side of the wafer. The z axis is orthogonal to each of the x and y axes.

[0076] As used herein, whether a component (e.g., a layer or device) is "in contact with," "above," or "below" another component (e.g., a layer or device) of a 3D memory device is determined relative to the substrate of the 3D memory device in the z-direction (a vertical direction perpendicular to the xy plane, e.g., the thickness direction of the substrate) when the substrate is disposed on the bottom-most surface of the 3D memory device in the z-direction. The same ideas for describing spatial relationships are applied throughout this disclosure. Additionally, in the description of this disclosure, the term "depth" may be used to indicate a distance or length from a top or bottom surface of one reference item (e.g., a substrate) along the z-direction.

[0077] FIG. 3 illustrates a schematic diagram of an exemplary system 300 having a memory device according to some aspects of the disclosure. The system 300 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage. As shown in FIG. 3, the system 300 may include a host 302 and a memory system 304 having one or more memory devices 306 and a memory controller 308. The host 302 may be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 302 may be configured to transmit data to the memory device 306 and receive data from the memory device 306.

[0078] The memory device 306 can be any memory device disclosed herein, such as the 3D memory devices 200 and 201. In some implementations, as described in more detail below, the memory device 306 may include an array of memory cells each including a vertical transistor, and may further include self-aligned bitlines formed in the memory device between two overhangs and above the vertical transistors.

[0079] According to some aspects, a memory controller 308 may be coupled to the memory device 306 and the host 302 and may be configured to control the memory device 306. The memory controller 308 can manage data stored in the memory device 306 and communicate with the host 302. The memory controller 308 may be configured to control operations of the memory device 306, such as read, write, and refresh operations. The memory controller 308 may also be configured to manage various functions related to data stored or to be stored in the memory device 306, including, but not limited to, refresh and timing control, command / request translation, buffers and schedules, and power management.

[0080] In some implementations, the memory controller 308 may be further configured to determine the maximum memory capacity, number of memory banks, memory type and speed, data depth and data width of memory particles, and other important parameters that the computer system can use. Any other suitable functions may also be performed by the memory controller 308. The memory controller 308 may communicate with an external device (e.g., the host 302) according to a particular communication protocol. For example, the memory controller 308 may communicate with the external device through at least one of a variety of interface protocols, such as a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0081] 4 illustrates a schematic diagram of an exemplary memory device 400 including a peripheral circuit and an array of memory cells each having a vertical transistor according to some aspects of the disclosure. The memory device 400 may include a memory cell array 401 and a peripheral circuit 402 coupled to the memory cell array 401. The 3D memory devices 200 and 201 may be examples of memory devices 400 in which the memory cell array 401 and the peripheral circuit 402 may be included in the first semiconductor structure 202 and the second semiconductor structure 204, respectively. The memory cell array 401 may be any suitable memory cell array, such that each memory cell 408 may include a vertical transistor 410 and a storage unit 412 coupled to the vertical transistor 410. In some implementations, the memory cell array 401 may be a DRAM cell array, and the storage unit 412 may be a capacitor for storing an electric charge as binary information stored by each DRAM cell. It may also be understood that the memory cell array 401 may be implemented in another format (such as a PCM cell array) and the storage unit 412 may be implemented in a corresponding format (such as a PCM element).

[0082] 4, the memory cells 408 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 400 may include word lines 404 coupling the peripheral circuitry 402 and the memory cell array 401 for controlling switches of vertical transistors 410 in the memory cells 408 located in the rows, and bit lines 406 coupling the peripheral circuitry 402 and the memory cell array 401 for transmitting data to and / or receiving data from the memory cells 408 located in the columns. That is, each word line 404 is coupled to a respective row of the memory cells 408, and each bit line is coupled to a respective column of the memory cells 408.

[0083] Without being inconsistent with the scope of the present disclosure, a vertical transistor 410, such as a vertical metal oxide semiconductor field effect transistor (MOSFET), can replace a conventional planar transistor as a pass transistor of a memory cell 408 to reduce the area occupied by the pass transistor, the coupling capacitance, as well as the complexity of routing the interconnect. As shown in FIG. 4, in some implementations, unlike a planar transistor whose active area is formed in a substrate, the vertical transistor 410 can include a semiconductor body 414 that extends vertically (in the z-direction) above a substrate (not shown in FIG. 4). That is, the semiconductor body 414 can extend above the top surface of the substrate to expose not only the top surface of the semiconductor body 414, but also one or more side surfaces thereof. As shown in FIG. 4, for example, the semiconductor body 414 can have a cube shape to expose its four faces.

[0084] However, it may be understood that the semiconductor body 414 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, a cross-section of the semiconductor body 414 in a plan view (e.g., in the xy plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circle (or an elliptical shape), or any other suitable shape. It may also be understood that, without being inconsistent with the scope of the present disclosure, for a semiconductor body that has a circular or elliptical cross-section in a plan view, the semiconductor body may be considered to have multiple sides, such that the gate structure is in contact with more than one side of the semiconductor body.

[0085] 4, the vertical transistor 410 may also include a gate structure 416 in contact with one or more side surfaces of the semiconductor body 414, i.e., in one or more planes of the side of the active area. In other words, the active area of ​​the vertical transistor 410, i.e., the semiconductor body 414, may be at least partially surrounded by the gate structure 416. As shown in FIG. 4, the gate structure 416 may include a gate dielectric 418 covering one or more side surfaces of the semiconductor body 414, for example, in contact with four sides of the semiconductor body 414. The gate structure 416 may also include a gate electrode 420 covering and in contact with the gate dielectric 418.

[0086] The gate dielectric 418 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. For example, the gate dielectric 418 may include silicon oxide, i.e., a gate oxide. The gate electrode 420 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 420 may include doped polysilicon, i.e., a gate poly. In some implementations, the gate electrode 420 includes multiple conductive layers, such as a W layer overlying a TiN layer. It may be understood that in some examples, the gate electrode 420 and the word line 404 may be a continuous conductive structure. In other words, the gate electrode 420 may be considered as a part of the word line 404 that forms the gate structure 416, or the word line 404 may be considered as an extension of the gate electrode 420 to be coupled to the peripheral circuitry 402.

[0087] As shown in FIG. 4, the vertical transistor 410 may further include a pair of source and drain (also known as S / D, doped regions, source and drain electrodes) formed at two ends of the semiconductor body 414 in the vertical direction (z direction), respectively. The source and drain may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). The source and drain may be separated by a gate structure 416 in the vertical direction (z direction). In other words, the gate structure 416 may be formed vertically between the source and drain. As a result, when a gate voltage applied to a gate electrode 420 of the gate structure 416 may exceed a threshold voltage of the vertical transistor 410, one or more channels (not shown) of the vertical transistor 410 may be formed in the semiconductor body 414 vertically between the source and drain. That is, according to some implementations, each channel of the vertical transistor 410 may also be formed in the vertical direction along which the semiconductor body 414 extends.

[0088] In some implementations, as shown in FIG. 4, the vertical transistor 410 can be a multi-gate transistor. That is, the gate structure 416 can contact more than one side (e.g., four sides in FIG. 4) of the semiconductor body 414 to form more than one gate, so that more than one channel can be formed between the source and drain during operation. In some implementations, the multi-gate vertical transistor can include a double-gate vertical transistor (e.g., a dual-side gate vertical transistor), a tri-gate vertical transistor (e.g., a tri-side gate vertical transistor), and a gate-all-around (GAA) vertical transistor.

[0089] Although the vertical transistor 410 is shown in FIG. 4 as a multi-gate transistor (i.e., a GAA transistor), it can be understood that the vertical transistor disclosed herein can be a single-gate transistor. That is, the gate structure 416 can be in contact with a single side of the semiconductor body 414, for example, for the purpose of increasing transistor and memory cell density. Although the gate dielectric 418 is shown as being separate from other gate dielectric materials of adjacent vertical transistors (not shown), it is also understood that the gate dielectric 418 can be part of a continuous dielectric layer having multiple gate dielectric materials of the vertical transistor. In some implementations, the source and drain are formed at two ends of the semiconductor body 414 in the vertical direction (z-direction), respectively, and therefore overlap in a plan view. Also, the metal wiring coupled to the vertical transistor 410 can be simplified because the interconnects can be routed in different planes. For example, the bit line 406 and the storage unit 412 can be formed on opposite sides of the vertical transistor 410. In one example, the bit line 406 may be coupled to a drain at the top of the semiconductor body 414 , while the storage unit 412 may be coupled to a source at the bottom of the semiconductor body 414 .

[0090] As shown in FIG. 4, a storage unit 412 may be coupled to the source of the vertical transistor 410. The storage unit 412 may include any device capable of storing binary data (e.g., 0 and 1), including, but not limited to, a capacitor for a DRAM cell and a FRAM cell, and a PCM element for a PCM cell. In some implementations, the vertical transistor 410 may control the selection and / or state switching of each storage unit 412 coupled to the vertical transistor 410. FIG. 5 shows a schematic circuit diagram of an example memory device 500 including peripheral circuits and an array of dynamic random access memory (DRAM) cells according to some aspects of the disclosure. In some implementations as shown in FIG. 5, each memory cell 408 of FIG. 4 may be a DRAM cell 502 including a transistor 504 (e.g., implemented using a vertical transistor) and a capacitor 506 (e.g., an example of the storage unit 412 in FIG. 4). The gate of transistor 504 (e.g., corresponding to gate electrode 420) may be coupled to a word line 404, the drain of transistor 504 may be coupled to a bit line 406, and the source of transistor 504 may be coupled to one electrode of a capacitor 506, the other electrode of capacitor 506 may be coupled to a low potential such as ground.

[0091] The peripheral circuits 402 may be coupled to the memory cell array 401 through bit lines 406, word lines 404, and any other suitable metal wiring. As described above, the peripheral circuits 402 may include any suitable circuitry for facilitating operation of the memory cell array 401 by applying and sensing voltage and / or current signals through the word lines 404 and bit lines 406 to and from each memory cell 408, as shown in Figure 4. The peripheral circuits 402 may include various types of peripheral circuits formed using CMOS technology.

[0092] 6 illustrates a plan view of an example array of memory cells 602 each including a vertical transistor in a memory device 600 according to some aspects of the disclosure. As shown in FIG. 6, the memory device 600 may include a number of wordlines 604 each extending in a lateral direction (the x-direction referred to as the wordline direction). The memory device 600 may also include a number of bitlines 606 each extending in another lateral direction (the y-direction referred to as the bitline direction) perpendicular to the lateral direction.

[0093] Figure 6 illustrates an example array of memory cells 408 of Figure 4. The memory cells 602 of Figure 6 may be formed at the intersections of word lines 604 and bit lines 606, although in some implementations the memory cells may not be formed at the intersections of word lines and bit lines. In some implementations, each memory cell 602 includes a vertical transistor (e.g., vertical transistor 410 of Figure 4) having a semiconductor body 608 and a gate structure 610. The semiconductor body 608 may extend in a vertical direction (z-direction, not shown) that is orthogonal to the first and second lateral directions (x- and y-directions).

[0094] As shown in FIG. 6, in some implementations, the vertical transistor may be a multi-gate transistor in which the gate structure contacts multiple sides (e.g., all four sides) of the semiconductor body (the active region in which the channel is formed). The gate structure 610 may include a gate dielectric 612 that completely surrounds the semiconductor body 608 in a plan view, and a gate electrode 614 that completely surrounds the gate dielectric 612. In some implementations, the gate dielectric 612 is oriented laterally in the bitline direction and the wordline direction between the gate electrode 614 and the semiconductor body 608. It may also be understood that FIG. 6 only illustrates an exemplary implementation of the vertical transistor. In other implementations, the vertical transistor may include a tri-gate transistor or a double-gate transistor. In other implementations, the vertical transistor disclosed herein may include a single-gate transistor (also known as a single-sided gate transistor) in an axisymmetric arrangement with respect to adjacent transistors in the bitline direction as a result of dividing a multi-gate transistor (e.g., a double-gate transistor) using trench isolation extending along the wordline direction. The present disclosure is not limited thereto.

[0095] In accordance with the scope of the present disclosure, the array of memory device 600 may further include a plurality of isolation structures 616. Each of the isolation structures 616 may include a protrusion, and along the word line direction (i.e., the x-direction in FIG. 6), a vertical transistor (such as 410 in FIG. 4) of the memory cell 602 may be disposed in a respective recess, each of which may be formed between two of the protrusions in a plan view. Each isolation structure 616 and its corresponding protrusion are integral, and the term "integral" may be used to describe that each isolation structure 616 and its protrusion may be based on the same structure, and in some examples, they may include substantially the same material. The plan view may be based on a first plane (e.g., an xz plane) defined along the word line direction. Thus, the formation of the bit lines 606 may be easily located with respect to the recesses, and the bit lines 606 may be formed in the recesses.

[0096] In some implementations, the protrusions may extend continuously in the bitline direction (i.e., the y-direction) as shown in Figure 6, while in other implementations the protrusions may be separated, for example by trench isolation, or may be discontinuous. It may also be understood that Figure 6 does not show a cross-section of memory device 600 in the same lateral plane, and that wordlines 604 and bitlines 606 may be formed in different lateral planes to simplify routing.

[0097] FIG. 7 shows a perspective view that illustrates a schematic of an exemplary 3D memory device 700 including protrusions for forming self-aligned bitlines according to some aspects of the present disclosure. In the 3D memory device 700, the bitline 702 may be formed at least partially in a recess 704 between two protrusions 706 in contact with a vertical transistor 708 of a column. The bitline 702 may be in contact with a drain of the vertical transistor 708 to couple the bitline 702 with the vertical transistor 708 in the recess 704 along the bitline direction (i.e., the y-direction in FIG. 7). Each protrusion 706 may be formed in contact with a corresponding isolation structure 712. The recess 704 and the protrusion 706 may provide a self-aligning mechanism for forming the bitline 702. In some implementations, a projection of the bitline 702, disposed between the two protrusions 706, into a second plane (e.g., an xy plane) may not overlap with a projection of each of the two isolation structures into the second plane. A second plane orthogonal to the first plane (eg, the xz plane) is defined according to the word line direction. A plurality of word lines 710 may be formed along a second lateral direction.

[0098] Through this approach, issues in known techniques can be addressed (effective process window can be increased, insufficient bitline pick-up overlay window issues caused by bonding process can be eliminated, etc.) Although the isolation structure 712 and the protrusion 706 are shown with dashed lines to indicate the position of the vertical transistor 708 in Figure 7, it can be understood that in some implementations, they may extend continuously in the bitline direction, as shown in Figure 6.

[0099] FIG. 8 shows a flowchart of an example method 800 for forming a 3D memory device with self-aligned bitlines according to some aspects of the disclosure. The method 800 proceeds to 802, where a plurality of isolation structures may be formed. Each of the isolation structures may be processed to form the protrusions 706 of FIG. 7 for alignment of the bitlines 702. At 802, a substrate 900 may be prepared. As shown in FIG. 9A, the substrate 900 may be a silicon-on-insulator (SOI) substrate including a handle layer, a device layer, and a buried oxide (BOX) layer between the device layer and the handle layer. The term "device layer" may be used to describe that a semiconductor component is formed at or within this layer.

[0100] In some implementations, the substrate 900 may be a silicon substrate, so that each of the device layer and the handle layer may include silicon, while the BOX layer may include silicon oxide and function as an insulating layer. In some implementations, to form the isolation structure 712 as shown in FIG. 7, first portions of the handle layer and the device layer may each be removed (e.g., by etching) along a first lateral direction (the y-direction referred to as the bit line direction), for example through the BOX layer, to form a trench (not shown). In some embodiments, each trench may extend continuously along the first lateral direction and include a depth by extending vertically from a top surface of the device layer to enter the handle layer. The trench may then be filled with a dielectric material, such as silicon oxide. As a result, a first laterally extending isolation structure 902 may be formed in the substrate 900, as shown in FIG. 9A.

[0101] The method 800 may proceed to 804. At 804, a plurality of memory cells (e.g., memory cell 602 of FIG. 6) may be formed. Each of the memory cells may include a vertical transistor. In some implementations, to form the vertical transistors and other suitable components (such as word lines), the second portion of the handle layer may be removed (e.g., etched from the front side) along a second lateral direction to form trenches 904, as shown in FIG. 9B. In some implementations, each trench 904 may include a depth by continuously extending along the second lateral direction and extending vertically from the top surface of the device layer until it reaches the BOX layer. In other words, the BOX layer may function as a stop layer in this process. As a result, the depth of the trenches 904 may be less than the depth of the trenches for forming the isolation structure 902 in FIG. 9A. In this disclosure, the second lateral direction is equivalent to the x-direction and may be referred to as the word line direction.

[0102] In some implementations, as shown in FIG. 9C, vertical transistors 906 may be formed at least in part in trenches 904. As described above, each vertical transistor 906 may include a semiconductor body, a gate structure, a source, and a drain (not shown). In some implementations, the semiconductor bodies may be epitaxially grown from the substrate 900 in the respective trenches 904. Fabrication processes for epitaxially growing the semiconductor bodies may include, but are not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), or any combination thereof. Thus, the semiconductor bodies may have the same material as the substrate 900. In some implementations, doped regions may be formed in the substrate 900 by ion implantation and / or thermal diffusion, which may function, for example, as the source and drain of the vertical transistor 906. The vertical transistor 906 in FIG. 9C may be provided as an example implementation of the vertical transistor 410 in FIG. 4.

[0103] 9C , each vertical transistor 906 may be formed between two isolation structures 902 in a top plan view (e.g., in the xy plane) and in a cross-sectional plan view (e.g., in the xz plane). In some implementations, a word line 908 may be formed in the trench 904, and a word line contact 910 may be formed. The word line 908 may be connected to the gate electrodes of the vertical transistors 906 in a row, while the word line contact 910 may be coupled to and controlled by the peripheral circuitry 402 of FIG.

[0104] In some implementations, a storage unit (e.g., a capacitor) and a source line 912 may be formed that are connected to the vertical transistor 906. The capacitor may be an example implementation of the storage unit 412 of FIG. 4. In some implementations, one or more interlayer dielectric (ILD) layers 901 may be formed over the top surface of the substrate 900 by depositing a dielectric material using one or more thin film deposition processes, including, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some examples, the dielectric material of the ILD layer 901 may include silicon oxide. An electrode and a capacitor dielectric may then be formed in the ILD layer 901 to function as a capacitor that contacts the vertical transistor 906 (e.g., the source of the vertical transistor 906). In some implementations, each of the electrodes may be formed to the respective source by patterning and etching an electrode hole aligned with the respective source using lithography and etching processes, and depositing a conductive material to fill the electrode hole using a thin film deposition process. In some implementations, the word lines and source lines may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the source lines may include tungsten (W).

[0105] In some examples, appropriate portions of trenches 904 may be filled with a dielectric material, such as silicon oxide, so that wordlines 908 may be electrically isolated from later-formed bitlines. Overall, vertical transistors 906 may be formed by a series of processes, including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, planarization processes (e.g., chemical mechanical planarization, CMP), and any other suitable processes.

[0106] The method 800 may proceed to 806. At 806, the substrate 900 may be processed to form a protrusion at one end of each isolated structure. In some implementations, a carrier substrate 903 (i.e., a handle substrate) may be bonded to the front side of the substrate 900 to form the semiconductor structures 905 using any suitable bonding process, such as anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding. In one example, fusion bonding may be performed between a layer of silicon and a layer of silicon, between a layer of silicon and a layer of silicon oxide, or between a layer of silicon oxide and a layer of silicon oxide, using pressure and heat. In another example, anodic bonding may be performed between a layer of silicon oxide (ion glass) and a layer of silicon, using voltage, pressure, and heat. As used herein, the term "front side" of the substrate 900 may refer to the side with the active layer (i.e., device layer) of the substrate.

[0107] After bonding, the semiconductor structure 905 may then be flipped upside down, and the substrate 900 may be on top of the carrier substrate 903. Subsequently, as shown in FIG. 9D, the top surface of the semiconductor structure 905 (i.e., the handle layer of the substrate 900 on the back side) may be removed to expose the BOX layer. In some implementations, the BOX layer may function as a stop layer in a planarization and / or etching process, and a planarization process (e.g., CMP) and / or an etching process may be performed to remove the handle layer of the substrate 900 until it is stopped by the BOX layer. Through this manner, one end of each isolation structure 902 may be exposed to form a protrusion 9022, and the remaining part of the isolation structure 902 may still remain in the substrate 900. As a result, a recess 914 may be formed between two protrusions 9022. 9D, the protrusion 9022 may protrude relative to the BOX layer in the z-direction, and the recess 914 may extend continuously in the first lateral direction (y-direction, also known as the bitline direction). In some implementations, the vertical transistor 906 may be disposed below the recess 914. As used herein, the term "protrusion" may refer to a portion that protrudes from an adjacent surface (e.g., the BOX layer), while the term "recess" may refer to a portion that is recessed from an adjacent portion.

[0108] Returning to FIG. 8 , the method 800 may proceed to 808, where a plurality of bitlines may be formed based on the protrusions 9022 of the isolation structures 902. In some implementations, one or more conductive materials may be disposed in the recesses 914 to form the bitlines. The one or more conductive materials may include polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), a silicide, or a combination thereof. For example, as shown in FIG. 9E , the BOX layer in the recesses 914 (between the protrusions 9022) may be removed, and a contact layer 916, such as a silicide layer using a silicide process, may be formed in the recesses 914. In some implementations, the contact layer 916 may be formed in the main memory area where the vertical transistors 906 are formed.

[0109] The silicidation process is a process of forming a thin film of metal silicide (also called "silicide") on the top surface of the substrate 900 by heating metal and silicon to high temperatures. Metals used in silicidation may include refractory metals such as titanium, tungsten, or cobalt. The contact layer 916 can lower the contact resistance between the vertical transistor 906 and the bit line and improve the conductivity of the bit line, which can help speed up data transmission in the memory device.

[0110] 9F, the at least one conductive layer for forming the bit line may further include a conductive layer 918 disposed on the contact layer 916 in the recess 914. In some implementations, the conductive layer 918 may be formed by depositing a conductive material, such as a metal (e.g., tungsten) or a metal compound, over the contact layer 916 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, to fill the recess 914. In some implementations, a planarization process (e.g., chemical mechanical planarization, CMP) may be performed to remove material remaining after forming the conductive layer 918 and obtain planarization of the conductive layer 918 and the protrusion 9022. In some implementations, the top surface of the conductive layer 918 may be substantially coplanar with the top surface of the protrusion 9022. Through this approach, the conductive layer 918 and the contact layer 916 may be disposed between the two protrusions 9022, and the projections of the conductive layer 918 and the contact layer 916 onto a plane (e.g., an xy plane) perpendicular to the cross-sectional plane (e.g., an xz plane) may not substantially overlap with the projections of any one of the two isolation structures onto that plane.

[0111] In some implementations, after forming the bit lines, at least a portion of the isolation structure 902 may be removed to form an opening, and the opening may be filled with tetraethyl orthosilicate (TEOS) to create a gap with a lower dielectric constant. By creating a gap between conductive lines (e.g., bit lines) in a memory device, the capacitance between the conductive lines can be reduced, which reduces signal delay and crosstalk between adjacent conductive lines. It can improve the overall performance of the device and achieve faster data transfer rates.

[0112] According to the implementations provided by the present disclosure, a self-aligned mechanism for forming bit lines can be provided. As a result, the effective process window can be further enlarged. In addition, the problem of insufficient bit line pick-up overlay window caused by the bonding process can be eliminated. This can simplify the process flow, reduce costs, and eliminate additional mask layers.

[0113] In some implementations, the memory device having the isolation structure 712 and the protrusion 706 on the isolation structure, as shown in FIG. 7, may be formed by a method different from the method shown in FIG. 9A-FIG. 9F. FIG. 10 shows a flowchart of an example method 1000 for forming an isolation structure in a 3D memory device according to some aspects of the present disclosure. At 1002 of the method 1000, a transfer substrate 1100 as shown in FIG. 11A may be provided. In some examples, the transfer substrate 1100 may include a silicon substrate. An oxide pad layer 1102 may be formed on the top surface of the transfer substrate 1100. In some implementations, an oxide pad layer 1102 including silicon oxide (e.g., thermally grown local oxidation of silicon (LOCOS)) may be formed on the transfer substrate 1100.

[0114] At 1004, a cutting layer 1104 can be formed in the transfer substrate 1100, for example, using ion implantation. In some implementations, as shown in FIG. 11A, light elements such as hydrogen ions can be implanted into the transfer substrate 1100 to a desired depth, for example, by controlling the energy of the ion implantation process, to form the cutting layer 1104 in the transfer substrate 1100. Based on the cutting layer 1104, the transfer substrate 1100 can be divided into two main parts including a device layer and a handle layer.

[0115] The method 1000 of FIG. 10 may proceed to 1006, where a sacrificial layer 1106 may be formed on the oxide pad layer 1102 of the transfer substrate 1100. In some implementations, the material of the sacrificial layer 1106 may include silicon nitride (SiN). The sacrificial layer 1106 may be used to define a pattern (location) for forming recesses. Furthermore, in the case of shallow trench isolation (STI) and silicon oxide CMP, the sacrificial layer 1106 may also be used as a stop layer to help control the depth of the trench or oxide layer being formed. For example, in an STI process, the sacrificial layer 1106 may be used as a stop layer during the CMP process to prevent over-polishing the oxide in the trench.

[0116] In some implementations, to form the isolation structure 1108, a first portion of the transfer substrate 1100 in the active area (including a first portion of the device layer and a first portion of the oxide pad layer 1102 and the sacrificial layer 1106) may be removed (e.g., using an etch) along a first lateral direction (referred to as the y-direction, bit line direction) to form a trench (not shown). The trench may be filled with a dielectric material, e.g., silicon oxide. As a result, as shown in FIG. 11B, the isolation structure 1108 in the first lateral direction may be formed in the active area. The terms "active area" and "main memory area" in this disclosure may be used interchangeably to refer to the area where the memory cells are formed.

[0117] In some implementations, by removing the second portion of the transfer substrate 1100 (including the second portion of the device layer and the second portions of the oxide pad layer 1102 and the sacrificial layer 1106), one or more dummy regions 1110 may also be defined and formed in the peripheral area of ​​the transfer substrate 1100. Openings may be formed in the peripheral area outside the main memory area and filled with a dielectric material. The dummy regions 1110 may include some dummy features, such as contacts and / or vias, that are later formed in the dummy regions 1110. These dummy features may also improve the efficiency and yield of the fabrication process while increasing the performance and reliability of the memory device.

[0118] In some implementations, a planarization / thinning process such as CMP may be performed to polish and smooth the top surface (front side) of the transfer substrate 1100 having the isolation structures 1108 to remove any remaining dielectric material. In some implementations, the top surface of the sacrificial layer 1106 may be substantially coplanar with the top surface of the isolation structures 1108.

[0119] The method 1000 of FIG. 10 may proceed to 1010. At 1010, the transfer substrate 1100 may be split at the cut layer 1104, for example, by applying a mechanical force to the transfer substrate 1100, i.e., by peeling the device layer from the transfer substrate 1100 along the cut layer 1104. It may be understood that the transfer substrate 1100 may be split at the cut layer 1104 by any suitable means, including but not limited to mechanical forces, such as thermal means, acoustic means, optical means, etc., or any combination thereof. After separation, the device layer of the transfer substrate 1100 may be flipped upside down, and the front side (i.e., active layer) of the transfer substrate 1100 may be transferred and bonded to a carrier substrate 1101 to form a semiconductor structure 1103 using a transfer bonding process. In some examples, the carrier substrate 1101 may be a silicon substrate.

[0120] Transfer bonding may include any suitable substrate / wafer bonding process, including, for example, anodic bonding and fusion (direct) bonding. It may be appreciated that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) may be formed on one or both sides of the bonding interface of the semiconductor structure 1103. For example, the silicon oxide layer 1111 may be formed using fusion bonding to form a SiO 2 -SiO 2 11A-11C 。 Isolation structures 1108 may be formed on the top surface of the carrier substrate 1101 to enable bonding. In some implementations, the backside of the semiconductor structure 1103 (i.e., the backside of the previous device layer) may be thinned. In some implementations, a planarization process such as CMP may be performed to polish and smooth the top surface of the semiconductor structure 1103 and adjust the thickness of the semiconductor structure 1103 until the backside isolation structures 1108 are exposed. Isolation structures 1108 may be formed in the memory device using various methods shown in FIG. 11A-11C .

[0121] After forming the isolation structures 1108 shown in FIG. 11C, memory cells including vertical transistors may be formed in the memory device, as in 804 of method 800, as shown in FIG. 11D-FIG. 11F. In some implementations, to form the vertical transistors and appropriate semiconductor components, a portion of the semiconductor structure 1103 may be removed (e.g., etched from the top of the semiconductor structure 1103) along a second lateral direction (e.g., x-direction) to form a trench 1112, as shown in FIG. 11D. In this disclosure, the second lateral direction is equivalent to the x-direction and may be referred to as the word line direction. In some examples, the depth of the trench 1112 (from the top surface to the bottom surface along the z-direction) may be less than the depth of each of the isolation structures 1108, as shown in FIG. 11D. In some implementations, the sacrificial layer 1106 may act as a stop layer during the removal process, and that portion of the semiconductor structure 1103 may be removed until it is stopped by the sacrificial layer 1106. The trenches 1112 may then be filled with a dielectric material, such as silicon oxide.

[0122] 11E, a portion of the dielectric material in the trench 1112 may be removed and memory cells may be formed in the trench 1112. As described above, each memory cell may include a vertical transistor 1114 having a semiconductor body, a gate structure, a source, and a drain. In some implementations, doped regions that function, for example, as the source and drain of the vertical transistor 1114 are formed in the substrate by ion implantation and / or thermal diffusion. In some implementations, the semiconductor body may be formed from a portion of the dielectric material in the trench 1112.

[0123] Similarly, each vertical transistor 1114 may be formed between two isolation structures 1108 in top view and cross-sectional view (as shown in FIG. 11E). In some implementations, word lines and word line contacts may also be formed in the dummy regions 1110. Word lines may be formed and connected to the gate electrodes of the vertical transistors, while word line contacts may be formed and coupled to and controlled by the peripheral circuitry 402 of FIG.

[0124] In some implementations, a storage unit (e.g., capacitor 1116 in FIG. 11E) and a capacitor contact 1118 may be formed to connect with the vertical transistor 1114. The capacitor 1116 may be an exemplary implementation of the storage unit 412 in FIG. 4 and may include a dielectric material having a high-k value (e.g., higher than 3.9). In some implementations, one or more interlayer dielectric (ILD) layers 1120 may be formed over the top surface of the semiconductor structure 1103, for example, by depositing a dielectric material using one or more thin film deposition processes including CVD, PVD, ALD, or any combination thereof, but not dammed. In some examples, the material of the ILD layer 1120 may include silicon oxide. Subsequently, electrodes and a capacitor dielectric material may be formed in the ILD layer 1120 to function as the capacitor 1116 in contact with and electrically connected to the vertical transistor 1114 (e.g., its source). A vertical transistor 1114 and a capacitor 1116 may be formed in the main memory area, while a capacitor contact 1118 connecting with the capacitor 1116 may be formed in the peripheral area. Thus, an electrical path from the vertical transistor 1114, the capacitor 1116 to the capacitor contact 1118 may be formed.

[0125] In some implementations, word lines and source lines may be formed and may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the word lines may include tungsten (W).

[0126] In some implementations, as shown in FIG. 11F, the front side of the semiconductor structure 1103 of FIG. 11E may be bonded to a base substrate 1105, and the carrier substrate 1101 and the silicon oxide layer 1111 on the back side of the semiconductor structure 1103 may be removed to expose the sacrificial layer 1106. The bonding and removing processes may include one or more processes as described above, and the present disclosure is not limited thereto. As a result, as shown in FIG. 11F, a semiconductor structure 1107 having a memory cell (including a storage unit and a vertical transistor 1114 formed between two isolation structures 1108) and appropriate semiconductor components may be formed on the base substrate 1105.

[0127] After formation of the semiconductor structure 1107 including the memory cell and appropriate semiconductor components, a protrusion based on the isolation structure may be formed, as in 806 of the method 800 of FIG. 8. As shown in FIG. 11G, a lithography process may be performed to pattern the front surface of the semiconductor structure 1107 using an etching mask 1122 (e.g., a photoresist mask) based on the design and / or location of the isolation structure 1108, and one or more dry etching and / or wet etching processes, such as reactive ion etching (RIE), may be performed to remove portions of the sacrificial layer 1106 and the oxide pad layer 1102 in the main memory area that cover the vertical transistor 1114 along the y direction (referred to as the bit line direction). Although FIG. 11G shows the etching mask 1122, it may be understood that other forms of masks may be applied.

[0128] As a result, one end of each isolation structure 1108 in the main memory area can be exposed, thereby forming a protrusion 1124 on each isolation structure 1108. Meanwhile, in some implementations, the sacrificial layer 1106 and the pad oxide layer 1102 in the peripheral area can remain and cover it in some regions, as shown in FIG.

[0129] 11H , a recess 1126 may be formed between the two protrusions 1124 of the isolation structure 1108 accordingly. In some implementations, the vertical transistor 1114 may be disposed below the recess 1126, and a drain (not shown) of the vertical transistor 1114 may be exposed in the recess 1126.

[0130] In some implementations, a plurality of bitlines may be formed, as in 808 of method 800. In some implementations, as shown in FIG. 11I, an interconnect layer 1128 including a conductive material may be disposed in the recess 1126 to contact the drain of the vertical transistor 1114, thereby bringing out the drain of the vertical transistor 1114 to form a portion of the bitline. In some examples, the conductive material of the interconnect layer 1128 may include polysilicon. The polysilicon layer prior to the formation of the metal layer provides a good adhesion layer for the metal layer, ensuring that the metal layer can better adhere to the layer behind while acting as a barrier layer to prevent diffusion of metal to the layer behind. Nevertheless, in some implementations, the polysilicon layer may be omitted.

[0131] In some implementations, rapid thermal annealing (RTA) may be applied to remove, reduce, or eliminate residual stress in the semiconductor structure 1107. During the fabrication process, residual stress may build up in the memory device, which may affect the performance and reliability of the memory device. RTA is used to remove the residual stress by exposing the memory device to a short burst of high temperature for a short period of time, such as a few seconds. In some implementations, a planarization process, such as CMP, may be performed on the front side of the semiconductor structure 1107 to polish and smooth the top surface of the semiconductor structure 1107 and adjust its thickness. In some implementations, the top surface of the interconnect layer 1128 may be substantially coplanar with the top surface of the two protrusions between which the interconnect layer 1128 is disposed. In some implementations, the top surface of the interconnect layer 1128 may be substantially coplanar with the top surface of the sacrificial layer 1106 in the peripheral area.

[0132] In some implementations, one or more interlayer dielectric (ILD) layers 1130 may be formed over the top surface (front side) of the semiconductor structure 1107, for example, by depositing a dielectric material using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some examples, the material of the ILD layer 1130 may include silicon oxide. In some implementations, a metal layer 1132 including a conductive material may be disposed over the interconnect layer 1128, thus forming a bit line. For example, the conductive material of the metal layer 1132 may include any suitable conductive material, such as a metal (e.g., tungsten (W)).

[0133] In some implementations, as shown in FIG. 11J, the metal layer 1132 may include metal points formed in the corresponding interconnect layer 1128. In some implementations, as shown in FIG. 11J, a suitable process may be applied to expose the capacitor contact 1118 at the top surface of the ILD layer 1130. For example, the dummy region 1110 and a portion of the ILD layer 1130 may be removed (e.g., by etching) to expose the capacitor contact 1118 in the ILD layer 1120 and form one or more holes (not shown). A conductive material may then be charged into the one or more holes such that electrical contact is made with the capacitor contact 1118 in the ILD layer 1120. The conductive material may be the same as the material that forms the capacitor contact 1118 in the ILD layer 1120. As a result, the capacitor contact 1118 faces the front side of the semiconductor structure 1107 and may be exposed. In some examples, portions of the capacitor contacts 1118 are formed at different stages so that seam portions 1134 may be formed at each capacitor contact 1118 and the sidewalls of the capacitor contacts 1118 may have offset shapes (not necessarily along straight lines) at the seam portions 1134. Through this exemplary scheme, the capacitor contacts 1118 extend along the z-direction along which the vertical transistors 1114 may be formed.

[0134] 11J provides implementations of the interconnect layer 1128 and the metal layer 1132. It can be understood that FIGs. 11I-11J merely provide example implementations according to the scope of the present disclosure, and the present disclosure is not limited thereto. For example, in some implementations, the interconnect layer 1128 can be deposited at the bottom of the depression 1126, while at the top of the depression 1126, one or more layers from the ILD layer 1130 can be omitted, as the metal layer 1132 can be deposited on the interconnect layer 1128.

[0135] In some implementations shown in FIG. 11D, formation of trench 1112 (as shown in FIG. 11D) stops at or before sacrificial layer 1106, and the depth of trench 1112 is shallower than the depth of isolation structure 1108. However, it can be understood that in some implementations, trench 1212 may penetrate sacrificial layer 1206, as shown in FIG. 12A. In some examples, a semiconductor structure 1203 similar or identical to semiconductor structure 1103 may be provided on substrate 1201. In accordance with the scope of the disclosure, a portion of semiconductor structure 1203 may be removed (e.g., etched from the front side) along a second lateral direction (e.g., x-direction) to form trench 1212, as shown in FIG. 12A, and the portion of semiconductor structure 1203 may be removed until it penetrates sacrificial layer 1206. In some examples, trench 1212 may be filled with a dielectric material, for example, silicon oxide. Subsequently, a portion of the dielectric material in trench 1212 may be removed, and memory cells may be formed in trench 1212 .

[0136] In some implementations, as shown in FIG. 12B, after forming the memory cell, the capacitor, the capacitor contact, the word line 1238, the isolation structure 1208 with the protrusion 1224, the recess 1226, etc. as the semiconductor structure 1207, the upper side of the semiconductor structure 1203 can be bonded to the base substrate 1205. Details of the fabrication process can be referred to the above description regarding FIG. 11E-FIG. 11H, and are omitted here. As shown in FIG. 12B, due to the trench 1212 penetrating the sacrificial layer 1206, each protrusion 1224 of the isolation structure 1208 may exhibit a discontinuous configuration in the bit line direction, as well as the recess 1226. Then, an interconnect layer 1228 including a conductive material may be disposed in the discontinuously shaped recess 1226 to contact the drain of the vertical transistor 1204, thereby drawing out the drain of the vertical transistor 1204. For example, the conductive material of the interconnect layer 1228 may include polysilicon. Thus, the interconnect layer 1228 as formed in the discontinuous recesses 1226 may also have a disconnected shape.

[0137] In some implementations, the semiconductor bodies of each pair of two adjacent vertical transistors (e.g., 1204A and 1204B) in the bitline direction (y-direction) may be formed by separating two semiconductor pillars using a trench isolation 1202 extending in the wordline direction (x-direction). The trench isolation 1202 and the wordlines 1238 may be staggered in the bitline direction. In some implementations, the trench isolation 1202 may be formed in the center of the semiconductor pillar (not shown) such that the resulting pairs of semiconductor bodies are line-symmetrical with respect to the trench isolation 1202, and the pairs of vertical transistors 1204 having semiconductor bodies are similarly formed when their respective gate structures are line-symmetrical with respect to the trench isolation 1202.

[0138] By splitting the double-gate vertical transistor into a single-gate vertical transistor using trench isolation 1202, the number of memory cells (and cell density) in the bit line direction can be doubled compared to a structure with double-gate vertical transistors without overly complicating the fabrication process. On the other hand, it can be understood that in some examples, the trench isolation 1202 extending in the word line direction may not be formed, so that two adjacent semiconductor bodies separated by respective trench isolations 1202 can be integrated into a single semiconductor body having two opposing sides in the bit line direction in contact with the gate structure.

[0139] In some implementations, a rapid thermal annealing (RTA) may also be applied to remove, reduce, or eliminate residual stress in the semiconductor structure 1207. In some implementations, a planarization process, such as CMP, may also be performed on the top surface of the semiconductor structure 1207. In some implementations, one or more interlayer dielectric (ILD) layers 1230 may also be formed over the top surface of the semiconductor structure 1207. In some examples, the material of the ILD layer 1230 may also include silicon oxide.

[0140] In some implementations, as shown in FIG. 12C, a metal layer 1232 including a conductive material may also be formed over the interconnect layer 1228, thereby forming a bit line. For example, the conductive material of the metal layer may include any suitable conductive material, such as a metal (e.g., tungsten (W)). In some implementations, as shown in FIG. 12D, the metal layer 1232 may include a continuous conductive trace connecting the corresponding discontinuous interconnect layer 1228 to form a bit line. In some implementations, as shown in FIG. 12D, a suitable process may also be applied to expose the capacitor contact 1216 on the top surface of the ILD layer 1230. The capacitor contact 1216 may be formed in a manner to orient the capacitor 1234 on the top surface of the peripheral area. In some examples, the sidewalls of the capacitor contact 1216 may have a shifted shape (or may not follow a straight line) at a seam portion 1240 formed by the capacitor contact 1216 being formed in different stages. In some implementations, after formation of the bitlines, a portion of the isolation structure 1208 may be removed to form an opening, and the opening may be filled with TEOS to create a void.

[0141] In some implementations, the isolation structures 712 and the protrusions 706 on the isolation structures as shown in FIG. 7 may be formed in yet another manner different from the manner shown in FIG. 9A-9F and FIG. 11A-11C. FIG. 13 shows a flowchart of an example method 1300 for forming isolation structures in a 3D memory device according to some aspects of the disclosure. At 1302 of the method 1300, a transfer substrate 1400 may be provided. In some examples, the transfer substrate 1400 may include a silicon substrate.

[0142] Further, at 1304 of the method 1300, a cutting layer 1402 may be formed in the substrate 1400, for example, using ion implantation. In some implementations, as shown in FIG. 14A, light elements such as hydrogen ions may be implanted in the substrate 1400 to a desired depth, for example, by controlling the energy of the ion implantation process, to form the cutting layer 1402 in the transfer substrate 1400. In accordance with the scope of the present disclosure, as shown in FIG. 14A, a first oxide pad layer 1404, such as a silicon oxide layer, may be formed on the transfer substrate 1400. In some implementations, the first oxide pad layer may be formed, for example, through thermally grown local oxidation of silicon (LOCOS). Subsequently, a sacrificial layer 1406 may be formed on the first oxide pad layer 1404, for example, through one or more thin film deposition processes. The one or more thin film deposition processes may include, but are not limited to, CVD, PVD, ALD, or any combination thereof. In some implementations, the material of the sacrificial layer 1406 may include silicon nitride (SiN). As explained above, the sacrificial layer 1406 may be used to define the pattern (locations) for forming the recesses. Additionally, for shallow trench isolation (STI) and silicon oxide CMP, the sacrificial layer 1406 may be used as a stop layer to help control the depth of the trench or oxide layer formed. For example, in an STI process, the sacrificial layer 1406 may be used as a stop layer during the CMP process to prevent over-polishing the oxide in the trenches.

[0143] The method 1300 may proceed to 1306. At 1306, the device layer 1408 of the transfer substrate 1400 may be split at the cut layer 1402, for example, by applying a mechanical force to the transfer substrate 1400, i.e., peeling the device layer 1408 from the handle layer of the transfer substrate 1400. After separation, the device layer 1408 of the transfer substrate 1400 may be flipped upside down and the front side of the device layer 1408 may be transferred and bonded to the carrier substrate 1401 to form the semiconductor structure 1403, for example, using a transfer bonding process. In some examples, the carrier substrate 1401 may include a silicon substrate.

[0144] In some implementations, a second oxide pad layer 1410, such as a silicon oxide layer, may be formed on at least one of the carrier substrate 1401 or the device layer 1408 to better bond the device layer 1408 to the carrier substrate 1401. Then, the semiconductor structure 1403 may be formed. As shown in FIG. 14B, the semiconductor structure 1403 may have a sandwich structure similar to an SOI substrate, but the BOX layer of the SOI substrate may be replaced by an oxidized SiN mixed interface between the device layer 1408 and the carrier substrate 1401.

[0145] In some implementations, the backside of the semiconductor structure 1403, i.e., the backside of the former carrier substrate 1401, may be thinned after bonding. For example, a planarization process such as CMP may be performed on the backside of the semiconductor structure 1403 to adjust the thickness of the semiconductor structure 1403.

[0146] Further, the method 1300 may proceed to 1308. At 1308, a first portion of the semiconductor structure 1403 may be removed (e.g., using etching) in the active area along a first lateral direction (referred to as the y-direction, bit line direction) to form a trench. The trench may be filled with a dielectric material, e.g., silicon oxide. As a result, as shown in FIG. 14C, an isolation structure 1412 extending in the first lateral direction may be formed in the trench of the active area. In some implementations, one or more dummy regions 1110 may also be defined and formed in the semiconductor structure 1403 through removing a second portion of the semiconductor structure 1403 to form an opening and filling the opening with a dielectric material. In some examples, a planarization process, such as CMP, may be performed to polish and smooth the top surface of the semiconductor structure 1403 having the isolation structure 1412 to remove excess silicon oxide.

[0147] In some implementations, the subsequent process after Fig. 14C may be at least partially similar / identical to the above description regarding Figs. 11D-11J. For ease of explanation, the details of the process may refer to the details in the above description.

[0148] Therefore, the present disclosure provides a memory device having a vertical transistor and a self-aligned mechanism for forming a bit line. In some implementations, a recess can be formed on the vertical transistor between two of the protrusions in the memory device. Therefore, the formation of the bit line can be easily located with respect to the recess, and the bit line can be formed in the recess accordingly. As a result, the lithography process for the bit line pickup can be avoided, and the effective process window can be increased. As a result, the process flow is simplified, the cost is reduced, and an additional lithography mask is omitted.

[0149] Thus, the foregoing description of specific implementations reveals the general nature of the present disclosure, such that others may easily modify and / or adapt such specific implementations to various applications by applying knowledge of the art without undue experimentation and without departing from the general concept of the present disclosure. Such adaptations and modifications are therefore intended to be within the meaning and equivalents of the disclosed implementations, based on the teaching and guidance presented herein. It should be understood that the language or terminology herein is intended to be descriptive rather than limiting, and should be interpreted by those skilled in the art in light of the teaching and guidance.

[0150] The embodiments of the present disclosure are described above with the aid of functional building blocks illustrating implementations of specified functions and relationships of those functions. For convenience of explanation, the boundaries of these functional building blocks are arbitrarily defined herein. Alternative boundaries may be defined as long as the specified functions and their functions are appropriately performed.

[0151] The Summary and Abstract are not intended to be limiting of the disclosure and the appended claims in any way, as they may describe one or more, but not all, example implementations of the disclosure as contemplated by the inventors.

[0152] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0153] 202 First Semiconductor Structure 204 Second Semiconductor Structure 206 Bonding Boundary 300 Systems 302 Host 304 Memory System 306 Memory Devices 308 Memory Controller 400 Memory Devices 401 Memory Cell Array 402 Peripheral Circuit 404 Word Line 406 bit lines 408 memory cells 410 Vertical Transistor 412 Storage Unit 414 Semiconductor body 416 Gate Structure 418 Gate Dielectric 420 Gate electrode 500 Memory Devices 502 DRAM cells 504 Transistor 506 Capacitor 600 Memory Devices 602 Memory Cells 604 Word Line 606 bit lines 608 Semiconductor body 610 Gate Structure 612 Gate Dielectric 614 Gate electrode 616 Separate structure 700 3D Memory Device 702 bit lines 704 Hollow 706 Protrusion 708 Vertical Transistor 710 Word Line 712 Separate structure 900 Substrate 901 ILD layer 902 Separate structure 903 Carrier Board 904 Trench 905 Semiconductor Structure 906 Vertical Transistor 908 Word Line 910 Word Line Contact 912 Source Line 914 Hollow 916 Contact layer 918 Conductive layer 1101 Carrier Board 1102 Oxide Pad Layer 1103 Semiconductor Structure 1104 Cut layer 1105 Base board 1106 Sacrificial Layer 1107 Semiconductor Structure 1108 Separate structure 1110 Dummy area 1111 Silicon oxide layer 1112 Trench 1114 Vertical Transistor 1116 Capacitor 1118 Capacitor Contact 1120 ILD layer 1122 Etching mask 1124 Protrusion 1126 Hollow 1128 Interconnection Layer 1130 ILD layer 1132 Metal layer 1134 Joint part 1201 Board 1203 Semiconductor Structure 1204 Vertical Transistor 1205 Base Board 1206 Sacrificial Layer 1207 Semiconductor Structure 1208 Separate structure 1212 Trench 1224 Protrusion 1226 Hollow 1228 Interconnection Layer 1230 ILD layer 1232 Metal layer 1234 Capacitor 1240 Joint 1400 Transfer Board 1401 Carrier Board 1402 Cut layer 1403 Semiconductor Structure 1404 Oxide Pad Layer 1406 Sacrificial Layer 1408 Device Layer 1410 Oxide Pad Layer 1412 Separate structure 9022 Protrusion

Claims

1. an array of memory cells each comprising a vertical transistor, wherein along a first direction, one of the vertical transistors is disposed between two of the isolation structures in a plan view, each of the isolation structures comprising a protrusion, the isolation structure and the corresponding protrusion being integral; a plurality of bit lines comprising at least one conductive layer, the at least one conductive layer being disposed between two protrusions of the two isolation structures and in contact with the one of the vertical transistors to couple the one of the bit lines to the one of the vertical transistors.

2. the plan view is based on a first plane aligned along the first direction; 2. The memory device of claim 1, wherein a projection of the at least one conductive layer onto a second plane disposed between the two protrusions has substantially no overlap with a projection of each of the two isolation structures onto the second plane, and the second plane is orthogonal to the first plane.

3. 2. The memory device of claim 1, further comprising a plurality of word lines extending in the first direction and configured to connect gates of the vertical transistors, wherein a depth of one of the word lines is less than a depth of one of the isolation structures.

4. 2. The memory device of claim 1, further comprising a plurality of storage units, one of said storage units being connected to a corresponding one of said vertical transistors on an opposite side of said bit line.

5. The memory device of claim 4 , wherein the one of the storage units comprises a capacitor.

6. The memory device of claim 5 , wherein the capacitor is disposed in one or more interlayer dielectric (IDL) layers on opposite sides of the bitline.

7. the array of memory cells is disposed within a main memory area; 6. The memory device of claim 5, further comprising a capacitor contact disposed in a peripheral area outside the main memory area and electrically connected to the capacitor in the main memory area, the capacitor contact extending along a third direction in which the vertical transistor extends and comprising a seam portion, and a sidewall of the capacitor contact comprising an offset shape at the seam portion.

8. The memory device of claim 1 , wherein a surface of the at least one conductive layer of the bit line is substantially flush with surfaces of the two protrusions of the two isolation structures.

9. The at least one conductive layer is a contact layer disposed between the two protrusions and in contact with the one of the vertical transistors; The memory device according to claim 1 , further comprising: a metal layer disposed between the two protrusions and in contact with the contact layer.

10. the contact layer comprises a silicide; The memory device of claim 9 , wherein the metal layer comprises tungsten.

11. The memory device of claim 1 , wherein the at least one conductive layer comprises an interconnect layer disposed between the two protrusions and in contact with the one of the vertical transistors.

12. the interconnect layer is disposed in the primary memory area and configured to connect to the one of the vertical transistors; 12. The memory device of claim 11, wherein a sacrificial layer is disposed in a peripheral area outside the main memory area, and a surface of the interconnect layer in the main memory area is substantially coplanar with a surface of the sacrificial layer in the peripheral area.

13. The memory device of claim 12 , wherein an oxide pad layer is disposed in the peripheral area and beneath the sacrificial layer.

14. The memory device of claim 11 , wherein the interconnect layer comprises polysilicon.

15. The memory device of claim 11 , wherein a surface of the interconnect layer is substantially flush with surfaces of the two protrusions of the two isolation structures.

16. 12. The memory device of claim 11, wherein the bitlines further comprise a metal layer in one or more interlevel dielectric (ILD) layers disposed adjacent to and in contact with the interconnect layer.

17. 17. The memory device of claim 16, wherein the interconnect layer extends continuously adjacent the one of the vertical transistors in a second direction perpendicular to the first direction.

18. The memory device of claim 17 , wherein the metal layer comprises metal points disposed on the interconnect layer.

19. the interconnect layer is separated in a second direction perpendicular to the first direction; 20. The memory device of claim 16, wherein the metal layer comprises metal wiring connecting the interconnect layers.

20. the array of memory cells is disposed in a first semiconductor structure; 2. The memory device of claim 1, further comprising a second semiconductor structure bonded to the first semiconductor structure and comprising peripheral circuitry, the peripheral circuitry coupled to the array of memory cells through the bit lines and configured to control the array.

21. configured to store data; a first semiconductor structure having peripheral circuitry; bonded to the first semiconductor structure; an array of memory cells each comprising a vertical transistor, wherein along a first direction, one of the vertical transistors is disposed between two of the isolation structures in a plan view, each of the isolation structures comprising a protrusion, the isolation structure and the corresponding protrusion being integral; a plurality of bit lines including at least one conductive layer, the at least one conductive layer being disposed between two protrusions of the two isolation structures and in contact with the one of the vertical transistors to couple the one of the bit lines to the one of the vertical transistors, and the memory cells being coupled to the peripheral circuit through the bit lines; a second semiconductor structure comprising: A memory device comprising: a memory controller coupled to the memory device and configured to control the memory cells through the peripheral circuits.

22. 1. A method of forming a memory device, comprising: forming a plurality of isolation structures; forming an array of memory cells each comprising a vertical transistor, one of the vertical transistors being disposed in plan view between two of the isolation structures along a first direction perpendicular to a second direction along which the isolation structures extend; forming a plurality of protrusions on each of the isolation structures; forming a plurality of bit lines comprising at least one conductive layer, the at least one conductive layer being disposed in a recess between two protrusions of the two isolation structures and in contact with the one of the vertical transistors to couple the one of the bit lines to the one of the vertical transistors.

23. 23. The method of claim 22, further comprising forming a plurality of capacitors in one or more inter-layer dielectric (IDL) layers, one of the capacitors being connected to a corresponding one of the vertical transistors on an opposite side of the bit line.

24. The array of memory cells and the capacitor are disposed within a main memory area, and the method comprises:

24. The method of claim 23, further comprising forming a capacitor contact in a peripheral area outside the main memory area, electrically connected to the one of the capacitors connected to the one of the vertical transistors in the main memory area, the capacitor contact extending along a third direction in which the vertical transistors extend and comprising a seam portion, and a sidewall of the capacitor contact comprising an offset shape at the seam portion.

25. forming the plurality of isolation structures, providing a substrate including a device layer, a handle layer, and a buried oxide (BOX) layer between the device layer and the handle layer; removing first portions of the device layer and the handle layer to form a plurality of first trenches along the second direction through at least the BOX layer; and filling each of the plurality of first trenches with a first dielectric material to form the isolation structure in the substrate.

26. removing a second portion of the device layer to form a second plurality of trenches along the first direction; forming the memory cell comprises forming the vertical transistor corresponding to the second trench; 26. The method of claim 25, wherein the method further comprises forming a plurality of word lines each corresponding to one of the second trenches and configured to connect gates of the vertical transistors in a row of the array of memory cells.

27. 27. The method of claim 26, wherein a depth of one of the second trenches is less than a depth of one of the first trenches.

28. The step of forming the protrusion further comprises: bonding the substrate to a carrier substrate at a front side of the substrate; 28. The method of claim 27, comprising removing the BOX layer and a remaining handle layer of the substrate to expose the isolation structures, wherein one end of each of the isolation structures forms a protrusion, and the recess is formed between the two protrusions of the two isolation structures.

29. 28. The method of claim 27, wherein the recess is a third trench extending along the second direction.

30. forming the plurality of bit lines, removing a portion of the BOX layer in the third trench adjacent to the one of the vertical transistors; and depositing the at least one conductive layer in the third trench, wherein a surface of the at least one conductive layer is substantially flush with surfaces of the two protrusions of the isolation structure.

31. The at least one conductive layer is a contact layer disposed in the third trench and in contact with the one of the vertical transistors; 31. The method of claim 30, further comprising: a metal layer disposed in the third trench and adjacent the contact layer.

32. the contact layer comprises a silicide; 32. The method of claim 31 , wherein the metal layer comprises tungsten.

33. forming the plurality of isolation structures, providing a transfer substrate comprising a silicon substrate, a cut layer in the silicon substrate, and an oxide pad layer on the silicon substrate; forming a sacrificial layer on the oxide pad layer; removing portions of the pad oxide layer and the sacrificial layer in a device layer of the transfer substrate to form a plurality of fourth trenches along the second direction; filling each of the plurality of fourth trenches with a second dielectric material to form the isolation structure; dividing the device layer from the transfer substrate along the cutting layer; bonding a front side of the device layer to a carrier substrate to form a first semiconductor structure; and removing a backside of the device layer to expose the isolation structure.

34. the portion of the pad oxide layer and the sacrificial layer that is removed is a first portion of the pad oxide layer and the sacrificial layer; the array of memory cells is disposed within a main memory area; 34. The method of claim 33, wherein the oxide pad layer and a second portion of the sacrificial layer remain in a peripheral area outside the main memory area.

35. 34. The method of claim 33, further comprising implanting the transfer substrate to a depth to form the cutting layer in the transfer substrate.

36. removing portions of the first semiconductor structure to form a plurality of fifth trenches along the first direction; forming the memory cell comprises forming the vertical transistor corresponding to the fifth trench; 34. The method of claim 33, wherein the method further comprises forming a plurality of word lines each corresponding to one of the fifth trenches and configured to connect gates of the vertical transistors in a row of the array of memory cells.

37. The step of forming the protrusion further comprises: bonding a front side of the first semiconductor structure to a base substrate to form a second semiconductor structure; removing a portion of the second semiconductor structure to expose the sacrificial layer; and removing, using a mask, portions of the sacrificial layer and the pad oxide layer to expose the vertical transistor and the isolation structures, wherein one end of each of the isolation structures forms a protrusion, and the recess is formed between the two protrusions of the two isolation structures.

38. 37. The method of claim 36, wherein a depth of one of the fifth trenches is less than a depth of one of the isolation structures.

39. 39. The method of claim 38, wherein the recess is a sixth trench extending along the second direction.

40. forming the plurality of bit lines, depositing an interconnect layer in the sixth trench and in contact with the one of the vertical transistors, a surface of the interconnect layer being substantially flush with surfaces of the two protrusions of the isolation structure, and the at least one conductive layer comprising the interconnect layer; 40. The method of claim 39, comprising forming a metal layer in one or more interlevel dielectric (ILD) layers and adjacent to the interconnect layer.

41. the interconnect layer comprises polysilicon; 41. The method of claim 40, wherein the metal layer comprises tungsten.

42. 41. The method of claim 40, wherein the metal layer comprises metal points on the interconnect layer.

43. 39. The method of claim 38, wherein a depth of one of the fifth trenches is approximately equal to a depth of one of the isolation structures.

44. forming the plurality of bit lines, depositing an interconnect layer in the recess and in contact with the one of the vertical transistors, a surface of the interconnect layer being substantially flush with surfaces of the two protrusions of the isolation structure, and the at least one conductive layer comprising the interconnect layer; 44. The method of claim 43, comprising forming a metal layer in one or more interlevel dielectric (ILD) layers and adjacent to the interconnect layer.

45. the interconnect layer comprises polysilicon; 45. The method of claim 44, wherein the metal layer comprises tungsten.

46. the interconnect layer is separated in the second direction; 45. The method of claim 44, wherein the metal layer comprises metal wiring connecting the interconnect layers.

47. forming the plurality of isolation structures, providing a transfer substrate comprising a cut layer in a silicon substrate, a device layer comprising an oxide pad layer on the silicon substrate, and a sacrificial layer on the oxide pad layer; dividing a device layer from the transfer substrate along the cutting layer; bonding a front side of the device layer to a carrier substrate to form a third semiconductor structure; removing portions of the third semiconductor structure to form a plurality of seventh trenches along the second direction; and filling each of the plurality of seventh trenches with a third dielectric material to form the isolation structure.

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