Adaptive Edge Termination by Design for High-Voltage Silicon Carbide Power Devices with High Efficiency and Robustness

Abstract

The present invention provides a semiconductor device having two or more termination units. Each termination unit has a via channel, a connecting via, a floating field ring, a metal plate, and a floating field plate. The floating field ring can include a first floating field ring having a first width and a second floating field ring having a second width. The first width and the second width can be different widths. The metal plate is coupled to the first floating field ring through the via channel. The first floating field plate is coupled to the metal plate through the connecting via. The termination units form an adaptive electric field distribution, which is configured to dissipate a voltage that transfers from a drain of the semiconductor device to a source of the semiconductor device.

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to high voltage semiconductor devices having predetermined parameters that enable increased performance, ruggedness and reliability. [Background technology]

[0002] Typically, traditional high voltage or high power technologies use semiconductors to perform edge termination and potential field distribution by implementing the highest possible termination voltage above the breakdown voltage. These edge termination designs often focus on the region inside the semiconductor, with only a few cases considering the region above the semiconductor surface.

[0003] Indeed, in the prior art, semiconductor edge termination elements are required to fix voltages, perform edge termination and potential field distribution.

[0004] For example, edge termination elements such as floating field plates are simply placed in an insulating layer on the semiconductor surface and are not connected to other edge termination elements such as metal plates or to floating field rings that are located within the semiconductor layer. That is, the edge termination elements are capacitively coupled to other edge termination elements. The exact nature of this capacitive coupling depends on the material, dielectric constant, conductance, etc. Therefore, since these edge termination elements in the insulating layer are not connected, the voltage regulation is strictly dependent on the material properties that affect the potential field distribution (i.e., leakage between the insulating layer and the edge termination element).

[0005] As another known example, some conventional edge termination techniques are tightly focused on regions below the semiconductor surface, such as floating field rings, junction termination extensions, reduced electric field (RESURF), or a combination of these. Nevertheless, the process control of epitaxial layer concentration and tight control of RESURF layer implantation have inherent manufacturability limitations, such as yield and reliability limitations.

[0006] The potential field distribution created by the insulating layer cannot be limited by designing the location and size of the edge termination elements. In other words, regardless of how the elements are located and sized, it is the capacitive coupling that dominates the potential field distribution. It should also be noted that a strict reliance on material properties to affect capacitive coupling is a significant limitation that prevents widespread adoption of conventional techniques using floating field plates as edge terminations.

[0007] What is needed are new and / or improved methods and systems for managing potential field distributions within semiconductor edge terminations and on semiconductor surfaces by enabling direct control of how edge termination elements generate potential field distributions. Moreover, it would be preferable to have a more comprehensive approach to high voltage termination design that addresses all aspects of the termination within and on the semiconductor edge termination region. Summary of the Invention

[0008] One or more embodiments relate to a semiconductor device having two or more termination units. Each termination unit includes a via channel, a connection via, a floating field ring, a metal plate, and a floating field plate. The floating field ring includes a first floating field ring having a first width and a second floating field ring having a second width. In one or more embodiments, the first width and the second width can be different. The metal plate is coupled to the first floating field ring through the via channel. The floating field plate is coupled to the metal plate through the connection via. The termination units form an electric field distribution configured to dissipate a voltage transferred from a drain of the semiconductor device to a source of the semiconductor device.

[0009] One or more embodiments also relate to a termination unit for a semiconductor device, the termination unit having a via channel, a connecting via, a plurality of floating field rings, a metal plate coupled to the first floating field ring through the via channel, and a floating field plate coupled to the metal plate through the connecting via, the drain side of the metal plate extending beyond the drain side of the epitaxial layer of the semiconductor device or located outside the drain side of the epitaxial layer of the semiconductor device, the drain side length of the metal plate being equal to or greater than the junction depth of the epitaxial layer.

[0010] Additionally, one or more embodiments relate to a method of making, implementing, modifying, and / or determining a design for a semiconductor device. The method may be implemented by software stored in a memory and executed by a processor. The method may determine a breakdown voltage design target based on a desired or predetermined breakdown voltage for the semiconductor design. The method may create a structure for a semiconductor design having at least two termination units. The structure may be generated according to or taking into account a breakdown voltage design target by utilizing or taking into account a configuration, layout or other parameters that include an incremental voltage drop per termination unit, a predetermined number of termination units, and / or an element or element design per termination unit. The method may also evaluate whether the structure has a homogenous distribution or energy below a critical field to determine a final termination layout design for the semiconductor device.

[0011] Further aspects and embodiments are disclosed herein. [Brief description of the drawings]

[0012] The invention may be more fully understood from the following description, taken in conjunction with the accompanying drawings, in which like reference numerals indicate like elements and in which: [Figure 1] FIG. 1 is a diagram illustrating an adaptive edge termination semiconductor device according to one or more embodiments. [Diagram 2] FIG. 2 is a diagram illustrating a termination unit according to one or more embodiments. [Diagram 3] FIG. 3 is a block diagram illustrating a method for manufacturing an adaptive edge termination semiconductor device according to one or more embodiments. [Figure 4] FIG. 4 is a diagram illustrating an electrical termination layer according to one or more embodiments. [Diagram 5] FIG. 5 is a diagram illustrating an adaptive edge termination semiconductor device structure in accordance with one or more embodiments. [Figure 6] FIG. 6 is a diagram illustrating the incremental distribution of the electric field in an adaptive edge termination semiconductor device in accordance with one or more embodiments. [Figure 7] FIG. 7 is a diagram illustrating an adaptive edge termination semiconductor device according to one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Various embodiments of the present invention, examples of which are illustrated in the accompanying drawings, are described in detail below. While the present invention will be described in conjunction with these embodiments, there is no intent to limit the present invention to these embodiments. To the contrary, the present invention encompasses alternatives, modifications and equivalents included within the spirit and scope of the present invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be appreciated that those skilled in the art will be able to practice the present invention without these specific details. Additionally, well-known methods, procedures, components, circuits, etc. are not described in detail so as not to unnecessarily obscure aspects of the present invention.

[0014] Several terms are used below, all of which are for reference purposes only and are not intended to be limiting. The terms "right", "left", "top" and "bottom" are directional terms in the drawings to which reference is made. The terms "a" and "one", as used in the claims and corresponding parts of the specification, are defined to include one or more of the elements listed, unless otherwise specified. This terminology includes not only the terms specifically listed above, but also derivatives of such terms and terms of similar import. The phrase "at least one" preceding one or more listed elements, such as "A, B or C", refers not only to any one of A, B or C, respectively, but also to any combination of A, B or C. It should be noted that some of the figures are partially transparent for purposes of explanation, illustration and demonstration only, but this does not imply that the elements themselves are transparent in their final manufactured form.

[0015] Additionally, although the terms "first," "second," etc. are used herein to denote various elements, these elements should not be limited to these terms. The intent of these terms is merely to distinguish one element from another element. For example, a first element could be read as a second element, and similarly, a second element could be read as a first element, without departing from the scope of the present invention. As used herein, the term "and / or" includes one or more of the listed elements, either alone or in combination.

[0016] Additionally, when an element, such as a layer, region, substrate, lead, clip, pad, or contact, is described as being on or extending into another element, the element may be directly on or extending into the other element, i.e., no intervening elements are present. Also, when an element is described as being "connected" or "coupled" to another element, this means that it is directly connected or coupled to the other element, and implies that some intervening elements are present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, this means that no intervening elements are present. Furthermore, these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0017] Relative terms such as "below" or "upper," "top" or "lower," or "horizontal" or "vertical" are used herein to describe the relationship of an element, layer or region to another element, layer or region, and these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0018] The accompanying drawings are not to scale and show only the structures as well as some of the various layers that form these structures. The accompanying drawings are generally representational and simplified structures that aid in the understanding of the invention and are not intended to reproduce the physical structures in detail. Furthermore, manufacturing processes and operations may be performed according to the processes and operations described herein; that is, many process operations occur before, after, or during the operations shown and described herein. Furthermore, embodiments of the present invention may be performed substantially without modification using these other (possibly prior art) processes and operations. Overall, embodiments of the present invention may be used in place of and / or complement most of the prior art processes without significantly affecting the surrounding processes and operations.

[0019] As used herein, the term "MOSFET" may be generally considered synonymous with the term "insulated gate field effect transistor (IGFET)" in that many modern MOSFETs use non-metal gates and / or non-oxide gate insulators. The term "MOSFET" as used herein does not necessarily imply or require FETs having metal gates and / or oxide gate insulators. Rather, the term "MOSFET" is intended to encompass devices commonly known as or referred to as MOSFETs.

[0020] The term "substantially equal" in this specification and claims is used to indicate design intent, not physical results. Semiconductor technology has embraced the ability to measure many aspects of semiconductors with high precision. Thus, when measurements are made with the available precision, the physical aspects of the semiconductor are not precise at the time of design. Furthermore, design technology can easily find variations in structures that are intended to be identical. Thus, phrases such as "substantially equal" should be interpreted as being designed to be equal according to manufacturing variations and measurement precision.

[0021] The present invention relates to semiconductors, and more particularly to adaptive edge termination by design for highly efficient, rugged silicon carbide power devices, which may be referred to herein as adaptive edge termination semiconductor devices or packages (which may also be referred to as "devices" or "packages" or "components").

[0022] In accordance with one or more aspects of the present invention, a semiconductor device (e.g., semiconductor device 100 of FIG. 1 ) and a design method (e.g., method 300 of FIG. 3 ) for manufacturing such a semiconductor device 100 includes an adaptive edge termination that controls or adapts how one or more termination elements in various layers of the semiconductor device manage a potential field distribution (which may also be referred to as an “electric field distribution”). The semiconductor device may be comprised of MOSFETs. In the case of the semiconductor device and design method, such control or adaptation is achieved through the design and use of one or more termination units that implement an adaptive voltage drop by determining some of the component parameters of such termination elements as well as by coupling and positioning the termination elements. By way of example, a conventional technique would be to group a field plate with two or more floating field rings for each termination unit that distributes a voltage that is adapted to parameters such as the physical properties of the components while leaving the voltage edge termination elements fixed in an insulating layer without connecting them to other edge elements. Such parameters may include, but are not limited to, the position, orientation, dimensional size, spacing, and materials used for such components.

[0023] One or more of the technical effects, advantages, and benefits of the above semiconductor device and design method include a design approach focus that improves the quality, stability, and long-term reliability of the performance and robustness of the semiconductor device. In contrast to the prior art, the semiconductor device and design method of the present invention do not require the elimination or reduction of constant voltages, but rather control the electric field distribution by design, form a physical charge barrier, and address the issues of manufacturing variations and dielectric film charges that destabilize termination breakdown voltages.

[0024] 1 is a diagram illustrating a semiconductor device 100 according to one or more embodiments. Generally, the parameters of the components of the semiconductor device 100 can include, but are not limited to, the materials, structures, positions, orientations, spacings, dimensions (such as widths, heights, depths, dimensions, areas, volumes, etc.), and shapes of the various elements or components. Such parameters are controlled and / or determined by a design method, preferably the method(s) described herein.

[0025] The diagram of FIG. 1 shows a semiconductor device 100 having two or more termination units (one example of such a unit is termination unit 101), a source 102, and a drain 103 of the semiconductor device 100. Five termination unit embodiments AE are shown in FIG. 1. The edge termination elements of the semiconductor device are identified / grouped according to AE, corresponding to termination units AE. The orientation in FIG. 1 follows the X1-X2 axis (which is generally parallel in the figure and has a direction between left and right as shown in FIG. 1) and the Y1-Y2 axis (which is generally vertical in the figure and has a direction between up and down as shown in FIG. 1). The X1 direction is opposite to the X2 direction, and the Y1 direction is opposite to the Y2 direction. Other orientations may also be tilted or angled and may be determined according to the X1-X2 and Y1-Y2 axes. The left side or left surface of a component in this specification may be referred to as the X1 side or X1 surface of the component, and the right side or right surface of a component may be referred to as the X2 side or X2 surface of the component. Similarly, the lower, bottom or downward facing surface of a component may be referred to as the Y1 side or Y1 surface, and the top, upper side or upward facing surface of a component may be referred to as the Y2 side or Y2 surface.

[0026] The semiconductor device 100 may have one or more doping configurations. Without being limited to the semiconductor device 100, illustrative doping configurations are described below. Additionally, as used herein, the letter "n" refers to an n-type dopant and the letter "p" refers to a p-type dopant. A plus sign "+" or a minus sign "-" is used to indicate a relatively high or low concentration of dopant, respectively. It should be noted that the above is not intended to limit the absolute doping ranges or other aspects of these regions. For example, a doping region described as n+ or n- may be an n-type doping region.

[0027] The diagram of Figure 1 illustrates a first region 105. The first region 105 can be comprised of one or more layers. The first region 105 preferably includes a substrate layer 110, a buffer layer 120, an epitaxial layer 130, and an electrical termination layer 135 having one or more floating field rings 145 therein. That is, the first region 105 can include one or more edge termination elements having one or more floating field rings 145 embedded / buried (e.g., buried layers) in the electrical termination layer 135.

[0028] Substrate layer 110 may form or have a portion of first region 105 that is used to produce at least buffer layer 120 and epitaxial layer 130. Buffer layer 120 and epitaxial layer 130 may be formed / grown on substrate layer 110 to have matching crystallinity. In one or more embodiments, because the doping of epitaxial layer 130 varies from factory to factory, the doping concentration of buffer layer 120 may be higher (e.g., 10% or higher) than epitaxial layer 130, as described herein.

[0029] Electrical termination layer 135 may be formed as or include one or more edge termination elements embedded in a depletion layer. Because electrical termination layer 135 acts as a barrier or transition region between epitaxial layer 130 and second region 150, floating field ring 145 does not directly contact or is not embedded in epitaxial layer 130, and one or more p-n junctions of semiconductor device 100 are shifted downward to where electrical termination layer 135 meets epitaxial layer 130. Floating field ring 145 is described in more detail below.

[0030] 1, a second region 150 is shown adjacent to the top or X2 side of the first region 105. The second region 150 can be comprised of one or more layers. The second region 150 can be comprised of a single material, such as a single insulating / dielectric material. In one or more embodiments, the second region 150 is preferably comprised of a dielectric film 160. As shown, the dielectric film 160 is designated AE and is a portion that mates with each termination unit AE.

[0031] In one or more embodiments, a dielectric film 160 can be formed having one or more connections (e.g., one or more channel vias 165 and one or more connection vias 175) and embedded edge termination elements (e.g., one or more metal plates 170 and one or more floating field plates 180). The one or more connections and edge termination elements can comprise metal and / or polysilicon. For example, floating field plate 180, which is described in more detail below, can comprise polysilicon.

[0032] A termination unit for use in one or more embodiments may comprise at least one (e.g., typically four or more) floating field ring 145, one channel via 165, one metal plate 170, one connection via 175, and one floating field plate 180. The channel via 165, metal plate 170, and connection via 175 used together in each termination unit AE may be comprised of a metal that is continuous (i.e., not a separate piece) from the corresponding floating field ring 145 to the floating field plate 180. In one or more embodiments, the metal plate 170 may be a section or piece, and the channel via 165 and connection via 175 may also be formed as the same section or layer, but may be different from the metal plate 170.

[0033] Additionally, each of the two or more termination units (of which termination unit 101 is an example) can be configured with one or more floating field rings 145. For example, as shown in FIG. 1, five example termination units AE have floating field rings 145, as indicated by the following alphanumeric characters. That is, the leftmost (i.e., X1 side of semiconductor device 100) termination unit A has five floating field rings 145.1A-145.5A, as well as channel via 165A, metal plate 175A, connection via 175A, and floating field plate 180A. The second leftmost termination unit B has five floating field rings 145.1B-145.5B, as well as channel via 165B, metal plate 175B, connection via 175B, and floating field plate 180B. The central termination unit C has five floating field rings 145.1C-145.5C as well as a channel via 165C, a metal plate 175C, a connection via 175C, and a floating field plate 180C. The second rightmost termination unit D (i.e., shown as an example of termination unit 101) has five floating field rings 145.1D-145.5D as well as a channel via 165D, a metal plate 175D, a connection via 175D, and a floating field plate 180D. The rightmost termination unit E (i.e., on the X2 side of semiconductor device 100) has four floating field rings 145.1E-145.4E as well as a channel via 165E, a metal plate 175E, a connection via 175E, and a floating field plate 180E.

[0034] Each floating field ring 145 has a dynamic configuration that acquires and / or adapts a voltage based on the parameter. The floating field rings 145 are constructed of metal and / or polysilicon in accordance with the one or more parameters. In one or more embodiments, the structure, size, width, dimensions, area, etc., of each floating field ring 145, as well as the location of each floating field ring 145 and the respective spacing of the floating field rings 145, allow the corresponding termination unit to dynamically adapt to the applied potential / voltage of the semiconductor device 100. In one or more embodiments, the floating field rings 145 have p-type regions formed at the same time and by the same process as the body of the semiconductor device 100 (e.g., a MOSFET) having implanted and diffused regions (e.g., electrical termination layer 135).

[0035] 1 also shows high voltage side metal plate 185 and gate 190. High voltage side metal plate 185 allows for distribution of any initial voltage on the drain side of semiconductor device 100. Additionally, gate 190 is in connection with the core of the semiconductor device and may be formed of the same material as floating field plate 180A.

[0036] In the orientation of the semiconductor device 100 shown in FIG. 1, the first region 105 has a bottom or Y1 surface and a top or Y2 surface. The second region 150 has a bottom or Y1 surface and a top or Y2 surface. The top surface (i.e., Y2 surface) of the first region 105 is adjacent to the bottom surface (i.e., Y1 surface) of the second region 150. In this state, the bottom side (i.e., Y1 side) of the dielectric film 160 contacts the first region 105, i.e., the top side (i.e., Y2 side) of the epitaxial layer 130. Furthermore, the electrical termination layer 135 may extend from the left side or X1 side to the right side or X2 side in the X1-X2 direction. The left side or X1 side of the electrical termination layer 135 may be aligned with the left side or X1 side of the epitaxial layer 130, and the right side or X2 side of the electrical termination layer 135 may be located within the epitaxial layer 130. In the Y1-Y2 direction, electrical termination layer 135 may extend from a bottom surface or Y1 plane of dielectric film 160 to an area or depth below the bottom surface or Y1 plane of floating field ring 145 in epitaxial layer 130. In one or more embodiments, termination unit 101 may extend from a top surface or Y2 plane of second region 150 to a bottom surface or Y1 plane of first region (i.e., substrate layer 110), as will be further described with reference to FIG.

[0037] Generally, breakdown voltage (BV) is the applied voltage at which effective impact ionization occurs and some current begins to flow in any device (such as semiconductor device 100). The termination region at the edge of a typical high voltage device is susceptible to BV instability because the voltage in the termination region varies from the source voltage (usually at ground potential) to the drain voltage (at full drain potential) at the edge of the typical high voltage device. Unless properly managed, this voltage can propagate to the surface of the typical high voltage device, causing field distribution problems. A typical high voltage device in the prior art can manage a BV of approximately 300 volts. In contrast, one or more embodiments of the semiconductor device 100 disclosed herein can manage a BV of 650 volts or more. Examples of "high" BVs, without intending to be limiting, include 650 volts, 800 volts, 900 volts, 1000 volts, and 1200 volts. Specifically, the semiconductor device 100 according to the embodiment of the present invention is designed for high robustness, reliability and stability at least above 650 volts, and therefore has the capability of handling high voltage, high current and high temperature. In other words, in the case of the semiconductor device 100, since a sudden voltage transition from the source potential (i.e., ground potential or source 102 potential) to the highest voltage may occur, the device is designed with two or more termination units 101 to improve the electric field distribution.

[0038] For example, the first region 105 of the semiconductor device can be constructed using a single material, such as a single n-type material. Examples of the semiconductor device 100 include, but are not limited to, a pn junction diode, a Schottky diode, and an insulated gate bipolar transistor (IGBT). Examples of n-type materials include, but are not limited to, silicon, silicon carbide, and gallium nitride. In one or more embodiments, the first region 105 can be constructed of a silicon carbide (SiC) material. That is, the semiconductor device 100 is a SiC device, which exhibits superior performance in high voltage applications over prior art silicon (Si) devices. In particular, SiC exhibits superior performance because it has a bandgap that is approximately three times larger (e.g., approximately 3.26 eV) than Si (e.g., approximately 1.12 eV).

[0039] The doping concentration of any layer in the first region 105, such as the electrical termination layer 135, can be determined, adjusted, and / or controlled by design methods described herein (such as method 300 of FIG. 3). For example, the electrical termination layer 135 can be doped based on a range. An example doping range for the electrical termination device 135 is 30%-70% of the epitaxial layer 130. For example, the floating field ring 145 can be doped as p-type, the electrical termination layer 135 being a lightly doped p-type layer, and the remainder of the first region 105 being doped as an n-type layer. For example, overdoping the electrical termination layer 135 can prevent the floating field ring 145 from acquiring and distributing electrical potential. Additionally, the electrical termination layer 135 can reduce the dependency of the floating field ring 145 on the doping level of the epitaxial layer 130, thereby expanding the manufacturing range of the process. Furthermore, the doping degree increases as the semiconductor device 100 moves away from the second region 150 (e.g., as the doping degree of the buffer layer 140 becomes 10% or more higher than that of the epitaxial layer 130). Typically, for each termination unit A-E, a channel via 165 connects a corresponding floating field ring 145 to a corresponding metal plate 170. Further, a connection via 175 connects a corresponding floating field plate 180. The channel via 165, the connection via 175, and the metal plate 170 can be made of metal. The floating field plate 180 is an excessively highly doped polysilicon, such as -type, if the first region 105 is n-type, or vice versa.

[0040] Continuing with the description, reference is made to FIG. 2, which shows in detail the termination unit 101 of the diagram of FIG. 1 according to one or more embodiments. The termination unit 101 of FIG. 2 has floating field rings 145.1D-145.5D therein. The termination unit 101 of FIG. 2 has a dielectric film 160D and includes a channel via 165D, a metal plate 170D, and a connection via 175 therein as well as a floating field plate 180D. The termination unit 101 of FIG. 2 shows the technical effect, advantage and effect that not all the floating field rings 145.1D-145.5D need to be connected to the floating field plate 180, which greatly simplifies the manufacturing process and eliminates the need for advanced lithography techniques / equipment to specialize the design for manufacturing. Thus, as shown, when one floating field ring 145.1D is bonded to the floating field plate 180D, the remaining floating field rings 145.2D-145.5D do not need to be bonded.

[0041] 2 may be considered to extend along the X1-X2 direction, with each floating field ring 145 having a left or X1 side facing in the X1 direction, a right or X2 side facing in the opposite direction, a bottom or Y1 side facing in the Y1 direction, and a top or Y2 side facing in the opposite X2 direction. For example, a termination unit 101 may extend from the right or X2 side 291 of floating field ring 145.5C, which is located immediately to the left (i.e., in the X1 direction) of wider floating field ring 145.1D, to the X2 side 292 of floating field ring 145.1D, which is located to the left (i.e., in the X1 direction) of the next wider floating field ring 145.1E.

[0042] 2 may be considered to extend in the Y1-Y2 direction. For example, the termination unit 101 in FIG. 2 may extend from the lower surface, or Y1 plane, of the substrate layer 110 to the upper surface, or Y2 plane, of the dielectric film 160. In another example, the termination unit 101 in FIG. 2 may extend from the Y1 plane of the electrical termination layer 135 to the upper surface, or Y2 plane, of the dielectric film 160.

[0043] Continuing with the description of termination unit 101 in Figure 1 and / or Figure 2, a voltage transition occurs from the highest voltage at drain 102 (and the right side or X2 side of the diagram) to ground or source 101 (and the left side or X1 side of the diagram). One or more technical effects, advantages and / or advantages of a semiconductor device 100 having a termination unit according to some embodiments of the present invention include achieving the best possible electric field distribution in response to this transition.

[0044] Incidentally, in the Y1-Y2 direction in Fig. 1 and Fig. 2 (i.e., along the axial direction from the substrate layer 110 to the surface of the first region 150), a certain distance is required to realize the electric field distribution. In the X1-X2 lateral direction in Fig. 1 and Fig. 2 (i.e., along the axis from the left to the right), the metal plate 170 constitutes a mechanical barrier at the region surface, and each part is graded by acquiring a potential / voltage through the channel via 165. That is, the potential / voltage acquired by each floating field ring 145 is transferred from the channel via 165 to the metal plate 170, and then transferred (by shorting) to the floating field plate 180 through the connection via 175. In this way, the voltage of each termination unit 101 (and more specifically, the floating field plate 180 therein) is not constant. Rather, the potential / voltage or the voltage drop per termination unit AE is adapted by design according to the position and dimensions of the floating field ring 145 in the electrical termination layer 135.

[0045] Specifically, the voltage drop is controlled by an adaptive matrix of plates 170, 180 and floating field ring 145, where "adaptive" refers to acquiring voltage as an accumulation of voltages, and "matrix" refers to the configuration of plates 170, 180 and floating field ring 145. In this manner, the adaptive matrix manages the change in electric field distribution due to the gradual voltage drop distribution controlled by the gradual controlled voltage drop of floating field ring 145, because these components occupy unique locations (e.g., by physical distance, location, orientation, dimensions, etc.) and can be configured with a design methodology for given specifications and electric field distribution throughout dielectric film 160 and electrical termination layer 135 (depending on physical size and dimensions, and which materials are located next to each other or adjacent to each other).

[0046] In one or more embodiments, the adaptation matrix thus has a particular configuration of plates 170 and 180 in combination with floating field ring 145. This adaptation matrix illustrates a profound and fundamental difference between semiconductor device 100 of FIG. 1 and the prior art. As described herein, in the case of prior art field plates, the voltage (either the source voltage or the drain voltage, which is determined by the device and cannot be adapted) is fixed. In contrast, the use of the adaptation matrix of plates 170 and 180 makes it possible to obtain an "adaptive" voltage that is acquired as a voltage that accumulates on floating field ring 145 in termination unit AE and is distributed in an adaptive manner from within the termination configuration arising through vias 175 and 185.

[0047] In one or more embodiments, the dielectric film 160 can be described as an interlayer dielectric (ILD) that resides on the semiconductor material (i.e., first region 105) and is located between different buried elements. It should be noted that for dielectric films deposited during device fabrication, as well as during device assembly and packaging, molding compounds are commonly used that can lower the BV due to degradation of the electric field distribution. For example, the electric field may shift or become large (e.g., 5E5 to 4E6 volts / cm or more) during normal use or during burn-in and qualification of the device, causing functional problems or device derating and not being able to maintain the electrical parameters of the device. Nevertheless, the adaptive matrix of plates 170 and 180 and termination units AE controls the voltage drop (due to the incremental and controllable voltage drop of the floating field rings) and the electric field distribution does not change.

[0048] 3 is a block diagram illustrating a method 300 for manufacturing an adaptive edge termination semiconductor device according to one or more embodiments. The method 300 is preferably used to provide a structure based methodology that utilizes or relies on target specifications for a device design, which may be, for example, specifications based on end user, customer or designer requirements or specifications, or the intended use of the semiconductor device, the intended function of the semiconductor device, end user, customer or designer preferences, or another source (i.e., design documents or technical documents or specifications) to determine an initial layout that may be refined based on, for example, BV design goals.

[0049] For example, the method 300 provides an iterative process for designing a semiconductor device with adaptive edge termination, such as the semiconductor device 100 of FIG. 1, by determining, setting, testing, and redesigning and testing unique or predefined design parameters. These design parameters may include the quantity / number of termination units, and the structure, dimensions, configuration, composition, and elements of these units. By utilizing an iterative process, the method 300 may design and refine a termination by obtaining a voltage at the floating field ring 145 by coupling the voltage drop at the termination to the metal and floating field plates 170 and 180, and distributing this voltage. It is noted that devices rated at 300 volts or higher are typically designated as "high" voltage devices. One or more technical effects, advantages, and benefits of the method include the ability to fabricate semiconductor devices capable of achieving a voltage distribution of at least approximately 650 volts (e.g., 1200 volts or more, or even several thousand volts).

[0050] The method 300 may be implemented using software stored in at least one memory and executed by at least one processor. The at least one memory and at least one processor may be replaced by other hardware, such as a bus or other communication mechanism, or may be included in the computing system or environment. The at least one processor may be any type of general purpose or specific processor, such as a CPU, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a graphics processing unit (GPU), a controller, a multi-core processing unit, a three-dimensional processor, a quantum computing device, or a combination thereof. The at least one processor may also have multiple processing cores, at least some of which may be configured to perform a specific function. Multiple parallel processes may also be performed. The at least one memory may be a non-transitory computer readable medium accessed by the at least one processor, and may include volatile media, non-volatile media, etc., and may be configured to store information, instructions, commands, or data that the at least one processor executes or processes. In one or more embodiments, the software may comprise or correspond to technology computer-aided design (TCAD) simulation software. Examples of TCAD include, but are not limited to, Synopsys TCAD and Silvaco TCAD. In one or more embodiments, the software may utilize machine learning (e.g., using neural networks) and / or artificial intelligence.

[0051] The method 300 begins at block 310 where a breakdown voltage (BV) design target (i.e., a defined or pre-determined target for a semiconductor design) is determined and / or set. The breakdown voltage design target may be, for example, a BV for a semiconductor design (e.g., a SiC device design) plus or minus a pre-determined percentage or range. The BV and semiconductor design may be determined according to device design specifications, for example, taking into account the intended use and desired functionality of the device. The device design specifications preferably detail the desired characteristics of the semiconductor device to be targeted or manufactured (e.g., device design target specifications and parameters), and may be stored in a medium, such as an electronic medium. The software may be utilized to receive and / or analyze the device design specifications to aid in determining the semiconductor design and BV. In one or more embodiments, the software may receive one or more inputs (e.g., user input) to consider, determine, select, test, or set various characteristics, such as the BV, of the semiconductor design.

[0052] In one or more embodiments, a BV can be selected as the breakdown voltage design target, or the design target value for the breakdown voltage can be set as a percentage greater than the target BV. For example, an input value that is 10% greater than the device design specs can be selected as an initial input value, which is the focus of any simulations using the software. For example, if the device design specs indicate a BV of 650 volts, 800 volts, 900 volts, 1000 volts, 1200 volts, or 1800 volts, the selected breakdown voltages can be 715 volts, 880 volts, 900 volts, 1100 volts, 1320 volts, and 1980 volts, respectively. In one or more embodiments, the breakdown voltage design target can be selected from a range, such as 200 volts to 1800 volts. It should be noted that these ranges and voltage values ​​are exemplary and are not intended to be limiting.

[0053] The method 300 of the present invention then proceeds to one or more of blocks 320, 330, and 340, which may be performed in parallel or in any order. It is noted that during any of the operations of blocks 320, 330, and 340, the software may utilize or may utilize TCAD simulation software in terms of semiconductor design.

[0054] In block 320, an incremental voltage drop is determined and / or set for each termination unit. The incremental voltage drop for each termination unit does not represent a specific value because the incremental voltage drop may be an acquired voltage or a dynamically adapted value resulting in the adaptive termination unit. The incremental voltage drop for each termination unit represents an approximate target value to allow for variability and flexibility in the design. For example, if the selected incremental voltage drop is 200 volts, this represents a range of ±10 volts to less than 200 volts. Note that the incremental voltage drop is a median value detailed in the device design specifications, and the software may receive inputs regarding the device design specifications from which the median value may be determined. In one or more embodiments, the software may receive one or more inputs (i.e., user input, etc.) to determine / select the incremental voltage drop. In this manner, the design may implement an initial portion of the adaptive edge termination to determine / set the incremental voltage drop for each termination unit. The software may determine which incremental elements of the SiC have acquired or dynamically adapted voltages. This can be done, for example, by varying various target specifications and parameters of the design.

[0055] It should be noted that the consideration of incremental voltage drop is completely inapplicable to the prior art, since conventional dielectric layer elements fix the voltage via capacitive coupling governing the potential field distribution according to material properties (as these conventional dielectric layer elements are non-adaptive, there is no need to determine the incremental voltage drop). In one or more embodiments, the incremental voltage drop can be selected from a range, such as a range of 50 volts to 300 volts, and can be set as an approximate target value, such as a range of 50 volts, 100 volts, 120 volts, 150 volts, 200 volts, or 300 volts. It should be noted that these ranges and approximate target values ​​are exemplary and not limiting.

[0056] In block 330, the quantity / number of termination units is determined and / or set. According to an exemplary breakdown voltage design target and the determined incremental voltage drop, the minimum / number of termination units is selected from a predefined range. For example, the range may be from 4 units to 8 units. For example, if the selected breakdown voltage target is 715 volts and the selected incremental voltage drop is 200 volts, the software determines the required number of termination units to be 4. With four termination units and 715 volts, the incremental voltage drop can be evaluated to be 178.75 (which is insignificant within ±10 of 200 volts). Note that each termination unit is 89.38 volts with the software being able to redesign based on the location of this termination unit and select 715 volts for subsequent iterations.

[0057] In block 340, the quantity / number of elements (e.g., floating field rings 145) per termination unit is determined and / or configured. For example, by running TCAD simulation software in one or more termination units, the software determines the number of elements to be placed along a region of 4 elements to 6 elements, etc. for that termination unit. The software then repeats this determination for the next termination unit until all termination units have the specified number of elements. Note that the region of elements may be "denser" or "narrower" than the region of the termination unit. For reference, a region of 4 elements to 6 elements is "denser" or "narrower" than a region of 4 termination units to 8 termination units. This "denser" or "narrow" configuration of elements indicates that it is possible to form smaller, more densely packed elements while facilitating termination layout design.

[0058] At block 350, a structure for the semiconductor device is generated. The structure can be generated according to a breakdown voltage design goal by using one or more of the incremental voltage drop per termination unit, the number of termination units, and the amount of elements per termination. For example, the software can generate the structure using the incremental voltage drop per termination unit, the number of termination units, and / or the amount of elements per termination unit as inputs to the TCAD simulation software. For example, the structure can include parameters for elements / components of the termination units or components of the entire semiconductor device. During the generation of the structure, the software automatically determines the size and dimensions of the floating field rings for each termination unit and their spacing.

[0059] 2, using device design specifications and software simulations described herein, floating field ring 145.1D of termination unit 101 may be determined to have a dimension A, floating field ring 145.2D of termination unit 101 may be determined to have a dimension B, floating field ring 145.3D of termination unit 101 may be determined to have a dimension C, floating field ring 145.4D of termination unit 101 may be determined to have a dimension D, and floating field ring 145.5D of termination unit 101 may be determined to have a dimension E. A, B, C, D and E may be dimensions such as height (in cross section), width (in cross section) and / or volume.

[0060] In this embodiment, these dimensions are A>B, A>C, A>D, and A>E. Furthermore, the dimensions B, C, D, and E may be substantially the same. However, these dimensions may be the same or different as determined by a design method, preferably one or more methods described herein.

[0061] Referring to FIG. 2, the device design specifications and software simulations described herein may be used to determine a spacing (or distance) S1 between floating field rings 145.1D and 145.2D, a spacing S2 between floating field rings 145.2D and 145.3D, a spacing S3 between floating field rings 145.3D and 145.4D, and a spacing S4 between floating field rings 145.4D and 145.5D. Furthermore, S1>S2 and S2, S3, and S4 may be substantially the same, but the spacings (distances) may be the same or different. This spacing determination may be made throughout the structure. Referring to FIG. 4, FIG. 4 is a diagram 400 illustrating an electrical termination layer 135 according to one or more embodiments.

[0062] Diagram 400 illustrates aspects of electrical termination layer 135 that may be determined in terms of creating one or more structures. Diagram 400 illustrates gaps 410 for floating field ring group 412, gaps 420 and 424 for floating field ring group 426, gaps 440 and 444 for floating field ring group 446, gaps 460 and 464 for floating field ring group 466, and gaps 480 and 484 for floating field ring group 486. It should be noted that floating field ring groups 416, 426, 446, 466, and 486 may each be aligned with termination units AE of FIGS. 1 and 2. The dimensions of each of the gaps 410, 420, 424, 440, 444, 460, 464, 480, and 484 can be set along a predetermined range, i.e., from submicron level (e.g., 0.0001 mm) to micron level (e.g., 0.009 mm). The dimensions of each of the gaps 410, 420, 424, 440, 444, 460, 464, 480, and 484 can be changed during initial mutual setting, or can be set uniformly.

[0063] In one or more embodiments, during creation of one or more structures, the width of each floating field ring 145.1 that connects to the floating field plate 170 through the channel via 165 can be set to be wider than any of the uncoupled floating field rings 145.2-145.5. Additionally, during creation of one or more structures, the uncoupled floating field rings 145.2-145.5 can maintain the same width. For example, the coupling of the floating field ring 145.1 to the metal plate 170 and floating field plate 180 combination is determined by the software for the appropriate floating field plate 145.1 that exhibits a predetermined voltage drop (e.g., 20 volts to 300 volts depending on the voltage level of the spec design). Similarly, the above group (i.e., 492, 494, 495, 496, and 498) corresponds to a particular metal plate 170 and floating field plate 180 combination, although not all floating field rings 145 are coupled to a particular metal plate 170 and floating field plate 180 combination.

[0064] In decision block 360, the structure is evaluated. For example, FIG. 5 illustrates a diagram of a semiconductor device structure 500 according to one or more embodiments. Structure 500 illustrates an exemplary output of block 350 that a customer or designer can evaluate on a display or screen. Structure 500 is an adaptive edge termination having floating field rings 506 and 545 in termination area 546, and having metal floating field plate 570 and polysilicon floating field plate 580. Layer 590 can be an ILD (e.g., an interlevel or interlayer dielectric material, typically thermal oxide and / or deposited oxide). Note that floating field ring 545 connected to floating field plate 570 can be a p-well for an n-channel MOSFET. The p-well can be the same as the p-body layer of the n-channel MOSFET.

[0065] Decision block 360 has sub-blocks 365 and 375 which test and verify the homogeneity distribution (upper bound homogeneity) of the entire structure, for example using the software described above, and which energies of the structure are below the critical electric field of internal elements.

[0066] For sub-block 365, the electric field distribution of one or more structures is evaluated, such as by using TCAD simulation, to ensure that the distribution is homogeneous. For example, during evaluation, it may be desirable to minimize the number of floating field rings and / or termination units to simplify the final semiconductor device. Additionally, the software may be configured to reduce the dimensions of each of the gaps 410, 420, 424, 440, 444, 460, 464, 480, and 484 from their initial settings, such as by individually modifying (increasing or decreasing) these settings. Additionally, the software evaluation may involve the software receiving one or more inputs, such as a specific designated factory, and manufacturing the final semiconductor device while considering the process design rules of the factory. In this manner, the software considers and determines aspects of manufacturability.

[0067] For sub-block 375, TCAD simulation software is used to evaluate the critical field for each element of one or more structures, where the critical field for each element can be a field that identifies incompatible materials for forming the element (i.e., BV). For example, the tolerance of the epitaxial layer 130 as determined by the supplier / fabric can be taken into account by the software when evaluating the doping range of the electrical termination layer 135, such that a typical doping level range can be considered for the electrical termination layer 135 that is below the critical field.

[0068] In this way, performance is optimized by TCAD simulation software during device design. Starting with a structure with equally spaced elements and simulation, the breakdown voltage of the structure can be restored (i.e., the structure will not go over or under designed) and the electric field distribution can be restored (i.e., the structure will not exceed the critical electric field of the material (e.g., silicon with a particular rating) and the electric field distribution will be homogenous). In one or more embodiments, the electric field maximum is less than 50% (10%-40%) of the electric field. The software (customer / designer) can observe, evaluate, and verify that the value is within an acceptable range, such as 10%-20%. If not, the method 300 can be repeated (looped back) at one or more method steps, adjusting any of the previously selected parameters and running another simulation.

[0069] Continuing with the description, reference is now made to FIG. 6, which is a diagram 600 illustrating the incremental distribution of the electric field in an adaptive edge termination semiconductor device according to one or more embodiments. Generally speaking, as the voltage increases rapidly during operation, the potential of each floating field ring (e.g., 145) increases until a limiting value is reached. This incremental increase explains the adaptive / dynamic nature of the embodiments described herein. As shown in diagram 600, the incremental distribution of the electric field covers the X1 side or left edge of the termination at source 102 or ground potential to the X2 edge or right edge of the termination at drain 103 (at peak voltage). For example, the voltage starts at zero across the adaptive edge termination semiconductor device 600. As the voltage increases, the potential of the first termination unit on the X1 side or leftmost side increases until it reaches a limit of 70 volts (shown as 69.2 volts). The remaining termination units continue to increase as well. The voltage remains high after the fifth and final termination unit, requiring further evaluation and adjustment by the software (customer / designer). In some cases, it is possible to provide different end units at equal intervals and / or with varying numbers of elements per end unit.

[0070] In one or more embodiments, the dimensions of the last metal plate and / or the last floating field plate (moving from the X1 direction to the X2 direction, moving to the right in the drawing) can be set, determined, or adjusted to accommodate this voltage stacking. Referring to FIG. 7, FIG. 7 is a diagram illustrating an adaptive edge termination semiconductor device in accordance with one or more embodiments. Metal plate 170E (i.e., the right or last metal plate or drain side metal plate) has a length 705 (which is an additional portion of source side length 710) and a drain side length 715. The source side length and drain side lengths 710 and 715 are measured from the drain side or X2 plane of epitaxial layer 135. Note that the drain side or X2 plane of metal plate 170E extends outside or beyond the drain side or X2 plane of epitaxial layer 135. In one or more embodiments, drain side length 715 is equal to or greater than a junction depth 720 of epitaxial layer 135. For example, drain side length 715 can have a 2:1 size ratio to junction depth 720. Additionally, floating field plate 180E (i.e., the last floating field plate or the drain side floating field plate) can have a drain side or X2 plane inside or within the drain side of epitaxial layer 135, as shown by X1-X2 distance 730. That is, extending metal plate 170E longer can accommodate voltage stacking by spreading the voltage over a larger surface distance (i.e., drain side length 715 equal to or greater than junction depth 720).

[0071] In block 390, a final termination layout design is determined that targets the breakdown voltage design goal. The final termination layout design uses the electric field distribution to keep the peak electric field in the insulating layer small, so that the charge instability present in the insulating layer does not cause high electric fields and BV degradation. For example, for SiC material, the high electric field can reach 5E5 to 4E6 volts / cm, and the maximum electric field area is the maximum electric field value in the device, and the electric field is not uniform across the device, which results in a significant area limitation. That is, the semiconductor device 100 has a "robust and stable" BV. In other words, the BV remains constant throughout the life of the semiconductor device 100 under different operating conditions and does not change during the stress evaluation and qualification procedures required for the qualification of the semiconductor device.

[0072] Different semiconductor embodiment embodiments have been described with reference to the accompanying drawings. These embodiments are not mutually exclusive, and features found in one embodiment may be used in combination with features of one or more of the other embodiments to achieve the accompanying embodiments. Accordingly, the embodiments shown in the accompanying drawings are for illustrative purposes only and are not intended to limit the invention in any manner.

[0073] Those skilled in the art will appreciate that additional method steps, such as additional cutting, curving, laminating or layering, may be used.

[0074] The above description is for illustrative purposes only and is not intended to be limiting, and the present invention can be implemented in various different embodiments without departing from the spirit and scope of the invention. Although the present invention has been described in detail above, those skilled in the art will readily appreciate that numerous physical changes can be made to the present invention without changing the inventive ideas and principles specifically disclosed herein. In addition, numerous embodiments incorporating only a small portion of the preferred embodiment are possible, and such small portion does not change the inventive ideas and principles disclosed herein. The embodiments of the present invention and the configurations optionally employed are in all respects illustrative and / or explanatory only, and not limiting. The scope of the present invention as described above, as well as all alternatives and modifications of the embodiments that fall within the meaning and scope of the claims, are all within the scope of the present invention. [Explanation of symbols]

[0075] 100 Semiconductor Devices 105 First area 110 Base layer 120 Buffer Layer 130 Epitaxial Layer 135 Electrical Termination Layer 150 Second area 185 High voltage side metal plate 190 Gates 300 ways 360 Decision Block 400 Diagram 500 Structure 546 Termination Area 570 Metal Floating Field Plate 580 Polysilicon floating field plate 590 layers 705 Length 715 Drain side length 720 Junction Depth 730 X1-X2 distance 102, 103 Drain 170, 710 Source side length 365, 375 subblocks 310, 320, 330, 340, 350, 390 blocks 412, 416, 426, 446, 466, 486 Floating Field Rings 410, 420, 424, 440, 444, 460, 464, 480, 484 Gap 101, AE terminal unit 145.1, 180, 180A, 180B, 180C, 180D, 180E Floating Field Plates 160, 160D Dielectric film 165, 165A, 165B, 165C, 165D, 165E Channel Vias 170, 170E, 175A, 175B, 175C, 175D, 175E Metal Plate 175, 175A, 175B, 175C, 175D, 175E Connection Vias 145, 145.1B-145.5B, 145.1C-145.5C, 145.1D-145.5D, 145.1E-145.4E, 506, 545 Floating Field Ring 291, 292 X2 side A, B, C, D, E dimensions

Claims

1. 1. A semiconductor device having two or more termination units, each of the two or more termination units comprising: Via Channel, Connection vias, a plurality of floating field rings, the first floating field ring having a first width and a second floating field ring having a second width different from the first width; a metal plate coupled to the first floating field ring through the via channel; and a floating field plate coupled to the metal plate through the connecting via; The two or more termination units provide a field distribution configured to dissipate a voltage propagating from a drain of the semiconductor device to a source of the semiconductor device. A semiconductor device comprising:

2. 2. The semiconductor device of claim 1, wherein each of the two or more termination units extends from a first region of the semiconductor device into a second region of the semiconductor device.

3. 3. The semiconductor device of claim 2, wherein the first region comprises at least one of an insulator film, the metal plates of the two or more termination units, and a floating field plate of the two or more termination units.

4. 3. The semiconductor device of claim 2, wherein a plurality of floating field rings of each of said two or more termination units are present in an electrical termination layer in said second region.

5. 2. The semiconductor device of claim 1, wherein a width of each of the two or more termination units extends from an outer wall of the first floating field ring to an outer wall of the second floating field ring.

6. The semiconductor device of claim 1 , wherein the first width is greater than the second width.

7. 2. The semiconductor device of claim 1, wherein each of the two or more termination units is configured to contribute to the electric field distribution according to a voltage drop between the termination units.

8. 2. The semiconductor device of claim 1, wherein the floating field plate of each of the two or more termination units is associated with at least one of a plurality of floating field rings of the same termination unit.

9. 2. The semiconductor device of claim 1, wherein at least one of the plurality of floating field rings of each of the two or more termination units is not accompanied by a corresponding floating field plate of the same termination unit.

10. 2. The semiconductor device of claim 1, wherein each of said plurality of floating field plates is made of polysilicon.

11. 2. The semiconductor device of claim 1, wherein the conductor device is a metal-oxide-semiconductor field effect transistor.

12. providing said plurality of floating field rings in an implanted layer of the same conductivity type as said floating field rings; 2. The semiconductor device of claim 1, wherein the implanted layer has a doping concentration that is lower than a doping concentration of the plurality of floating field rings.

13. 13. The semiconductor device of claim 12, wherein the doping concentration of the implanted layer is within a range of about 30% to about 70% higher than a doping concentration of an epitaxial layer of the semiconductor device.

14. 2. The semiconductor device of claim 1, wherein a drain side of a drain side metal plate extends beyond a drain side of an epitaxial layer of the semiconductor device.

15. 2. The semiconductor device of claim 1, wherein a drain side length of the drain side metal plate is equal to or greater than a junction depth of an epitaxial layer of the semiconductor device.

16. 1. A method for forming a semiconductor device, the method comprising: determining a breakdown voltage design target based on a predetermined breakdown voltage for the semiconductor device; generating a structure for a semiconductor device having at least two termination units in accordance with said breakdown voltage design goal utilizing one or more incremental voltage drops per termination unit, a predetermined number of termination units, and a predetermined amount of elements per termination unit; Evaluating whether the structure constitutes a uniform portion or energy below a critical field; and determining a final termination layout design for said semiconductor device; 1. A method for forming a semiconductor device comprising:

17. 17. The method of claim 16, wherein the predetermined number of termination units is selected from the range of 4 units to 8 units, and the amount of elements per termination is selected from the range of 4 units to 6 units.

18. 17. The method of claim 16, further comprising using software to perform a simulation to automatically determine element dimensions and inter-element gaps for each end unit of the structure as the structure is generated.

19. 17. The method of claim 16, further comprising iteratively repeating one or more steps to optimize the structure to the final termination layout design by adjusting one or more of an incremental voltage drop per termination unit, the number of termination units, and an amount of elements per termination unit.

20. A termination unit for a semiconductor device, comprising: Via Channel, Connection vias, Multiple floating field rings, a metal plate coupled to the first floating field ring through the via channel; and a floating field plate coupled to the metal plate through the connecting via; having a drain side of the metal plate extends beyond a drain side of an epitaxial layer of the semiconductor device, and a drain side length of the metal plate is equal to or greater than a junction depth of the epitaxial layer; 1. A termination unit for a semiconductor device comprising:

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