ECS CIRCUIT, ECS METHOD, AND MEMORY

Abstract

An embodiment of the present invention provides an ECS circuit, an ECS method, and a memory, the ECS circuit comprising: an ECS control module, a command generation module, an address counting module, and an error tracking and recording module, in which the ECS control module is configured to receive a mode control signal and generate an ECS command signal based on the mode control signal; the command generation module is configured to generate an internal command signal based on the ECS command signal, the internal command signal is used to perform a corresponding ECS ​​operation; the address counting module is configured to perform address counting based on the internal command signal and generate an end-of-count signal when counting of a target address is completed; the error tracking and recording module is configured to receive an error signal and generate an error tracking signal based on the end-of-count signal and the error signal, the error tracking signal is used to record error information of the ECS operation.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application is filed based on a Chinese patent application filed with the China Patent Office on October 8, 2022, bearing application number 202211222144.2 and titled "ECS CIRCUIT, ECS METHOD, AND MEMORY", and claims priority to the Chinese patent application, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the field of semiconductor technology, and in particular to ECS circuits, ECS methods, and memories. [Background technology]

[0003] With the continuous development of semiconductor technology, people's demand for data transmission speed is increasing when manufacturing and using devices such as computers. In order to achieve higher data transmission speeds, devices such as memory that can transmit a series of data at double data rate (DDR) have appeared.

[0004] However, as memory transmission speeds become faster and faster, errors may occur in memory due to factors such as shrinkage of memory cells and row hammering, in which case it is necessary to perform error detection on the memory and correct the detected errors in a timely manner. Taking dynamic random access memory (DRAM) as an example, it is necessary to perform a complete error check and scrub (ECS) on the DRAM at least once every 24 hours. Summary of the Invention [Problem to be solved by the invention]

[0005] Embodiments of the present invention provide an ECS circuit, an ECS method, and a memory. [Means for solving the problem]

[0006] In a first aspect, an embodiment of the present invention provides an ECS circuit comprising an ECS control module, a command generation module, an address counting module, and an error tracking module, wherein: the ECS control module is configured to receive a mode control signal and generate ECS command signals based on the mode control signal; the command generation module is configured to generate internal command signals based on the ECS command signals, the internal command signals being used to perform corresponding ECS ​​operations; The address count module is configured to perform address counting based on the internal command signal, and generate a count end signal when counting of target addresses is completed; The error tracking recording module is configured to receive an error signal and generate an error tracking signal based on the count end signal and the error signal, and the error tracking signal is used to record error information of the ECS operation.

[0007] In some embodiments, the mode control signal comprises a multi-purpose command (MPC) signal or a refresh command signal, where: the ECS control module is further configured to generate the ECS command signals based on the MPC signals when the ECS operation is in a manual ECS mode of operation; or The ECS control module is further configured to generate the ECS command signal based on the refresh command signal when the ECS operation is in an automatic ECS operation mode.

[0008] In some embodiments, the ECS control module includes a first timing module and a command control module, wherein: the first timing module is configured to generate an ECS identification signal; The command control module is configured to receive the ECS identification signal, and, if the ECS identification signal is in a valid state, obtain a refresh command signal, and generate the ECS command signal based on the refresh command signal.

[0009] In some embodiments, the first timing module is configured to receive a first clock signal, count based on the first clock signal, generate the ECS identification signal, and send the ECS identification signal to the command control module, where when a count value meets a predetermined condition, the ECS identification signal is in an enabled state.

[0010] In some embodiments, the first timing module is further configured to stop the counting when the ECS identification signal is in a valid state; The command control module is further configured to generate a reset signal after generating the ECS command signal based on the refresh command signal, and send the reset signal to the first timing module to control the first timing module to resume counting and put the ECS identification signal into an invalid state.

[0011] In some embodiments, the command control module is further configured to output the received refresh command signal as an internal refresh signal to perform a refresh operation when the ECS identification signal is in an invalid state.

[0012] In some embodiments, the command generation module includes an internal command generation module and a second timing module, wherein: The internal command generation module is configured to sequentially generate an activation signal, a read command signal, a write command signal, and a precharge signal according to a predetermined timing condition after receiving the ECS command signal; the second timing module is configured to control a time interval between the activation signal and the read command signal to satisfy a first timing condition, control a time interval between the read command signal and the write command signal to satisfy a second timing condition, and control a time interval between the write command signal and the precharge signal to satisfy a third timing condition; Here, the predetermined timing condition includes the first timing condition, the second timing condition, and the third timing condition.

[0013] In some embodiments, the ECS circuit further comprises a bank control module and a bank array, the bank array including at least one bank group, the bank group including at least one bank, the bank including at least one row and at least one column, where: the bank control module is configured to receive the internal command signal and perform an ECS operation on the bank array based on the internal command signal; The bank control module is further configured to generate the error signal and send the error signal to the error tracking module when error information is detected during execution of the ECS operation.

[0014] In some embodiments, the address counting module includes a column counting module, a row counting module, and an array counting module, where: the column count module is configured to receive the precharge signal, perform column counting for a target row based on the precharge signal, and generate a column output signal and a column done signal when column counting for the target row is completed; the row count module is configured to receive the precharge signal and the column output signal, perform row counting for a target bank based on the precharge signal and the column output signal, and generate a row output signal and a row end signal when row counting for the target bank is completed; The array count module is configured to receive the precharge signal and the row output signal, perform a bank count for a target bank group based on the precharge signal and the row output signal, generate a bank output signal and a bank end signal when the bank count for the target bank group is completed, perform a bank group count for the bank array based on the precharge signal and the bank output signal, and generate a bank group end signal and an ECS end signal when the bank group count for the bank array is completed.

[0015] In some embodiments, the array counting module includes a bank counting module and a bank group counting module, wherein: the bank count module is configured to receive the precharge signal and the row output signal, perform bank counting for a target bank group based on the precharge signal and the row output signal, and generate the bank output signal and the bank end signal when bank counting for the target bank group is completed; The bank group count module is configured to receive the precharge signal and the bank output signal, perform a bank group count for the bank array based on the precharge signal and the bank output signal, and generate the bank group end signal and the ECS end signal when a bank group count for the bank array is completed.

[0016] In some embodiments, the column count module is further configured to, after generating the column output signal and the column done signal, continue column counting of a next target row until column counting of each row of the bank array is completed; the row count module is further configured to, after generating the row output signal and the row end signal, continue row counting of a next target bank until row counting of each bank of the bank array is completed; The array count module is further configured to continue bank counting of a next target bank group after generating the bank output signal and the bank end signal until bank counting of each bank group of the bank array is completed.

[0017] In some embodiments, the error tracking module includes a first error tracking module, wherein: The first error tracking and recording module is configured to receive a counting mode signal, and determine that the counting mode of the first error tracking and recording module is a codeword counting mode when the counting mode signal is a first value, or determine that the counting mode of the first error tracking and recording module is a row counting mode when the counting mode signal is a second value.

[0018] In some embodiments, the first error tracking module is configured to receive the error signal when the counting mode is the codeword counting mode, perform codeword counting based on the error signal, determine a first count value upon receiving the ECS end signal, compare the first count value with a first threshold, and store the first count value if the first count value is greater than or equal to the first threshold, where the first count value is used to represent the number of codewords in which error information exists in the bank array.

[0019] In some embodiments, the first error tracking module is configured to receive the error signal and the column end signal when the counting mode is the row counting mode, perform error row counting based on the error signal and the column end signal, determine a second count value upon receiving the ECS end signal, compare the second count value with a second threshold, and store the second count value if the second count value is greater than the second threshold, where the second count value is used to represent the number of rows in the bank array in which at least one error information exists.

[0020] In some embodiments, the error tracking module further comprises a second error tracking module, wherein: the second error tracking and recording module is configured to receive the error signal, count error information of a target row according to the error signal and the end of column signal, and after determining a third count value of the target row, compare the third count value with a target count value stored in a first register module; if the third count value is greater than the target count value, scrub the target count value stored in the first register module, and save the third count value as a target count value in the first register module; continue to perform error counting of a next target row according to the error signal and the end of column signal until receiving the end of ECS signal; and determine a target count value stored in the first register module when the end of ECS signal is received, wherein the third count value is used to represent the number of codewords in which error information exists in the target row.

[0021] In some embodiments, the second error tracking and recording module is further configured to store address information corresponding to the target count value in a second register module when storing the target count value in a first register module, where the address information includes row address information, bank address information, and bank group address information corresponding to the target count value.

[0022] In some embodiments, the second error tracking module is further configured to, after receiving the ECS end signal, compare the currently stored target count value in the first register module with a third threshold, and if the target count value is greater than or equal to the third threshold, retain the target count value stored in the first register module and the address information stored in the second register module, and scrub the target count value stored in the first register module and the address information stored in the second register module if the target count value is less than the third threshold.

[0023] In a second aspect, embodiments of the present invention provide an ECS method applied to an ECS circuit according to the first aspect, the method comprising: receiving, by the ECS control module, a mode control signal and generating ECS ​​command signals based on the mode control signal; receiving, by the command generation module, the ECS command signal and generating an internal command signal based on the ECS command signal, the internal command signal being used to perform a corresponding ECS ​​operation; receiving the internal command signal by the address count module, performing address counting according to the internal command signal, and generating a count end signal when the counting of the target address is completed; receiving, by the error tracking recording module, the count end signal and the error signal, and generating an error tracking signal based on the count end signal and the error signal, wherein the error tracking signal is used to record error information of the ECS operation.

[0024] In a third aspect, an embodiment of the present invention provides a memory comprising an ECS circuit according to the first aspect. Effect of the Invention

[0025] An embodiment of the present invention provides an ECS circuit, an ECS method, and a memory, the ECS circuit comprising: an ECS control module, a command generation module, an address counting module, and an error tracking and recording module, in which the ECS control module is configured to receive a mode control signal and generate an ECS command signal based on the mode control signal; the command generation module is configured to generate an internal command signal based on the ECS command signal, the internal command signal is used to perform a corresponding ECS ​​operation; the address counting module is configured to perform address counting based on the internal command signal, and generate an end-of-count signal when counting of a target address is completed; the error tracking and recording module is configured to receive an error signal and generate an error tracking signal based on the end-of-count signal and the error signal, the error tracking signal is used to record error information of the ECS operation. In this way, an embodiment of the present invention can generate an ECS command signal based on the mode control signal to perform an ECS operation, thereby performing complete error detection and scrubbing on the memory; and, after the execution of the ECS operation is completed, can generate an error tracking signal based on the error signal and the count end signal to record the error information of the ECS operation, thereby quickly locating and repairing the location where the error information exists in the memory, and ultimately improving the performance of the memory. [Brief description of the drawings]

[0026] [Figure 1] FIG. 2 is an exemplary structural diagram of an ECS circuit configuration according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic diagram of ECS operating mode selection according to an embodiment of the present invention. [Diagram 3] FIG. 2 is an exemplary structural diagram of an ECS control module configuration according to an embodiment of the present invention. [Figure 4] FIG. 2 is an exemplary structural diagram of a configuration of a command generating module according to an embodiment of the present invention; [Diagram 5] FIG. 2 is a schematic diagram of a partial structure of an ECS circuit according to an embodiment of the present invention. [Figure 6] FIG. 2 is an exemplary structural diagram of a bank array configuration according to an embodiment of the present invention. [Figure 7] FIG. 13 is an exemplary structural diagram of an address counting module configuration according to an embodiment of the present invention; [Figure 8] FIG. 13 is an exemplary structural diagram of another address counting module configuration according to an embodiment of the present invention; [Figure 9] FIG. 2 is a schematic diagram of a specific structure of an ECS circuit according to an embodiment of the present invention; [Figure 10] 1 is an exemplary flow chart of an ECS method according to an embodiment of the present invention. [Figure 11] FIG. 2 is an exemplary structural diagram of a memory configuration according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In the following, the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention. It can be understood that the specific embodiments described in this specification are only for illustrating the relevant invention, and do not limit the present invention. It should be further noted that, for convenience of description, only the parts related to this application are shown in the drawings.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art. The terms used herein are only for the purpose of describing the embodiments of the present invention and are not intended to limit the present invention.

[0029] In the following description, the term "some embodiments" refers to a subset of all possible embodiments, and it is understood that the terms "some embodiments" may refer to the same or different subsets of all possible embodiments, which may be combined with each other to the extent not inconsistent.

[0030] The terms "first / second / third" referred to in the embodiments of the present invention are merely intended to distinguish between similar objects and do not represent a particular order of the objects, and it will be understood that "first / second / third" may, in some cases, be interchangeable with a particular order or precedence, such that the embodiments of the present invention described herein may be performed in an order other than that illustrated or described.

[0031] Before describing the embodiments of the present invention in more detail, first, the nouns and terms referred to in the embodiments of the present invention will be explained. The nouns and terms referred to in the embodiments of the present invention have the following interpretations.

[0032] Dynamic Random Access Memory (DRAM) Double Data Rate (DDR) 5th generation DDR standard (DDR5 SPEC: DDR5 Specification) Multi-Purpose Command (MPC) Error Check and Scrub (ECS) Mode Register (MR) Auto Refresh (REFab:Auto_Refresh) Self-Refresh (Self_REF or SRE:Self_Refresh) Error Check and Correct (ECC) Taking DDR5 DRAM as an example, in the ECS mode, the DRAM can read and correct the detected error codeword, and write the corrected data back to the bank array while recording the error count, which requires that the DRAM perform a complete error detection and scrub at least once every 24 hours. The ECS operation mode includes an automatic operation mode and a manual operation mode, which can be selected by the mode register signal MR14 OP [7]. When performing an automatic ECS operation, the refresh command signal and the self-refresh command signal can be used to obtain the ECS command signal, and when performing a manual ECS operation, the MPC signal is required, and the MR15 can also determine whether to perform a manual ECS operation during self-refresh.

[0033] In order to realize the functions of error detection and scrubbing, and recording detected error information, an embodiment of the present invention provides an ECS circuit including an ECS control module, a command generation module, an address counting module, and an error tracking and recording module, where the ECS control module is configured to receive a mode control signal and generate an ECS command signal based on the mode control signal, the command generation module is configured to generate an internal command signal based on the ECS command signal, the internal command signal is used to perform a corresponding ECS ​​operation, the address counting module is configured to perform address counting based on the internal command signal and generate an end-of-count signal when counting of the target address is completed, and the error tracking and recording module is configured to receive the error signal and generate an error tracking signal based on the end-of-count signal and the error signal, the error tracking signal is used to record error information of the ECS operation. In this way, an embodiment of the present invention can generate an ECS command signal based on the mode control signal to perform an ECS operation, thereby performing complete error detection and scrubbing on the memory; and, after the execution of the ECS operation is completed, can generate an error tracking signal based on the error signal and the count end signal to record the error information of the ECS operation, thereby quickly locating and repairing the location where the error information exists in the memory, and ultimately improving the performance of the memory.

[0034] Hereinafter, each embodiment of the present invention will be described in detail with reference to the drawings.

[0035] In one embodiment of the present invention, Fig. 1 illustrates an exemplary structural diagram of an ECS circuit 10 according to an embodiment of the present invention. As shown in Fig. 1, the ECS circuit 10 may include an ECS control module 11, a command generation module 12, an address counting module 13, and an error tracking module 14, where: The ECS control module 11 is configured to receive a mode control signal and generate an ECS command signal based on the mode control signal; The command generation module 12 is configured to generate an internal command signal based on the ECS command signal, the internal command signal being used to perform a corresponding ECS ​​operation; The address count module 13 is configured to perform address counting based on the internal command signal, and generate a count end signal when the counting of the target address is completed; The error tracking recording module 14 is configured to receive the error signal and generate an error tracking signal based on the count end signal and the error signal, and the error tracking signal is used to record error information of the ECS operation.

[0036] It should be noted that the embodiment of the present invention relates to an overall framework design of an ECS circuit in an integrated circuit design, particularly for a DRAM DDR5 chip that needs to perform a complete error detection and scrub on the DRAM at least once every 24 hours. The overall framework of the ECS circuit is used to generate an ECS command signal, some internal command signals, and an error tracking signal to perform internal read / write error detection and repair while detecting error information. The ECS circuit can be applied to related circuits for performing ECS ​​functions in a DRAM DDR5 chip, but is not limited to this scope, and the design can also be adopted in other memory chips, and internal command generation, timing control and counting circuits, etc.

[0037] In addition, taking the ECS operation applied to DRAM as an example, the ECS circuit according to the embodiment of the present invention can realize error detection and scrubbing of the bank array. In brief, the function that the embodiment of the present invention is to realize is to generate an ECS command signal using a multi-purpose command signal (which can be represented by MPC) or a refresh command signal in a manual ECS operation mode and an automatic ECS operation mode, generate an internal command signal required to perform an ECS operation internally, perform complete error detection and scrubbing for the DRAM, and use other modules to track and record the detected error information. Here, the refresh command signal may include a refresh signal (which can be represented by REFab) and a self-refresh signal (which can be represented by Self-REF). Thus, in the embodiment of the present invention, the ECS command signal may be generated based on the MPC signal or the refresh command signal, or based on other appropriate signals, and is not particularly limited here.

[0038] 1, the ECS control module 11 is a module for generating an ECS command signal, and each time an ECS command signal is generated, the DRAM executes one ECS operation correspondingly, where one ECS operation is performed for one memory bit in the bank array, and the ECS operation is used to determine whether there is a codeword error in the detected memory bit and correct the codeword error if detected.

[0039] Regarding the manner of generating the ECS command signals, in some embodiments, the ECS control module is further configured to receive an ECS mode selection signal and determine that the ECS mode of operation is a manual ECS mode of operation if the ECS mode selection signal is a first value or determine that the ECS mode of operation is an automatic ECS mode of operation if the ECS mode selection signal is a second value.

[0040] In some embodiments, ECS control module 11 is further configured to generate ECS command signals based on the MPC signals when the ECS operation is in a manual ECS mode of operation; or The ECS control module 11 is further configured to receive a first mode register signal when the ECS operation is in a manual ECS operation mode, and generate an ECS command signal based on the first mode register signal and the refresh command signal; or The ECS control module 11 is further configured to generate an ECS command signal based on the refresh command signal when the ECS operation is in the automatic ECS operation mode.

[0041] Note that Fig. 2 shows a schematic diagram of the selection of the ECS operation mode according to an embodiment of the present invention. As shown in Fig. 2, the ECS operation mode includes a manual ECS operation mode and an automatic ECS operation mode, and can be selected based on an ECS mode selection signal, where the ECS mode selection signal can be a mode register signal MR14_OP[7], when MR14_OP[7] is equal to 1, the DRAM executes the manual ECS operation mode, and when MR14_OP[7] is equal to 0, the DRAM executes the automatic ECS operation mode. In the embodiment of the present invention, 1 represents a high level logic 1, and 0 represents a low level logic 0.

[0042] In the manual ECS operation mode, when the ECS control module receives a specific MPC signal, it generates an ECS command signal based on the MPC signal to perform an ECS operation, where the specific MPC signal can indicate that the value of the MPC signal is 00001100.

[0043] Furthermore, in the manual ECS operation mode, it is determined whether to perform an ECS operation according to a refresh command signal and a first mode register signal, in which the refresh command signal refers to a self-refresh signal (Self-REF) and the first mode register signal refers to a mode register signal MR15 OP[3]. It can be understood that when receiving a Self-REF signal, the DRAM needs to perform a self-refresh operation, and MR15 OP[3] can determine whether an ECS operation needs to be performed before performing a self-refresh operation, and if MR15 OP[3] is equal to 1, one ECS operation needs to be performed when proceeding to self-refresh, that is, the ECS control module generates an ECS command signal according to the first mode register signal and the Self-REF signal whose specific bit has a value of 1 to perform an ECS operation. If MR15 OP[3] is equal to 0, no ECS operation is performed when self-refreshing, that is, the ECS control module does not generate an ECS command signal and the DRAM performs a self-refresh operation.

[0044] In the automatic ECS operation mode, the refresh command signal includes a self-refresh signal (Self-REF) and a refresh signal (REFab), and when a REFab signal is received, an ECS command signal can be generated based on the REFab signal to perform an ECS operation, or when proceeding to self-refresh, an ECS command signal can be generated based on the Self-REF signal to perform an ECS operation, where the average time between the execution of error detection and scrubbing can be represented by tECSint.

[0045] That is, in different ECS operation modes, an ECS command signal can be generated based on different command signals to perform an ECS operation, where in the automatic ECS operation mode, an automatic ECS operation can be performed based on a refresh signal (REFab) or based on a self-refresh signal (Self_REF), and in the manual ECS operation mode, an ECS operation can be performed based on a specific MPC signal or can be combined with a first mode register signal to determine whether to perform an ECS operation when self-refreshing. In this way, the ECS control module can generate an ECS command signal based on an MPC signal and / or a refresh command signal to perform an ECS operation, simplifying the process required to generate an ECS operation, and further, in combination with a mode register signal, can select different ECS operation modes and determine whether an ECS operation needs to be performed, thereby enhancing the flexibility of performing an ECS operation.

[0046] Further, regarding the configuration of the ECS control module, FIG. 3 illustrates an exemplary structural diagram of the configuration of the ECS control module 11 according to an embodiment of the present invention. As shown in FIG. 3, in some embodiments, the ECS control module 11 includes a first timing module 111 and a command control module 112, where: The first timing module 111 is configured to generate an ECS identification signal; The command control module 112 is configured to receive the ECS identification signal, and if the ECS identification signal is in a valid state, obtain a refresh command signal, and generate an ECS command signal based on the refresh command signal.

[0047] 3, the ECS control module 11 mainly includes a first timing module 111 and a command control module 112. Here, the command control module 112 selects which ECS operation mode to execute through the mode register signal MR14 OP[7], and executes the automatic ECS operation mode, i.e., the default mode of DDR5, when MR14 OP[7]=0, and executes the manual ECS operation mode when MR14 OP[7]=1, and the value of the MPC signal must be OP[7:0]=00001100.

[0048] In addition, since the DRAM requires that complete error detection and scrubbing be performed on the entire bank array at least once within 24 hours, in the automatic ECS operation mode, the first timing module must plan the ECS interval time so that error detection and scrubbing of the entire bank array is completed within 24 hours.

[0049] That is, in the automatic ECS operation mode, the first timing module 111 can generate and send an ECS identification signal (represented as ECS_Flag in FIG. 3) to the command control module 112, and the ECS_Flag signal goes into an active state at every specific preset time interval. The command control module 112 receives the ECS_Flag signal, and when the ECS_Flag signal is in an active state, obtains a refresh command signal, and generates an ECS command signal (represented as ECS_CMD in FIG. 3) based on the obtained refresh command signal. Here, the refresh command signal may include at least one of a refresh signal (REFab) and a self-refresh signal (Self-REF).

[0050] Regarding the manner in which the first timing module plans timing, in some embodiments, the first timing module is configured to receive a first clock signal, count based on the first clock signal, generate an ECS identification signal, and send the ECS identification signal to the command control module, where the ECS identification signal is in an enabled state when the count value meets a predetermined condition.

[0051] In addition, when the first timing module performs timing planning, it counts the first clock signal, and if the count value meets the predetermined condition, the ECS_Flag is in an active state, at which time the command control module 112 obtains a refresh command signal and generates an ECS command signal to instruct the execution of an ECS operation. It should be noted that the refresh command signal obtained here is the refresh command signal that appears after the count value meets the predetermined condition, so compared with the time when the count value meets the predetermined condition, the refresh command signal obtained here specifically refers to the next refresh command signal that appears, and can be abbreviated as the next refresh command signal. In this way, by planning the interval time of the ECS operation based on whether the count value meets the predetermined condition, it is possible to ensure that one complete error detection and scrubbing can be performed within 24 hours.

[0052] Here, the first clock signal may be a clock signal having a fixed frequency generated by an oscillator. For example, when the period of the first clock signal is 4.4 microseconds (μs), in the case of a 16 GB memory configuration, in order to complete one complete error detection and scrubbing for the DRAM within 24 hours, the time interval of the ECS operation needs to be set to 644 μs, and then, in order to complete one count, the count value needs to be about 644 / 4.4=146, at which time the count value satisfies the predetermined condition. That is, when the count value reaches 146, an ECS identification signal in a valid state can be generated.

[0053] In some embodiments, the first timing module is further configured to stop counting when the ECS identification signal is in a valid state; The command control module is further configured to generate a reset signal after generating the ECS command signal based on the refresh command signal, and send the reset signal to the first timing module to control the first timing module to resume counting and put the ECS identification signal into an invalid state.

[0054] In addition, in the embodiment of the present invention, the ECS_Flag signal may be in an active state or an inactive state, where the first timing module 111 generates an active ECS_Flag signal at regular time intervals to generate an ECS command signal, and the command control module 112 generates a reset signal (represented as Reset in FIG. 3) after generating the ECS command signal and sends it to the first timing module 111, so that the ECS_Flag signal becomes an inactive state and the first timing module 111 resumes counting.

[0055] In some embodiments, the command control module is further configured to output the received refresh command signal as an internal refresh signal to perform a refresh operation when the ECS identification signal is in an invalid state.

[0056] Specifically, the level value of the ECS identification signal may include a first value and a second value, where the first value may be a logic 1 indicating a high level and the second value may be a logic 0 indicating a low level, or the first value may be a logic 0 indicating a low level and the second value may be a logic 1 indicating a high level, but is not limited thereto.

[0057] Illustratively, when the level value of the ECS identification signal is logical 1, it can be determined that the ECS identification signal is in a valid state; otherwise, when the level value of the ECS identification signal is logical 0, it can be determined that the ECS identification signal is in an invalid state.

[0058] In addition, in the embodiment of the present invention, when the ECS identification signal is in a valid state, the refresh command signal received at the next timing is extracted, and an ECS command signal is generated based on the refresh command signal, and at the same time, the corresponding extracted refresh command signal is erased, and an ECS operation is performed. When the ECS identification signal is in an invalid state, the refresh command signal is not extracted, but is directly output as an internal refresh signal, and a refresh operation is performed. In FIG. 3, the internal refresh signal is represented by REF_NEW.

[0059] That is, the first timing module generates one valid ECS flag signal ECS_Flag every fixed time interval and stops counting the timing. The ECS_Flag signal is transmitted to the command control module, which then retrieves the next REFab signal or Self_REF signal to generate an ECS command signal, at the same time, the corresponding retrieved refresh command disappears, and then generates a reset signal and sends it to the first timing module to reset the ECS_Flag signal reset to an invalid value, causing the first timing module to resume counting. During the period when the ECS_Flag signal is an invalid value, no refresh command is retrieved and the REF_NEW signal is directly obtained, so that the ongoing refresh operation is not affected.

[0060] In this way, the command control module 112 "pulls out" the refresh command signal, i.e., when generating an ECS command signal, the corresponding refresh command signal disappears, so that no refresh operation is performed during the execution of an ECS operation. In this way, the power consumption of the memory during the execution of the ECS can be reduced, and memory failure caused by simultaneously executing a refresh operation during the execution of an ECS operation can also be prevented.

[0061] Further, as shown in FIG. 1 , after generating an ECS command signal, the ECS control module 11 sends the ECS command signal to the command generating module 12, and the command generating module 12 generates an internal command signal based on the ECS command signal, where the internal command signal is a command signal required to perform an ECS operation.

[0062] Regarding the command generating module 12, referring to FIG. 4, an exemplary structural diagram of the configuration of the command generating module 12 according to an embodiment of the present invention is shown. As shown in FIG. 4, in some embodiments, the command generating module 12 includes an internal command generating module 122 and a second timing module 121, where: The internal command generation module 122 is configured to sequentially generate an activation signal, a read command signal, a write command signal, and a precharge signal according to a predetermined timing condition after receiving the ECS command signal; the second timing module 121 is configured to control a time interval between the activation signal and the read command signal to satisfy a first timing condition, control a time interval between the read command signal and the write command signal to satisfy a second timing condition, and control a time interval between the write command signal and the precharge signal to satisfy a third timing condition; Here, the predetermined timing conditions include a first timing condition, a second timing condition, and a third timing condition.

[0063] In addition, the internal command signal may include an activation signal (Active, represented by ACT in FIG. 4), a read command signal (Read, represented by RD in FIG. 4), a write command signal (Write, represented by WR in FIG. 4), and a precharge signal (Precharge, represented by PRE in FIG. 4). Specifically, after receiving an ECS command signal (represented by ECS_CMD in FIG. 4), the internal command generating module 122 sequentially generates an ACT signal, an RD signal, a WR signal, and a PRE signal according to a predetermined timing condition, where the timing between each internal command signal is controlled by the second timing module 121.

[0064] Note that the time interval between the ACT signal and the RD signal is represented by tRCD, the time interval between the RD signal and the WR signal is represented by WL, and the time interval between the WR signal and the PRE signal is represented by tWR. Exemplarily, after receiving an ECS command signal, the internal command generation module first generates an ACT signal, delays the ACT signal by tRCD under the control of the second timing module 121 and then obtains an RD signal, then delays the RD signal by WL under the control of the second timing module 121 and then obtains a WR signal, and then delays the WR signal by tWR under the control of the second timing module 121 and then obtains a PRE signal.

[0065] The main functions of the command generation module 12 are as follows: In the automatic ECS operation mode and the manual ECS operation mode, the ECS control module 11 controls the MPC signal, the REFab signal, and the Self_REF signal, respectively, to generate and send the ECS command signal to the command generation module 12. The minimum time required to execute each ECS operation is recorded as tECSc. Within this time, the ECS needs to perform internal read / write and error detection / correction on a specific column (i.e., one specific memory bit in the bank array) of a specific row in a specific bank of a specific bank group controlled by a count pointer (the count pointer points to the clock signal of the address count module), so it self-generates the internal ACT command signal, RD command signal, WR command signal, and PRE command signal, and the timing between the command signals needs to satisfy tRCD, WL, and tWR, so that one ECS operation is completed within tECSc, that is, the sum of tRCD, WL, and tWR needs to be smaller than (or equal to) tECSc in order to prevent the execution of the ECS operation from timing out. Here, the control of the timing between the command signals can be specifically realized by a delay line.

[0066] Furthermore, the ECS operation can be realized by controlling the bank array by the bank control module. Figure 5 shows a schematic diagram of a partial structure of an ECS circuit according to an embodiment of the present invention. As shown in Figure 5, in some embodiments, the ECS circuit 10 further includes a bank control module 15 and a bank array 16, the bank array 16 including at least one bank group, the bank group including at least one bank, the bank including at least one row and at least one column, where: the bank control module 15 is configured to receive the internal command signals and perform ECS operations on the bank array based on the internal command signals; The bank control module 15 is further configured to generate an error signal and send the error signal to the error tracking module 14 if error information is detected during the execution of an ECS operation.

[0067] In addition, in Fig. 5, the description of the ECS control module 11 and the command generation module 12 can refer to the above contents, and will not be repeated here. Regarding the bank array 16, referring to Fig. 6, an exemplary structural diagram of the configuration of the bank array 16 according to an embodiment of the present invention is shown. In the example shown in Fig. 6, the bank array 16 (also called Array, DRAM Array) includes four bank groups (BG: Bank Growp) of BG0, BG1, BG2, and BG3, and each bank group includes four banks (BA: Bank) of BA0, BA1, BA2, and BA3. Taking BA3 of BG1 as an example, the bank BA3 includes six rows (Row) of ROW0, ROW1, ROW2, ROW3, ​​ROW4, and ROW5, and the bank BA3 includes five columns (Col: Column) of Col0, Col1, Col2, Col3, and Col4. 6, each circle represents one memory bit, and for example, in BA3, the location of memory bit Bit00 can be identified by ROW0 and Col0. Each ECS operation is performed on one memory bit in the bank array 16.

[0068] In addition, the command generation module 12 generates an internal command signal and sends it to a bank control module 15 (also called a DRAM control module, DRAM Control), and the bank control module 15 performs an ECS operation on a memory bit in the bank array 16 based on the internal command signal.

[0069] It should be noted that the ECS operation may include an activation operation, a read operation, an error calibration operation, a write operation, and a precharge operation. The bank control module 15 first receives an ACT signal to activate a word line of a corresponding address, and then receives an RD signal to read a codeword from a memory bit, where the ECS circuit may further include an error correction circuit, which executes an error detection and correction (ECC) algorithm, and the read codeword is sent to the error correction circuit for checking. Here, the codeword may include data and parity, and the error correction code may be used to generate the parity from the data. When performing the error calibration operation, the error calibration circuit may detect an error in the codeword, calibrate the error in the codeword, and generate a calibrated codeword. When receiving a WR signal, the bank control module 15 performs a write operation to write the calibrated codeword into the memory bit. Also, if no error in the codeword is detected, there is no need to perform a write operation, and finally, when receiving a PRE signal, the bank control module 15 performs a precharge.

[0070] In addition, when a code word containing error information is detected during ECS ​​operation, an error signal is generated and sent to the error tracking and recording module, so that the error tracking and recording module can record and track the error information. Since the error information is an error detected from the data read from the bank array using an error detection and correction (ECC) algorithm, the error signal is also called an ECC error signal, and is represented by ECC_Error in FIG. 5.

[0071] In this manner, according to an embodiment of the present invention, an internal command signal is generated based on an ECS command signal, and an ECS operation is performed based on the internal command signal, thereby realizing error detection and scrubbing of the bank array.

[0072] In addition, the bank array 16 here may be one memory die (Die) in the DRAM, and by performing ECS ​​operations in the same manner for each Die, complete error detection and scrubbing for the DRAM is achieved.

[0073] While the bank control module performs the ECS operation on the bank array based on the internal command signal, the address count module further performs address counting based on the internal command signal and generates a count end signal. Here, the address count module performs counting based on the PRE signal, and the PRE signal is used as a clock signal for the address count module. The address count module can respectively count columns, rows, banks, and bank groups of the bank array, and generate and send a count end signal to the error tracking and recording module when the counting is completed. Here, the count end signal includes: a column end signal indicating the counting completion of each memory bit of a row, a row end signal indicating the counting completion of each row of a bank, a bank end signal indicating the counting completion of each bank of a bank group, a bank group end signal indicating the counting completion of each bank group of the bank array, and an ECS end signal indicating the counting completion of all memory bits in the entire bank array. In addition, the address calculation module sends address information, such as column address information, bank information, and bank group information, to the error tracking and recording module, so that the error tracking and recording module can store the required address information.

[0074] Regarding the address counting module, refer to Fig. 7, which shows an exemplary structural diagram of the configuration of the address counting module 13 according to an embodiment of the present invention. As shown in Fig. 7, in some embodiments, the address counting module 13 includes a column counting module 131, a row counting module 132, and an array counting module 133, where: The column count module 131 is configured to receive a precharge signal, perform column counting for a target row based on the precharge signal, and generate a column output signal and a column end signal when the column counting for the target row is completed; the row count module 132 is configured to receive the precharge signal and the column output signal, perform row counting for the target bank based on the precharge signal and the column output signal, and generate a row output signal and a row end signal when the row counting for the target bank is completed; The array count module 133 is configured to receive a precharge signal and a row output signal, perform a bank count for a target bank group based on the precharge signal and the row output signal, generate a bank output signal and a bank end signal when the bank count for the target bank group is completed, perform a bank group count for a bank array based on the precharge signal and the bank output signal, and generate a bank group end signal and an ECS end signal when the bank group count for the bank array is completed.

[0075] In addition, in FIG. 7, PRE represents a precharge signal, Col_Wrap represents a column output signal, COL_END represents a column end signal, Row_Wrap represents a row output signal, ROW represents row address information, BA represents bank address information, BG represents bank group address information, the bank address information and the bank group address information are collectively represented as BG / BA in FIG. 7, ECS_END represents an ECS end signal, and these address information need to be sent to the error tracking and recording module 14; furthermore, the row end signal (also referred to as ROW_END) indicates that counting of rows in one bank is completed, the bank end signal (also referred to as BA_END) indicates that counting of banks in one bank group is completed, and the bank group end signal (also referred to as BG_END) indicates that counting of all bank groups in the bank array is completed.

[0076] Still taking the bank array 16 shown in FIG. 6 as an example, the operation process of the address count module 13 will be described with reference to FIG. 7. Assume that the configuration of each BA of the bank array 16 is the same as BA3 of BG1. In each BG, each memory bit is represented as Bitxy, where x indicates the row in which the memory bit is located in the BA, and y indicates the column in which the memory bit is located in the BG. For example, Bit32 indicates the memory bit determined by ROW3 and Col2 in the BA. The memory bit on which the ECS operation is currently being performed is represented as the target memory bit, and the row, bank, and bank group to which the target memory bit belongs are represented as the target row, target bank, and target bank group, respectively. For example, when an ECS operation is being performed on Bit11 of BA2 of BG1, the target row is ROW1 of BA2 of BG1, the target bank is BA2 of BG1, and the target bank group is BG1. Here, each count module uses the PRE signal as a clock.

[0077] The column counting module 131 can sequentially count the memory bits included in each row in the bank array 16. In this way, in one complete ECS process for the bank array 16, first, the ECS operation is sequentially performed for each memory bit in the first row ROW0 of BA0 of BG0. When performing the ECS operation for Bit00, the corresponding PRE signal is sent to the clock edge of the column counting module 131 (in FIG. 7, the clock edge of each counting module is represented by CNT_CLK), and the column count value of ROW0 is increased by one each time a PRE signal is received. It can be understood that the column count value indicates the number of memory bits that have completed the ECS operation in the target row. Since ROW0 includes five memory bits, when the column count value of ROW0 becomes 5, it indicates that the column count of ROW0 is completed. At this time, the column counting module 131 generates one Col_Wrap signal and one COL_END signal, where the Col_Wrap signal is sent to the row counting module 132, and the COL_END signal is sent to the error tracking and recording module. After completing the column counting of ROW0, the column counting module 131 resets the count value to zero, and then continues to perform the column counting of ROW1, and sequentially counts each row of the bank array 16 according to this process until completing the column counting of each row of the bank array 16. That is, after generating a column output signal and a column end signal, the column counting module 131 is further configured to continue the column counting of the next target row, until completing the column counting of each row of the bank array.

[0078] The row counting module 132 performs counting according to the PRE signal and the Col_Wrap signal. Still taking BA0 of BG0 as an example, specifically, after the column counting module 131 completes counting ROW0, it generates one Col_Wrap signal to send to the row counting module 132, and the row count value of the target bank counted by the row counting module 132 increases by one. It can be understood that the row count value indicates the number of rows in the target bank that have completed the ECS operation. After the column counting module 131 completes counting ROW1, it similarly sends one Col_Wrap signal to the row counting module 132, and the row count value of the target bank increases by one again, and so on. Because BA0 contains six rows, when the row count value of the target bank becomes six, it indicates that the row counting of BA0 is completed. In this case, the row counting module 132 generates a Row_Wrap signal and row address information (ROW), where the Row_Wrap signal is sent to the bank counting module 1331, and the row address information is sent to the error tracking module 14. In addition, in the counting process, the row counting module 132 generates a row end signal (ROW_END) after finishing the row counting of the target bank, to indicate that the row counting of the target bank is completed. After completing the row counting of BA0, the row counting module 132 resets the count value to zero, and then continues to perform the row counting of BA1, and sequentially counts each BA of the bank array 16 according to this process until completing the counting of each BA of the bank array 16. That is, the row counting module 132 is further configured to continue the row counting of the next target bank after generating a row output signal and the row end signal, until completing the row counting of each bank of the bank array.

[0079] The array counting module 133 not only counts banks, but also counts bank groups. Regarding the array counting module 133, refer to FIG. 8, which shows an exemplary structural diagram of another address counting module 13 configuration according to an embodiment of the present invention. As shown in FIG. 8, in some embodiments, the array counting module includes a bank counting module 1331 and a bank group counting module 1332, where: The bank count module 1331 is configured to receive a precharge signal and a row output signal, perform bank counting on a target bank group according to the precharge signal and the row output signal, and generate a bank output signal and a bank end signal when the bank counting of the target bank group is completed; The bank group count module 1332 is configured to receive a precharge signal and a bank output signal, perform a bank group count for the bank array based on the precharge signal and the bank output signal, and generate a bank group end signal and an ECS end signal when the bank group count for the bank array is completed.

[0080] It should be noted that the bank counting module 1331 performs counting based on the PRE signal and the Row_Wrap signal. Still taking BG0 as an example, after the row counting module 132 completes counting BA0, it generates and sends one Row_Wrap signal to the bank counting module 1331, and the bank count value of the target bank group counted by the bank counting module 1331 is increased by one. As can be seen, the bank count value indicates the number of banks in the target bank group that have completed ECS operations, and after the row counting module 132 completes counting BA1, it similarly generates and sends one Row_Wrap signal to the bank counting module 1331, and the bank count value of the target bank group is further increased by one, and so on, and since BG0 includes four BAs, when the bank count value of the target bank group becomes four, it indicates that the counting of the banks of BG0 is completed. In this case, the bank counting module 1331 generates a BA_Wrap signal and bank address information (BA), where the BA_Wrap signal is sent to the bank group counting module 1332, and the bank address information is sent to the error tracking and recording module 14. Also, in the counting process, the bank counting module 1331 generates a bank end signal (BA_END) after finishing the counting of the bank of the target bank group to indicate that the counting of the bank of the target bank group is completed. After completing the counting of the bank of BG0, the bank counting module 1331 resets the count value to zero, and then continues to perform row counting of BG1, and sequentially counts each BG of the bank array 16 according to this process until completing the counting of each BG of the bank array 16. That is, the bank counting module 1331 in the array counting module 133 is further configured to continue bank counting of the next target bank group after generating a bank output signal and a bank end signal, until completing the bank counting of each bank group of the bank array.

[0081] The bank group counting module 1332 performs counting based on the PRE signal and the BA_Wrap signal. After the bank counting module 1331 completes counting BG0, it generates one BA_Wrap signal to send to the bank group counting module 1332, and the count value of the bank group is increased by one. As can be seen, the count value of the bank group indicates the number of bank groups that have completed ECS operation in the bank array 16, and after the bank counting module 1331 completes counting BG1, it similarly generates one BA_Wrap signal to send to the bank group counting module 1332, and the count value of the bank group is further increased by one, and so on. Since the bank array 16 includes four BGs, when the count value of the bank group becomes four, it indicates that the count of the bank groups in the bank array 16 is completed, i.e., the ECS operation of all memory bits in the bank array 16 is completed. In this case, the bank group counting module 1332 generates bank group address information (BG) and an ECS_END signal, where the bank group address information and the ECS_END signal are both sent to the error tracking and recording module 14. Also, in the counting process, after the bank group counting module 1332 finishes counting the bank groups in the bank array, it further generates a bank group end signal (BG_END) to indicate that the counting of the bank groups in the bank array is completed. After completing the counting of the bank groups, the bank group counting module 1332 resets the count value to zero and counts according to the above process until it performs the next ECS operation on the bank array 16.

[0082] It can be understood that the bank count module 1331 is configured to perform bank counting for a bank group, the bank group count module 1332 is configured to perform counting for a bank group in a bank array, and the bank count module 1331 and the bank group count module 1332 can be integrated into one module, the array count module 133, to achieve related functions.

[0083] It should be noted that in the embodiment of the present invention, each output signal and count signal (or ECS command signal, etc.) generated may be a high-level pulse, that is, when a certain condition is met, these signals will be in a valid state, so that the corresponding module can generate other signals or perform operations such as counting, reading, writing, etc. based on these signals.

[0084] That is, the main function of the address count module (also called address counter) is as follows: To perform a complete error detection and scrub on the DRAM, it is necessary to access the rows and columns of all banks of all bank groups. For each ECS operation, the address count module increments the column address count (i.e., the column count of the target row) after each internal PRE command signal, and after the column address count of the target row is completed, the row address count (i.e., the row count of the target bank) starts to increment, and continues until all the code words of each row of one bank are accessed, and then the bank count (i.e., the bank count of the target bank group) starts to increment, and repeats the process of accessing the code words of the previous bank, and when the count of all the banks of one bank group is completed, the bank group count (bank group count) starts to increment, and continues until all the banks of the DRAM are accessed, thus completing one complete error detection and scrub operation.

[0085] In this way, by using the PRE command signal as a clock for the address count module when performing an ECS operation to count for each row, bank, and bank group, no additional clocks are required and it is possible to accurately determine whether the ECS operation for the row, bank, and bank group is complete.

[0086] Thus, in the embodiment of the present invention, the internal command signal PRE generated by the command generation module is used as the clock signal of the address count module, and each time an ECS operation is performed, the column count module (also called column address counter, COL_CNT) starts to count up, and when the counting of one row of column address is completed, it outputs the Col_Wrap signal as the input of the row count module (also called row address counter, ROW_CNT), and the row count module starts to count up, and when the counting of one bank of row address count is completed, it outputs the Row_Wrap signal as the input of the array count module (BG / BA counter, BA / BG_CNT), and when the BG / BA count is completed and the ECS_END signal is output, it indicates that one complete error detection and scrubbing is completed. When the COL_END signal is output, it indicates that one row count is completed and is applied to the row mode of the error counter.

[0087] The address counting module sends a count end signal and address information to the error tracking and recording module, and the error tracking and recording module generates an error tracking signal according to the count end signal, the address information and the error signal to record the error information of the ECS operation, where the count end signal mainly includes a column end signal and an ECS end signal, and the address information mainly includes row address information, bank address information and bank group address information.

[0088] Regarding the error tracking and recording module, based on Fig. 5, and referring to Fig. 9, a schematic diagram of a specific structure of the ECS circuit 10 according to an embodiment of the present invention is shown. As shown in Fig. 9, the error tracking and recording module 14 includes a first error tracking and recording module 141 and a second error tracking and recording module 142.

[0089] Regarding the first error tracking and recording module 141, in some embodiments, the first error tracking and recording module 141 is configured to receive a counting mode signal, and determine that the counting mode of the first error tracking and recording module 141 is a codeword counting mode when the counting mode signal is a first value, or determine that the counting mode of the first error tracking and recording module 141 is a row counting mode when the counting mode signal is a second value.

[0090] It should be noted that the first error tracking and recording module 141 (also referred to as EC:ERROR_COUNT) has two operation modes, a codeword count mode and a row count mode, and these two operation modes can be switched based on a count mode signal, where the count mode signal may be MR14 OP[5] (in FIG. 9, MR14 OP[5] is represented as MRS). When the value of the count mode signal is a first value, the codeword count mode is performed to count the number of codeword errors in the bank array, and when the value of the count mode signal is a second value, the row count mode is performed to count the number of rows in which at least one codeword error exists in the bank array.

[0091] Here, the first value may be a logic 1 indicating a high level, and the second value may be a logic 0 indicating a low level, or the first value may be a logic 0 indicating a low level, and the second value may be a logic 1 indicating a high level, and there is no particular limitation thereto.

[0092] In this way, the operation mode of the first error tracking and recording module is determined by the counting mode signal, so that it can not only count the code words in which error information exists in the bank array, but also count the rows in which at least one error information exists in the bank array, thereby improving the flexibility of recording error information and can be set according to needs in practical applications.

[0093] Further, when the counting mode is a codeword counting mode, as shown in FIG. 9 , in some embodiments, the first error tracking module 141 is configured to receive an error signal, perform codeword counting based on the error signal, and upon receiving an ECS end signal, determine a first count value, compare the first count value with a first threshold value, and store the first count value if the first count value is greater than or equal to the first threshold value, where the first count value is used to represent the number of codewords in which error information exists in the bank array.

[0094] It should be noted that in the embodiment of the present invention, the error information mainly refers to the error information of the codeword, so the error information is also called codeword error. In the codeword counting mode, the first error tracking and recording module needs to count the codewords in which there is error information in the bank array. Here, every time the bank control module detects one codeword error in the bank array, an error signal (represented as ECC_Error in FIG. 9) is generated. Here, when a codeword error is detected, ECC_Error can be one high level pulse, so that the first error tracking and recording module can count the codewords in which there is error information in the bank array according to ECC_Error, and upon receiving an ECS end signal (represented as ECS_END in FIG. 9), which indicates that one complete ECS operation of the bank array is completed, in this case the first error tracking and recording module stops counting and obtains a first count value. As can be understood, the first count value indicates the number of codewords in which there is error information in the bank array.

[0095] 9, the location where the first count value is stored may be mode register 20 (MR20). Furthermore, in the codeword count mode, the DRAM can ignore the number of codeword errors that are less than a first threshold, that is, if the first count value is less than the first threshold, the DRAM does not store the first count value in MR20, and stores the first count value only if the first count value is equal to or greater than the first threshold.

[0096] In an embodiment of the present invention, the first threshold can be determined by the error count threshold and the memory density of the bank array, where the error count threshold (ETC: Error Threshold Count) can be set based on the mode register signal MR15 OP[2:0] (in FIG. 9, MRS further represents MR15 OP[2:0]), for example, in DDR5, when OP[2:0] is 000B, ETC is 4, when OP[2:0] is 001B, ETC is 16, when OP[2:0] is 010B, ETC is 64, when OP[2:0] is 011B, ETC is 256, when OP[2:0] is 100B, ETC is 1024, and when OP[2:0] is 101B, ETC is 4096. Here, the default setting of ETC is 256 per memory unit, where one memory unit can represent 1Gb.

[0097] Assuming that the memory density of the bank array is 16 Gb and the ETC is 4, if the number of codeword errors per 1 Gb is less than 4, it is ignored, and if the number of codeword errors is less than 4×16=64 across the entire bank array, it is ignored. That is, in this example, the first threshold is 64, and if the first count value is 64 or more, the first count value is loaded and stored in the MR20, otherwise it is not stored. Then, the first count value is reset and counting is restarted when the next complete ECS operation is performed.

[0098] In this way, in the codeword counting mode, the first error tracking and recording module can count the codewords in which error information exists in the bank array to obtain a first count value, and store the first count value in the mode register based on a first threshold value, and only store the first count value for subsequent use when the number of error information is too large, thereby saving power consumption and storage space.

[0099] Further, when the counting mode is a row counting mode, as shown in FIG. 9 , in some embodiments, the first error tracking module is configured to receive an error signal and a column end signal, perform error row counting based on the error signal and the column end signal, determine a second count value upon receiving an ECS end signal, compare the second count value with a second threshold value, and store the second count value if the second count value is greater than the second threshold value, where the second count value is used to represent the number of rows in which at least one error information exists in the bank array.

[0100] In addition, in the row counting mode, the first error tracking module needs to count the rows in the bank array that have at least one error information, that is, the second count value represents the number of rows that have at least one codeword error.

[0101] In one specific implementation, in order to count the rows that have at least one error information, the first error tracking module needs to receive ECC_Error and a column end signal (Col_END). Illustratively, when receiving ECC_Error representing error information, the first error tracking module 141 counts according to ECC_Error to obtain a row error count value; when receiving Col_END, it indicates that one complete ECS operation of all memory bits of the current row is completed; at this time, if the row error count value of the current row is greater than 0, it indicates that there is at least one codeword error in the current row, and the second count value is increased by 1; otherwise, the second count value is not increased, and the row error count value is reset to zero, and the count is resumed according to ECC_Error; when receiving the next Col_END, it again determines whether the second count value needs to be increased by 1 according to the row error count value; this step is repeated until receiving ECS_END, which indicates that one complete ECS operation of the bank array is completed; when receiving ECS_END, the first error tracking module stops counting and obtains a second count value.

[0102] In another implementation, ECC_Error may be a pulse signal generated when a row with a codeword error is detected, in which case the first error tracking module directly counts ECC_Error to obtain a second count value representing the number of rows with codeword errors. Or the first error tracking module is connected to a selection module, which selects a codeword count mode or a row count mode based on a count mode signal, in the codeword count mode, the selection module generates a first pulse signal based on ECC_Error, and the first error tracking module counts the first pulse signal to obtain a first count value, and in the row count mode, the selection module generates a second pulse signal based on ECC_Error, and the first error tracking module counts the second pulse signal to obtain a second count value.

[0103] When storing the second count value, the location for storing it may be the mode register 20 (represented as MR20 in FIG. 9). Furthermore, in the row count mode, the DRAM may ignore the row error count less than a second threshold, i.e., if the second count value is less than the second threshold, the second count value is not stored in MR20, and the second count value is stored only if the second count value is equal to or greater than the second threshold.

[0104] In the embodiment of the present invention, it is assumed that the second threshold is 4, and if the second count value is equal to or greater than 4, the second count value is loaded and stored in the MR20, otherwise it is not stored. Then, the second count value is reset and restarts counting when the next complete ECS operation is performed. Also, the second threshold may be the ETC described above, and the method of determining the second threshold may be the same as the method of determining the first threshold.

[0105] In this way, in the row counting mode, the first error tracking and recording module can count the rows in the bank array that have error information to obtain a second count value, and store the second count value in the mode register based on the second threshold value, and can save power consumption and storage space by storing the second count value for subsequent use only when the number of rows that have error information is too large.

[0106] Regarding the second error tracking and recording module 142, as shown in FIG. 9, in some embodiments, the second error tracking and recording module 142 is configured to receive an error signal, count the error information of the target row according to the error signal and the end of column signal, and after determining a third count value of the target row, compare the third count value with the target count value stored in the first register module, and if the third count value is greater than the target count value, scrub the target count value stored in the first register module, and save the third count value as the target count value in the first register module, and continue to perform error counting of the next target row according to the error signal and the end of column signal until receiving an end of ECS signal, and determine the target count value stored in the first register module when the end of ECS signal is received, where the third count value is used to represent the number of codewords in which error information exists in the target row.

[0107] In addition, the second error tracking module 142 (also called EPRC (Error Per Row Counter)) can count the codeword errors of each row in the bank array, and store the number of codeword errors of the row with the largest number of codeword errors and the address information of the row. Here, the second error tracking module 142 can count the error information of each row based on ECC_Error and Col_END. For example, counting the error information for the i-th row of the bank array is performed, and assuming that the bank array includes a total of N rows, where N is an integer greater than 0, i is an integer greater than 0 and less than or equal to N, and receiving a Col_END signal indicates that the ECS operation of all memory bits in the i-th row is completed, in which case the counting of the error information for the i-th row can be ended, and the obtained count value is a third count value, and the third count value represents the number of error information (i.e., the number of error code words) in the i-th row.

[0108] Note that starting from the error count of the first row, if there is at least one error information in the first row, i.e., if the third count value of the first row is greater than 0, the third count value corresponding to the first row is stored in the first register module as the target count value, where the first register module can be the mode register 19 (represented by MR

[19] in FIG. 9). Then, continue to perform the error count of the second row, compare the obtained third count value with the target count value stored in the register, and if the third count value corresponding to the second row is greater than the target count value, scrub the target count value stored in the first register module, and store the third count value corresponding to the second row as the new target count value in the first register module, and so on for the next row, and each time a larger third count value appears, the target count value in the first register module is replaced, so that the target count value stored in the first register module is always the third count value corresponding to the row with the largest number of error information among the rows counted so far. In this way, when the ECS end signal is received, the target count value stored in the first register module is the third count value of the row with the largest number of error information.

[0109] It can be understood that if no error information appears from the first row to the i-1th row, and error information appears for the first time in the ith row, the ith row does not have a target count value to be compared, so the third count value corresponding to the ith row is directly stored in the first register module as the target count value. Alternatively, the second error tracking and recording module is configured to receive an error signal, count the error information of the first row according to the error signal and the column end signal, determine the third count value of the first row, and then store the third count value of the first row as the target count value in the first register module, and perform counting for the target row according to the above scheme after the first row count is finished, in which case the target row refers to other rows other than the first row. In this case, the third count value of the first row can be stored in the first register module even if it is 0, and for the second row, its corresponding third count value is compared with 0 to determine the final target count value.

[0110] In addition, each time the third count value is stored in the first register module as a target count value, the second error tracking and recording module is further configured to store address information corresponding to the target count value in the second register module when storing the target count value in the first register module, where the address information includes row address information, bank address information, and bank group address information corresponding to the target count value.

[0111] Here, the second register module may include a mode register 16, a mode register 17, and a mode register 18, which are represented as MR[16:18] in FIG. 9. As can be seen, every time the target count value in the first register module is replaced with a third larger count value, the address information in the second register module is also replaced with the corresponding address information. In this way, when receiving an ECS end signal, the second register module stores the row address information, bank address information, and bank group address information of the row with the largest number of error information.

[0112] Moreover, in some embodiments, the second error tracking and recording module is further configured to, after receiving the ECS end signal, compare the currently stored target count value in the first register module with a third threshold, and if the target count value is greater than or equal to the third threshold, retain the target count value stored in the first register module and the address information stored in the second register module, and scrub the target count value stored in the first register module and the address information stored in the second register module if the target count value is less than the third threshold.

[0113] In addition, in the embodiment of the present invention, the target count value and its corresponding address information can be stored only if the final target count value is greater than a third threshold value, where the third threshold value is also called row error count threshold value (RETC), and in DDR, the value of RETC can be fixed at 4. For example, when the value of RETC is equal to 4, if the final target count value is greater than 4, the target count value in the first register module is retained, and the address information in the second register module is retained; otherwise, the address information of the current target count value is scrubbed.

[0114] 6, the address information of the final target count value is BG1-BA2-ROW1, which indicates that the target row is the second row ROW1 of the bank BA2 of the bank group BG1 in the bank array, where the row address information, bank address information, and bank group address information are sent to the error tracking and recording module during the counting process of the address counting module, so that the error tracking and recording module can accurately store the address information corresponding to the target count value.

[0115] In this way, the second error tracking and recording module can store information of the row with the largest number of error information in the mode register based on the third threshold, and only store the information of the error row for subsequent use when the number of error information is too large, thereby saving power consumption and storage space.

[0116] In FIG. 9, the target count value is represented by REC[5:0] and stored in MR19, and address information corresponding to the target count value is represented by MAX_ADD, including row address information, bank address information, and bank group address information, and is stored in MR[16:18], respectively. Here, ROW and BG / BA output by the row count module and the array count module are used to record specific information of the row address with the largest error count and store it in a register. That is, in the embodiment of the present invention, the error tracking signal mainly refers to the first count value or the second count value stored in the first error tracking record module, and the final target count value stored in the second error tracking record module and its corresponding address information, and these error tracking signals can record information such as the number of errors in the bank array. In addition, when storing the first count value, the second count value, and the target count value, one-hot encoding can be used to encode and store the first count value, the second count value, and the target count value.

[0117] In brief, the error tracking module includes two error counters: a first error tracking module (EC) and a second error tracking module (EPRC). The EC module has two modes, which need to be switched according to MR14 OP[5]: when OP[5]=0, it is in row count mode, in which ECC_Error and COL_END are used to count rows with at least one error; when OP[5]=1, it is in codeword count mode, in which the ECC_Error signal is used to count the number of errors in a codeword. Once all ECSs are completed, the result of EC is loaded into MR20 based on ETC, and EC is reset after its value is transferred to the mode register.

[0118] The EPRC module uses ECC_Error, BG / BA, and ROW to record the row with the largest number of error information, and also records the address information MAX_ADD of the row with the largest number of error information. Once all ECS is completed, the address information is loaded into MR[16:18], and the error count of the row is loaded into MR19 according to RETC. Here, the data recorded by EC and EPRC are not directly loaded into registers, but are loaded into corresponding registers according to ETC and RETC after one complete ECS operation is completed.

[0119] In addition, the module that performs the counting function according to the embodiment of the present invention can be realized by a synchronous counter or an asynchronous counter, and is not particularly limited here.

[0120] An embodiment of the present invention provides an ECS circuit, and generates an ECS command signal based on a mode control signal to perform an ECS operation, so as to perform complete error detection and scrubbing on the memory; and after the execution of the ECS operation is completed, an error tracking signal can be generated based on the error signal and the count end signal to record the error information of the ECS operation, so as to quickly locate and repair the location where the error information exists in the memory, and ultimately improve the performance of the memory.

[0121] In another embodiment of the present invention, referring to Fig. 10, an exemplary flow chart of an ECS method according to an embodiment of the present invention is shown. As shown in Fig. 10, the method may include the following steps:

[0122] In step S1001, a mode control signal is received by an ECS control module, and an ECS command signal is generated based on the mode control signal.

[0123] In step S1002, an ECS command signal is received by a command generating module, and an internal command signal is generated based on the ECS command signal, and the internal command signal is used to perform a corresponding ECS ​​operation.

[0124] In step S1003, the address count module receives the internal command signal, performs address counting based on the internal command signal, and generates a count end signal when the counting of the target address is completed.

[0125] In step S1004, the count end signal and the error signal are received by an error tracking recording module, and an error tracking signal is generated according to the count end signal and the error signal, where the error tracking signal is used to record error information of the ECS operation.

[0126] In some embodiments, the mode control signal includes a multi-purpose command (MPC) signal or a refresh command signal, and generating the ECS command signal based on the mode control signal includes: generating ECS ​​command signals based on the MPC signals when the ECS operation is in a manual ECS operation mode; or If the ECS operation is in an automatic ECS operation mode, it may include generating an ECS command signal based on the refresh command signal.

[0127] In addition, in different ECS operation modes, ECS operation can be generated based on different command signals, where in the automatic ECS operation mode, the automatic ECS operation can be performed based on the refresh signal (REFab) or the self-refresh signal (Self_REF), and in the manual ECS operation mode, the ECS operation can be performed based on a specific MPC signal or in combination with a first mode register signal, to determine whether to perform an ECS operation when self-refreshing.

[0128] In some embodiments, generating the ECS command signal based on the mode control signal includes: generating, by a first timing module, an ECS identification signal; The method may include receiving, by the command control module, an ECS identification signal; and, if the ECS identification signal is in a valid state, obtaining a refresh command signal; and generating an ECS command signal based on the refresh command signal.

[0129] In some embodiments, generating, by the first timing module, the ECS identification signal includes: The method may include receiving a first clock signal by a first timing module, counting based on the first clock signal, generating an ECS identification signal, and sending the ECS identification signal to a command control module, where when the count value meets a predetermined condition, the ECS identification signal is in an active state.

[0130] In some embodiments, the method further comprises: When the ECS identification signal is in an active state, the first timing module stops counting; The method may further include: after generating the ECS command signal based on the refresh command signal, the command control module generates a reset signal and sends the reset signal to the first timing module to control the first timing module to resume counting and put the ECS identification signal into an invalid state.

[0131] In some embodiments, the method further comprises: The method may further include, when the ECS identification signal is in an invalid state, outputting, by the command control module, the received refresh command signal as an internal refresh signal to perform a refresh operation.

[0132] In some embodiments, generating the internal command signal based on the ECS command signal includes: receiving an ECS command signal by an internal command generating module, and sequentially generating an activation signal, a read command signal, a write command signal, and a pre-charge signal according to a predetermined timing condition after receiving the ECS command signal; and controlling, by a second timing module, a time interval between the activation signal and the read command signal to satisfy a first timing condition, a time interval between the read command signal and the write command signal to satisfy a second timing condition, and a time interval between the write command signal and the pre-charge signal to satisfy a third timing condition; Here, the predetermined timing conditions include a first timing condition, a second timing condition, and a third timing condition.

[0133] In some embodiments, the method further comprises: The method may further include receiving an internal command signal by the bank control module, performing an ECS operation on the bank array based on the internal command signal, and generating an error signal and sending the error signal to the error tracking module if error information is detected during the execution of the ECS operation.

[0134] In some embodiments, performing address counting based on the internal command signal and generating an end-of-count signal when the counting of the target address is completed includes: receiving, by a column count module, a precharge signal; performing column counting for a target row according to the precharge signal; and generating a column output signal and a column end signal when the column counting for the target row is completed; receiving, by a row count module, a precharge signal and a column output signal, performing row counting for the target bank according to the precharge signal and the column output signal, and generating a row output signal and a row end signal when the row counting for the target bank is completed; The array count module may include receiving a precharge signal and a row output signal, performing a bank count for a target bank group based on the precharge signal and the row output signal, and generating a bank output signal and a bank end signal when the bank count for the target bank group is completed, and performing a bank group count for a bank array based on the precharge signal and the bank output signal, and generating a bank group end signal and an ECS end signal when the bank group count for the bank array is completed.

[0135] In some embodiments, receiving, by the array count module, a precharge signal and a row output signal, performing a bank count for a target bank group based on the precharge signal and the row output signal, and generating a bank output signal and a bank done signal when the bank count for the target bank group is completed, performing a bank group count for a bank array based on the precharge signal and the bank output signal, and generating a bank group done signal and an ECS done signal when the bank group count for the bank array is completed. receiving, by a bank count module, a precharge signal and a row output signal, performing bank counting on a target bank group according to the precharge signal and the row output signal, and generating a bank output signal and a bank end signal when the bank counting of the target bank group is completed; The method may include receiving a precharge signal and a bank output signal by a bank group count module, performing a bank group count for the bank array based on the precharge signal and the bank output signal, and generating a bank group end signal and an ECS end signal when the bank group count for the bank array is completed.

[0136] In some embodiments, the method further comprises: After generating the column output signal and the column end signal, the column count module continues to count columns of the next target row until the column count of each row of the bank array is completed; After generating the row output signal and the row end signal, the row count module continues row counting of the next target bank until the row counting of each bank of the bank array is completed; The method may further include: after generating the bank output signal and the bank end signal, the bank count module continues bank counting of the next target bank group until bank counting of each bank group of the bank array is completed.

[0137] In some embodiments, the method further comprises: The method may further include receiving, by the first error tracking and recording module, a counting mode signal, and determining that the counting mode of the first error tracking and recording module is a codeword counting mode if the counting mode signal is a first value, or determining that the counting mode of the first error tracking and recording module is a row counting mode if the counting mode signal is a second value.

[0138] In some embodiments, in the codeword count mode, generating the error tracking signal based on the end-of-count signal and the error signal comprises: The first error tracking module may include receiving an error signal, performing codeword counting based on the error signal, determining a first count value upon receiving an ECS end signal, comparing the first count value with a first threshold value, and storing the first count value if the first count value is greater than or equal to the first threshold value, where the first count value is used to represent the number of codewords in which error information exists in the bank array.

[0139] In some embodiments, in the row count mode, generating the error tracking signal based on the end-of-count signal and the error signal includes: The first error tracking module may include receiving the error signal and the column end signal, performing error row counting based on the error signal and the column end signal, determining a second count value upon receiving an ECS end signal, comparing the second count value with a second threshold value, and storing the second count value if the second count value is greater than the second threshold value, where the second count value is used to represent the number of rows in the bank array in which at least one error information exists.

[0140] In some embodiments, generating the error tracking signal based on the terminal count signal and the error signal comprises: The method may include: receiving, by a second error tracking and recording module, the error signal; counting the error information of the target row based on the error signal and the end of column signal; determining a third count value of the target row; comparing the third count value with the target count value stored in the first register module; and if the third count value is greater than the target count value, scrubbing the target count value stored in the first register module, and saving the third count value in the first register module as the target count value; and continuing to perform error counting of the next target row based on the error signal and the end of column signal until receiving an ECS end signal; and determining the target count value stored in the first register module when an ECS end signal is received, where the third count value is used to represent the number of codewords in which error information exists in the target row.

[0141] In some embodiments, the method further comprises: When storing the target count value in the first register module, it may further include storing address information corresponding to the target count value in the second register module, where the address information includes row address information of the row corresponding to the target count value, bank address information, and bank group address information.

[0142] In some embodiments, the method further comprises: The method may further include: after receiving the ECS end signal, comparing the currently stored target count value in the first register module with a third threshold, and if the target count value is greater than or equal to the third threshold, retaining the target count value stored in the first register module and the address information stored in the second register module, and scrubbing the target count value stored in the first register module and the address information stored in the second register module if the target count value is less than the third threshold.

[0143] It should be noted that the ECS method according to the embodiment of the present invention is applied to the ECS circuit according to the above embodiment, and details not disclosed in the embodiment of the present invention can be understood by referring to the description of the above embodiment.

[0144] According to an ECS method according to an embodiment of the present invention, an ECS command signal is generated based on a mode control signal to perform an ECS operation, thereby performing complete error detection and scrubbing on the memory; and after the execution of the ECS operation is completed, an error tracking signal is generated based on the error signal and the count end signal to record the error information of the ECS operation, thereby enabling the location where the error information exists in the memory to be quickly located and repaired, and ultimately improving the performance of the memory.

[0145] In another embodiment of the present invention, referring to Figure 11, an exemplary architectural diagram of a configuration of memory 20 according to an embodiment of the present invention is shown. As shown in Figure 11, the memory 20 may include the ECS circuit 10 described in any of the embodiments above.

[0146] In some embodiments, the memory 20 may include DRAM.

[0147] It should be noted that the embodiment of the present invention is concerned with the design of the overall framework of the new operation mode of DDR5, the error detection and scrubbing mode, in which in the manual ECS operation mode and the automatic ECS operation mode, an ECS command signal is generated via MPC, REFab, and SREF, thereby realizing the error detection and scrubbing operation of the corresponding address by the internal self-generated command. In addition, the errors found in the ECS operation are recorded in the EC and EPRC, and the count of the address count module is incremented every time the ECS command is completed. The timing control between the command generation module and the timing control module in the ECS design must ensure that one ECS operation can be completed within tECSc, and that one complete error detection and scrubbing operation can be performed on the DRAM within at least 24 hours.

[0148] In the embodiment of the present invention, in the case of DRAM, it can not only meet memory standards such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, but also meet memory standards such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, and the like, and is not particularly limited here.

[0149] In an embodiment of the present invention, the memory 20 is provided with the ECS circuit 10 described in the above embodiment, so that ECS operation can be realized for the memory, thereby improving the performance of the memory.

[0150] The above are only illustrative embodiments of the present invention, which do not limit the protection scope of the present invention.

[0151] It should be noted that, in the present invention, the terms "comprise," "include," or any other variation thereof, are intended to be non-exclusive inclusive, whereby a process, method, article, or apparatus that includes a set of elements does not merely include those elements, but also includes other elements not expressly listed, as well as inherent elements of the process, method, article, or apparatus. Unless otherwise limited, an element qualified with the expression "comprises..." does not exclude the presence of other similar elements in the process, method, article, or apparatus that includes the element.

[0152] The numbers of the above embodiments of the present invention do not indicate superiority or inferiority of the embodiments, but are intended for convenience of explanation.

[0153] The methods disclosed in the several method embodiments provided in the present invention can be arbitrarily combined to obtain new method embodiments, unless there is a contradiction.

[0154] The features disclosed in the various product embodiments provided herein may be combined in any manner, unless inconsistent, to arrive at new product embodiments.

[0155] The features disclosed in the various method or circuit embodiments provided herein may be combined in any manner, unless inconsistent, to produce new method or circuit embodiments.

[0156] The above content is only a specific embodiment of the present invention, and the protection scope of the present invention is not limited thereto. Any modifications or replacements that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. [Industrial Applicability]

[0157] An embodiment of the present invention generates an ECS command signal based on the mode control signal to perform an ECS operation, thereby performing complete error detection and scrubbing on the memory; and after the execution of the ECS operation is completed, generates an error tracking signal based on the error signal and the count end signal to record the error information of the ECS operation, thereby quickly locating and repairing the location where the error information exists in the memory, and ultimately improving the performance of the memory.

Claims

1. An error detection and scrubbing (ECS) circuit, comprising: an ECS control module; a command generation module; an address counting module; and an error tracking module; the ECS control module is configured to receive a mode control signal and generate ECS command signals based on the mode control signal; the command generation module is configured to generate an internal command signal based on the ECS command signal, the internal command signal being used to perform a corresponding ECS ​​action; The address count module is configured to perform address counting based on the internal command signal, and generate a count end signal when counting of target addresses is completed; The error detection and scrubbing (ECS) circuit, wherein the error tracking recording module is configured to receive an error signal and generate an error tracking signal based on the count end signal and the error signal, and the error tracking signal is used to record error information of the ECS operation.

2. The mode control signal includes a multi-purpose command (MPC) signal or a refresh command signal; the ECS control module is further configured to generate the ECS command signal based on the MPC signal when the ECS operation is in a manual ECS mode of operation; or The ECS control module is further configured to generate the ECS command signal based on the refresh command signal when the ECS operation is in an automatic ECS operation mode.

2. The ECS circuit of claim 1.

3. the ECS control module includes a first timing module and a command control module; the first timing module is configured to generate an ECS identification signal; the command control module is configured to receive the ECS identification signal, obtain a refresh command signal when the ECS identification signal is in a valid state, and generate the ECS command signal based on the refresh command signal.

3. The ECS circuit of claim 2.

4. The first timing module is configured to receive a first clock signal, perform a count based on the first clock signal, generate the ECS identification signal, and send the ECS identification signal to the command control module, and when a count value satisfies a predetermined condition, the ECS identification signal is in an enabled state.

4. The ECS circuit of claim 3.

5. the first timing module is further configured to stop the counting when the ECS identification signal is in a valid state; The command control module is further configured to generate a reset signal after generating the ECS command signal based on the refresh command signal, and send the reset signal to the first timing module to control the first timing module to resume counting and put the ECS identification signal into an invalid state.

5. The ECS circuit of claim 4.

6. The command control module is further configured to output the received refresh command signal as an internal refresh signal to perform a refresh operation when the ECS identification signal is in an invalid state.

6. The ECS circuit of claim 5.

7. the command generation module includes an internal command generation module and a second timing module; The internal command generation module is configured to sequentially generate an activation signal, a read command signal, a write command signal, and a precharge signal according to a predetermined timing condition after receiving the ECS command signal; the second timing module is configured to control a time interval between the activation signal and the read command signal to satisfy a first timing condition, control a time interval between the read command signal and the write command signal to satisfy a second timing condition, and control a time interval between the write command signal and the precharge signal to satisfy a third timing condition; the predetermined timing condition comprises the first timing condition, the second timing condition, and the third timing condition.

2. The ECS circuit of claim 1.

8. the ECS circuit further comprises a bank control module and a bank array, the bank array including at least one bank group, the bank group including at least one bank, the bank including at least one row and at least one column; the bank control module is configured to receive the internal command signal and perform an ECS operation on the bank array based on the internal command signal; The bank control module is further configured to generate an error signal and transmit the error signal to the error tracking module when error information is detected during execution of the ECS operation.

8. The ECS circuit of claim 7.

9. the address counting module includes a column counting module, a row counting module, and an array counting module; the column count module is configured to receive the precharge signal, perform column counting for a target row based on the precharge signal, and generate a column output signal and a column done signal when column counting for the target row is completed; the row count module is configured to receive the precharge signal and the column output signal, perform row counting for a target bank based on the precharge signal and the column output signal, and generate a row output signal and a row end signal when row counting for the target bank is completed; the array count module is configured to receive the precharge signal and the row output signal, perform a bank count for a target bank group based on the precharge signal and the row output signal, generate a bank output signal and a bank end signal when the bank count for the target bank group is completed, perform a bank group count for the bank array based on the precharge signal and the bank output signal, and generate a bank group end signal and an ECS end signal when the bank group count for the bank array is completed; 9. The ECS circuit of claim 8.

10. the array counting module includes a bank counting module and a bank group counting module; the bank count module is configured to receive the precharge signal and the row output signal, perform bank counting for a target bank group based on the precharge signal and the row output signal, and generate the bank output signal and the bank end signal when bank counting for the target bank group is completed; the bank group count module is configured to receive the precharge signal and the bank output signal, perform a bank group count for the bank array based on the precharge signal and the bank output signal, and generate the bank group end signal and the ECS end signal when the bank group count for the bank array is completed.

10. The ECS circuit of claim 9.

11. the column count module is further configured to, after generating the column output signal and the column end signal, continue column counting of a next target row until a column count of each row of the bank array is completed; the row count module is further configured to, after generating the row output signal and the row end signal, continue row counting of a next target bank until row counting of each bank of the bank array is completed; the array count module is further configured to, after generating the bank output signal and the bank end signal, continue bank counting of a next target bank group until bank counting of each bank group of the bank array is completed; 10. The ECS circuit of claim 9.

12. The error tracking module includes a first error tracking module; The first error tracking module is configured to receive a counting mode signal, and determine that a counting mode of the first error tracking module is a codeword counting mode when the counting mode signal is a first value, or determine that a counting mode of the first error tracking module is a row counting mode when the counting mode signal is a second value.

11. The ECS circuit of claim 10.

13. the first error tracking module is configured to receive the error signal when the counting mode is the codeword counting mode, perform codeword counting based on the error signal, determine a first count value when the ECS end signal is received, compare the first count value with a first threshold value, and store the first count value when the first count value is equal to or greater than the first threshold value; the first count value is used to represent the number of code words in which error information exists in the bank array; 13. The ECS circuit of claim 12.

14. the first error tracking module is configured to receive the error signal and the end of column signal when the counting mode is the row counting mode, perform error row counting based on the error signal and the end of column signal, determine a second count value when the end of ECS signal is received, compare the second count value with a second threshold value, and store the second count value when the second count value is greater than the second threshold value; The second count value is used to represent the number of rows in which at least one error information exists in the bank array.

13. The ECS circuit of claim 12.

15. The error tracking module further includes a second error tracking module; the second error tracking and recording module is configured to receive the error signal, count error information of a target row according to the error signal and the end of column signal, and after determining a third count value of the target row, compare the third count value with a target count value stored in a first register module; if the third count value is greater than the target count value, scrub the target count value stored in the first register module, and save the third count value as a target count value in the first register module; continue to perform error counting of the next target row according to the error signal and the end of column signal until receiving the end of ECS signal; and when receiving the end of ECS signal, determine a target count value stored in the first register module, the third count value being used to represent the number of code words in which error information exists in the target row.

11. The ECS circuit of claim 10.

16. The second error tracking module is further configured to store address information corresponding to the target count value in a second register module when storing the target count value in the first register module, the address information including row address information, bank address information, and bank group address information corresponding to the target count value; 16. The ECS circuit of claim 15.

17. The second error tracking module is further configured to: after receiving the ECS end signal, compare the currently stored target count value in the first register module with a third threshold; if the target count value is equal to or greater than the third threshold, retain the target count value stored in the first register module and the address information stored in the second register module; and if the target count value is less than the third threshold, scrub the target count value stored in the first register module and the address information stored in the second register module.

17. The ECS circuit of claim 16.

18. 18. An error detection and scrubbing (ECS) method applied to an ECS circuit according to any one of claims 1 to 17, comprising the steps of: receiving, by the ECS control module, a mode control signal and generating an ECS command signal based on the mode control signal; receiving, by the command generation module, the ECS command signal and generating an internal command signal based on the ECS command signal, the internal command signal being used to perform a corresponding ECS ​​action; and receiving the internal command signal by the address count module, performing address counting according to the internal command signal, and generating a count end signal when the counting of the target address is completed; receiving, by the error tracking recording module, the count end signal and an error signal; and generating an error tracking signal based on the count end signal and the error signal, wherein the error tracking signal is used to record error information of the ECS operation.

19. A memory comprising an ECS circuit according to any one of claims 1 to 17.

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