Usage-based memory mapping

Abstract

1. An apparatus for executing a software program, comprising: a processing unit; at least one memory component each connected to the processing unit and mapped to a memory address range of the processing unit; and a memory mapping circuit connected to the processing unit and to the memory component and configured to: access statistical counters collected while the processing unit is executing the software program, in each of a plurality of iterations, and generate a mapping between a first memory address range and a second memory address range in accordance with an analysis of the statistical counters, subject to identifying the first range and the second range; and in response to receiving a memory access command from the processing unit including a first memory address within the first range, replace the first memory address with a second memory address within the second range in accordance with the mapping in the memory access command.

Description

[Technical field]

[0001] The present disclosure relates to computerized devices, and more particularly, but not exclusively, to computerized devices having two or more memory components.

[0002] For simplicity, hereinafter the term "system" will be used to mean a computerized system, and these terms will be used interchangeably. [Background technology]

[0003] There are countless metrics for measuring the performance of a computerized system, such as throughput, i.e., the amount of tasks executed in a specified time interval, and latency, i.e., the amount of time a task is delayed before being executed. For example, improving the performance of a system by increasing the throughput of the system and additionally or alternatively reducing the latency of the system depends, among other factors, on the amount of computer resources available to the system and how well the various components of the system work together. For example, the performance of a system can be improved by reducing the latency when accessing memory and additionally or alternatively increasing the throughput of memory accesses.

[0004] Memory components with relatively high performance access characteristics, such as low latency memory components or memory components with high throughput, such as static RAM (SRAM), are illustratively more expensive than memory components with lower performance access characteristics, such as dynamic RAM (DRAM). To balance the cost and performance of a system, it is common to design the memory of a system using two or more types of memory components. Some common system designs organize multiple memory components in multiple tiers of memory, with smaller, faster tiers shadowing larger, slower tiers that act as caches to the larger tiers. In some designs, there is a hierarchy of tiers, where only the largest tier is available for use by a software program, i.e., addressable using the software program's application memory address, and other tiers in the hierarchy act as hierarchical caches.

[0005] Some other system designs make all layers of memory addressable using the software program's application memory address. In such systems, the performance of the system is affected by the distribution of the software program's application memory among multiple layers of memory, i.e., among one or more memory components of the system. When the software program's application memory comprises multiple application memory regions, performance can be improved when frequently accessed application memory regions are stored in one or more high performance memory components, while lower performance memory components are used to store less frequently accessed application memory regions.

[0006] The term non-uniform memory access (NUMA) refers to a computerized system having two or more memory components, where some characteristics of memory access from a processing unit to a memory component, such as latency, and additionally or alternatively throughput, depend on the topology of the system, such as the location of the memory component relative to the processing unit. As with the systems described above, in a system with NUMA, the performance of the system may be affected by the distribution of application memory of a software program among one or more memory components. Summary of the Invention

[0007] The present disclosure includes a description of an apparatus and method for memory management. In some embodiments described herein, a memory mapping circuit is used to map application memory of a software program executed by a processing unit among one or more memory components connected to the processing unit without requiring calculations by the processing unit and without affecting a memory mapping table used by an operating system executed by the processing unit. In further such embodiments, the memory mapping circuit is configured to replace a first memory address within a first memory address range with a second memory address within a second memory address range in a memory access command received from the processing unit according to a mapping between the first memory address range and the second memory address range generated according to an analysis of one or more statistical counters collected while the processing unit executes the software program. By using the memory mapping circuit to generate a mapping between the first memory address range and the second memory address range and replacing memory addresses in the memory access command according to the generated mapping, the amount of processing overhead required from the processing unit to update the distribution of multiple application memory regions of the software program among one or more memory components is reduced, thus improving the performance of the device.

[0008] These and other objects are achieved by the features of the independent claims. Further implementation forms are evident from the dependent claims, the description and the drawings. [Means for solving the problem]

[0009] According to a first aspect, an apparatus for executing a software program comprises: a processing unit; at least one memory component each connected to the processing unit and mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; and a memory mapping circuit connected to the processing unit and to the at least one memory component and configured to: in each management iteration of a plurality of management iterations, access one or more of a plurality of statistical counters collected while the processing unit is executing the software program, and generate a mapping between a first memory address range of the plurality of memory address ranges and a second memory address range of the plurality of memory address ranges according to an analysis of the one or more statistical counters, subject to identifying the first memory address range and the second memory address range; and in response to receiving at least one memory access command from the processing unit including a first memory address within the first memory address range, replace the first memory address with a second memory address within the second memory address range in accordance with the mapping in the at least one memory access command.

[0010] According to a second aspect, a method for managing memory in an apparatus for executing one or more software programs includes, in each management iteration of a plurality of management iterations, accessing one or more of a plurality of statistical counters collected while the processing unit is executing at least one of the one or more software programs by a memory mapping circuit connected to a processing unit and to at least one memory component connected to the processing unit, each of the at least one memory component being mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; generating a mapping between a first memory address range of the plurality of memory address ranges and a second memory address range of the plurality of memory address ranges according to an analysis of the one or more statistical counters, subject to identifying the first memory address range and the second memory address range; and, in response to receiving at least one memory access command from the processing unit including a first memory address within the first memory address range, replacing in the at least one memory access command the first memory address with a second memory address within the second memory address range according to the mapping.

[0011] According to a third aspect, a software program product for memory management includes a non-transitory computer-readable storage medium and first program instructions, the first program instructions including: at each management iteration of a plurality of management iterations, a memory mapping circuit coupled to a processing unit and to at least one memory component coupled to the processing unit, each of the at least one memory component being mapped to at least one memory address range of a plurality of memory address ranges of the processing unit, the memory mapping circuit accessing one or more of a plurality of statistical counters collected while the processing unit is executing at least one of the one or more software programs, and accessing one or more of the statistical counters by the memory mapping circuit. and second program instructions for generating, in response to receiving from the processing unit at least one memory access command including a first memory address in the first memory address range, a mapping between a first memory address range of the plurality of memory address ranges and a second memory address range of the plurality of memory address ranges in accordance with the analysis, conditioned on identifying the first memory address range and the second memory address range, and for replacing, in the at least one memory access command, the first memory address with a second memory address in the second memory address range in accordance with the mapping. According to a third aspect, the first and second program instructions are executed by at least one computerized processor from a non-transitory computer-readable storage medium.

[0012] In one implementation of the first and second aspects, the plurality of statistical counters comprises a high access counter, a low access counter, and a plurality of range access counters, each associated with one of the plurality of memory address ranges. Optionally, accessing the one or more statistical counters comprises accessing at least one of the low access counter and the high access counter, performing another analysis comprising at least one of the low access counter and the high access counter, and accessing at least one range access counter according to another result of the other analysis. Using a watermark counter, e.g., a high access counter or a low access counter, in addition to the plurality of range access counters facilitates reducing the amount of access to the plurality of range access counters, and reduces the amount of computing resources required for memory mapping compared to a method of accessing all of the plurality of range access counters.

[0013] In another implementation of the first and second aspects, the apparatus further comprises at least one memory tracking circuit coupled to the processing unit and the at least one memory component. Optionally, at least one of the plurality of statistical counters is implemented in the at least one memory tracking circuit configured to update at least one of the plurality of statistical counters in response to receiving a memory access command from the processing unit in each tracking iteration of the plurality of tracking iterations. Implementing the statistical counters in the memory tracking circuit reduces an amount of computing resources required to track one or more memory accesses compared to implementing the statistical counters in a page table of an operating system executed by the processing unit executing a software program. Optionally, the memory mapping circuit is further configured to access one or more of the plurality of statistical counters by accessing the at least one memory tracking circuit. Optionally, the memory mapping circuit is further configured to set at least one of a low access threshold and a high access threshold in the at least one memory tracking circuit. Optionally, the memory mapping circuit sets at least one of a low access threshold and a high access threshold in the at least one memory tracking circuit according to yet another result of the yet another analysis comprising the one or more statistical counters. Setting a low access threshold and additionally or alternatively a high access threshold improves the accuracy of the high access counter and the low access counter, improving the accuracy of memory mapping calculated according to one or more statistical counters.

[0014] In a further implementation of the first and second aspects, the memory mapping circuitry further comprises a plurality of address mappings each mapping one of the plurality of memory address ranges to a media address range, the media address range being another of the plurality of memory address ranges. Mapping one of the plurality of memory address ranges to a media address range being another of the plurality of memory address ranges allows an application memory region of the software program to be moved from one memory component to another memory component without modifying an operating system page table that maps application addresses of the software program to physical addresses of the processing unit, reducing an amount of interruption to one or more services provided by the device that executes the software program. Optionally, generating the mapping between the first memory address range and the second memory address range includes updating the media address range of each of the address mappings of the first memory address range to be the second memory address range. Optionally, the memory mapping circuitry is configured to perform a plurality of management iterations while the processing unit executes the software program. By performing multiple management iterations of generating a memory mapping while a processing unit executes a software program, the performance of the device executing the software program can be improved without increasing the amount of interruption to one or more services provided by the device executing the software program.

[0015] In a further implementation of the first and second aspects, the memory mapping circuitry is further configured to copy at least one data value stored in a first one of the at least one memory components associated with the first memory address range to a second one of the at least one memory components associated with the second memory address range, conditional on identifying the first memory address range and the second memory address range according to the analysis of the plurality of statistical counters. Optionally, the application memory of the software program comprises a plurality of application memory areas, each of which is stored in one of the at least one memory components. Optionally, the at least one data value is part of at least one application memory area of ​​the plurality of application memory areas. Copying the one or more data values ​​that are part of the application memory of the software program improves the performance of the device that executes the software program without increasing the amount of interruption to one or more services provided by the device that executes the software program.

[0016] In a further implementation of the first and second aspects, the processing unit executes the software program by executing an operating system having an operating system page size for memory management. Optionally, at least one of the plurality of memory address ranges addresses an amount of memory different from the operating system page size. Mapping memory using a memory address range having a range size not equal to any of the set of operating system page sizes improves the accuracy of analysis of one or more statistical counters, thus improving the performance of the device executing the software program.

[0017] Other systems, methods, features, and advantages of the present disclosure will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims.

[0018] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the implementation pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the implementations, exemplary methods and / or materials are described below. In case of conflict, the patent specification, including definitions, will control. Additionally, the materials, methods, and examples are merely illustrative and are not intended to be necessarily limiting.

[0019] Some embodiments are herein described, by way of example only, with reference to the accompanying drawings, in which: With particular reference now to the drawings in detail, it is emphasized that the particulars shown are by way of example and for illustrative purposes of the embodiments, In this regard, the description made with the aid of the drawings will make apparent to those skilled in the art how the embodiments may be practiced. [Brief description of the drawings]

[0020] [Figure 1] 1 is a schematic block diagram of an exemplary apparatus according to some embodiments. [Diagram 2] FIG. 2 is a schematic block diagram of an exemplary address mapping according to some embodiments. [Diagram 3] FIG. 2 is a schematic block diagram of an exemplary memory mapping according to some embodiments. [Figure 4] FIG. 13 is a schematic block diagram of another example memory mapping according to some embodiments. [Diagram 5] 1 is a flow chart that generally illustrates an optional operational flow for memory mapping, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The term "processing unit" as used herein refers to any type of programmable or non-programmable circuitry configured to perform the operations described below. A processing unit may comprise hardware as well as software. For example, a processing unit may comprise one or more processors and a temporary or non-transitory memory carrying programs that cause the processing unit to perform respective operations when the programs are executed by the one or more processors.

[0022] In addition, the term "physical address" as used herein means an address used by a processing unit in a memory access request to access a memory component. In addition, the term "application address" as used herein means an address used by an application. The application address may be a virtual address, in which case the application address needs to be translated into a physical address in order to access one or more memory components. In addition, the term "media address" as used herein means an address recognized by a memory component. The processing unit may use a media address in a memory access request. Optionally, the memory address in the memory access request is mapped to the media address. The term "memory mapping" as used herein refers to mapping an application memory address of a software program to a physical address in a memory access request sent by a processing unit. Such mapping may be used to translate an application address into a physical address that identifies a location in a memory component where application data or instructions are stored.

[0023] Additionally, as used herein, the terms "memory access request" and "memory access command" are both used to mean a request to access a memory component for purposes of reading from, and additionally or alternatively writing to, a memory component, and the terms are used interchangeably. A memory access request may be generated when executing computer instructions of a software program that includes memory access computer instructions.

[0024] Additionally, as used herein, the terms "memory address range" and "memory address range" are both used interchangeably to mean a range of memory addresses.

[0025] In order to assign each of a plurality of application memory regions to one or more memory components connected to a processing unit such that system performance is improved, some systems track accesses to the one or more memory components and use the collected tracking information to identify application memory regions that should be moved from one memory component to another. Some existing tracking methods maintain access counters in a page table that is used by an operating system executed by the processing unit to map application addresses of software programs to physical addresses of the processing unit. Some such methods update the counters in the page table each time memory is accessed. Analysis of the multiple counters in the page table requires merging counters of multiple virtual pages that are mapped to a common physical page. Some methods further require sorting the multiple counters to classify page table entries, for example, to identify page table entries that describe high access application memory regions. In addition, moving an application memory region from one memory component to another memory component requires computational resources of the processing unit to update the page table and possibly to copy the application memory region from one memory component to the other memory component. Such methods require computational resources of the processing unit and thus reduce system performance. Furthermore, one or more means provided by the system for executing software programs may be suspended while the page table is being updated.

[0026] In order to reduce the amount of computing resources of the processing unit used to map application memory to one or more memory components, the present disclosure proposes in some embodiments described herein to use a memory mapping circuit connected to the processing unit and to the one or more memory components to generate a mapping between one or more physical addresses of the processing unit and one or more media addresses of the one or more memory components, and to replace, in a memory access command received from the processing unit, the memory address of the memory access command with a media address of one of the memory components according to the generated mapping. Optionally, the memory address of the memory access command is a first physical memory address within a first memory address range of the processing unit, the range of memory addresses being one of a plurality of memory address ranges of the processing unit. Optionally, the media address is a second physical memory address within a second memory address range of the plurality of memory address ranges. Such a mapping between the one or more physical addresses used by the processing unit and the one or more media addresses recognized by the one or more memory components allows the application memory region to be moved from one memory component to another without modifying the operating system's page tables, which map application addresses of software programs to physical addresses of the processing unit. Refraining from modifying the page table reduces an amount of disruption to one or more services provided by a system executing the software program. Optionally, the memory mapping circuitry generates the mapping at each of a plurality of management iterations. Optionally, the memory mapping circuitry generates the mapping while the processing unit executes the software program.

[0027] Optionally, the mapping is generated according to an analysis of one or more statistical counters collected while the processing unit executes the software program. Optionally, the statistical counters are indicative of a plurality of memory access commands. For example, if the processing unit has a plurality of memory address ranges and each of the one or more memory components is mapped to one or more of the plurality of memory address ranges, the statistical counters may be range access counters associated with the memory address ranges that indicate the number of times the memory address range is accessed within the plurality of memory access commands. Optionally, the statistical counters indicate an amount of range access counters that meet the identified criteria. For example, the statistical counter may be a watermark counter that indicates an amount of range access counters that exceed a high access threshold, the high access threshold indicating an amount of accesses to the memory address range that is considered high. Alternatively, the watermark counter may indicate an amount of range access counters that are below a low access threshold, the low access threshold indicating an amount of other accesses to the memory address range that is considered low. Optionally, the statistical counters indicate an amount of memory access commands received from the processing unit. Optionally, the one or more processing circuits receive the memory access command in each of the multiple iterations and update at least one statistical counter of the multiple statistical counters in each of the multiple iterations.

[0028] Performing the analysis by the memory mapping circuitry reduces the amount of computing resources of the processing unit required to perform the analysis compared to performing the analysis by the processing unit, thereby improving performance of the system when executing the software program, for example by increasing throughput and additionally or alternatively reducing latency when executing one or more tasks of the software program.

[0029] Optionally, the memory mapping circuitry is further configured to copy one or more data values ​​stored in a first memory component of the one or more memory components to a second memory component of the one or more memory components, the first memory component being associated with a first memory address range and the second memory component being associated with a second memory address range. Optionally, the memory mapping circuitry copies the one or more data values ​​from the first memory component to the second memory component conditioned on identifying the first memory address range and the second memory address range according to analysis of the one or more statistical counters. Copying the one or more data values ​​by the memory mapping circuitry reduces an amount of interruption to one or more services provided by the system executing the software program compared to copying the one or more data values ​​by a processing unit.

[0030] Optionally, at least one of the one or more statistical counters is implemented in one or more tracing circuits coupled to the processing unit and the one or more memory components. Implementing the statistical counter in the tracing circuit reduces an amount of resources used by the processing unit to trace multiple memory accesses, e.g., reduces an amount of memory accesses performed by the processing unit, and additionally or alternatively reduces an amount of processor cycles of the processing unit used to calculate the memory mapping. Optionally, the memory mapping circuit is further configured to configure the one or more tracing circuits.

[0031] When the processing unit executes an operating system, the operating system may address a plurality of memory components using a plurality of operating system memory pages. It is common not to use any page size for the plurality of operating system memory pages, i.e., each of the plurality of operating system memory pages has one of the identified set of page sizes. When memory access tracking is performed using the operating system's page table, the granularity of the memory access tracking is according to the page size of each of the plurality of operating system memory pages. In some embodiments described herein, at least one identified memory address range of the plurality of memory address ranges has a range size that is not equal to any of the set of page sizes. By tracking the plurality of memory access commands according to the plurality of memory address ranges using one or more range access counters, the plurality of memory access commands can be tracked at a granularity different from the operating system's page size, which improves the accuracy of the memory mapping calculated according to the plurality of statistical counters compared to the memory mapping calculated when tracking is according to the operating system's page size, and thus improves the accuracy of the allocation of the plurality of application memory regions to the one or more memory components, thereby improving the performance of the system.

[0032] Before describing at least one embodiment in detail, it is to be understood that the embodiments are not necessarily limited in their application to the details of construction and the arrangement of components and / or methods set forth in the following description and / or illustrated in the drawings and / or examples. Implementations described herein are capable of other embodiments or of being practiced or carried out in various ways.

[0033] The embodiments may be systems, methods, and / or computer program products. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the embodiments.

[0034] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), static random access memories (SRAMs), portable compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, and any suitable combinations of the above. A computer-readable storage medium as used herein should not be construed as a transitory signal itself, such as an electric signal transmitted over a wire, or an electromagnetic wave or other freely propagating electromagnetic wave, or an electromagnetic wave propagating through a wave guide or other transmission medium (e.g., a light pulse passing through a fiber optic cable).

[0035] The computer readable program instructions described herein may be downloaded from a computer readable storage medium or over a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, into each computing / processing device or to an external computer or external storage device. The network may comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing / processing device.

[0036] The computer readable program instructions for carrying out the operations of the embodiments may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or source or object code, either natively compiled or just-in-time (JIT) compiled, written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, Java, Object-Oriented Fortran, interpreted programming languages ​​such as JavaScript, Python, and traditional procedural programming languages ​​such as the "C" programming language, Fortran, or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to perform aspects of the embodiments.

[0037] Aspects of the embodiments are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to the embodiments. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0038] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to manufacture a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions may also be stored on a computer readable storage medium capable of directing a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that a computer readable storage medium having instructions stored thereon includes an article of manufacture including instructions implementing aspects of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0039] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operational steps to generate a computer-implemented process, such that the instructions, executing on the computer, other programmable apparatus, or other device, perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0040] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or part of instructions that includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that executes the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0041] Reference is now made to Figure 1, which illustrates a schematic block diagram of an exemplary apparatus, according to some embodiments. In such an embodiment, a processing unit 101 is connected to at least one memory component 120.

[0042] For brevity, hereafter, the term “memory component 120” is used to mean “at least one memory component 120”, and these terms are used interchangeably. Optionally, memory component 120 comprises one memory component, e.g., memory component 120C. Optionally, memory component 120 comprises multiple memory components, e.g., memory component 120A, memory component 120B, and memory component 120C. The memory components may be random access memory (RAM) components, e.g., SRAM components or DRAM components. Other examples of memory components include read-only memory (ROM) components, electrically erasable programmable ROM (EEPROM), and non-volatile RAM (NVRAM). Optionally, one or more of memory components 120 are electrically coupled to processing unit 101. Optionally, one or more of memory components 120 are connected to processing unit 101 via a host memory controller (not shown).

[0043] Optionally, one or more of the memory components 120 are cache memory components of the processing unit 101. Optionally, one or more of the memory components 120 are connected to other cache memory components (not shown) that are additionally connected to the processing unit 101.

[0044] Optionally, one or more memory tracking circuits 130 are coupled to the processing unit 101 and to the memory components 120. Optionally, each of the memory components 120 is mapped to at least one memory address range of the multiple memory address ranges of the processing unit 101.

[0045] Reference is now also made to Figure 2, which illustrates a schematic block diagram of an exemplary address mapping 200, according to some embodiments. In this example, memory component 120A is mapped to memory address range 201A, memory address range 201B, and memory address range 201C of multiple memory address ranges 201. Thus, when processing unit 101 accesses a memory address in one of memory address range 201A, memory address range 201B, and memory address range 201C, processing unit 101 accesses the memory component.

[0046] Similarly, memory component 120B is mapped to memory address range 201D of multiple memory address ranges 201, and memory component 120C is mapped to memory address range 201E and memory address range 201F of multiple memory address ranges 201.

[0047] Optionally, processing unit 101 executes an operating system that uses a plurality of operating system memory pages to address memory component 120. Optionally, each of the plurality of operating system memory pages has a page size that is one of an identified set of page sizes. Optionally, at least one of the plurality of memory address ranges 201 has a size that is not a member of the identified set of page sizes.

[0048] Referring again to Figure 1, optionally, memory mapping circuitry 110 is coupled to the processing unit 101 and to the memory component 120.

[0049] Optionally, memory mapping circuit 110 includes a plurality of address mappings. Optionally, each address mapping of the plurality of address mappings maps one of the plurality of memory address ranges 201 to a media address range, which is another of the plurality of memory address ranges 201.

[0050] Reference is now also made to Figure 3, which illustrates a schematic block diagram of an exemplary memory mapping 300, according to some embodiments. In this example, the plurality of address mappings 321 includes address mapping 321A, which maps memory address range 201A to a memory address range associated with memory component 120A, e.g., media address range, which is memory address range 201A.

[0051] Similarly, in this example, the plurality of address mappings 321 includes address mapping 321D, which maps memory address range 201D to another range of memory addresses associated with memory component 120B, such as another range of media addresses, which is memory address range 201D.

[0052] Additionally, in this example, the plurality of address mappings 321 includes address mapping 321E, which maps memory address range 201E to a further memory address range associated with memory component 120C, e.g., a further range of media addresses, e.g., memory address range 201E.

[0053] Furthermore, in this example, the plurality of address mappings 321 includes an address mapping 321B that maps memory address range 201B, an address mapping 321C that maps memory address range 201C, and an address mapping 321F that maps memory address range 201F.

[0054] When the application memory of the software program executed by the processing unit 101 comprises a plurality of application memory regions 301, one or more of the plurality of memory regions may be stored in one of the memory components and associated with one of the plurality of memory address ranges 201. In this example, application memory region 301A of the plurality of application memory regions 301 is stored in memory component 120A and associated with memory address range 201A. When the processing unit 101 sends a memory access command to access application memory region 301A, the memory access command includes a first memory address within memory address range 201A. Memory component 120A responds to the memory address command when address mapping 321A maps memory address range 201A to a media address range that is memory address range 201A.

[0055] Similarly, application memory area 301B of the plurality of application memory areas 301 is stored in memory component 120B and associated with memory address range 201D, and application memory area 301C of the plurality of application memory areas 301 is stored in memory component 120C and associated with memory address range 201E.

[0056] According to some embodiments, memory mapping circuitry 110 optionally generates a new mapping for a memory address range of the plurality of memory address ranges 201 .

[0057] Reference is now also made to FIG. 4, which shows a schematic block diagram of another exemplary memory mapping 400, according to some embodiments. In this example, instead of memory mapping 321A, a new memory mapping 421A is generated, which maps memory address range 201A to a new media address range, which is a memory address range in memory component 120C, for example memory address range 201F. Optionally, application memory area 301A associated with memory address range 201A is now stored in memory component 120C, not memory component 120A. In this example, when processing unit 101 sends a new memory access command to access application memory area 301A, the new memory access command includes a first memory address in memory address range 201A. In this example, address mapping 421A maps memory address range 201A to a new media address range, which is memory address range 201F, so that in some embodiments memory mapping circuit 120 replaces the first memory address in the new memory access command with a second memory address within memory address range 201F, such that memory component 120C responds to the new memory address command instead of memory component 120A.

[0058] Thus, in this example, without modifying the page tables that map multiple application memory regions 301 to multiple memory address ranges 201, processing unit 101 accesses application memory region 301A using memory address range 201A, even though application memory region 301A is stored in memory component 120C as before and not in memory component 120A.

[0059] To manage memory, the memory mapping circuitry 110 in the system 100 may implement the following optional methods.

[0060] Reference is now also made to FIG. 5, which illustrates a flow chart that generally illustrates an optional operational flow 500 for memory mapping, according to some embodiments.

[0061] For simplicity, hereinafter the term "mapping circuitry" will be used to mean "memory mapping circuitry" and these terms will be used interchangeably.

[0062] In such an embodiment, at 501, the mapping circuit 110 accesses one or more of a plurality of statistical counters collected while the processing unit 101 executes the software program. Optionally, the plurality of statistical counters comprises a plurality of range access counters, each associated with one of the plurality of memory address ranges 201. Optionally, the plurality of statistical counters comprises one or more watermark counters, each associated with a frequency of access to a memory component. The watermark counter may indicate a quantity of the memory access range accessed with a frequency associated with the watermark counter. The watermark counter may be a high access counter indicating a quantity of the range access counters of the plurality of range access counters that exceed a high access threshold, indicating frequent accesses to a respective memory component associated with the range access counter that exceeds a high access threshold. For example, a range access counter of the memory address range 201A that exceeds a high access threshold may indicate frequent accesses to the memory component 120A associated with the memory address range 201A. Another example of a watermark counter is a low access counter indicating a quantity of the range access counters of the plurality of range access counters that exceed a low access threshold. There may be three or more watermark counters, each associated with one of a plurality of access frequencies to the memory component, and each watermark counter of the three or more watermark counters may be associated with an access threshold indicative of the access frequency associated therewith, i.e., indicative of the amount of range access counters of the plurality of range access counters that exceed the threshold associated with the watermark counter.

[0063] Optionally, accessing the one or more statistical counters includes the mapping circuit accessing at least one of a low access counter and a high access counter. Optionally, accessing the one or more statistical counters includes the mapping circuit performing an initial analysis including the accessed low access counter and additionally or alternatively the high access counter. Optionally, accessing the one or more statistical counters includes the mapping circuit accessing at least one range access counter according to an initial result of the initial analysis.

[0064] Optionally, in each of the one or more access iterations, the mapping circuit 110 accesses one or more range access counters one at a time. Optionally, in each of the one or more access iterations, the mapping circuit 110 accesses a subset of the plurality of range access counters. Optionally, the management component 110 denies access to at least one range access counter upon identifying a stop condition, e.g., receiving an amount of the range access counter that exceeds a threshold equal to the value of a previously accessed watermark counter.

[0065] Optionally, at least one of the multiple statistical counters is implemented in one or more memory tracking circuits 130. Optionally, the one or more memory tracking circuits 130 are configured to update at least one of the multiple statistical counters in each tracking iteration of the multiple tracking iterations in response to receiving a memory access command from the processing unit 101. Optionally, the memory mapping circuit accesses the one or more statistical counters by accessing the one or more memory tracking circuits 130.

[0066] Optionally, at least one other of the plurality of statistical counters is implemented in one of the memory components 120. In some cases, one memory component implementing the at least one other statistical counter is a cache memory component of the processing unit 101. Optionally, at least one other of the plurality of statistical counters is implemented in another cache memory component connected to one or more of the memory components 120.

[0067] Optionally, the memory mapping circuit 110 accesses one or more statistical counters while the processing unit 101 executes a software program.

[0068] At 502, mapping circuit 110 optionally performs an analysis of one or more statistical counters. Optionally, at 507, mapping circuit 110 identifies a first memory address range, e.g., memory address range 201A, and a second memory address range, e.g., memory address range 201F. In some cases, mapping circuit 110 identifies the first memory address range and the second memory address range according to the analysis of one or more statistical counters. For example, if the results of the analysis indicate high frequency access to application memory region 301A using memory address range 201A, mapping circuit 110 may identify memory address range 201A as the first memory address range.

[0069] At 510, mapping circuit 110 optionally generates a mapping between a first memory address range and a second memory address range, for example mapping 421A between memory address range 201A and memory address range 201F. Optionally, mapping 421A is generated by updating the media address range of mapping 321A from memory address range 210A to memory address range 201F.

[0070] Optionally, the memory mapping circuit 110 generates the mapping while the processing unit 101 executes a software program.

[0071] Optionally, at 520, the mapping circuit 110 copies one or more data values, for example at least a portion of the application memory area 301A, from memory component 120A associated with memory address range 201A to memory component 120C associated with memory address range 201F.

[0072] Optionally, before generating mapping 421A and before copying the one or more data values, mapping circuitry 110 suspends access to memory components 120A and 120C from processing unit 101. Optionally, after copying the one or more data values, processing circuitry 110 re-enables access to memory components 120A and 120C from processing unit 101.

[0073] Optionally, copying one or more data values ​​from memory component 120A to memory component 120C includes swapping between the one or more data values ​​and one or more other data values ​​stored in memory component 120C, such that after the swap, the one or more data values ​​are stored in memory component 120C and the one or more other data values ​​are stored in memory component 120A. Optionally, the swapping between the one or more data values ​​and the one or more other data values ​​includes using one or more intermediate memory areas. Optionally, the one or more intermediate memory areas are in one of the memory components 120. Optionally, the one or more intermediate memory areas are in mapping circuit 110.

[0074] Optionally, the mapping circuit 110 repeats one or more of 501, 502, 507, 510 and 520 in each of a plurality of supervised iterations. Optionally, the mapping circuit 110 performs a plurality of supervised iterations while the processing unit 101 executes the software program.

[0075] Optionally, at 540, memory mapping circuit 110 receives one or more memory access commands from processing unit 101. Optionally, the one or more memory access commands include a first memory address within memory address range 201A. Optionally, in response to receiving the one or more memory access commands, at 541, mapping circuit 110 replaces the first memory address in the one or more memory access commands with a second memory address within memory address range 201F in accordance with memory mapping 421A.

[0076] Optionally, the processing unit 101, while executing the software program, optionally sends one or more memory access commands to access the application memory of the software program, for example the application memory area 301A.

[0077] Optionally, the memory mapping circuit 110 sets a plurality of thresholds, such as one or more of a low access threshold or a high access threshold, in the one or more memory tracking circuits 130. Optionally, the memory mapping circuit 110 performs further analysis, including one or more statistical counters. Optionally, the memory mapping circuit 110 sets the one or more thresholds according to further results of the further analysis.

[0078] Optionally, the memory mapping circuit 110 sets a low access threshold and additionally or alternatively sets a high access threshold while the processing unit 101 executes the software program, optionally in at least one of the multiple management iterations.

[0079] The description of various embodiments is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications or technical improvements to the technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0080] It is expected that many related memory mapping circuits and memory tracking circuits will be developed during the life of the patent originating from this application, and the scope of the terms memory mapping circuits and memory tracking circuits is intended to include a priori all such new technologies.

[0081] As used herein, the term "about" refers to ±10%.

[0082] The terms "comprises," "comprising," "includes," "including," "having" and their conjugations mean "including but not limited to." This term encompasses the terms "consisting of" and "consisting essentially of."

[0083] The phrase "consisting essentially of" means that the composition or method may include additional components and / or steps, but only if the additional components and / or steps do not materially change the basic and novel characteristics of the claimed composition or method.

[0084] As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" can include a plurality of compounds, including mixtures thereof.

[0085] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments and / or to exclude the incorporation of features from other embodiments.

[0086] The term "optionally" is used herein to mean "provided in some embodiments and not provided in other embodiments." Any particular embodiment may include multiple "optional" features, unless such features are inconsistent.

[0087] Throughout this application, various embodiments may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the embodiments. Thus, the description of a range should be considered to have specifically disclosed all possible subranges as well as individual numerical values ​​within that range. For example, the description of a range such as 1 to 6 should be considered to have specifically disclosed subranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

[0088] Whenever a numerical range is given herein, it is meant to include any recited numbers (fractional or integer) within the given range. The phrases "ranging between" a first indicated number and a second indicated number and "ranging from" a first indicated number to a second indicated number are used interchangeably herein and are meant to include the first and second indicated numbers and all fractional and integer numbers therebetween.

[0089] It is understood that certain features of embodiments that are described for clarity in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features of embodiments that are described for brevity in the context of a single embodiment may also be provided separately or in any suitable subcombination or as appropriate in any other described embodiment. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments unless the embodiments are inoperable without those elements.

[0090] While the embodiment has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the spirit and broad scope of the appended claims.

[0091] It is the intention of the applicants that all publications, patents, and patent applications mentioned in this specification are incorporated herein by reference in their entirety as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated herein by reference. Furthermore, citation or identification of any reference in this application should not be construed as an admission that such reference is available as prior art to the present invention. To the extent headings are used, they should not be construed as necessarily limiting. Additionally, any priority documents of this application are incorporated herein by reference in their entirety. [Explanation of symbols]

[0092] 100 Systems 101 Processing Unit 110 Memory mapping circuit 120 Memory Components 120A Memory Components 120B Memory Components 120C Memory Components 130 Memory Tracking Circuit 200 Address Mapping 201 Memory Address Range 201A Memory Address Range 201B Memory Address Range 201C Memory Address Range 201D Memory Address Range 201E Memory Address Range 201F Memory Address Range 300 Memory Mapping 301 Application Memory Area 301A Access application memory area 301B Application memory area 301C Application Memory Area 321 Address Mapping 321A Address Mapping 321B Address Mapping 321C Address Mapping 321D Address Mapping 321E Address Mapping 321F Address Mapping 400 Memory Mapping 421A New memory mapping 500 Operational Flow

Claims

1. 1. An apparatus for executing a software program, comprising: A processing unit; at least one memory component, each connected to the processing unit and mapped to at least one of a plurality of memory address ranges of the processing unit; a memory mapping circuit coupled to the processing unit and to the at least one memory component, In each management iteration of multiple management iterations, accessing one or more of a plurality of statistical counters collected during execution of the software program by the processing unit; generating a mapping between a first memory address range of the plurality of memory address ranges and a second memory address range of the plurality of memory address ranges conditioned on identifying the first memory address range and the second memory address range in accordance with an analysis of the one or more statistical counters; and in response to receiving at least one memory access command from the processing unit including a first memory address within the first memory address range, replacing the first memory address with a second memory address within the second memory address range in accordance with the mapping in the at least one memory access command. a memory mapping circuit configured to An apparatus comprising:

2. 2. The apparatus of claim 1, wherein the plurality of statistical counters comprises a high access counter, a low access counter, and a plurality of range access counters, each associated with one of the plurality of memory address ranges.

3. at least one memory tracking circuit coupled to the processing unit and to the at least one memory component; at least one of the plurality of statistical counters is implemented in the at least one memory tracking circuit configured to update at least one of the plurality of statistical counters in response to receiving a memory access command from the processing unit in each tracking iteration of a plurality of tracking iterations; the memory mapping circuitry is further configured to access the one or more of the plurality of statistical counters by accessing the at least one memory tracking circuitry.

3. Apparatus according to claim 1 or 2.

4. the memory mapping circuitry further comprising a plurality of address mappings each mapping one of the plurality of memory address ranges to a media address range, the media address range being another of the plurality of memory address ranges; generating the mapping between the first memory address range and the second memory address range includes updating the respective media address ranges of the respective address mappings of the first memory address range to be the second memory address range; 4. Apparatus according to any one of claims 1 to 3.

5. The memory mapping circuit includes: conditioned on identifying the first memory address range and the second memory address range in accordance with the analysis of the plurality of statistical counters, copying at least one data value stored in a first memory component of the at least one memory component associated with the first memory address range to a second memory component of the at least one memory component associated with the second memory address range.

5. The apparatus of claim 1 , further configured to:

6. the software program application memory comprises a plurality of application memory areas, each of which is stored in one of the at least one memory component; the at least one data value is a portion of at least one application memory area of ​​the plurality of application memory areas; 6. The apparatus of claim 5.

7. 7. The apparatus of claim 1, wherein the memory mapping circuitry is configured to perform the multiple management iterations while the processing unit is executing the software program.

8. Accessing the one or more statistical counters includes: accessing at least one of the low access counter and the high access counter; performing another analysis comprising at least one of the low access counter and the high access counter; accessing at least one range access counter according to another result of the another analysis; 8. The apparatus according to claim 2 , comprising:

9. 9. The apparatus of claim 3, wherein the memory mapping circuitry is further configured to set at least one of a low access threshold and a high access threshold in the at least one memory tracking circuit.

10. 10. The apparatus of claim 9, wherein the memory mapping circuitry sets at least one of the low access threshold and the high access threshold in accordance with further results of further analysis in the at least one memory tracking circuitry comprising the one or more statistical counters.

11. the processing unit executes the software program by executing an operating system having an operating system page size for memory management; at least one of the plurality of memory address ranges addresses an amount of memory different from the operating system page size; 11. Apparatus according to any one of claims 1 to 10.

12. 1. A method for managing memory in a device for executing one or more software programs, comprising: by a memory mapping circuit coupled to a processing unit and to at least one memory component coupled to the processing unit, in each management iteration of the plurality of management iterations, each of the at least one memory component being mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; accessing one or more of a plurality of statistical counters collected while the processing unit is executing at least one of the one or more software programs; generating a mapping between a first memory address range of the plurality of memory address ranges and a second memory address range of the plurality of memory address ranges according to an analysis of the one or more statistical counters, subject to identifying the first memory address range and the second memory address range; in response to receiving at least one memory access command from the processing unit including a first memory address within the first memory address range, replacing the first memory address with a second memory address within the second memory address range in accordance with the mapping in the at least one memory access command; The method includes:

13. 1. A software program product for memory management, comprising: a non-transitory computer readable storage medium; First program instructions, by a memory mapping circuit coupled to a processing unit and to at least one memory component coupled to the processing unit, in each management iteration of the plurality of management iterations, each of the at least one memory component being mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; accessing one or more of a plurality of statistical counters collected while the processing unit is executing at least one of the one or more software programs; and generating a mapping between a first memory address range of the plurality of memory address ranges and a second memory address range of the plurality of memory address ranges in accordance with an analysis of the one or more statistical counters, subject to identifying the first memory address range and the second memory address range. and a first program instruction for: second program instructions, in response to receiving at least one memory access command from the processing unit including a first memory address within the first memory address range, for replacing the first memory address in the at least one memory access command with a second memory address within the second memory address range according to the mapping; Equipped with the first and second program instructions are executed by at least one computerized processor from the non-transitory computer-readable storage medium. Software program products.

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