Resistive Random Access Memory Random Number Generator

Abstract

A random number generator is disclosed that includes a resistive random access memory (RRAM) device including: a first electrode, a second electrode, a third electrode located between the first and second electrodes, at least one electrically insulating layer separating the first and second electrodes from the third electrode, the at least one electrically insulating layer having a substantially uniform thickness, a first filament that is electrically conducting and extends through the at least one electrically insulating layer, a second filament that is located within the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer, a voltage source configured to apply a voltage to at least one of the first electrode and the second electrode, and a voltage sensor configured to sense the voltage at the third electrode to determine whether the first filament or the second filament is more resistive.

Description

[Technical field]

[0001] The present disclosure relates to random number generation, and more particularly to non-volatile, high density integrated circuit memory devices based on resistive random access memory capable of generating random numbers, and related methods. [Background technology]

[0002] Random number generation (RNG) is used in all manner of systems today. True random number generators (TRNG) create a sequence of values ​​where one value does not affect any subsequently generated values. Software-based pseudorandom number generators (PRNG) use a seed to generate numbers in a statistically similar manner to the numbers from a TRNG, albeit in a completely deterministic fashion. Unique hardware identification using a physically unclonable function (PUF) is also used for random number generation. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a random number generator is provided comprising a plurality of resistive random access memory (RRAM) devices, each RRAM device including: a first electrode, a second electrode, a third electrode located between the first and second electrodes, at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, the at least one electrically insulating layer having a substantially uniform thickness, a first filament that is electrically conductive and extends through the at least one electrically insulating layer, a second filament that is located within the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer, a voltage source configured to apply a voltage to at least one of the first electrode and the second electrode, and a voltage sensor configured to sense a voltage at the third electrode to determine whether the first filament or the second filament is more resistive.

[0004] According to some embodiments of the present disclosure, a device is provided that includes at least one pair of resistive random access memory (RRAM) devices, the at least one pair of resistive random access memory (RRAM) devices including a first and a second RRAM device. Each RRAM device includes a top electrode, a bottom electrode, an electrically insulating layer separating the top electrode from the bottom electrode, the electrically insulating layer having a substantially similar thickness to the electrically insulating layer of the other RRAM device in the pair, a first filament extending through the electrically insulating layer and connecting the top electrode and the bottom electrode in the first RRAM device, and a second filament in the insulating layer of the second RRAM device that does not extend through the electrically insulating layer of the second RRAM device. The device also includes an electrically insulating partition between at least a portion of the first RRAM device and at least a portion of the second RRAM device, a voltage source configured to apply a voltage to the at least one pair of RRAM devices, and a voltage sensor configured to sense a voltage difference between the first RRAM device and the second RRAM device.

[0005] According to some embodiments of the present disclosure, a method for generating random numbers is provided. One operation in the method is individually assembling a plurality of resistive random access memory (RRAM) devices. The assembling operation further includes assembling each RRAM device to include a first electrode, a second electrode, a third electrode located between the first electrode and the second electrode, and at least one electrical insulating layer separating the first and second electrodes from the third electrode. A next operation is the at least one electrical insulating layer separating the first and second electrodes from the third electrode. A further operation is introducing a first low resistance filament between the first electrode and the second electrode of each of the RRAM devices, and introducing a second low resistance filament between the first electrode and the second electrode of each of the RRAM devices. Another operation is applying a voltage bias to the first and second electrodes in each of the RRAM devices to randomly change the state of one of the first low resistance filament or the second low resistance filament to a high resistance state. A further operation is to sense a voltage on the third electrode. A next operation is to measure a first resistance value between the first electrode and the third electrode, and a second resistance value between the second electrode and the third electrode. An additional operation is to compare the sensed voltage on the third electrode to the first and second resistance values, and assign a logical value of 1 or 0 to each RRAM device based on the comparison.

[0006] According to one aspect, a random number generator is provided, the random number generator comprising a plurality of resistive random access memory (RRAM) devices, each RRAM device including: a first electrode, a second electrode, a third electrode located between the first and second electrodes, at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, the at least one electrically insulating layer having a substantially uniform thickness, a first filament that is energized and extends through the at least one electrically insulating layer, a second filament that is located within the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer, a voltage source configured to apply a voltage to at least one of the first electrode and the second electrode, and a voltage sensor configured to sense a voltage at the third electrode to determine whether the first filament or the second filament is more resistive.

[0007] According to another aspect, a device is provided comprising at least one pair of resistive random access memory (RRAM) devices, the at least one pair of RRAM devices comprising first and second RRAM devices, each RRAM device including: a top electrode; a bottom electrode; an electrically insulating layer separating the top electrode from the bottom electrode, the electrically insulating layer having a substantially similar thickness as an electrically insulating layer of another RRAM device in the pair; a first filament extending through the electrically insulating layer and connecting the top electrode and the bottom electrode in the first RRAM device; a second filament in the insulating layer of the second RRAM device that does not extend through the electrically insulating layer of the second RRAM device; an electrically insulating partition between at least a portion of the first RRAM device and at least a portion of the second RRAM device; a voltage source configured to apply a voltage to the at least one pair of RRAM devices; and a voltage sensor configured to sense a voltage difference between the first RRAM device and the second RRAM device.

[0008] According to another aspect, a method for generating random numbers is provided, the method including individually assembling a plurality of resistive random access memory (RRAM) devices, the assembling further including assembling each RRAM device to include a first electrode, a second electrode, a third electrode located between the first electrode and the second electrode, and at least one electrically insulating layer separating the first and second electrodes from the third electrode; introducing a first low resistance filament between the first electrode and the second electrode of each of the RRAM devices; introducing a second low-resistance filament therebetween; applying a voltage bias to the first and second electrodes in each of the RRAM devices to randomly change a state of one of the first low-resistance filament or the second low-resistance filament to a high-resistance state; sensing a voltage at the third electrode; measuring a first resistance value between the first electrode and the third electrode; measuring a second resistance value between the second electrode and the third electrode; comparing the sensed voltage at the third electrode to the first and second resistance values; and assigning a logical value of 1 or 0 to each RRAM device based on the comparison.

[0009] According to another aspect, a method for generating random numbers is provided, the method including assembling a plurality of resistive random access memory (RRAM) devices, each RRAM device including a first electrode, a second electrode, a third electrode located between the first electrode and the second electrode, at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, the at least one electrically insulating layer having a substantially uniform thickness, a first filament that is electrically conducting and extends through the at least one electrically insulating layer, a second filament that is located within the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer, a voltage source configured to apply a voltage to at least one of the first electrode and the second electrode, and a voltage sensor configured to sense a voltage at the third electrode to determine whether the first filament or the second filament is more resistive.

[0010] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

[0011] The drawings included in this application are incorporated in and form a part of this specification. They illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The drawings are merely illustrative of certain embodiments and are not intended to be limiting of the disclosure. [Brief description of the drawings]

[0012] [Figure 1A] 1A-1D are cross-sectional views of schematic representations of a structure at assembly stages / steps / actions of a method or process for forming the structure according to an embodiment of the present disclosure. [Figure 1B] 1B is a cross-sectional view of a schematic representation of a structure that is an alternative to the structure of FIG. 1A, at an alternative assembly stage / step / action of a method or process for forming the structure, according to an embodiment of the present disclosure. [Diagram 2] 1C is a cross-sectional view of a schematic representation of the structure of either FIG. 1A or FIG. 1B at a next successive assembly stage / step / operation of a method or process for forming the structure, according to an embodiment of the present disclosure. [Diagram 3] 3 is a cross-sectional view of a schematic representation of the structure of FIG. 2 at a next successive assembly stage / step / operation of a method or process for forming the structure, according to an embodiment of the present disclosure. [Figure 4A] 1A-1D are cross-sectional views of schematic representations of a structure at assembly stages / steps / actions of a method or process for forming the structure according to an embodiment of the present disclosure. [Figure 4B] 4B is a cross-sectional view of a schematic representation of a structure that is an alternative to the structure of FIG. 4A, at an alternative assembly stage / step / action of a method or process for forming the structure, according to an embodiment of the present disclosure. [Diagram 5]4C is a cross-sectional view of a schematic representation of the structure of either FIG. 4A or FIG. 4B at a next successive assembly stage / step / operation of a method or process for forming the structure, according to an embodiment of the present disclosure. [Figure 6] 6 is a cross-sectional view of a schematic representation of the structure of FIG. 5 at a next successive assembly stage / step / operation of a method or process for forming the structure, according to an embodiment of the present disclosure. [Figure 7A] 1A-1D are cross-sectional views of schematic representations of a structure at assembly stages / steps / actions of a method or process for forming the structure according to an embodiment of the present disclosure. [Figure 7B] 7B is a cross-sectional view of a schematic representation of a structure that is an alternative to the structure of FIG. 7A, at an alternative assembly stage / step / action of a method or process for forming the structure, according to an embodiment of the present disclosure. [Figure 8] 7C is a cross-sectional view of a schematic representation of the structure of either FIG. 7A or FIG. 7B at a next successive assembly stage / step / operation of a method or process for forming the structure, according to an embodiment of the present disclosure. [Figure 9] 9 is a cross-sectional view of a schematic representation of the structure of FIG. 8 at a next successive assembly stage / step / operation of a method or process for forming the structure, according to an embodiment of the present disclosure. [Figure 10] 1A-1D are cross-sectional views of schematic representations of a structure at assembly stages / steps / actions of a method or process for forming the structure according to an embodiment of the present disclosure. [Figure 11] 11 is a cross-sectional view of a schematic representation of the structure of FIG. 10 at a next successive assembly stage / step / operation of a method or process for forming the structure, according to an embodiment of the present disclosure. [Figure 12] 12 is a cross-sectional view of a schematic representation of the structure of FIG. 11 at a next successive assembly stage / step / operation of a method or process for forming the structure, according to an embodiment of the present disclosure. [Figure 13]13A-13C are cross-sectional views of schematic representations of the structure of FIG. 12 at the next successive assembly stages / steps / operations of a method or process for forming the structure, according to an embodiment of the present disclosure. [Figure 14] 14 is a cross-sectional view of a schematic representation of the structure of FIG. 13 at a next successive assembly stage / step / operation of a method or process for forming the structure, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] While the present disclosure is susceptible to various modifications and alternative forms, details of which have been shown by way of example in the drawings and will be described in detail. It is to be understood, however, that it is not intended to limit the disclosure to the particular embodiments described. On the contrary, it is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.

[0014] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to RNGs, and more particularly to non-volatile (NV), high density IC memory devices based on resistive random access memory (RRAM or ReRAM) capable of generating random numbers, and related methods. The present disclosure is not necessarily limited to such applications, and various embodiments of the present disclosure may be understood through the discussion of various examples using this context.

[0015] The integrity of the semiconductor supply chain is a critical security need. The loss of trusted semiconductor foundries has highlighted the need to verify that chips installed in critical systems are trustworthy. The use of resistive random access memory (RRAM) devices for the generation of unique electronic fingerprints to identify chips is desirable. RRAM is a type of NV random access (RAM) computer memory that works by varying the resistance across a dielectric solid material, often referred to as a memristor. The basic idea is that a dielectric, which is normally insulating, can be made to conduct through filaments or conductive paths that form after the application of a sufficiently high voltage. The conductive paths can result from different mechanisms, including vacancy or metal defect migration.

[0016] The present disclosure comprises a memristor device. A typical memristor device, such as a RRAM, has two critical resistance states: a high resistance state (HRS) and a low resistance state (LRS). To change a memristor device from the HRS to the LRS (called a SET operation), a voltage bias V SET must be applied to the device. In practice, a current limit is usually imposed on the device during SET; otherwise, an unrestrained high current through the device would permanently establish LRS by electrically breaking down the oxide. Once a device is in LRS, it can be turned off by a voltage that is typically lower than the voltage V RESET However, without current limiting, it can be switched back to HRS by RESET operation.

[0017] Several embodiments of RRAM random number generators having different structures are disclosed herein. One feature and advantage of at least one disclosed embodiment is that the structure can generate multiple random number patterns that are important for protecting hardware, and is applicable to both PUF and RNG. At least one disclosed embodiment uses series-connected RRAM devices with metal oxide layers deposited simultaneously (i.e., having the same thickness and composition in both series-connected devices) for PUF and / or RNG applications.

[0018] Another feature and advantage of at least one disclosed embodiment is that the RESET of a pair of series-connected RRAM devices can be used to generate a random number pattern, unlike previous devices that exploit the variability of individual devices.

[0019] As disclosed herein, for at least one embodiment, a pair of RRAM devices or one RRAM device with a portion separated by a dielectric layer is first formed. When a positive voltage is applied, two filaments are formed through the insulating layer(s) in the RRAM device(s). Then, a RESET bias, or a voltage bias (negative voltage) is applied to the pair of devices connected in series. This process randomly RESETs one of the two devices to HRS due to the stochastic nature of the RESET process. When one device RESETs to HRS, most of the applied voltage is dropped in the one device that is HRS, while the other device remains in LRS. The device resistances of the pair of RRAM devices are compared, for example, by sensing the voltage of the middle electrode between the two RRAM devices. One RRAM device will have a high resistance and the other RRAM device will have a low resistance. Based on the two voltages or resistances to half the sensed voltage, a logical value of 1 or 0 is assigned. The RESET process, being self-limiting, creates a large difference in resistance (i.e., LRS and HRS) between the pair of RRAM devices (or one RRAM device that is at least partially split). This makes the PUF / RNG more robust to read noise (e.g., 1 / f noise, random telegraph noise) compared to conventional RRAM-based PUFs that exploit the variability of HRS. Thus, yet another feature and advantage of at least one disclosed embodiment is that the structure is less susceptible to read noise and retention due to competing RESET mechanisms compared to conventional non-volatile memory (NVM)-based PUFs. A further feature and advantage of at least one embodiment of the present disclosure is that the large sensing margin allows for improved retention of the random state.

[0020] Referring first to FIG. 1A, a cross-sectional view of a schematic representation of a structure 100 is shown at an assembly stage / step / operation of a method or process for forming a final structure. FIG. 1B is an alternative structure to that of FIG. 1A. FIGS. 2 and 3 illustrate subsequent assembly stages / steps / operations of a method or process for forming the final structure in FIG. 3. It should be understood that FIG. 3 presents, in schematic form, only a portion of a semiconductor or IC chip as it will ultimately be assembled and placed in use. Circuit elements may be formed both above and below the structure 100 shown in FIG. 3. Other embodiments of structures disclosed and shown herein are also portions of semiconductor or IC chips. Features and formations related to such structures are described in detail below.

[0021] For the sake of brevity, conventional techniques associated with semiconductor device or IC chip fabrication may or may not be described in detail herein. Moreover, various tasks and process operations described herein may be combined into more comprehensive procedures or processes having additional operations or functionality not described in detail herein. In particular, because various operations in the manufacture of semiconductor devices or ICs are well known, for the sake of brevity, many conventional operations are only briefly described herein or omitted entirely without providing well-known process details.

[0022] 1A and 1B show a structure 100 having a bottom electrode 105, a first insulator material layer 110 located on the bottom electrode 105, an intermediate electrode 115 located on the first insulator material layer 110, a second insulator material layer 120 located on the intermediate electrode 115, and a top electrode 125 located on the second insulator material layer 120. The arrangement of the electrodes and layers (105, 110, 115, 120, 125) described above may be described as "horizontally arranged" or "horizontally stacked", meaning that the layers and electrodes extend along a horizontal direction and are layered on top of each other. Horizontally arranged may also be described as vertically stacked. Alternatively, the electrodes and layers (105, 110, 115, 120, 125) may be described as parallel to each other. Alternatively, the arrangement of the electrodes and layers (105, 110, 115, 120, 125) may be described as being arranged or mounted in parallel.

[0023] For example, the electrodes 105, 115, 125 (and the electrodes of other embodiments described herein below) may be made of any of a variety of materials, including, for example, n-doped polysilicon and p-doped polysilicon, metals including carbon (C), aluminum (Al), copper (Cu), nickel (Ni), chromium (Cr), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), platinum (Pt), gold (Au), iridium (Ir), tantalum (Ta), tungsten (Tb), and the like. The electrodes 105, 115, 125 may be made of any suitable conductive and semiconductive materials, including, but not limited to, metals including (W), conductive metal nitrides, conductive metal oxides including tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, titanium silicide, ruthenium (IV) oxide (RuO2), and transition metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or 1,4,7-triacyclononane (TaCN). The electrodes 105, 115, 125 may be applied by, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), plasma-enhanced atomic layer deposition (PE-ALD), thermal atomic layer deposition, and physical vapor deposition (PVD), among others.

[0024] The first and second insulator material layers 110, 120 (as well as the insulator material layers of other embodiments described herein below) may be comprised of an electrically insulating material including, for example, hafnium oxide (HfO2), silicon oxide (SiO2), or silicon nitride (Si3N4), among others. The first and second insulator material layers 110, 120 may be applied by, for example, CVD, PE-CVD, PVD, PE-ALD, thermal atomic layer deposition, high density chemical vapor deposition (HDP-CVD), spin-on dielectric processes (SOD), and the like.

[0025] In FIG. 1A, a positive voltage is shown to be applied between the bottom electrode 105 and the top electrode 125. The application of a positive voltage (e.g., by a battery) between the two external electrodes (bottom electrode 105 and top electrode 125) results in the formation or creation of a first filament 130 in the insulator material layer 110 between the bottom electrode 105 and the intermediate electrode 115. The application of a positive voltage also results in the creation of a second filament 135 in the second insulator material layer 120 between the intermediate electrode 115 and the top electrode 125. Alternatively, in FIG. 1B, a voltage bias is shown to be applied between the bottom electrode 105 and the top electrode 125, with the intermediate electrode 115 being grounded (shown as "GND"). The first filament 130 and the second filament 135 are similarly formed as shown in the first and second insulator material layers 110, 120. In the alternative process operations of both Figures 1A and 1B, the first and second filaments 130, 135 that are formed are low resistance filaments.

[0026] In FIG. 2, the next process operation after FIG. 1A or FIG. 1B is shown, where the voltage source is reversed to provide a negative voltage or RESET bias. As a result of the voltage being reversed, both the first and second filaments 130, 135 tend to be reduced (or shrink) or become HRS. However, only one of the two filaments 130, 135 is reduced or destroyed and becomes HRS, which occurs randomly. In FIG. 2, the first filament 130 is shown still bridging the electrodes 105 and 115 or being LRS, while the second filament 135 is shown to be reduced (i.e., destroyed or becomes an open circuit), although the opposite may alternatively occur. The randomness of one of the two filaments being reduced while the other remains bridged results in the random number generation of the present disclosure. When one of the filaments is depleted, nearly all of the applied voltage drops between the two electrodes that the filament originally bridged (in the illustrated case of filament 135, most of the voltage drop is between conductors 115 and 125), so no voltage is available to deplete the bridging filament (filament 130 in the above example).

[0027] FIG. 3 shows a process operation after FIG. 2, where a positive voltage is applied to the top electrode 125 and the bottom electrode 105 is grounded. The applied voltage is a "read voltage" (VRD), which is typically smaller in amplitude than the "formation voltage" required in the previous step to form the filament. The device resistances of a pair of RRAM devices in the structure 100 are compared between the two RRAM devices. Based on the voltage of the middle electrode 115 relative to half the sense voltage, a logic value of 1 or 0 is assigned. As shown in FIG. 3, the bottom electrode 105 and the middle electrode 115 are shorted by the first filament 130 and are therefore at the same potential. An operational amplifier (shown as a triangle with "+" and "-" inputs), otherwise known as a "comparator", compares the "+" terminal voltage to the "-" terminal voltage, and since the voltage difference is 0, which is not greater than ½VRD, the voltage output (V OUT ) is 0. If instead the first filament 130 and the second filament 135 were swapped and the first filament 130 were instead reduced (not shown in the figure), the top electrode 125 and the middle electrode 115 would instead be shorted by the second filament 135 and they would be at the same potential. The operational amplifier, or comparator, would then compare the "+" terminal voltage with the "-" terminal voltage and, since VRD is greater than 1 / 2VRD, find that V OUT is equal to 1.

[0028] 3, for example, if the resistance between the bottom electrode 105 and the intermediate electrode 115 is greater than the resistance measured between the top electrode 125 and the intermediate electrode 115, then a logical value of 1 is assigned. Additionally, if the resistance between the bottom electrode 105 and the intermediate electrode 115 is less than the resistance measured between the top electrode 125 and the intermediate electrode 115, then a logical value of 0 is assigned.

[0029] 4A and 4B show a structure 200 of two serially connected RRAM devices. The two RRAM devices in the structure 200 can be formed as one unit by including a bottom electrode 205, an insulator material layer 210 disposed on the bottom electrode 205, and a top electrode 215 disposed on the insulator material layer 210. In an operation in a process for forming the structure 200 as shown in FIG. 4A and 4B, the two parts of such a metal-insulator-metal (MIM) structure are separated, and a dielectric material separator 240, for example, silicon nitride, is placed to divide the two parts of the MIM structure to form the structure 200. As a result of the two RRAM devices being formed simultaneously, the insulator material layers of the two devices are substantially uniform or nearly uniform in thickness and composition. If the thickness and composition of the insulator material layer are the same in both RRAM devices in which the filament can be formed, less bias may be present in the structure and the system of random number generation.

[0030] 4A and 4B show a first RRAM device (left side) formed with a bottom electrode 205, an insulator material layer 210, and a top electrode 215, and a second RRAM device (right side) formed with the same layers as in the first RRAM device, but with layers marked with '. The second RRAM device includes a bottom electrode 205', a middle electrode 210', and a top electrode 215'. FIG. 4A shows a first filament 230 and a second filament 235 formed in the first and second RRAM devices, respectively. The first and second filaments 230, 235 are formed by applying a positive voltage (e.g., by a battery) between the two RRAM devices. In FIG. 4B, alternatively, the first filament 230 and the second filament 235 are formed by applying a positive voltage to the bottom electrodes 205 and 205' and a ground to the top electrodes 215 and 215'.

[0031] In FIG. 5, the next process operation after FIG. 4A or FIG. 4B is shown, where the voltage source is reversed to provide a negative voltage or RESET bias between the first bottom electrode 205 and the second bottom electrode 205'. As a result of the voltage being reversed, both the first and second filaments 230, 235 tend to be reduced (or shrink) or become HRS. However, only one of the two filaments 230, 235 randomly reduces or breaks and becomes HRS. In FIG. 5, the first filament 230 is shown to still be bridged or LRS and the second filament 235 is reduced (i.e., broken or open), but the opposite may alternatively occur.

[0032] 6 shows a process operation after FIG. 5, where a read voltage is applied to electrode 205 and electrode 205′ is grounded. The device resistance of a pair of RRAM devices in structure 200 is measured by sensing the voltage of top electrodes 215 and 215′ between the two RRAM devices. A logic value of 1 or 0 is assigned based on the voltage of top electrodes 215 and 215′ relative to half the sense voltage. As shown in FIG. 6, bottom electrode 205 and top electrode 215 are shorted by first filament 230 and therefore are at the same potential V RD An operational amplifier or "comparator" (shown as a triangle with "+" and "-" inputs) compares the "+" terminal voltage to the "-" terminal voltage and checks if the voltage difference is positive (approximately 1 / 2V RD ), so the voltage output of the operational amplifier (V OUT ) is saturated to a logic one. If instead the first filament 230 and the second filament 235 were swapped and the first filament 230 were instead reduced (not shown in the figure), then the top electrode 215' and the bottom electrode 205' would instead be shorted by the second filament 235 and they would be at the same potential. The operational amplifier would then compare the "+" terminal voltage to the "-" terminal voltage and, since the voltage difference is negative, V OUT is saturated to logic 0.

[0033] 6, for example, if the resistance between the bottom electrode 205 and either the top electrode 215 or 215' is less than the measured resistance between either the top electrode 215 or 215' and the bottom electrode 205', a logical value of 1 is assigned. Additionally, if the resistance between the bottom electrode 205' and either the top electrode 215 or 215' is less than the measured resistance between either the top electrode 215 or 215' and the bottom electrode 205, a logical value of 0 is assigned.

[0034] 7A and 7B show a structure 300 including an upper electrode 315 disposed on an insulator material layer 310 disposed on a first and second lower electrode 305, 305'. A dielectric material separator 340, for example made of silicon nitride, is placed to separate the first and second lower electrodes 305, 305'. In an operation within a process to form the structure 300 as shown in FIG. 7A and FIG. 7B, the two lower electrodes 305, 305' may be cut or otherwise separated / divided, and the dielectric material separator 340 may be inserted between the two lower electrodes 305, 305'. As a result of the structure 300, the insulator material layer 310 is substantially uniform or uniform in thickness. If the thickness of the insulator material layer 310, in which the filaments may be formed, is substantially uniform, less bias may be present within the structure 300 and the resulting random number generating system.

[0035] 7A and 7B show a first filament 330 and a second filament 335 formed in the insulator material layer 310, with the first filament 330 connecting the first bottom electrode 305 and the top electrode 315, and the second filament 335 connecting the second bottom electrode 305' and the top electrode 315. In FIG. 7A, the first and second filaments 330, 335 are formed by applying a positive voltage between the first bottom electrode 305 and the second bottom electrode 305'. In FIG. 7B, alternatively, the first filament 330 and the second filament 335 are formed by applying a positive voltage between the first bottom electrode 305 and the second bottom electrode 305' and a ground to the top electrode 315.

[0036] In FIG. 8, the next process operation after FIG. 7A or FIG. 7B is shown, where the voltage source is reversed to provide a negative voltage or RESET bias between the first bottom electrode 305 and the second bottom electrode 305'. As a result of the voltage being reversed, both the first and second filaments 330, 335 tend to be reduced (or shrink) or become HRS. However, only one of the two filaments 330, 335 is reduced or destroyed and becomes HRS, which occurs randomly. In FIG. 8, the first filament 330 is shown still bridging the bottom electrode 305 and the top electrode 315 or being LRS, while the second filament 335 is shown to be reduced (i.e., destroyed or open), although the opposite may alternatively occur.

[0037] FIG. 9 shows the next process operation after FIG. 8, where a voltage is applied to the first bottom electrode 305 and the second bottom electrode 305' is grounded. The device resistance in the structure 300 is measured by sensing the voltage at the top electrode 315. A logic value of 1 or 0 is assigned based on the voltage at the top electrode 315 relative to half the sense voltage. As shown in FIG. 9, the bottom electrode 305 and the top electrode 315 are shorted by the first filament 330 and are therefore at the same potential. An operational amplifier or "comparator" (shown as a triangle with "+" and "-" inputs) compares the "+" terminal voltage to the "-" terminal voltage and detects that the voltage difference is approximately positive ½ V. RD Therefore, the voltage output of the operational amplifier (V OUT ) is a logic one. If instead the first filament 330 and the second filament 335 were swapped and the first filament 330 were instead reduced (not shown in the figure), then the top electrode 315' and the bottom electrode 305' would instead be shorted by the second filament 335 and they would be at the same potential. The operational amplifier or "comparator" would then compare the "+" terminal voltage with the "-" terminal voltage and, since the voltage difference is negative, V OUT is equal to logical 0.

[0038] 9, for example, if the resistance between the second bottom electrode 305' and the top electrode 315 is greater than the measured resistance between the top electrode 315 and the first bottom electrode 305, a logical value of 1 is assigned. Additionally, if the resistance between the second bottom electrode 305' and the top electrode 315 is less than the measured resistance between the top electrode 315 and the first bottom electrode 305, a logical value of 0 is assigned.

[0039] Referring to FIG. 10, a first operation is shown in the process of forming a structure 400 having at least one fin and an additional region (two such regions are shown in the figure). A base or substrate 445 is provided and a first metal fin 450 is formed on the base 445. The base 445 may comprise a semiconductor substrate formed of silicon (Si), although other suitable materials may be used. One process that may be used to form the first metal fin 450 is to deposit a conductive film such as W, then use lithography followed by reactive ion etching (RIE) to define and etch the metal or conductive fin 450. Materials that may be used for the metal fin 450 include, but are not limited to, W, TiN, Ta, Cu, and Ag.

[0040] Figure 11 illustrates the next process operation following that of Figure 10. A conformal dielectric material layer 455 is applied over the first metal fin 450 and the base 445. Methods that may be used to apply the conformal dielectric material layer 455 include, but are not limited to, atomic layer deposition (ALD), CVD, and partial oxidation of the first metal fin 450 (e.g., in the case of a W fin, a "film" of tungsten trioxide (WO3) can be formed).

[0041] 12 next shows the structure 400 after two operations: 1) forming (in other words, "sandwiching") a first metal region 460 and a second metal region 465 on either side of a first metal fin 450, on which a metal material is deposited and coated with a conformal dielectric layer 455, and 2) the structure 400 is planarized. The first and second metal regions 460 and 465 may be formed generally as shown as "regions," although other shapes and configurations are contemplated. Formation of such first and second metal regions 460, 465 includes deposition of a metal, such as W or TiN, using CVD or physical vapor deposition (PVD) (sputtering), followed by polishing away excess metal above the base 445 by a method such as chemical mechanical polishing (CMP).

[0042] The arrangement of the fins, regions, and dielectric layers (450, 455, 460, 465) described above may be described as "vertically disposed" or "vertically stacked," meaning that the layers, fins, and regions (450, 455, 460, 465) extend substantially upward along a vertical direction and are disposed alongside one another. This term refers to their arrangement relative to one another (the fins, regions, and dielectric layers (450, 455, 460, 465)). Alternatively, the fins, regions, and layers (450, 455, 460, 465) may be described as applied or placed parallel to one another.

[0043] 13, an operation is shown in which a positive voltage is applied (e.g., by using a battery) between first region 460 and second region 465. As a result of the positive voltage being applied, a first filament 470 and a second filament 475 are formed on either side of conformal layer 455, with first filament 470 connecting first metal fin 450 to first region 460 and second filament 475 connecting first metal fin 450 to second region 465.

[0044] In FIG. 14, the next process operation after FIG. 13 is shown, where the voltage source is reversed to provide a negative voltage or RESET bias between the first region 460 and the second region 465. As a result of the voltage being reversed, both the first and second filaments 470, 475 tend to be reduced (or shrink) or become HRS. However, only one of the two filaments 470, 475 is reduced or destroyed and becomes HRS, which occurs randomly. In FIG. 14, the first filament 470 is shown still bridging or LRS, while the second filament 475 is shown to be reduced (i.e., destroyed or open), although the opposite may alternatively occur. As in the previously disclosed embodiment, a logical value of 1 or 0 may be assigned based on the voltage of the first and second regions 460, 465 relative to half the sense voltage. As shown, fin 450 and first region 460 are shorted by first filament 470 and are therefore at the same potential. An operational amplifier or "comparator," as in other embodiments disclosed herein, may be used to compare the voltages and assign a logical value of 0 or 1 accordingly.

[0045] The disclosed structures 100, 200, 300, and 400 may enable multiple generation of random patterns, which is important for secure hardware. The structures 100, 200, 300, and 400 are applicable to both PUFs and RNGs. RNGs are essential for generating random cryptographic keys for secure transmission protocols. Recently, RNG concepts based on switching variability in low-voltage memory technologies such as Spin Transfer Torque (STT) Magnetic Random Access Memory (MRAM) and RRAM have been proposed. Switching statistical variability in RRAM has been similarly applied to develop PUFs and to improve learning in neuromorphic circuits.

[0046] For the purpose of this description, certain aspects, advantages, and novel features of the present disclosure are described herein. The disclosed method and system should not be interpreted as being limiting in any way. Instead, the present disclosure is directed to all novel and non-obvious features and aspects of the various disclosed embodiments, both alone and in various combinations and subcombinations with each other. The present method and system are not limited to any particular aspect or feature or combination thereof, and the disclosed embodiments do not require that any one or more particular advantages exist or problems are solved.

[0047] Although some operations of the disclosed embodiments are described in a particular sequential order for convenient presentation, it should be understood that such a manner of description encompasses rearrangements unless a particular order is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed simultaneously. Furthermore, for simplicity, the accompanying figures may not show the various ways in which the disclosed methods may be used in conjunction with other methods. Additionally, the description sometimes uses terms such as "provide" or "achieve" to describe the disclosed methods. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms may vary depending on the particular implementation and are readily discernible by those of ordinary skill in the art.

[0048] As used in this application and the claims, the singular forms "a," "an," and "the" include the plural forms unless the context clearly indicates otherwise. Additionally, the term "comprises" means "comprising."

[0049] The description of various embodiments of the present disclosure is presented for illustrative purposes, but is not intended to be exclusive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, and to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A random number generator comprising: a plurality of resistive random access memory (RRAM) devices; Each of the RRAM devices comprises: A first electrode; A second electrode; and a third electrode located between the first electrode and the second electrode; at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, the at least one electrically insulating layer having a substantially uniform thickness; a first filament that is electrically conductive and extends through the at least one electrically insulating layer; and a second filament located within the at least one electrically insulating layer and not extending through the at least one electrically insulating layer; a voltage source configured to apply a voltage to at least one of the first electrode and the second electrode; a voltage sensor configured to sense a voltage on the third electrode to determine whether the first filament or the second filament is more resistive; and Including, a random number generator.

2. 2. The random number generator of claim 1, wherein the at least one electrically insulating layer includes a first electrically insulating layer separating the first electrode from the third electrode, and a second electrically insulating layer separating the second electrode from the third electrode.

3. 3. The random number generator of claim 2, wherein the first electrode, the second electrode, and the third electrode, and the first electrical insulation layer and the second electrical insulation layer are layered in a horizontal arrangement.

4. 4. The random number generator of claim 1, wherein the first electrode, the second electrode, and the third electrode are arranged parallel to each other.

5. 5. The random number generator of claim 1, wherein the at least one electrically insulating layer is a single conformal layer of electrically insulating material.

6. 6. The random number generator of claim 1, wherein the at least one electrically insulating layer has a substantially uniform composition.

7. 7. The random number generator of claim 1, wherein the at least one electrically insulating layer has a substantially uniform thickness.

8. the first filament and the second filament are low resistance filaments; the voltage source is configured to apply a voltage bias to randomly change a state of one of the first low-resistance filament or the second low-resistance filament to a state of high resistance; The random number generator is measuring a first resistance between the first electrode and the third electrode; measuring a second resistance between the second electrode and the third electrode; comparing the sensed voltage at the third electrode to the first resistance value and the second resistance value; The random number generator of claim 1 , further operable to assign a logical value of 1 or 0 to each of said RRAM devices based on said comparison.

9. the at least one insulating layer comprises an insulating layer having a first side and a second side, the third electrode is disposed on one of the first side and the second side, the first electrode and the second electrode are disposed on the other of the first side and the second side with an electrically insulating partition therebetween, the electrically insulating partition forming at least one pair of resistive random access memory (RRAM) devices comprising first and second RRAM devices; Each of the RRAM devices comprises: an upper electrode comprising the third electrode; a lower electrode comprising one of the first electrode and the second electrode; 2. The random number generator of claim 1 , wherein the first filament extends through the one electrical insulating layer and connects the top electrode and the bottom electrode in the first RRAM device, and the second filament in the one insulating layer of the second RRAM device does not extend through the electrical insulating layer of the second RRAM device, the voltage source is configured to apply a voltage to at least one pair of the RRAM devices, and the voltage sensor is configured to sense a voltage difference between the first RRAM device and the second RRAM device.

10. A device, comprising: at least one pair of resistive random access memory (RRAM) devices, the at least one pair of resistive random access memory (RRAM) devices comprising a first and a second RRAM device; Each of the RRAM devices comprises: An upper electrode; A lower electrode; an electrically insulating layer separating the top electrode from the bottom electrode, the electrically insulating layer having a thickness substantially similar to an electrically insulating layer of another RRAM device in the pair; a first filament extending through the electrically insulating layer and connecting the top electrode and the bottom electrode in the first RRAM device; a second filament in the insulating layer of the second RRAM device that does not extend through the electrically insulating layer of the second RRAM device; an electrically insulating partition between at least a portion of the first RRAM device and at least a portion of the second RRAM device; a voltage source configured to apply a voltage to at least one pair of the RRAM devices; a voltage sensor configured to sense a voltage difference between the first and second RRAM devices; and A device comprising:

11. The device of claim 10 , further comprising a comparator configured to compare a voltage difference between the first RRAM device and the second RRAM device.

12. The device of claim 10 or 11, wherein the comparator is configured to assign a logical value of 1 or 0 to each of the RRAM devices.

13. 13. The device of claim 10, wherein the electrically insulating partition separates the bottom electrode of the first RRAM device from the bottom electrode of the second RRAM device and the top electrode of the first RRAM device from the top electrode of the second RRAM device.

14. The device of claim 10 , wherein the electrically insulating partition separates the bottom electrode of the first RRAM device from the bottom electrode of the second RRAM device.

15. 15. The device of claim 10, wherein the at least one electrically insulating layer has a substantially uniform thickness.

16. 1. A method for generating random numbers, comprising: Individually fabricating a plurality of resistive random access memory (RRAM) devices, comprising: A first electrode; A second electrode; and a third electrode located between the first electrode and the second electrode; and at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode. introducing a first low resistance filament between the first electrode and the second electrode of each of the RRAM devices; introducing a second low resistance filament between the first electrode and the second electrode of each of the RRAM devices; applying a voltage bias to the first electrode and the second electrode of each of the RRAM devices to randomly change a state of one of the first low resistance filament or the second low resistance filament to a high resistance state; sensing a voltage on the third electrode; measuring a first resistance between the first electrode and the third electrode; measuring a second resistance between the second electrode and the third electrode; comparing the sensed voltage of the third electrode to the first resistance value and the second resistance value; and assigning a logical value of 1 or 0 to each of said RRAM devices based on said comparing. A method comprising:

17. 17. The method of claim 16, wherein the logical value of one is assigned when the first resistance value is greater than the second resistance value.

18. 18. The method of claim 16 or 17, wherein the logical value of 0 is assigned when the first resistance value is less than the second resistance value.

19. 19. The method of claim 16, wherein the at least one electrically insulating layer of each of the RRAM devices includes a first electrically insulating layer separating the first electrode from the third electrode, and a second electrically insulating layer separating the second electrode from the third electrode.

20. 20. The method of claim 19, wherein the first, second, and third electrodes and the first and second electrically insulating layers are layered in a horizontal arrangement.

21. 21. The method of claim 16, wherein the first electrode, the second electrode, and the third electrode are arranged parallel to each other.

22. 22. The method of any of claims 16 to 21, wherein the at least one electrically insulating layer is a single conformal layer of electrically insulating material.

23. 1. A method for generating random numbers, comprising: and fabricating a plurality of resistive random access memory (RRAM) devices, each of the RRAM devices comprising: A first electrode; A second electrode; and a third electrode located between the first electrode and the second electrode; at least one electrically insulating layer separating the first and second electrodes from the third electrode, the at least one electrically insulating layer having a substantially uniform thickness; a first filament that is electrically conductive and extends through the at least one electrically insulating layer; and a second filament located within the at least one electrically insulating layer and not extending through the at least one electrically insulating layer; a voltage source configured to apply a voltage to at least one of the first electrode and the second electrode; and a voltage sensor configured to sense a voltage at the third electrode to determine whether the first filament or the second filament is more resistive.

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