Electron-hole spin qubit transistor and method of forming electron-hole spin qubit transistor

Abstract

The inventive concept relates to a spin qubit transistor including a base layer, a first qubit including a first operation semiconductor island and a first readout semiconductor island arranged at a distance in the range of 3-10 nm from each other, and a second qubit including a second operation semiconductor island and a second readout semiconductor island arranged at a distance in the range of 3-10 nm from each other, each of the semiconductor islands having a size that causes each of the semiconductor islands to exhibit single electron-hole three-dimensional quantum confinement, each of the semiconductor islands forming a heterojunction with the base layer. The first operation semiconductor island and the second operation semiconductor island are each configured to have a unique resonant frequency. The inventive concept further includes a method of forming a spin qubit transistor, and a quantum computer including at least one spin qubit transistor.

Description

[Technical field]

[0001] The inventive concepts described herein relate generally to spin qubit transistors and quantum computers. [Background technology]

[0002] The idea of ​​a quantum computer has been around since the dawn of today's classical computers. In a quantum computer, the classical bits of a computer are represented by qubits. Based on quantum physics, qubits can be in more than one state at a time. Traditional spin qubits are based on silicon qubits that use electrostatic confinement. (1-x) Ge (x) It is based on heterostructures such as GaAs / Ge or AlGaAs / GaAs. By applying a voltage to the gate electrode, a potential energy landscape is created using a two-dimensional electron gas (2DEG). There is still room for improvement in order to realize a quantum computer. Summary of the Invention

[0003] It is an object of the inventive concept to provide a spin qubit transistor suitable for scalability. It is a further object of the inventive concept to provide a quantum computer using a plurality of spin qubit transistors. These and other objects of the inventive concept are at least partly met by the invention as defined in the independent claims. Preferred embodiments are set out in the dependent claims.

[0004] In this specification, abbreviations for natural elements are used according to the periodic table, e.g., Al means aluminum, Ga means gallium, In means indium, N means nitrogen, and Si means silicon.

[0005] According to a first aspect, there is provided an electron-hole spin qubit transistor, comprising: A base layer; a first quantum bit including a first computing semiconductor island and a first readout semiconductor island spaced apart from each other by a distance in the range of 3 to 10 nm; a second quantum bit including a second computation semiconductor island and a second readout semiconductor island spaced apart from each other by a distance in the range of 3 to 10 nm; each of the semiconductor islands has a size that causes each of the semiconductor islands to exhibit three-dimensional quantum confinement of a single electron-hole, each of the semiconductor islands forming a heterojunction with the base layer; The spin qubit transistor further comprises: a support material disposed over each of the semiconductor islands to embed each semiconductor island; a source terminal electrically connected to the first operational semiconductor island through the supporting material; a drain terminal electrically connected to the second operational semiconductor island through the support material; a first gate terminal disposed above the first computational semiconductor island and configured to microwave modulate a spin state of the first computational semiconductor island; a second gate terminal disposed above the first readout semiconductor island and configured to read out a state of the first readout semiconductor island; a third gate terminal disposed above the second operational semiconductor island and configured to microwave modulate a spin state of the second operational semiconductor island; a fourth gate terminal disposed above the second readout semiconductor island and configured to read out a state of the second readout semiconductor island; A spin qubit transistor is provided, wherein a first operational semiconductor island and a second operational semiconductor island are configured to each have a unique resonant frequency.

[0006] It is recognized that the qubit may comprise a physical semiconductor island. Thus, the qubit may be realized without the use of a two-dimensional electron gas. The inventors have realized that it is advantageous to encode quantum information in the total angular momentum of the electron-hole qubit. Thus, the qubit may be a two-level qubit, singlet (S) and triplet (T), that physically comprises two semiconductor islands with a tunnel junction between them. In other words, the qubit may be in a singlet (0,2) or triplet (1,1) state. Thus, the first qubit comprises a first operation semiconductor island and a first readout semiconductor island with a tunnel junction between them. The second qubit comprises a second operation semiconductor island and a second readout semiconductor island with a tunnel junction between them. Qubits according to the present invention that comprise physical semiconductor islands have less crosstalk than qubits defined by a two-dimensional electron gas. It is noted that the spin qubit transistor may comprise more than two qubits. Thus, a spin qubit transistor may contain 2, 5, 10, 100, or even thousands of qubits. More than two qubits are sometimes called qudits or qudits. The use of qudits improves fidelity to the original. It is an advantage of the inventive concept that the number of qubits is scalable.

[0007] A qubit can be described as an electromagnetic resonator, typically with a size of 10 16 High quality factor and associated resonant frequency better than

[0008]

number

[0009] Resonant driving of a qubit involves a probability |α0| over time. 2 , |α1| 2This induces a sinusoidal oscillation of |S> (where α0, α1 are the coefficients of superposition of the two quantum states |0> back to |1>), called a Rabi oscillation. Resonance occurs when the frequency of the oscillating magnetic field is equal to the energy difference between the Zeeman energy levels of the qubit. The qubit has a spontaneous transition time from quantum state |S> back to |T>.

[0010] The semiconductor island according to the invention can be considered as an ideal isolated quantum mechanical one-level artificial atom. This follows from the fact that the semiconductor island is formed, for example, by strain relaxation during metalorganic vapor phase epitaxy (MOVPE). The inventors have in particular found that the double semiconductor island according to the invention has an energy difference ΔE>>k B They noticed that it can be constructed to behave as a two-level quantum singlet and triplet system with T. At room temperature, k B T is 0.0258 eV. This allows the qubit to be driven fast. In particular, it does not excite the qubit to the third or fourth quantum state. The size of the semiconductor island can be tuned to an excited state with ΔE>>kT. The inventors have realized that the double semiconductor island according to the present invention is advantageous for computing entangled states in quantum computers using electron-hole spin qubits.

[0011] Strong spin-orbit interaction promotes the quantization of the total angular momentum. In the present invention, the spin-orbit interaction is the interaction of magnetic fields that occurs, for example, when an atomic nucleus orbits around an unpaired electron to form a current loop. This generates a magnetic field. The energy shift of the quantum state, E SO ~Z 4 The energy contribution from the spin-orbit interaction, which gives the energy contribution, depends on the size of the nucleus. Larger atoms have a larger atomic number Z, and relativistic effects generally dictate that the magnetic field from the nucleus is larger the larger Z, and therefore the magnitude of the spin-orbit interaction.

[0012] According to the invention, it is advantageous to use wide band gap semiconductors. Thus, InN can be a good choice, since the band gap of the semiconductor island can be selected to be the highest for the potential energy well with GaN for electron holes. This allows the spin-orbit coupling of the semiconductor island to reach a maximum value for infinite potential well height (Scientific Reports, 2018, 8:7400, DOI:10.1038 / s41598-018-25692-2).

[0013] A single heavy electron hole in a semiconductor island forms the ground state, but the energy difference between the ground and excited states becomes large and separates according to the Schrödinger equation. Using holes as charge carriers in a semiconductor results in smaller errors than using electrons as charge carriers. Due to the small size of the semiconductor islands, excitation to levels higher than the Zeeman splitting can be neglected. Coulomb blockade provides a single positive charge or electron hole in each of the semiconductor islands. The self-capacitance of a semiconductor island charged with a single positive charge +e is given by Coulomb blockade theory as C=e 2 / ΔE, which in this case can be determined from the magnetic field strength B0.

[0014] The symmetry of the electron-hole ground state wave function is π-symmetric (not σ-symmetric) and the spin quantum number is 3 / 2. Electron qubits suffer from the trade-off between making a qubit with a long decoherence time with a slow gate time, or making a qubit with the fastest possible gate time with a short decoherence time. Electron qubits require weak spin-orbit coupling to achieve long decoherence times. Electron-hole qubits behave differently from electron qubits, providing long decoherence times through high drive speeds and high spin-orbit coupling. Therefore, it is an advantage of the present invention to use confined electron-holes. (Quantum Information (2021) 7:54; https: / / doi.org / 10.1038 / s41534-021-00386-2).

[0015] The base layer may comprise an alloy of AlGaN. (y) Ga (1-y) The base layer may comprise an alloy of InGaN. The base layer may comprise an alloy of InGaN. (z) Ga (1-z) N, where z>0 or z=0. The base layer may be disposed beneath each individual semiconductor island and only distributes laterally with respect to a single semiconductor island. The base layer may be disposed beneath a plurality of semiconductor islands. Thus, the base layer may be disposed beneath a pair of semiconductor islands configured into a qubit. The base layer may be disposed beneath a plurality of qubits. The base layer is configured to form a heterojunction with the semiconductor island. Thus, there is a strain in the surface between the base layer and the semiconductor island. The base layer may be a monolayer. The base layer may be a plurality of monolayers stacked on top of each other.

[0016] Operational semiconductor islands are defined as physical islands. By physical, it is understood that each of the semiconductor islands has a nanoscale miniaturized size that exhibits three-dimensional quantum confinement of a single electron hole. As such, the semiconductor islands are physically grown and are not held together by electrostatic means. Operational semiconductor islands are configured for a single electron hole. Thus, they are configured to have one single electron hole as a charge carrier.

[0017] The readout semiconductor island is defined as a physical island. By physical, it is understood that each of the semiconductor islands has a size that exhibits three-dimensional quantum confinement of a single electron-hole. As such, the semiconductor islands are physically grown and are not held together by electrostatic means. The readout semiconductor island is configured for a single electron-hole. Thus, it is configured to have one single electron-hole as a charge carrier.

[0018] The semiconductor islands can be interpreted as "quantum dots." Thus, the semiconductor islands can be configured as quantum dots that exhibit three-dimensional quantum confinement of a single electron-hole.

[0019] Spin blockade is used to configure a non-interacting state between each of the operation semiconductor islands and each of the readout semiconductor islands of one quantum bit. The Zeeman effect is used to split the electron-hole ground state at a magnetic field strength B0 and configure a deterministic excited state with a pre-known energy difference ΔE based on the magnetic field strength. The barrier between the multiple readout semiconductor islands may be significantly higher to prevent readout crosstalk. Each of the readout semiconductor islands with a second and fourth gate each can be used to read out the quantum state, (0,2) or (1,1), of each of the operation semiconductor islands.

[0020] In one embodiment, the computational and readout semiconductor islands may be cubes confined by a three-dimensional infinite potential energy well. Thus, according to the Schrödinger equation, the solution to the wave function is the eigenfunction:

[0021]

number

[0022] The energy levels are as follows:

[0023]

number

[0024] Here, E n is the energy of the quantum state, and n x , n y , n z is a quantum number, m h is the mass of the electron-hole and a is the cubic width of the potential energy well. Therefore, the ground state energy E1 of a GaN semiconductor island is given by the Schrödinger equation:

[0025] However, it should be understood that the potential energy well is not infinite. A GaN semiconductor island may be a cube of width 2b surrounded by AlGaN, with a potential energy barrier V0. (In practice, the GaN semiconductor island may be a cube of width 2b surrounded by AlGaN.) 0.20 Ga 0.80 The band gap of the AlGaN alloy composition is given by the formula E g (Al x Ga 1-x N) = xEg(AlN) + (1-x)E g (GaN). Therefore, the barrier height is V0 = E g (Al x Ga 1-x N)-E g Instead, the even-parity energy levels E n The solution to is given by:

[0026]

number

[0027] And the solution for the odd parity energy levels En is given by:

[0028]

number

[0029] Negative values ​​of energy are electron-hole bound states. With an AlN composition of 7.8%, the height of the potential energy barrier provided by the AlGaN alloy may be 0.2 eV, and the cube width of the GaN semiconductor island may be 2 nm, resulting in a ground state of -0.06 eV with even parity. The entanglement between the operational semiconductor islands is related to the tunneling probability or transition probability that may be constituted by the surrounding AlGaN alloy. Thus, the thickness of the surrounding AlGaN alloy may be 1 nm. Thus, the potential energy barrier V0 is 0.2 eV for a 1 nm thick AlGaN semiconductor island. 0.08 Ga 0.92 When N surrounds the GaN semiconductor island as a shell layer, it is 0.2 eV. The transition probability T is given by

[0030]

number

[0031] The transition probability can be configured to be 1% for ground state energies V0-E1<0.21 eV. An 80% transition probability occurs very close to the top of the finite potential energy barrier, i.e., ~0.5 meV from the top. The transition probability can be increased by applying a bias to the barrier electrodes, thereby lowering the potential energy barrier between the computing semiconductor islands. The tunneling probability between the computing and readout semiconductor islands can be similarly increased by forming an Al shell layer surrounding the GaN semiconductor islands. 0.08 Ga 0.92 N, it can be configured to be 1% in the ground state. A fractional occupancy of |S> back to |T>, say 99%, is sufficient to correlate the electron-holes to provide an entangled quantum state between qubits.

[0032] In one embodiment, the spin qubit transistor can include a barrier electrode disposed between and above the computation semiconductor island and the readout semiconductor island to reduce the height of the effective potential energy barrier.

[0033] The source is disposed in ohmic contact with the first qubit through the support material.

[0034] The electrical contact between the source terminal and the first operational semiconductor island through the supporting material may be a tunnel contact.

[0035] The drain is disposed in ohmic contact with the second qubit through the support material.

[0036] The electrical contact between the drain terminal and the second operational semiconductor island through the supporting material may be a tunnel contact.

[0037] The effect of the transistor is that one hole moves from source to drain with a measurable average current.

[0038] The first and third gate terminals are configured to modulate the first and second computation semiconductor islands, respectively. Thus, the first and third gate terminals are configured to change the quantum state of the computation semiconductor islands. The modulation by the first and third gates induces a rotation of the spin of each of the first and second computation quantum dots. The effect of the transistor is that one hole moves from the source to the drain with a measurable average current. The modulation applied to the first and third gates is to flip the total angular momentum from |T> to |S>. This spin rotation removes the spin blockade constraint. Thus, the electron-hole can tunnel from the first computation semiconductor island to the second computation semiconductor island. As a result, the (0,2) state collapses by emitting the electron-hole to the drain, and the hole from the source is continuously fed back to the first computation semiconductor island restoring the initial spin blockade in the (1,1) charge configuration.

[0039] The first and third gates are disposed on top of the first and second computing semiconductor islands. By top, it is noted that the first and third gates are disposed on the support material at locations relative to the respective locations of the first and second computing semiconductor islands. Thus, the first gate is disposed such that it can modulate the first computing semiconductor island. The third gate is disposed such that it can modulate the second computing semiconductor island.

[0040] The first and third gates are configured to modulate each of the operational semiconductor islands. Under resonant microwave modulation, the qubit state undergoes so-called Rabi oscillations, where the probability |α0| 2 , |α1| 2 varies sinusoidally with time. Consider a semiconductor island with an energy splitting ΔE between E1 and E2. We perturb the energy with a frequency

[0041]

number

[0042] This is done by microwave modulation applied to the first or third gate. For example, if the quantum state is |T> in each of the computation semiconductor islands, a short perturbation with microwave power will produce a small amplitude and become |S>. If the power is continued, the quantum state will be fully transferred to |S>, called a π pulse. According to the present invention, this operation flips each of the readout semiconductor islands. The readout of the first and second readout transistor islands is performed by the second and fourth gates. It is widely understood that quantum operations can be realized using a combination of CNOT quantum gates and single qubit rotation CROT. CNOT gates operate on quantum registers consisting of two qubits. The classical computational analogue of the CNOT gate is the reversible XOR gate. The controlled CNOT gate flips the readout semiconductor island only if the respective computation transistor island is in state |S>, as mentioned above. Similarly, the CROT gate is equivalent to the CNOT gate, except that the spins rotate by π / 2 around the z axis.

[0043] A support material embeds each of the semiconductor islands. The support material may be a material configured to be a charge carrier for electron holes. Thus, the support material may be a p-doped material or, in some embodiments, p-doped GaN. The support material may be a dielectric material. The support material may be configured for heavy electron holes. Heavy electron hole states are ideal for qubits because the total angular momentum of different qubits can be coupled over large distances by tunneling through a linear or 2D array of semiconductor islands. The electron hole spins are related in quantum mechanics by the total angular momentum operator J 2In accordance with the present invention, a single heavy electron-hole quantum state can be constructed by separating the light hole subband from the heavy electron-hole subband that provides a pure heavy electron-hole state, where the lowest energy state at k=0 of the wave vector is the heavy electron-hole quantum state. The heavy electron-hole quantum state can be determined by the physical size of the semiconductor island, e.g., 1-10 nm, and the size of the p-Al as the hole reservoir. (y) Ga (1-y) GaN strained by N underlayer or p-In as hole reservoir (Z) Ga (1-z) By straining the InN with an underlayer of N, the semiconductor island can be configured with a single heavy electron-hole state, i.e., without an external magnetic field, which can be achieved with greater confinement, allowing for longer hole spin relaxation times.

[0044] According to electric dipole spin resonance (EDSR), the effective mass m * and the g-factor is estimated as follows:

[0045]

number

[0046] and,

[0047]

number

[0048] The g-factor of InAs / GaAs quantum dots is described in G. Medeiros-Ribeiro et al. Appl. Phys. A (2003) as follows:

[0049]

number

[0050] The g-factor approaches 1.9 for both bulk InN and bulk GaN. Therefore, according to the invention, it is advantageous that the quantum dots are defined by a heterojunction of aluminum gallium nitride (AlGaN) and gallium nitride (GaN). The size and strain of the quantum dots are used to set the Rabi frequency.

[0051] Note that due to its unique resonant frequency, each computing semiconductor island has a unique frequency. The frequency of a computing semiconductor island is not shared with other computing semiconductor islands or other readout semiconductor islands. Note that two computing semiconductor islands can have the same frequency if they are separated by a sufficient distance that they do not interfere with each other.

[0052] Each semiconductor island is made of Al (x) Ga (1-x) Each operational semiconductor island may include a unique AlN alloy, where 1>x>0. (x) Ga (1-x) Thus, each operational semiconductor island may contain a unique AlN alloy that is not shared with other semiconductor islands. (x) Ga (1-x) It may contain N. (x) Ga (1-x) The N alloy is configured to provide the frequency to the semiconductor island. (x) Ga (1-x) The N alloy provides a computational semiconductor island with the unique resonant frequency. (y) Ga (1-y) N (where 1>y≧0). Thus, the base layer may be GaN or Al (y) Ga (1-y) It may be any alloy of N.

[0053] Each semiconductor island is made of In (z) Ga (1-z)Each operational semiconductor island may comprise a unique InN alloy, where 1>z>0. (z) Ga (1-z) Thus, each operational semiconductor island may contain a unique InN alloy that is not shared with other semiconductor islands. (z) Ga (1-z) N may be included. (z) Ga (1-z) The N alloy is configured to provide a frequency to the semiconductor island. (z) Ga (1-z) The N alloy provides a computational semiconductor island with the unique resonant frequency. (z) Ga (1-z) N (where 1>z≧0). Thus, the base layer may be InN or In (z) Ga (1-z) It may be any alloy of N.

[0054] Each semiconductor island is made of Al (x) Ga (1-x) The semiconductor may include a lower region comprising an N-alloy and an upper region comprising GaN. The base layer may be GaN and a heterojunction is formed at an interface between the lower region and the base layer.

[0055] Each semiconductor island is made of In (z) Ga (1-z) The semiconductor may include a lower region comprising an InN alloy and an upper region comprising InN. The base layer may be InN and a heterojunction is formed at an interface between the lower region and the base layer.

[0056] Each semiconductor island may have a unique size, resulting in a computing semiconductor island with a unique resonant frequency. Thus, the size of the semiconductor island may be decisive for the frequency.

[0057] The semiconductor islands are formed by epitaxial growth and can exhibit three-dimensional quantum confinement. Strain in the semiconductor islands can be formed during the growth of the GaN semiconductor islands, for example by selective area growth. The distance between the quantum dots can be controlled using selective area growth by nano-sized holes in a hard mask such as SiO2, Al2O3 or Si3N4. Thus, the epitaxial growth can be selective area growth. This allows the formation of semiconductor islands during pattern-controlled epitaxial growth, with short but extremely rapid growth on the order of 10 seconds. A 0-dimensional hole gas (0DHG) is formed within the quantum dots. The thickness of the AlGaN underlayer can be significantly thicker to reduce the Coulomb interaction of electrons and holes. In another embodiment of the invention, the AlGaN semiconductor islands are grown on GaN. Selective area growth for quantum dot formation is described in the literature Birudavolu, S. et al., Selective area growth of InAs quantum dots formed on a patterned GaAs substrate. Applied Physics Letters, 2004, 85, 2337-2339, the contents of which are incorporated herein by reference. Undoped GaN semiconductor islands that can be formed on InGaN are negatively polarized by strain. The semiconductor islands can be formed by Stranski-Krastanow growth.

[0058] Each of the semiconductor islands may be composed of a material having a wurtzite crystal structure. (z) Ga (1-z) N and Al (x) Ga (1-x)N has a wurtzite crystal structure that is not centrosymmetric; therefore, it lacks inversion symmetry. The quantum bits of electrons in these alloys are subject to piezoelectric phonons that cause incoherence. Symmetry breaking or inversion symmetry breaking can be brought about by straining the quantum dots in the heterostructure, splitting the valence band into light and heavy electron holes. The gate can be pulsed with microwave modulation, which reduces the tunnel barrier between two neighboring quantum dots. The coherence time of the quantum state must be longer than:

[0059]

number

[0060] Each of the computation semiconductor island and the readout semiconductor island may be disposed with a distance between them in the range of 3 to 10 nm. The semiconductor islands may be disposed in a plane parallel to the base layer. The semiconductor islands may be spaced apart from each other in said plane parallel to the base layer. The semiconductor islands may be disposed laterally with respect to each other.

[0061] The operation semiconductor island and readout semiconductor island of each quantum bit may each be arranged and positioned such that an electron-hole may be excited from the operation semiconductor island to the readout semiconductor island in each quantum bit.

[0062] The first qubit and the second qubit may be arranged and positioned to be entangled. The first operation semiconductor island and the second operation semiconductor island may be arranged and positioned to be entangled. The first qubit and the second qubit may be arranged such that the electron-hole spins of each of the operation semiconductor islands are entangled. It should be understood that in embodiments including more than two qubits, all of the qubits are entangled. The inventors have (1-z) Ga (z) N and its alloys, or Al (1-x) Ga(x) They have found that double semiconductor islands, or qubits, formed in N and its alloys are advantageous for computationally entangled states in quantum computers that use electron-hole spin qubits.

[0063] The first gate terminal may be configured to excite an electron hole to transition the first quantum bit from a singlet state to a triplet state. The first gate terminal may be configured to electrostatically excite an electron hole to transition the first quantum bit from a singlet state to a triplet state. The first gate may be configured to microwave modulate a spin state of a first operational semiconductor island of the first quantum bit. The first gate may be in ohmic contact with the base layer. The third gate terminal is configured to excite an electron hole to transition the first quantum bit from a singlet state to a triplet state. The third gate terminal is configured to electrostatically excite an electron hole to transition the second quantum bit from a singlet state to a triplet state. The third gate may be configured to microwave modulate a spin state of a second operational semiconductor island of the first quantum bit. The third gate may be in ohmic contact with the base layer. The coherence time of the quantum state is

[0064]

number

[0065] must be longer. The gates can be pulsed with microwave modulation which reduces the tunnel barrier between two adjacent computing semiconductor islands. The microwave modulation applied to the first and third gates is used to rotate the spin of the quantum dot. That is, a radio frequency electric field can be applied to the electrodes. The microwave modulation can be in bursts of time τ_burst. The flipping from |S> state to |T> state is the photoelectric effect

[0066]

number

[0067] This can be achieved by controlling the envelope amplitude and pulse duration of the microwave resonator gate, which when energized according to

[0068] The spin qubit transistor may further include a control electrode arrangement configured to modify a tunneling characteristic between the first and second computation semiconductor islands. Alternatively, the spin qubit transistor may further include a control electrode arrangement configured to modify a tunneling probability between the first and second computation semiconductor islands. The control electrode arrangement may be arranged in a same plane parallel to a plane of the semiconductor island in which the first, second, third and fourth gates are arranged. The control electrode arrangement may be arranged between the first and third gates. The control electrode arrangement may be configured to modify a region of material between the first and second computation semiconductor islands. The control electrode arrangement may be configured to reduce a potential barrier between the computation semiconductor islands. The region of material may be of the same material as the support material. The region may be a barrier region of a different material. The region may be an n-doped barrier region.

[0069] The spin qubit transistor may further include a control electrode arrangement configured to modify a tunneling characteristic between the first computation semiconductor island and the first readout semiconductor island. The control electrode arrangement may be disposed between the first gate and the second gate. The spin qubit transistor may further include a control electrode arrangement configured to modify a tunneling characteristic between the second computation semiconductor island and the second readout semiconductor island. The control electrode arrangement may be disposed between the third gate and the fourth gate. Alternatively, the spin qubit transistor may further include a control electrode arrangement configured to modify a tunneling probability between the first computation semiconductor island and the first readout semiconductor island. Alternatively, the spin qubit transistor may further include a control electrode arrangement configured to modify a tunneling probability between the second computation semiconductor island and the second readout semiconductor island. The control electrode arrangement may be disposed in the same plane parallel to the plane of the semiconductor island in which the first, second, third and fourth gates are disposed. The control electrode arrangement may be configured to modify an area of ​​material between the first computation semiconductor island and the first readout semiconductor island. The control electrode arrangement may be configured to modify a region of material between the second computational semiconductor island and the second readout semiconductor island. The control electrode arrangement may be configured to reduce a potential barrier between each of the computational semiconductor island and the readout semiconductor island. The region of material may be of the same material as the support material. The region may be a barrier region of a different material. The region may be an n-doped barrier region.

[0070] The support material may be p-doped GaN, and therefore may act as a hole reservoir for the semiconductor islands.

[0071] The support material may be a dielectric material.

[0072] The band structure of the semiconductor islands, including the computation and readout semiconductor islands, is configured to have a heavy electron hole at the origin of k-space by the composition of the base layer.

[0073] Another aspect of the inventive concept is forming a hard mask layer on the base layer; forming a first plurality of nano-sized cavities in the hard mask layer; exposing the base layer to a semiconductor reactant species to form a first plurality of operational semiconductor islands within the first plurality of nano-sized cavities; forming a second plurality of nano-sized cavities in the hard mask layer; exposing the base layer to a semiconductor reactant species to form a second plurality of operational semiconductor islands within the second plurality of nano-sized cavities; forming a third plurality of nano-sized cavities in the hard mask layer; within the third plurality of nano-sized cavities; a plurality of first readout semiconductor islands, each of which is disposed within a distance in a range of 3 to 10 nm from each of the plurality of first computation semiconductor islands; exposing the base layer to a semiconductor reactive species to form a plurality of second readout semiconductor islands, each of the second readout semiconductor islands being located within a distance in a range of 3-10 nm from each of the plurality of second computation semiconductor islands; removing the hard mask layer by wet etching or plasma etching; embedding the formed plurality of first computing semiconductor islands, the formed plurality of second computing semiconductor islands, and the formed plurality of first and second readout semiconductor islands in a support material laterally coated over the semiconductor islands; forming at least one source terminal electrically connecting with the plurality of first operational semiconductor islands through the support material; forming at least one drain terminal electrically connecting with the plurality of second operational semiconductor islands through the support material; forming a plurality of first gate terminals disposed above each of the plurality of first operational semiconductor islands, the first gate terminals configured to microwave modulate a spin state of each of the plurality of first operational semiconductor islands; forming a plurality of second gate terminals disposed above each of the plurality of first readout semiconductor islands, the second gate terminals configured to read out a state of each of the plurality of first readout semiconductor islands; forming a plurality of third gate terminals disposed above each of the plurality of second operational semiconductor islands configured to microwave modulate a spin state of each of the plurality of second operational semiconductor islands; and forming a plurality of fourth gate terminals disposed above each of the plurality of second readout semiconductor islands, the fourth gate terminals configured to read out a state of each of the plurality of second readout semiconductor islands.

[0074] It should be understood that there may be further optional steps between the steps of the method.

[0075] The present method provides a method for forming a spin qubit transistor. The method allows for the formation of three-dimensional semiconductor islands, such as physically determined semiconductor islands. The method allows for the formation of computing semiconductor islands made of unique alloys to give unique frequencies.

[0076] The distance between the first computational semiconductor islands may be between 5 and 15 nm.The distance between the second computational semiconductor islands may be between 5 and 15 nm.The semiconductor reactive species forming the first computational semiconductor islands may be a different alloy than the semiconductor reactive species forming the second computational semiconductor islands.

[0077] The method may include the additional step of forming a hard mask layer over the first and second semiconductor islands, respectively, prior to forming the second and third pluralities of nano-sized cavities.

[0078] The first and second operational semiconductor islands may be configured to be lattice-mismatched to the base layer to provide a Rabi frequency, such that the semiconductor reactive species may induce strain in the base layer.

[0079] The plurality of first computing semiconductor islands, the plurality of second computing semiconductor islands, and the plurality of readout semiconductor islands may form a matrix of quantum bits. Thus, the plurality of first computing semiconductor islands, the plurality of second computing semiconductor islands, and the plurality of readout semiconductor islands may form a qudit. Thus, the method may be used in the fabrication of large quantum computers.

[0080] The method may further include forming a cap layer on each of the plurality of first operational semiconductor islands and on each of the plurality of second operational semiconductor islands to form a heterostructure, whereby each of the first operational semiconductor islands and the second semiconductor islands may include two alloys.

[0081] Alternatively, a third aspect of the inventive concept comprises: Providing a layer structure including multiple semiconductor layers, each of a unique material / alloy, stacked together; forming a first hard mask layer over the plurality of semiconductor layers; forming a first plurality of nano-sized cavities through the first hard mask layer and extending to a first layer of the plurality of semiconductor layers at a first depth; exposing the layer structure to a first semiconductor reactive species to form a first plurality of operational semiconductor islands within the first plurality of nano-sized cavities; forming a second hard mask layer over the plurality of semiconductor layers; forming a second plurality of nano-sized cavities through the second hard mask layer and extending to a second one of the plurality of semiconductor layers at a second depth; exposing the layer structure to a second semiconductor reactant species to form a second plurality of operational semiconductor islands within the second plurality of nano-sized cavities; forming a third hard mask layer over the plurality of semiconductor layers; forming a third plurality of nano-sized cavities through the third hard mask layer and extending to a third one of the plurality of semiconductor layers at a third depth; exposing the layer structure to a third semiconductor reactive species to form a plurality of first and second readout semiconductor islands within a third plurality of nano-sized cavities; the first, second and third depths vary through at least one of the semiconductor layers; removing all of the hard mask layer by wet etching or plasma etching; embedding the formed plurality of first computing semiconductor islands, the formed plurality of second computing semiconductor islands, and the formed plurality of first and second readout semiconductor islands in a support material laterally coated over the semiconductor islands; forming at least one source terminal electrically connecting with the plurality of first operational semiconductor islands through the support material; forming at least one drain terminal electrically connecting with the plurality of second operational semiconductor islands through the support material; forming a plurality of first gate terminals disposed above each of the plurality of first operational semiconductor islands, the first gate terminals configured to microwave modulate a spin state of each of the plurality of first operational semiconductor islands; forming a plurality of second gate terminals disposed above each of the plurality of first readout semiconductor islands, the second gate terminals configured to read out a state of each of the plurality of first readout semiconductor islands; forming a plurality of third gate terminals disposed above each of the plurality of second operational semiconductor islands configured to microwave modulate a spin state of each of the plurality of second operational semiconductor islands; and forming a plurality of fourth gate terminals disposed above each of the plurality of second readout semiconductor islands, the fourth gate terminals configured to read out a state of each of the plurality of second readout semiconductor islands.

[0082] It is understood that the step of removing all of the hardmask layer by wet or plasma etching may be performed as a single step or alternatively as several steps throughout the disclosed method, and such multiple steps of removing hardmask layers may be performed at various stages of the disclosed method, as will be understood by those skilled in the art.

[0083] Thus, in accordance with a third aspect of the inventive concept, the unique frequency of each of the operational semiconductor islands is determined by the unique depth of the semiconductor island.

[0084] A fourth aspect of the inventive concept is a quantum computer including at least one spin qubit transistor according to the above. The computer may include a plurality of spin qubit transistors. Each spin qubit transistor of the quantum computer may include a plurality of qubits according to the above. The inventors are Al (1-x) Ga (x) N, or In (1-x) Ga (x) They found that double semiconductor islands formed in N and its alloys are favorable for computational entanglement of quantum computers using electron-hole spin qubits. Qubit processors with N qubits may be used. Parallelization of multiple N qubit processors on the same chip is also possible. Scaling quantum computers requires a physically recognized method of long-range coupling between qubits.

[0085] A feature described in relation to one embodiment may be incorporated into other embodiments, and the advantages of that feature apply to all embodiments in which it is incorporated.

[0086] Other objects, features and advantages of the inventive concepts will become apparent from the following detailed disclosure, the appended claims and the drawings.

[0087] In general, all terms used in the claims are to be interpreted according to their ordinary meaning in the art unless expressly defined otherwise herein. Moreover, the use of terms such as "first," "second," "third," etc. herein does not denote any order, quantity, or importance, but rather is used to distinguish one element from other elements. All references to "a / an / the [element, device, component, means, step, etc.]" shall be construed straightforwardly as referring to at least one instance of that element, device, component, means, step, etc., unless expressly stated otherwise. The steps of the methods disclosed herein do not have to be performed in the exact order disclosed, unless expressly stated otherwise.

[0088] The above, as well as additional objects, features and advantages of the inventive concept will be better understood through the following illustrative and non-limiting detailed description of the inventive concept, taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0089] [Figure 1] FIG. 1 is a cross-sectional view of a spin qubit transistor. [Diagram 2] FIG. 2 is a top cross-sectional view of a spin qubit transistor. [Figure 3A] FIG. 3A is a cross-sectional side view of a spin qubit transistor. [Figure 3B] FIG. 3B is a cross-sectional side view of a spin qubit transistor. [Figure 4A] FIG. 4A is a cross-sectional view of a spin qubit transistor. [Figure 4B] FIG. 4B is a cross-sectional view of a spin qubit transistor. [Diagram 5]FIG. 5 is a top cross-sectional view showing multiple spin qubit transistors, or qudits. [Figure 6] FIG. 6 is a diagram illustrating a method for forming a spin qubit transistor. [Figure 7A] FIG. 7A is a cross-sectional view showing a spin qubit transistor formed by the method of FIG. [Figure 7B] FIG. 7B is a top cross-sectional view showing multiple spin qubit transistors fabricated according to the method of FIG. [Figure 8] FIG. 8 illustrates an alternative method of forming a spin qubit transistor. [Figure 9A] FIG. 9A is a cross-sectional view showing a spin qubit transistor fabricated by the method of FIG. [Figure 9B] FIG. 9B is a cross-sectional view of a spin qubit transistor fabricated by the method of FIG. [Figure 10A] FIG. 10A is a diagram showing triplet states of a quantum bit. [Figure 10B] FIG. 10B is a diagram showing the singlet state of a quantum bit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0090] The figures are not necessarily to scale and generally show only those parts necessary to clarify the inventive concept, with other parts omitted or merely suggested.

[0091] Hereinafter, the technical contents and detailed description of the present invention will be described according to preferred embodiments in conjunction with the accompanying drawings, but are not used to limit the scope of the claims. The present invention can be embodied in many different forms and should not be construed as being limited to the embodiments described herein, but rather, these embodiments are provided for completeness and completeness, and to fully convey the scope of the present invention to those skilled in the art.

[0092] FIG 1 illustrates a cross-sectional view of an electron-hole spin qubit transistor 100. The illustrated spin qubit transistor 100 includes a first qubit 103 and a second qubit 105. The first qubit 103 includes a first operation semiconductor island 106. The first qubit 103 further includes a first readout semiconductor island 108 (not shown in FIG 1). The second qubit 105 includes a second semiconductor island 110. The second qubit 105 further includes a second readout semiconductor island 112 (not shown in FIG 1). The first operation semiconductor island 106 and the second operation semiconductor island 110 are each configured to have a unique resonant frequency.

[0093] The semiconductor islands 106, 108, 110, 112 have a size that causes each of the semiconductor islands 106, 108, 110, 112 to exhibit three-dimensional quantum confinement of a single electron-hole. Thus, each semiconductor island has a size that accommodates only one electron-hole. The semiconductor islands 106, 108, 110, 112 have dimensions of 4 nm. The semiconductor islands 106, 108, 110, 112 are made of Al (x) Ga (1-x) Each of the operational semiconductor islands 106, 108 may include a unique Al (x) Ga (1-x) Each of the semiconductor islands 106, 108 may include an InN alloy. (z) Ga (1-z) Each operational semiconductor island 106, 108 may include a unique InN alloy, where 1>z>0. (z) Ga (1-z) Thus, each operational semiconductor island 106, 108 may include a unique InN alloy. (z) Ga (1-z) The first computing semiconductor island 106 is entangled with the second computing semiconductor island 110. The computing semiconductor island 106 may have a N alloy, such that each computing semiconductor island 106, 108 has the unique resonant frequency.

[0094] The semiconductor islands 106, 108, 110, 112 are epitaxially grown on top of the base layer 102. The semiconductor islands 106, 108, 110, 112 have an axial direction perpendicular to the base layer 102. Each of the semiconductor islands 106, 108, 110, 112 forms a heterojunction with the base layer 102. The base layer 102 is illustrated as if it were a single entity, underlining the entire spin qubit transistor 100. However, the base layer 102 may be disposed only beneath each of the semiconductor islands 106, 108, 110, 112. The epitaxial growth of the semiconductor islands 106, 108, 110, 112 on the base layer 102 creates the strain between the materials necessary to form electron-holes. The base layer 102 is made of Al (y) Ga (1-y) N (where 1>y≧0). The base layer 102 may include In (z) Ga (1-z) N (where 1>z≧0).

[0095] The spin qubit transistor 100 further includes a support material 116. The support material 116 is disposed on top of and embeds each of the semiconductor islands 106, 108, 110, 112. The support material may be p-doped, thereby acting as a hole reservoir for the semiconductor islands 106, 108, 110, 112. Additionally, the support material 116 may be Al (y) Ga (1-y) It may also contain N. The support material 116 may be a dielectric material.

[0096] 1, the spin qubit transistor 100 further includes a source terminal S. The source terminal S is electrically connected to the first operational semiconductor island 106 through the support material 116. This electrical connection may be a tunnel connection. Additionally, the spin qubit transistor 100 includes a drain terminal D. The drain terminal D is electrically connected to the second operational semiconductor island 110 through the support material 116. This electrical connection may be a tunnel connection. The effect of the transistor is that one hole moves from the source S to the drain D with a measurable average current.

[0097] The spin qubit transistor 100 further includes a first gate terminal G1, a second gate terminal G2 (not shown in FIG. 1), a third gate terminal G3, and a fourth gate terminal G4 (not shown in FIG. 1). The first gate terminal G1 is disposed above the first operation semiconductor island 106. The first gate terminal G1 is configured for microwave modulation of the spin state of the first operation semiconductor island 106. The second gate terminal G2 is disposed above the first readout semiconductor island 108. The second gate terminal G2 is configured for readout of the quantum state of the first readout semiconductor island 108. The third gate terminal G3 is disposed above the second operation semiconductor island 110. The third gate terminal G3 is configured for microwave modulation of the spin state of the second operation semiconductor island 110. The fourth gate terminal G4 is disposed above the second readout semiconductor island 112. The fourth gate terminal G4 is configured for reading out the state of the second readout semiconductor island 112.

[0098] The first gate terminal G1 may be configured to excite an electron-hole to transition the first qubit 103 from a singlet state to a triplet state. The state of the first qubit 103 is read out by a second gate G2. The electron-hole may tunnel to the second qubit 105. The electron-hole from the second qubit 105 may tunnel to the drain.

[0099] The spin qubit transistor may further include a control electrode arrangement B. The control electrode arrangement B is configured to modify the tunneling characteristics between the first computing semiconductor island 106 and the second computing semiconductor island 110. Alternatively, the control electrode arrangement B is configured to modify the tunneling probability between the first computing semiconductor island 106 and the second computing semiconductor island 110. The control electrode arrangement B may be arranged between the first gate G1 and the third gate G3. The control electrode arrangement B may be configured to modify the region of material 114 between the first computing semiconductor island 106 and the second computing semiconductor island 110. The region of material 114 may be of the same material as the support material 116. The region of material 114 may be a barrier region of a different material. The region of material 114 may be an n-doped barrier region.

[0100] 2, a cross-sectional view of the spin qubit transistor 100 is shown from above. Many features are common to those in FIG. 1 and will not be repeated for the sake of brevity.

[0101] In Fig. 2 one can see the arrangement of the first readout semiconductor island 108 relative to the first computing semiconductor island 106. The first computing semiconductor island 106 and the first readout semiconductor island 108 are arranged laterally along an axis A. The distance between the first computing semiconductor island 106 and the first readout semiconductor island 108 is between 3 and 10 nm. The same arrangement is valid for the second semiconductor island 110 and the second readout semiconductor island 112, which are arranged laterally along an axis B. The distance between the axis A and the axis B can vary between 10 and 50 nm.

[0102] Viewed from above, it can be seen that the first, second, third and fourth gates G1, G2, G3, G4 are disposed on top of the first computation semiconductor island 106, the first readout semiconductor island 108, the second computation semiconductor island 110 and the second readout semiconductor island 112, respectively.

[0103] The control electrode arrangement B may be located between the first gate G1 and the third gate G3, and between the second gate G2 and the fourth gate G4.

[0104] Figures 3A and 3B show cross-sectional views of a spin qubit transistor from two opposing sides, many of whose features are common to those of Figures 1 and 2 and will not be repeated for the sake of brevity.

[0105] In FIG. 3A, the arrangement of the first computing semiconductor island 106 with respect to the first gate G1, the first readout semiconductor island 108, and the second gate G2 can be seen. The first gate G1 is disposed vertically above the first computing semiconductor island 106. The second gate G2 is disposed vertically above the first readout semiconductor island 108. In FIG. 3B, the arrangement of the second computing semiconductor island 110 with respect to the third gate G3, the second readout semiconductor island 112, and the fourth gate G4 can be seen. The third gate G3 is disposed vertically above the second computing semiconductor island 110. The fourth gate G4 is disposed vertically above the second readout semiconductor island 112. The gates G1, G2, G3, G4 are electrically connected to the semiconductor islands 106, 108, 110, 112, respectively, via the support material 116.

[0106] 4A and 4B, a cross-sectional side view of spin qubit transistor 100 is shown. Many features are common to those of FIG. 1 and will not be repeated for the sake of brevity.

[0107] 4A, the operational semiconductor islands 106, 110 have a capping layer 120. The capping layer 120 may cover a portion of the operational semiconductor islands 106, 110. The capping layer 120 may be Al (y) Ga (1-y) It may contain N.

[0108] 4B, the operational semiconductor islands 106, 110 have a shell layer 122. The shell layer 122 may cover the entire semiconductor islands 106, 110. The shell layer 122 may be made of Al (y) Ga (1-y) It may contain N.

[0109] The capping layer 120 or shell layer 122 may also be applied to the readout semiconductor islands 108, 112. The capping layer 120 or shell layer 122 as shown in Figures 4A and 4B may be used with any of the embodiments described herein, such as the embodiments of Figures 1, 2, 3A-3B, 5, 6, 7A-7B, 8, and 9A-9B.

[0110] 5, there is shown from above 16 pairs of first qubits 103 and second qubits 105 forming a qudit 118. As described with reference to Figures 1 to 4, the qudit 118 includes a number of spin qubit transistors.

[0111] A method 1000 for forming a spin qubit transistor 100 in accordance with the inventive concepts will now be described with reference to Figures 6, 7A and 7B. For clarity and brevity, the method will be described in terms of "steps", which are not necessarily processes that are separated in time or from one another, with the emphasis being that multiple "steps" may be performed simultaneously in parallel.

[0112] A method 1000 for forming an electron-hole spin qubit transistor 100 includes: Step 1001 of forming a hard mask layer 202 on a base layer 102; forming 1003 a first plurality of nano-sized cavities 204 in the hard mask layer 202; exposing 1005 the base layer 102 to a semiconductor reactive species to form a plurality of first operational semiconductor islands 106 within the first plurality of nano-sized cavities 204; forming 1007 a second plurality of nano-sized cavities 206 in the hard mask layer 202; exposing 1009 the base layer 102 to a semiconductor reactant species to form a plurality of second operational semiconductor islands 110 within the second plurality of nano-sized cavities 206; forming 1011 a third plurality of nano-sized cavities 208 in the hard mask layer 202; Within the third plurality of nano-sized cavities 208, a plurality of first readout semiconductor islands, each of which is disposed within a distance in a range of 3 to 10 nm from each of the plurality of first computation semiconductor islands; a step 1013 of exposing the base layer 102 to a semiconductor reactive species to form a plurality of second readout semiconductor islands, each of which is located within a distance in the range of 3 to 10 nm from each of the plurality of second computation semiconductor islands; A step 1015 of removing the hard mask layer by wet etching or plasma etching; and a step 1017 of embedding the formed first plurality of computing semiconductor islands, the formed second plurality of computing semiconductor islands, and the formed first and second plurality of readout semiconductor islands in a support material 116 laterally coated on the semiconductor islands; forming 1019 at least one source terminal S electrically connecting with the plurality of first operational semiconductor islands through the support material 116; forming 1021 at least one drain terminal D electrically connecting with the plurality of second operational semiconductor islands through the support material 116; forming 1023 a plurality of first gate terminals G1 disposed above each of the plurality of first operational semiconductor islands, the first gate terminals G1 being configured to microwave modulate a spin state of each of the plurality of first operational semiconductor islands; forming 1025 a plurality of second gate terminals G2 arranged above each of the plurality of first readout semiconductor islands, the second gate terminals G2 being configured to read out a state of each of the plurality of first readout semiconductor islands; forming 1027 a plurality of third gate terminals G3 disposed above each of the plurality of second operational semiconductor islands, the third gate terminals G3 being configured to microwave modulate a spin state of each of the plurality of second operational semiconductor islands; and forming 1029 a plurality of fourth gate terminals G4 disposed above each of the plurality of second readout semiconductor islands configured to read out a state of each of the plurality of second readout semiconductor islands.

[0113] In step 1001, a hard mask 202 is formed on the base layer 102. In step 1003, the hard mask further comprises a first plurality of nano-sized cavities 204. The plurality of nano-sized cavities may be made by etching.

[0114] In step 1005 of the method 1000, a plurality of first computing semiconductor islands 106 are formed by exposing the base layer 102 to a first semiconductor reactive species through the hard mask 202. The number of first computing semiconductor islands 106 formed may be at least two, such as 10, 50, 100, 1000, etc. As seen in FIG. 7B, the plurality of first computing semiconductor islands are arranged at a distance from each other. This distance may be selected so that two of the plurality of first computing semiconductor islands having the same frequency do not disturb or interfere with each other.

[0115] In step 1007, a second plurality of nano-sized cavities 206 is formed. The plurality of nano-sized cavities can be created by etching.

[0116] In step 1009, a plurality of second computing semiconductor islands 110 are formed by exposing the base layer 102 to a second semiconductor reactive species through the hard mask 202. The number of second computing semiconductor islands 110 formed may be at least two, such as 10, 50, 100, 1000, etc. As seen in FIG. 7B, the plurality of second computing semiconductor islands are spaced apart from each other. This distance may be selected so that two of the plurality of second computing semiconductor islands having the same frequency do not disturb or interfere with each other.

[0117] The first and second semiconductor reactants are different from each other. The number of second operational semiconductor islands 110 is equal to the number of first operational semiconductor islands 106.

[0118] In step 1013, a plurality of first and second readout semiconductor islands 108, 112 are formed by exposing the base layer 102 through the hard mask 202 to a third semiconductor reactant.

[0119] The first, second and third semiconductor reactive species are different from each other. The first and second readout semiconductor islands 108, 112 may each be fabricated with two different semiconductor reactive species. When the first and second readout semiconductor islands 108, 112 are fabricated with different semiconductor reactive species, they may be fabricated in two different steps.

[0120] The number of first and second computing semiconductor islands 106, 110 is equal to the number of first and second readout semiconductor islands 108, 112, respectively. The first readout semiconductor island 108 is paired with the first computing semiconductor island 106. The second readout semiconductor island 112 is paired with the second computing semiconductor island 110.

[0121] The first plurality of operational semiconductor islands 106 and the second plurality of operational semiconductor islands 110 may be configured to be lattice-mismatched to the base layer 102 to provide the Rabi frequency.

[0122] The plurality of first computation semiconductor islands 106, the plurality of second computation semiconductor islands 110, and the plurality of readout semiconductor islands 108, 112 form a matrix of quantum bits.

[0123] The method may further include a step 1031 of forming a cap layer on each of the plurality of first operational semiconductor islands 106 and on each of the plurality of second operational semiconductor islands 110 to form a heterostructure.

[0124] With reference to FIGS. 8, 9A and 9B, an alternative method 2000 of forming an electron-hole spin qubit transistor 100 is disclosed, Step 2001 of providing a layer structure including multiple semiconductor layers, each of a unique material / alloy, stacked on top of one another; forming a first hard mask layer on top of the plurality of semiconductor layers; forming 2005 a first plurality of nano-sized cavities through the first hard mask layer and extending to a first layer of the plurality of semiconductor layers at a first depth D1; exposing 2007 the layer structure to a first semiconductor reactive species to form a plurality of first operational semiconductor islands 106 within the first plurality of nano-sized cavities; forming a second hard mask layer over the plurality of semiconductor layers; forming 2011 a second plurality of nano-sized cavities through the second hard mask layer 202b and extending to a second one of the plurality of semiconductor layers at a second depth D2; exposing the layer structure to a second semiconductor reactant to form a second plurality of operational semiconductor islands 110 within the second plurality of nano-sized cavities; forming a third hard mask layer on top of the plurality of semiconductor layers; forming 2017 a third plurality of nano-sized cavities through the third hard mask layer 202c and extending to a third one of the plurality of semiconductor layers at a third depth D3; exposing 2019 the layer structure to a third semiconductor reactive species to form a plurality of first and second readout semiconductor islands 108, 112 within a third plurality of nano-sized cavities; the first, second and third depths D1, D2 differ by at least one of the semiconductor layers; removing all of the hard mask layer by wet or plasma etching 2021; embedding 2023 the formed plurality of first computing semiconductor islands 106, the formed plurality of second computing semiconductor islands 110, and the formed plurality of first and second readout semiconductor islands 108, 112 in a support material 116 laterally coated on the semiconductor islands 106, 108, 110, 112; forming 2025 at least one source terminal S electrically connecting with the plurality of first operational semiconductor islands 106 through the support material 116; forming 2027 at least one drain terminal D electrically connecting with the plurality of second operational semiconductor islands 110 through the support material 116; forming 2029 a plurality of first gate terminals G1 disposed above each of the plurality of first operational semiconductor islands 106, the first gate terminals G1 being configured to microwave modulate a spin state of each of the plurality of first operational semiconductor islands 106; forming 2031 a plurality of second gate terminals G2 arranged above each of the plurality of first readout semiconductor islands 108, the second gate terminals G2 being configured to read out a state of each of the plurality of first readout semiconductor islands 108; forming 2033 a plurality of third gate terminals G3 disposed above each of the plurality of second operational semiconductor islands 110, the third gate terminals G3 being configured to microwave modulate a spin state of each of the plurality of second operational semiconductor islands 110; and forming 2035 a plurality of fourth gate terminals G4 arranged above each of the plurality of second readout semiconductor islands 112, the fourth gate terminals G4 being configured to read out a state of each of the plurality of second readout semiconductor islands 112.

[0125] 9A and 9B, the layer structure of step 2001 is shown. Moreover, the layer structure has embedded computing semiconductor islands 106, 110. Different computing semiconductor islands are at different depths with respect to all layers of the semiconductor layer. It should be understood that the number of layers may be more than the four depicted in FIG. 9. Moreover, it should be understood that the computing semiconductor islands may have a large or small height distance between each other. In other words, as shown, the first computing semiconductor island 106 may be disposed in a first semiconductor layer, and the second semiconductor island 110 may be disposed in a second semiconductor layer, with an intermediate semiconductor layer or other layer disposed between the first and second semiconductor layers. Such other layer may be, for example, an etch stop layer.

[0126] In Figure 10A, the triplet (1,1) charge state of the qubit is shown, and in Figure 10B, the singlet (0,2) charge state of the qubit is shown.

[0127] As will be readily apparent to those skilled in the art, numerous modifications and variations may be made from the above description of the principles of the inventive concept, and all such modifications and variations are intended to be considered within the scope of the inventive concept as defined in the appended claims. EXAMPLES

[0128] Item 1. 1. An electron-hole spin qubit transistor (100), comprising: A base layer (102); a first quantum bit (103) including a first computing semiconductor island (106) and a first readout semiconductor island (108) arranged at a distance in the range of 3 to 10 nm from each other; a second quantum bit (105) including a second computing semiconductor island (110) and a second readout semiconductor island (112) arranged at a distance from each other in the range of 3 to 10 nm; each of the semiconductor islands has a size that causes each of the semiconductor islands to exhibit three-dimensional quantum confinement of a single electron-hole, each of the semiconductor islands forming a heterojunction with the base layer; The spin qubit transistor (100) further comprises: a support material (116) disposed over each of the semiconductor islands to embed each semiconductor island; a source terminal (S) electrically connected to the first operational semiconductor island (106) through the support material (116); a drain terminal (D) electrically connected to the second operational semiconductor island (110) through the support material (116); a first gate terminal (G1) disposed above the first operational semiconductor island (106) and configured to microwave modulate the spin state of the first operational semiconductor island (106); a second gate terminal (G2) disposed above the first readout semiconductor island (108) and configured to read out a state of the first readout semiconductor island (108); a third gate terminal (G3) disposed above the second operational semiconductor island (110) and configured to microwave modulate the spin state of the second operational semiconductor island (110); a fourth gate terminal (G4) disposed above the second readout semiconductor island (112) and configured to read out a state of the second readout semiconductor island (112); The first operational semiconductor island (106) and the second operational semiconductor island (110) are configured to each have a unique resonant frequency, the electron-hole spin qubit transistor (100). Item 2. Each semiconductor island is made of Al (x) Ga (1-x) N alloy, and each computing semiconductor island has its own Al (x) Ga (1-x) N alloy, thereby achieving a computational semiconductor island with a unique resonant frequency, and the base layer is an Al (y) Ga (1-y) Item 2. The electron-hole spin qubit transistor (100) of item 1, wherein N, x>y and y>0. Item 3. Each semiconductor island (106, 108, 110, 112) is made of Al (x) Ga (1-x) Item 2. The electron-hole spin qubit transistor (100) of item 1, comprising a lower region comprising an N-alloy and an upper region comprising GaN, the base layer being GaN, a heterojunction being formed at an interface between the lower region and the base layer, and x>y. Item 4. 2. The electron-hole spin qubit transistor of claim 1, wherein each semiconductor island has a unique size (106, 108, 110, 112), thereby achieving an operational semiconductor island (106, 110) with a unique resonant frequency. Item 5. 5. The electron-hole spin qubit transistor according to any one of items 1 to 4, wherein the semiconductor island is formed by epitaxial growth. Item 6. Item 6. The electron-hole spin qubit transistor of item 5, wherein the semiconductor islands are formed by Stranski-Krastanow growth. Item 7. 6. The electron-hole spin qubit transistor of item 5, wherein the epitaxial growth is selective area growth. Item 8. 8. The electron-hole spin qubit transistor of any one of items 1 to 7, wherein the semiconductor islands are arranged in a plane parallel to the base layer. Item 9. Item 9. The electron-hole spin qubit transistor of item 8, wherein the semiconductor islands are spaced apart from one another in a plane parallel to the base layer. Item 10. 10. The electron-hole spin qubit transistor of any of items 1 to 9, wherein the semiconductor islands are arranged laterally with respect to one another. Item 11. 11. The electron-hole spin qubit transistor (100) of any one of items 1 to 10, wherein the first gate terminal (G1) is configured to excite an electron-hole to transition the first qubit (103) from a singlet state (S) to a triplet state (T). Item 12. Item 12. The electron-hole spin qubit transistor (100) of item 11, wherein the first gate terminal (G1) is configured to electrostatically excite an electron-hole to transition the first qubit (103) from a singlet state (S) to a triplet state (T). Item 13. 13. The electron-hole spin qubit transistor of any one of items 1 to 12, wherein the third gate terminal is configured to excite an electron-hole to transition the first qubit from a singlet state to a triplet state. Item 14. Item 14. The electron-hole spin qubit transistor of item 13, wherein the third gate terminal is configured to electrostatically excite the electron-hole to transition the second qubit from a singlet state to a triplet state. Item 15. 15. The electron-hole spin qubit transistor of any of the preceding claims, wherein the spin qubit transistor further comprises a control electrode arrangement configured to modify tunneling characteristics between the first and second operational semiconductor islands. Item 16. Item 16. The electron-hole spin qubit transistor of item 15, wherein the control electrode arrangement is configured to alter a region of material between the first operational semiconductor island and the second operational semiconductor island. Item 17. 17. The electron-hole spin qubit transistor (100) according to any one of items 1 to 16, wherein each of the semiconductor islands (106, 108, 110, 112) is made of a material having a wurtzite crystal structure. Item 18. 18. The electron-hole spin qubit transistor of any of items 1 to 17, wherein the support material is P-doped, thereby acting as a hole reservoir for the semiconductor island. Item 19. 19. The electron-hole spin qubit transistor of any of items 1 to 18, wherein the operation semiconductor island and readout semiconductor island of each qubit are arranged and positioned such that an electron-hole can be excited from the operation semiconductor island to the readout semiconductor island in each qubit. Item 20. 20. The electron-hole spin qubit transistor of any one of items 1 to 19, wherein the first qubit and the second qubit are arranged and positioned to be entangled. Item 21. 21. The electron-hole spin qubit transistor of any one of items 1 to 20, wherein the first operational semiconductor island and the second operational semiconductor island are arranged and positioned so as to be entangled. Item 22. 22. The electron-hole spin qubit transistor (100) of any of items 1 to 21, wherein the band structure of the semiconductor islands (106, 108, 110, 112) is configured to have a heavy electron hole at the origin of k-space by the composition of the base layer (102). Item 23. forming a hard mask layer (202) on a base layer (102); forming (1003) a first plurality of nano-sized cavities (204) in the hard mask layer (202); exposing (1005) the base layer (102) to a semiconductor reactive species to form a plurality of first operational semiconductor islands (106) within the first plurality of nano-sized cavities (204); forming (1007) a second plurality of nano-sized cavities (206) in the hard mask layer (202); exposing (1009) the base layer (102) to a semiconductor reactive species to form a second plurality of operational semiconductor islands (110) within the second plurality of nano-sized cavities (206); forming (1011) a third plurality of nano-sized cavities (208) in the hard mask layer (202); within the third plurality of nano-sized cavities (208); a plurality of first readout semiconductor islands (108), each of which is disposed within a distance in the range of 3 to 10 nm from each of the plurality of first computation semiconductor islands (110); exposing (1013) the base layer (102) to a semiconductor reactive species to form a plurality of second readout semiconductor islands (112), each of which is located within a distance in the range of 3-10 nm from each of the plurality of second computation semiconductor islands (110); removing (1015) the hard mask layer by wet etching or plasma etching; embedding (1017) the formed plurality of first computing semiconductor islands (106), the formed plurality of second computing semiconductor islands (110), and the plurality of first and second readout semiconductor islands (108, 112) in a support material (116) laterally coated on the semiconductor islands (106, 108, 110, 112); forming (1019) at least one source terminal (S) electrically connecting with the plurality of first operational semiconductor islands (106) through the support material (116); forming (1021) at least one drain terminal (D) electrically connecting with the plurality of second operational semiconductor islands (110) through the support material (116); forming (1023) a plurality of first gate terminals (G1) disposed above each of the plurality of first operational semiconductor islands (106), the first gate terminals (G1) being configured to microwave modulate a spin state of each of the plurality of first operational semiconductor islands (106); forming (1025) a plurality of second gate terminals (G2) arranged above each of the plurality of first readout semiconductor islands (108), the second gate terminals (G2) being configured to read out a state of each of the plurality of first readout semiconductor islands (108); forming (1027) a plurality of third gate terminals (G3) disposed above each of the plurality of second operational semiconductor islands (110), the third gate terminals (G3) being configured to microwave modulate a spin state of each of the plurality of second operational semiconductor islands (110); and forming (1029) a plurality of fourth gate terminals (G4) disposed above each of the plurality of second readout semiconductor islands (112), the fourth gate terminals (G4) configured to read out a state of each of the plurality of second readout semiconductor islands (112). Item 24. Item 24. The method of item 23, wherein the plurality of first operational semiconductor islands and the plurality of second operational semiconductor islands are configured to be lattice-mismatched to the base layer (102) to provide a Rabi frequency. Item 25. 25. The method of claim 23 or 24, wherein the plurality of first computation semiconductor islands, the plurality of second computation semiconductor islands, and the plurality of readout semiconductor islands form a matrix of quantum bits. Item 26. 26. The method (1000) of claim 25, further comprising forming a cap layer (120) on each of the plurality of first operational semiconductor islands (106) and on each of the plurality of second operational semiconductor islands (108) to form a heterostructure. Item 27. Providing a layer structure (2001) including a plurality of semiconductor layers stacked together, each of the semiconductor layers being a unique alloy; forming a first hard mask layer over the plurality of semiconductor layers (2003); forming a first plurality of nano-sized cavities (2005) through the first hard mask layer and extending to a first one of the plurality of semiconductor layers at a first depth (D1); exposing (2007) the layer structure to a first semiconductor reactant species to form a plurality of first operational semiconductor islands (106) within the first plurality of nano-sized cavities; forming a second hard mask layer over the plurality of semiconductor layers (2009); forming a second plurality of nano-sized cavities (2011) through the second hard mask layer and extending to a second one of the plurality of semiconductor layers at a second depth (D2); exposing the layer structure to a second semiconductor reactant to form a second plurality of operational semiconductor islands (110) within the second plurality of nano-sized cavities (2013); forming a third hard mask layer over the plurality of semiconductor layers (2015); forming a third plurality of nano-sized cavities through the third hard mask layer and extending to a third one of the plurality of semiconductor layers at a third depth (2017); exposing the layer structure to a third semiconductor reactive species to form a plurality of first and second readout semiconductor islands (108, 112) within a third plurality of nano-sized cavities (2019); the first, second and third depths vary through at least one of the semiconductor layers; removing the hard mask layer by wet or plasma etching (2021); embedding (2023) the formed plurality of first computing semiconductor islands (106), the formed plurality of second computing semiconductor islands (110), and the formed plurality of first and second readout semiconductor islands (108, 112) in a support material (116) laterally coated over the semiconductor islands; forming (2025) at least one source terminal (S) electrically connecting with the plurality of first operational semiconductor islands (106) through the support material (116); forming (2027) at least one drain terminal (D) electrically connecting with the plurality of second operational semiconductor islands (110) through the support material (116); forming (2029) a plurality of first gate terminals (G1) disposed above each of the plurality of first operational semiconductor islands (106), the first gate terminals (G1) being configured to microwave modulate a spin state of each of the plurality of first operational semiconductor islands (106); forming (2031) a plurality of second gate terminals (G2) arranged above each of the plurality of first readout semiconductor islands (108), the second gate terminals (G2) being configured to read out a state of each of the plurality of first readout semiconductor islands (108); forming (2033) a plurality of third gate terminals (G3) disposed above each of the plurality of second operational semiconductor islands (110), the third gate terminals (G3) being configured to microwave modulate a spin state of each of the plurality of second operational semiconductor islands (110); and forming (2035) a plurality of fourth gate terminals (G4) disposed above each of the plurality of second readout semiconductor islands (112), the fourth gate terminals (G4) configured to read out a state of each of the plurality of second readout semiconductor islands (112). Item 28. 24. A quantum computer comprising at least one spin qubit transistor (100) according to any one of items 1 to 23.

Claims

1. 1. An electron-hole spin qubit transistor (100), comprising: a base layer (102); a first quantum bit (103) including a first computing semiconductor island (106) and a first readout semiconductor island (108) spaced apart from each other by a distance in the range of 3 to 10 nm; a second qubit (105) including a second operation semiconductor island (110) and a second readout semiconductor island (112) spaced apart from each other by a distance in the range of 3 to 10 nm; each of the semiconductor islands has a size that allows each of the semiconductor islands to exhibit three-dimensional quantum confinement of a single electron-hole, and each of the semiconductor islands forms a heterojunction with the base layer; The spin qubit transistor (100) further comprises: a support material (116) disposed on top of each of the semiconductor islands to embed each of the semiconductor islands; a source terminal (S) electrically connected to the first operational semiconductor island (106) through the support material (116); a drain terminal (D) electrically connected to the second operational semiconductor island (110) through the support material (116); a first gate terminal (G1) disposed above the first operational semiconductor island (106) and configured to microwave modulate the spin state of the first operational semiconductor island (106); a second gate terminal (G2) disposed above the first readout semiconductor island (108) and configured to read out a state of the first readout semiconductor island (108); a third gate terminal (G3) disposed above the second operational semiconductor island (110) and configured to microwave modulate the spin state of the second operational semiconductor island (110); a fourth gate terminal (G4) disposed above the second readout semiconductor island (112) and configured to read out a state of the second readout semiconductor island (112); The electron-hole spin qubit transistor (100) is configured such that the first operational semiconductor island (106) and the second operational semiconductor island (110) each have a unique resonant frequency.

2. Each semiconductor island is made of Al （ｘ） Ga （１－ｘ） N alloy, and each operational semiconductor island contains a unique Al （ｘ） Ga （１－ｘ） N alloy, thereby achieving the operational semiconductor island with the unique resonant frequency, and the base layer is Al （ｙ） Ga （１－ｙ） The electron-hole spin qubit transistor of claim 1 , wherein N, x>y and y>0.

3. Each semiconductor island (106, 108, 110, 112) is made of Al （ｘ） Ga （１－ｘ） 10. The electron-hole spin qubit transistor of claim 1, comprising: a lower region comprising an N-alloy; and an upper region comprising GaN, wherein the base layer is GaN, a heterojunction is formed at an interface between the lower region and the base layer, and x>y.

4. 10. The electron-hole spin qubit transistor of claim 1, wherein each semiconductor island has a unique size (106, 108, 110, 112) thereby achieving the operational semiconductor island (106, 110) with the unique resonant frequency.

5. 2. The electron-hole spin qubit transistor of claim 1, wherein the first gate terminal is configured to excite an electron-hole to transition the first qubit from a singlet state to a triplet state.

6. 6. The electron-hole spin qubit transistor of claim 5, wherein the first gate terminal is configured to electrostatically excite the electron-hole to transition the first qubit from the singlet state to the triplet state.

7. 10. The electron-hole spin qubit transistor of claim 1, wherein each of the semiconductor islands is made of a material having a wurtzite crystal structure.

8. 10. The electron-hole spin qubit transistor of claim 1, wherein the band structure of the semiconductor islands is configured by the composition of the base layer to have a heavy electron-hole at the origin of k-space.

9. forming a hard mask layer (202) on a base layer (102); forming a first plurality of nano-sized cavities (204) in the hard mask layer (202); exposing the base layer (102) to a semiconductor reactive species to form a plurality of first operational semiconductor islands (106) within the first plurality of nano-sized cavities (204); forming (1007) a second plurality of nano-sized cavities (206) in the hard mask layer (202); exposing (1009) the base layer (102) to a semiconductor reactive species to form a plurality of second operational semiconductor islands (110) within the second plurality of nano-sized cavities (206); forming (1011) a third plurality of nano-sized cavities (208) in the hard mask layer (202); within the third plurality of nano-sized cavities (208); a plurality of first readout semiconductor islands (108), each disposed within a distance in a range of 3 to 10 nm from each of the plurality of first processing semiconductor islands (110); exposing (1013) the base layer (102) to a semiconductor reactive species to form a plurality of second readout semiconductor islands (112), each of which is located within a distance ranging from 3 to 10 nm from each of the plurality of second processing semiconductor islands (110); removing the hard mask layer (1015) by wet etching or plasma etching; and embedding the formed first plurality of operational semiconductor islands (106), the formed second plurality of operational semiconductor islands (110), and the formed first and second readout semiconductor islands (108, 112) in a support material (116) laterally coated on the semiconductor islands (106, 108, 110, 112); forming (1019) at least one source terminal (S) electrically connecting with the plurality of first operational semiconductor islands (106) through the support material (116); forming (1021) at least one drain terminal (D) electrically connecting with the plurality of second operational semiconductor islands (110) through the support material (116); forming (1023) a plurality of first gate terminals (G1) disposed above each of the plurality of first operational semiconductor islands (106), the first gate terminals (G1) being configured to microwave modulate the spin state of each of the plurality of first operational semiconductor islands (106); forming (1025) a plurality of second gate terminals (G2) arranged above each of the plurality of first readout semiconductor islands (108), the second gate terminals (G2) being configured to read out a state of each of the plurality of first readout semiconductor islands (108); forming (1027) a plurality of third gate terminals (G3) disposed above each of the plurality of second operational semiconductor islands (110), the third gate terminals (G3) being configured to microwave modulate the spin state of each of the plurality of second operational semiconductor islands (110); and forming (1029) a plurality of fourth gate terminals (G4) disposed above each of the plurality of second readout semiconductor islands (112), the fourth gate terminals (G4) configured to read out a state of each of the plurality of second readout semiconductor islands (112).

10. 10. The method of claim 9, further comprising forming a cap layer over each of the plurality of first operational semiconductor islands and over each of the plurality of second operational semiconductor islands to form a heterostructure.

11. Providing a layer structure (2001) including a plurality of semiconductor layers stacked together, each of the semiconductor layers being a unique alloy; forming a first hard mask layer on top of the plurality of semiconductor layers (2003); forming a first plurality of nano-sized cavities (2005) through the first hard mask layer and extending to a first layer of the plurality of semiconductor layers at a first depth (D1); exposing (2007) the layer structure to a first semiconductor reactive species to form a plurality of first operational semiconductor islands (106) within the first plurality of nano-sized cavities; forming a second hard mask layer on top of the plurality of semiconductor layers (2009); forming a second plurality of nano-sized cavities (2011) through the second hard mask layer and extending to a second one of the plurality of semiconductor layers at a second depth (D2); exposing (2013) the layer structure to a second semiconductor reactive species to form a plurality of second operational semiconductor islands (110) within the second plurality of nano-sized cavities; forming a third hard mask layer on top of the plurality of semiconductor layers (2015); forming a third plurality of nano-sized cavities (2017) through the third hard mask layer and extending to a third layer of the plurality of semiconductor layers at a third depth; exposing (2019) the layer structure to a third semiconductor reactive species to form a plurality of first and second readout semiconductor islands (108, 112) within the third plurality of nano-sized cavities; the first, second, and third depths vary through at least one of the semiconductor layers; removing the hard mask layer (2021) by wet etching or plasma etching; and embedding the formed first plurality of operational semiconductor islands (106), the formed second plurality of operational semiconductor islands (110), and the formed first and second readout semiconductor islands (108, 112) in a support material (116) laterally coated on the semiconductor islands; forming (2025) at least one source terminal (S) electrically connecting with the plurality of first operational semiconductor islands (106) through the support material (116); forming (2027) at least one drain terminal (D) electrically connecting with the plurality of second operational semiconductor islands (110) through the support material (116); forming (2029) a plurality of first gate terminals (G1) disposed above each of the plurality of first operational semiconductor islands (106), the first gate terminals (G1) being configured to microwave modulate the spin state of each of the plurality of first operational semiconductor islands (106); forming (2031) a plurality of second gate terminals (G2) arranged above each of the plurality of first readout semiconductor islands (108), the second gate terminals (G2) being configured to read out a state of each of the plurality of first readout semiconductor islands (108); forming (2033) a plurality of third gate terminals (G3) disposed above each of the plurality of second operational semiconductor islands (110), the third gate terminals (G3) being configured to microwave modulate the spin state of each of the plurality of second operational semiconductor islands (110); and forming a plurality of fourth gate terminals (G4) disposed above each of the plurality of second readout semiconductor islands (112), the fourth gate terminals (G4) configured to read out a state of each of the plurality of second readout semiconductor islands (112).

12. A quantum computer comprising at least one spin qubit transistor (100) according to any one of claims 1 to 8.

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