Display device and manufacturing method thereof

Abstract

Provided is a display device comprising: a substrate having a display region including a first pixel region and a second pixel region adjacent to each other along a first direction, and a peripheral region outside the display region; an organic insulating layer disposed on an upper portion of the substrate; a connecting metal layer disposed on the organic insulating layer; and a planarization layer covering the connecting metal layer, wherein the planarization layer includes a first inner side surface which corresponds to the first pixel region and defines a contact hole exposing at least a portion of the connecting metal layer to the outside of the planarization layer, and which is a forward tapered inclined surface, and a second inner side surface which is a reverse tapered inclined surface along the first direction, and which defines a 1-1 hole which is located between the first pixel region and the second pixel region and exposes a portion of the organic insulating layer to the outside of the planarization layer.

Description

[Technical field]

[0001] The present invention relates to a display device and a manufacturing (or providing) method thereof, and more particularly, to a display device and a manufacturing (or providing) method thereof that can reduce leakage current and reduce manufacturing (or providing) costs. [Background technology]

[0002] Some layers included in the display device may be shared by a plurality of display elements, in which case, when a current is supplied to one display element, the current may also be supplied to other adjacent display elements via the layer shared by the plurality of display elements. Summary of the Invention [Problem to be solved by the invention]

[0003] When a current is supplied to adjacent display elements through a layer that is common to a plurality of display elements, the color purity of the display device may be reduced. To solve this problem, some display devices include an organic film separator. However, in such conventional display devices, the process of manufacturing (or providing) the display device becomes complicated in order to form the separator, which may increase the manufacturing cost.

[0004] The present invention aims to provide a display device and a manufacturing method thereof that can reduce leakage current and reduce manufacturing costs, including the above-mentioned problems, and is intended to solve various problems, including the above-mentioned problems, however, this is merely an example and the scope of the present invention is not limited thereto. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided a display device comprising: a display area including a first pixel area and a second pixel area adjacent to each other along a first direction; a substrate having a peripheral area outside the display area; a contact hole located in the first pixel area and exposing at least a portion of a lower connecting metal layer; and a planarization layer including a 1-1 hole located between the first pixel area and the second pixel area, wherein an inner side of the contact hole includes a forward tapered inclined surface and an inner side of the 1-1 hole includes a reverse tapered inclined surface.

[0006] The first pixel region and the second pixel region may be arranged along a first direction, and the 1-1 hole may extend in a second direction intersecting the first direction.

[0007] The display region further includes a third pixel region arranged along the second direction adjacent to the first pixel region, and the planarization layer further includes a 2-1 hole arranged between the first pixel region and the third pixel region and extending in the first direction, and an inner surface of the 2-1 hole includes an inverted tapered inclined surface.

[0008] The 1-1 hole and the 2-1 hole may be connected.

[0009] The display device may further include a pixel defining layer disposed on the planarization layer and including a 1-2 hole overlapping the 1-1 hole.

[0010] The inner side surface of the 1-2 hole also includes a forward tapered inclined surface.

[0011] The display region further includes a third pixel region arranged adjacent to the first pixel region along the second direction, the planarization layer is located between the first pixel region and the third pixel region and further includes a 2-1 hole extending in the first direction, an inner side of the 2-1 hole includes a reverse tapered inclined surface, and the pixel defining film further includes a 2-2 hole overlapping the 2-1 hole, an inner side of the 2-2 hole includes a forward tapered inclined surface.

[0012] The 1-2 hole and the 2-2 hole may be connected.

[0013] The display device may further include a pad disposed in the peripheral region.

[0014] The planarization layer covers the pad and includes a pad hole exposing at least a portion of the pad, and an inner side surface of the pad hole includes a forward tapered inclined surface.

[0015] The thickness of the planarization layer over the pads is smaller than the thickness of the planarization layer over the display area.

[0016] The display device may further include a pixel electrode interposed between the planarization layer and the pixel defining film, a counter electrode disposed to cover the pixel defining film, and an intermediate layer interposed between the pixel electrode and the counter electrode.

[0017] The intermediate layer and the counter electrode may cover the inner surface of the first-2 hole.

[0018] The intermediate layer and the counter electrode do not cover the inner side surface of the 1-1 hole.

[0019] The display device further includes an organic insulating layer disposed under the planarization layer, and a residual layer disposed on the organic insulating layer so as to be located inside the 1-1 hole, the residual layer containing at least a portion of the same material as the intermediate layer and also containing the same material as the counter electrode.

[0020] The remaining layer does not contact the inner side surface of the 1-1 hole.

[0021] According to one aspect of the present invention, there is provided a method for manufacturing (or providing) a display device, the method including: forming (or providing) a connecting metal layer on an upper portion of a substrate to provide a planarization layer having a plurality of inner surfaces; forming a planarization layer forming layer (e.g., a preliminary planarization layer) to cover the connecting metal layer by applying a negative photoresist; positioning a half-tone mask having a first shielding portion, a first semi-transmitting portion surrounding the first shielding portion, and a 2-1 shielding portion spaced apart from the first shielding portion and the first semi-transmitting portion on the planarization layer forming layer; and exposing the planarization layer forming layer through the half-tone mask.

[0022] The step of positioning the half-tone mask also includes a step of positioning the first shielding portion and the first semi-transmitting portion on a connection metal layer and positioning the 2-1 shielding portion spaced apart from the connection metal layer in a first direction.

[0023] The half-tone mask has a 2-2 shielding portion spaced apart from the first shielding portion and the first semi-transmitting portion, and the step of positioning the half-tone mask also includes a step of positioning the first shielding portion and the first semi-transmitting portion on a connection metal layer, positioning the 2-1 shielding portion spaced apart from the connection metal layer in a first direction, and positioning the 2-2 shielding portion spaced apart from the connection metal layer in a second direction intersecting the first direction.

[0024] The 2-1 shielding part and the 2-2 shielding part may be connected to each other.

[0025] According to one aspect of the present invention, the method includes forming a connecting metal layer and a pad on an upper portion of a substrate to provide a planarization layer having a plurality of inner surfaces; forming a planarization layer forming layer to cover the connecting metal layer and the pad by applying a negative photoresist; positioning a half-tone mask on the planarization layer forming layer, the half-tone mask having a first shielding portion, a first semi-transmitting portion surrounding the first shielding portion, a 2-1 shielding portion spaced apart from the first shielding portion and the first semi-transmitting portion, a third shielding portion, and a second semi-transmitting portion surrounding the third shielding portion; and exposing the planarization layer forming layer through the half-tone mask.

[0026] The step of positioning the half-tone mask also includes a step of positioning the first shielding portion and the first semi-transmitting portion on a connection metal layer, positioning the 2-1 shielding portion spaced apart from the connection metal layer in a first direction, and positioning the third shielding portion and the second semi-transmitting portion on the pad.

[0027] Other aspects, features, and advantages in addition to those described above will become apparent from the following detailed description of the invention, the claims, and the drawings. Effect of the Invention

[0028] According to an embodiment of the present invention as described above, a display device that can reduce leakage current and reduce manufacturing costs can be realized, however, it should be understood that the scope of the present invention is not limited to such effects. [Brief description of the drawings]

[0029] [Figure 1] 1 is a plan view illustrating a display device according to an embodiment of the present invention; [Diagram 2] 2 is an equivalent circuit diagram of one pixel included in the display device of FIG. [Diagram 3] FIG. 2 is an enlarged plan view of part I in FIG. [Figure 4] FIG. 2 is an enlarged plan view of a portion II in FIG. [Diagram 5] 1 is a cross-sectional view illustrating a display device according to an embodiment of the present invention; [Figure 6] FIG. 6 is an enlarged cross-sectional view of part A in FIG. 5. [Figure 7] FIG. 6 is an enlarged cross-sectional view of part B in FIG. 5. [Figure 8] FIG. 6 is an enlarged cross-sectional view of part C in FIG. 5. [Figure 9] FIG. 6 is an enlarged cross-sectional view of a portion D in FIG. 5. [Figure 10] 1 is a plan view illustrating a display device according to an embodiment of the present invention; [Figure 11] 2A to 2C are cross-sectional views that roughly illustrate a method for manufacturing the display device of FIG. [Figure 12] 2A to 2C are cross-sectional views that roughly illustrate a method for manufacturing the display device of FIG. [Figure 13] 2A to 2C are cross-sectional views that roughly illustrate a method for manufacturing the display device of FIG. [Figure 14] 2A to 2C are cross-sectional views that roughly illustrate a method for manufacturing the display device of FIG. [Figure 15] 2A to 2C are cross-sectional views that roughly illustrate a method for manufacturing the display device of FIG. [Figure 16] 1 is a diagram for explaining a taper angle of a negative photoresist. [Figure 17] 1 is a diagram for explaining a taper angle of a negative photoresist. [Figure 18] 1 is a diagram for explaining a taper angle of a negative photoresist. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] The present invention can be modified in various ways and can have various embodiments, but specific embodiments are illustrated in the drawings and will be described in detail by the detailed description. The advantages, features, and methods of achieving the present invention will become clear by referring to the embodiments described in detail below in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below, but can be embodied in various forms.

[0031] Hereinafter, an embodiment of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, the same or corresponding components are designated by the same reference numerals, and duplicate descriptions related thereto will be omitted.

[0032] In the following embodiments, when various components such as a layer, a film, a region, or a plate are described as being "on" another component, this does not only mean that the components are "directly on" the other component, but also includes the case where another component is interposed therebetween. In addition, for convenience of explanation, the size of the components may be exaggerated or reduced in the drawings. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to what is shown in the drawings.

[0033] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes on a Cartesian coordinate system, but may be interpreted in a broader sense including the three axes. For example, the x-axis, y-axis, and z-axis may be mutually orthogonal, but may also be non-orthogonal and represent mutually different directions.

[0034] In the following embodiments, terms such as first and second are not used in a limiting sense but are used only to distinguish one component from another component.

[0035] In the following embodiments, the singular expression includes the plural expression unless the context clearly indicates otherwise.

[0036] In the following embodiments, the terms "comprise" or "have" mean the presence of features or components described in the specification, without precluding the possibility that one or more other features or components may be added.

[0037] In this specification, "A and / or B" refers to the case where A is present, B is present, or A and B is present. And, "at least one of A and B" refers to the case where A is present, B is present, or A and B is present.

[0038] FIG. 1 is a plan view that diagrammatically illustrates a portion of a display device 1 according to an embodiment of the present invention. As illustrated in FIG. 1, the display device 1 also includes a display area DA in which a plurality of pixels PX are arranged, and a peripheral area PA located outside the display area DA (e.g., adjacent to the display area DA). Specifically, the peripheral area PA may entirely surround the display area DA. It is also understood that the substrate 100 included in the display device 1 has such a display area DA and peripheral area PA. That is, various components or layers of the display device 1 also include the display area DA and peripheral area PA as described above.

[0039] Each pixel PX of the display device 1 is an area (e.g., a planar area) that can emit light of a certain hue, and the display device 1 can provide an image using the light emitted from the pixel PX. For example, each pixel PX can emit green light, red light, or blue light.

[0040] The display area DA may have a polygonal shape including a rectangle as shown in Fig. 1. For example, on a plane (e.g., a plane defined by the x and y directions in Fig. 1), the display area DA may have a rectangular shape with a width longer than a height, a rectangular shape with a width shorter than a height, or a square shape. Alternatively, the display area DA may have various shapes such as an ellipse or a circle.

[0041] The peripheral area PA is also a non-display area where the pixels PX are not arranged. Drivers for providing electrical signals and power to the pixels PX may be arranged in the peripheral area PA. Pads 400 to which various electronic elements, printed circuit boards, etc. may be electrically connected may be arranged in the peripheral area PA. The pads 400 are arranged spaced apart from each other in the peripheral area PA and may be electrically connected to external components such as printed circuit boards and integrated circuit elements. The display device 1 may be connected to external components through the pads 400.

[0042] Fig. 2 is an equivalent circuit diagram of one pixel PX included in the display device 1 of Fig. 1. As shown in Fig. 2, one pixel PX also includes a pixel circuit PC and an organic light emitting element OLED as a light emitting element electrically connected thereto.

[0043] The pixel circuit PC also includes a first transistor T1, a second transistor T2, and a storage capacitor Cst. The second transistor T2 is a switching transistor connected to one or more signal lines such as a scan line SL and a data line DL, and may be turned on by a switching signal input from the scan line SL to transmit a data signal input from the data line DL to the first transistor T1. The storage capacitor Cst has one end electrically connected to the second transistor T2 and the other end opposite to the one end electrically connected to the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transmitted from the second transistor T2 and a driving power supply voltage ELVDD supplied to the driving voltage line PL.

[0044] The first transistor T1 is a driving transistor and is connected to the driving voltage line PL and the storage capacitor Cst. The first transistor T1 corresponds to the voltage value stored in the storage capacitor Cst and can control the magnitude of a driving current (e.g., an electrical driving current) flowing from the driving voltage line PL to the organic light emitting device OLED. The organic light emitting device OLED can emit light having a predetermined brightness according to the driving current. The counter electrode 230 (FIG. 5) of the organic light emitting device OLED can be supplied with an electrode power supply voltage ELVSS.

[0045] 2 illustrates a pixel circuit PC including two transistors and one storage capacitor, but the present invention is not limited thereto. For example, the number of transistors or the number of storage capacitors may be variously changed depending on the design of the pixel circuit PC.

[0046] 3 is an enlarged plan view of portion I of FIG. 1. As shown in FIG. 3, the connecting wires 1100 may be arranged in the peripheral area PA. The connecting wires 1100 may electrically connect signal lines, for example, data lines DL, arranged in the display area DA to pads 400. Each of the connecting wires 1100 includes a first portion 1101 extending in one direction to electrically connect the signal lines to the pads 400, and a second portion 1102 arranged at an end (for example, an end) of the first portion 1101.

[0047] The pad 400 may overlap (or correspond to) the connecting wire 1100. Specifically, the pad 400 may be located on the second portion 1102 of the connecting wire 1100 and overlap the connecting wire 1100.

[0048] FIG. 4 is an enlarged plan view of a portion II in FIG. 1. In FIG. 4, a plan view on a pixel definition film 215 is illustrated for convenience. As illustrated in FIG. 4, the display area DA of the substrate 100 also includes a plurality of pixel areas PXA1, PXA2, and PXA3 in which a plurality of pixels PX are arranged. Each pixel PX means a sub-pixel and includes a display element such as an organic light emitting element OLED. The pixel PX may emit, for example, green light, red light, or blue light. For example, the pixel PX may be a first pixel PX1 that emits green light, a second pixel PX2 that emits red light, or a third pixel PX3 that emits blue light. The green light is light that belongs to a wavelength band of about 495 nm to about 580 nm, the red light is light that belongs to a wavelength band of about 580 nm to about 780 nm, and the blue light is light that belongs to a wavelength band of about 400 nm to about 495 nm.

[0049] In the display area DA, a plurality of pixel electrodes 210-1, 210-2, and 210-3 may be arranged spaced apart from each other on a plane. For example, in the display area DA, a first pixel electrode 210-1, a second pixel electrode 210-2, and a third pixel electrode 210-3 may be arranged spaced apart from each other.

[0050] The pixel defining film 215 may include (or define) an opening 215OP that exposes (e.g., exposes to the outside of) each of the pixel electrodes 210-1, 210-2, and 210-3. Although not shown in FIG. 4, the light-emitting layers of the display elements that emit light may be located in the openings 215OP of the pixel defining film 215. The counter electrode 230 of the display element may be disposed on the light-emitting layers and on the pixel defining film 215. The counter electrode 230 may be integrally formed across the pixel electrodes 210-1, 210-2, and 210-3.

[0051] A stacked structure of any one of the pixel electrodes 210-1, 210-2, and 210-3, the light emitting layer, and the counter electrode 230 may form one organic light emitting element OLED. One opening 215OP of the pixel defining film 215 corresponds to one organic light emitting element OLED and may define one light emitting area EA.

[0052] For example, a light-emitting layer that emits green light is disposed in the opening 215OP that exposes the center of the first pixel electrode 210-1, and the first pixel PX1 also includes a light-emitting area EA defined by the opening 215OP. Similarly, a light-emitting layer that emits red light is disposed in the opening 215OP that exposes the center of the second pixel electrode 210-2, and the second pixel PX2 also includes a light-emitting area EA defined by the opening 215OP. Similarly, a light-emitting layer that emits blue light is disposed in the opening 215OP that exposes the center of the third pixel electrode 210-3, and the third pixel PX3 also includes a light-emitting area EA defined by the opening 215OP. However, the present invention is not limited thereto. For example, a light-emitting layer that emits blue or green light is disposed in the opening 215OP that exposes the center of the first pixel electrode 210-1, the opening 215OP that exposes the center of the second pixel electrode 210-2, and the opening 215OP that exposes the center of the third pixel electrode 210-3, and the first pixel PX1, the second pixel PX2, and the third pixel PX3 also include light-emitting areas EA defined by such openings 215OP. In such a case, the display device 1 also includes a light-emitting panel and a color panel that are stacked in the thickness direction (e.g., z direction) (or along the thickness direction (e.g., z direction)), and the blue light or green light emitted from the light-emitting layer of the light-emitting panel may be converted into red light, green light, and blue light or transmitted while passing through the color panel. In this way, the color panel is also called a color conversion panel.

[0053] The first pixel PX1 may be disposed in the first pixel region PXA1, the second pixel PX2 may be disposed in the second pixel region PXA2, and the third pixel PX3 may be disposed in the third pixel region PXA3. The first pixel region PXA1 and the second pixel region PXA2 may be positioned adjacent to each other along a first direction (e.g., a direction between the -x direction and the +y direction, i.e., the D1 direction), and the first pixel region PXA1 and the third pixel region PXA3 may be positioned adjacent to each other along a second direction (a direction between the -x direction and the -y direction, i.e., the D2 direction) intersecting the first direction (D1).

[0054] A first hole H1 or a second hole H2 may be disposed between the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3. The first hole H1 or the second hole H2 is substantially also a region between the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3. The first hole H1 may be disposed between the first pixel region PXA1 and the second pixel region PXA2 and may extend in the second direction (D2). The second hole H2 may be disposed between the first pixel region PXA1 and the third pixel region PXA3 and may extend in the first direction (D1). Each hole having a planar shape may extend in one or more directions on a plane, for example, in a direction corresponding to a major dimension of the planar shape. However, the present invention is not limited thereto.

[0055] In FIG. 4, the first hole H1 and the second hole H2 are illustrated as having a rectangular shape (e.g., a rectangular planar shape), but the present invention is not limited thereto. For example, the first hole H1 and / or the second hole H2 may have a polygonal shape including a quadrangle. That is, the first hole H1 and / or the second hole H2 may have a rectangular shape in which the width is longer than the height, a rectangular shape in which the width is shorter than the height, or a square shape. Alternatively, the first hole H1 and / or the second hole H2 may have various shapes such as an ellipse or a circle.

[0056] In FIG. 4, the multiple pixels PX are shown as being arranged in an RGBG type (a so-called pentile structure), but it goes without saying that they can be arranged in a variety of shapes such as a stripe type.

[0057] Fig. 5 is a cross-sectional view that diagrammatically illustrates a portion of a display device 1 according to an embodiment of the present invention. Specifically, Fig. 5 is a cross-sectional view taken along line III-III' in Fig. 4 and line IV-IV' in Fig. 3. Fig. 6 is an enlarged cross-sectional view of part A in Fig. 5, Fig. 7 is an enlarged cross-sectional view of part B in Fig. 5, and Fig. 8 is an enlarged cross-sectional view of part C in Fig. 5.

[0058] As shown in FIG. 5, the display device 1 according to the present embodiment includes a substrate 100. The substrate 100 may include various materials having flexible or bendable properties. For example, the substrate 100 may include glass, metal, or polymer resin. The substrate 100 may also include polymer resin such as polyethersulphone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Here, the substrate 100 may be modified in various ways, such as having a multi-layer structure including two layers each containing such a polymer resin and a barrier layer containing an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) interposed between the layers.

[0059] A display element and a thin film transistor TFT electrically connected to the display element may be located on the substrate 100. In Fig. 5, an organic light emitting element OLED is illustrated as being located on the substrate 100 as a display element. Such an organic light emitting element OLED being electrically connected to the thin film transistor TFT may be understood as meaning that a pixel electrode included in the organic light emitting element OLED is electrically connected to the thin film transistor TFT.

[0060] A pixel circuit PC can be disposed on the substrate 100. Since the structure of the pixel circuit PC of each pixel PX is the same as that of the other pixels PX, the following description will focus on one pixel circuit PC.

[0061] The pixel circuit PC includes a plurality of thin film transistors TFT and a storage capacitor Cst. For convenience of illustration, one thin film transistor TFT is shown in FIG. 5, but such a thin film transistor TFT may correspond to the driving thin film transistor T1 (FIG. 2) described above.

[0062] A buffer layer 201 including an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride may be interposed between the thin film transistor TFT and the substrate 100. Here, it goes without saying that the buffer layer 201 may also be located under the pad 400. Such a buffer layer 201 may play a role in increasing the smoothness of the upper surface of the substrate 100 or in preventing or minimizing the penetration of impurities from the substrate 100 into the semiconductor layer Act of the thin film transistor TFT.

[0063] As shown in Fig. 5, the thin film transistor TFT includes a semiconductor layer Act including amorphous silicon, polycrystalline silicon, an organic semiconductor material, or an oxide semiconductor material. The thin film transistor TFT also includes a gate electrode GE, a source electrode SE, and / or a drain electrode DE. The gate electrode GE may include various conductive materials and have various layered structures, for example, a Mo layer and an Al layer. Alternatively, the gate electrode GE may be a TiN x The source electrode SE and the drain electrode DE may also include various conductive materials and have various layered structures, for example including a Ti layer, an Al layer, and / or a Cu layer.

[0064] In order to ensure insulation between the semiconductor layer Act and the gate electrode GE, a gate insulating layer 203 containing an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride may be interposed between the semiconductor layer Act and the gate electrode GE. In FIG. 5, the gate insulating layer 203 is illustrated as having a shape corresponding to the entire surface of the substrate 100 and having a structure in which contact holes are formed in predetermined portions, but the present invention is not limited thereto. For example, the gate insulating layer 203 may be patterned to have the same shape (e.g., the same planar shape) as the gate electrode GE.

[0065] Additionally, a first interlayer insulating layer 205 containing an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be disposed on the gate electrode GE. The first interlayer insulating layer 205 may have a single-layer structure or a multi-layer structure containing the above-mentioned materials. In this manner, an insulating film containing an inorganic material may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). This also applies to the following embodiments and their modified examples.

[0066] The storage capacitor Cst may also include a first electrode CE1 and a second electrode CE2 overlapping each other with a first interlayer insulating layer 205 sandwiched therebetween. The storage capacitor Cst may overlap a thin film transistor TFT. In this regard, in the example of FIG. 5, a gate electrode GE of the thin film transistor TFT is used as the first electrode CE1 of the storage capacitor Cst. However, the present invention is not limited thereto. For example, the storage capacitor Cst may not overlap the thin film transistor TFT. The second electrode CE2 of the storage capacitor Cst may also include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multi-layer structure or a single-layer structure including the above-mentioned materials.

[0067] A second interlayer insulating layer 207 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be disposed on the second electrode CE2 of the storage capacitor Cst. The second interlayer insulating layer 207 may have a single-layer structure or a multi-layer structure including the above-mentioned materials.

[0068] The source electrode SE and the drain electrode DE may be disposed on such a second interlayer insulating layer 207. The data line DL is located on the same layer as the source electrode SE and the drain electrode DE, and may also contain the same material. When elements (layers) are on the same layer and / or contain the same material, these elements may be in the same layer as each other as parts of the same material layer, or may be in the same layer as each other while forming an interface with the same lower or upper layer, or may be formed by the same process, etc. However, the present invention is not limited thereto.

[0069] The source electrode SE, the drain electrode DE, and the data line DL may include a material having excellent conductivity. The source electrode SE and the drain electrode DE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multi-layer structure or a single-layer structure including such materials. For example, the source electrode SE, the drain electrode DE, and the data line DL may have a Ti / Al / Ti multi-layer structure.

[0070] However, it is needless to say that the present invention is not limited thereto. For example, the thin film transistor TFT may have only one of the source electrode SE and the drain electrode DE, or may have neither of them. For example, one thin film transistor TFT may not have a drain electrode DE, and another thin film transistor TFT connected to the thin film transistor TFT may not have a source electrode SE, and the semiconductor layers Act of the two thin film transistors may be connected to each other. Such a connection structure may produce the same effect as one thin film transistor TFT having a source electrode SE and another thin film transistor TFT having a drain electrode DE, and the source electrode SE of one thin film transistor TFT being connected to the drain electrode DE of the other thin film transistor TFT.

[0071] As shown in FIG. 5, the organic insulating layer 208 may be disposed to cover the thin film transistor TFT and the storage capacitor Cst. The organic insulating layer 208 may include an organic insulating material. For example, the organic insulating layer 208 may include a photoresist, BCB (benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), PMMA (polymethylmethacrylate), polystyrene, a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof. Although not shown in FIG. 5, a third interlayer insulating layer (not shown) may be further disposed under the organic insulating layer 208. The third interlayer insulating layer may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0072] A connecting metal layer CM may be disposed on the organic insulating layer 208, and the planarization layer 209 may cover the connecting metal layer CM. The connecting metal layer CM may include conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multi-layer structure or a single-layer structure including such materials. For example, the connecting metal layer CM may have a Ti / Al / Ti multi-layer structure. The connecting metal layer CM may include a plurality of connecting patterns arranged along the substrate 100.

[0073] The planarization layer 209 can provide a flat upper surface for the organic light emitting element OLED disposed thereon. The planarization layer 209 can also include an organic insulating material. For example, the planarization layer 209 can include photoresist, BCB, polyimide, HMDSO, PMMA, polystyrene, polymer derivatives having a phenol group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0074] The pad 400 may be disposed on the organic insulating layer 208, and the planarization layer 209 may cover the pad 400. The pad 400 may include the same material as the connection metal layer CM. Specifically, the pad 400 may include conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multi-layer structure or a single-layer structure including the above materials. For example, the pad 400 may have a Ti / Al / Ti multi-layer structure. The planarization layer 209 may include a plurality of holes HC, HP, H1-1, and H2-1. A detailed description of the plurality of holes will be given later.

[0075] In the display area DA, an organic light emitting element OLED may be disposed on the planarization layer 209. Specifically, a first organic light emitting element OLED1 and a second organic light emitting element OLED2 adjacent to each other along a first direction (D1) may be disposed on the planarization layer 209, and a third organic light emitting element OLED3 may be disposed on the planarization layer 209 adjacent to the first organic light emitting element OLED1 along a second direction (D2) intersecting the first direction (D1). The first organic light emitting element OLED1, the second organic light emitting element OLED2, and the third organic light emitting element OLED3 may each emit light of a different color. For example, the first organic light emitting element OLED1 may emit green light, the second organic light emitting element OLED2 may emit red light, and the third organic light emitting element OLED3 may emit blue light.

[0076] The first organic light emitting element OLED1 also includes a first pixel electrode 210-1, a first intermediate layer 220-1 including a first light emitting layer 222-1, and a counter electrode 230. The second organic light emitting element OLED2 also includes a second pixel electrode 210-2, a second intermediate layer 220-2 including a second light emitting layer 222-2, and a counter electrode 230. The third organic light emitting element OLED3 also includes a third pixel electrode 210-3, a third intermediate layer 220-3 including a third light emitting layer 222-3, and a counter electrode 230.

[0077] The first pixel electrode 210-1 may be disposed on the planarization layer 209. The second pixel electrode 210-2 may be disposed on the planarization layer 209 along a first direction (D1) so as to be adjacent to the first pixel electrode 210-1, and the third pixel electrode 210-3 may be disposed on the planarization layer 209 along a second direction (D2) intersecting the first direction (D1) so as to be adjacent to the first pixel electrode 210-1. The first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may be formed of a material such as ITO, In 2 O 3 Alternatively, the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may include a transparent conductive layer formed of a transparent conductive oxide such as IZO, and a reflective layer formed of a metal such as Al or Ag. For example, the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may have a three-layer structure of ITO / Ag / ITO.

[0078] 5, the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may contact one of the source electrode SE and the drain electrode DE through a connection metal layer CM and be electrically connected to the thin film transistor TFT. The connection metal layer CM may be interposed between the thin film transistor TFT and each of the pixel electrodes 210-1, 210-2, and 210-3. The connection metal layer CM may be connected to the thin film transistor TFT through a contact hole formed (or provided) in the organic insulating layer 208.

[0079] A pixel defining film 215 may be disposed on the planarization layer 209. The pixel defining film 215 has an opening 215OP corresponding to each pixel PX, i.e., an opening 215OP exposing at least the center of the pixel electrodes 210-1, 210-2, and 210-3 to the outside of the pixel defining film 215, thereby defining the region of each pixel PX. In addition, in the case shown in FIG. 5, the pixel defining film 215 increases the distance between the edges of the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 and the counter electrode 230 on the top of the first pixel electrode 210-1, the top of the second pixel electrode 210-2, and the top of the third pixel electrode 210-3, thereby preventing arcs (e.g., electrical arcs) from occurring at the edges of the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3. Such pixel defining films 215 may also include, for example, polyimide or organic materials such as HMDSO.

[0080] A first intermediate layer 220-1 may be disposed on the first pixel electrode 210-1. A second intermediate layer 220-2 may be disposed on the second pixel electrode 210-2, and a third intermediate layer 220-3 may be disposed on the third pixel electrode 210-3. The first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 may include a low molecular weight material or a high molecular weight material.

[0081] When the first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 contain a low molecular weight material, the first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc. are stacked in a single or composite structure, and may be formed (or provided) by a vacuum deposition method.

[0082] When the first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 include a polymer material, the intermediate layers 220-1, 220-2, and 220-3 may have a structure including a hole transport layer (HTL) and an emission layer (EML). In this case, the hole transport layer includes PEDOT (poly(3,4-ethylenedioxythiophene)), and the emission layers 222-1, 222-2, and 222-3 may include a polymer material such as a PPV (polyphenylene vinylene) system or a polyfluorene system. Such first intermediate layer 220-1, second intermediate layer 220-2, and third intermediate layer 220-3 may be formed by a screen printing method, an inkjet printing method, a laser induced thermal imaging (LITI), or the like. The first intermediate layer 220-1, the second intermediate layer 220-2 and the third intermediate layer 220-3 may include a layer that is integral with the plurality of pixel electrodes 210-1, 210-2 and 210-3, or may include layers patterned to correspond to the plurality of pixel electrodes 210-1, 210-2 and 210-3, respectively. A detailed description of the structures of the first intermediate layer 220-1, the second intermediate layer 220-2 and the third intermediate layer 220-3 will be provided later.

[0083] The counter electrode 230 may be disposed above the display area DA so as to cover the display area DA. That is, the counter electrode 230 may be integrally formed in the plurality of organic light emitting elements OLED1, OLED2, and OLED3, and may correspond to the plurality of pixel electrodes 210-1, 210-2, and 210-3. For example, the counter electrode 230 may be disposed so as to overlap with all of the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3. The counter electrode 230 may be disposed so as to cover not only the display area DA but also the peripheral area PA (FIG. 1).

[0084] Such a counter electrode 230 may be made of ITO, In 2 O 3 Alternatively, the counter electrode 230 may include a transparent conductive layer formed of IZO, or may include a semi-transparent film containing a metal such as Al or Ag. For example, the counter electrode 230 may be a semi-transparent film containing Mg or Ag. Although not shown in FIG. 5, a capping layer (not shown) may be located on the counter electrode 230. For example, the capping layer may include a material selected from an organic material, an inorganic material, and a mixture thereof, and may be provided as a single layer or multiple layers. As an optional embodiment, a LiF layer may be located on the capping layer.

[0085] As described above, the planarization layer 209 may include or define a plurality of holes HC, HP, H1-1, and H2-1. As shown in FIG. 6, which is an enlarged cross-sectional view of part A of FIG. 5, the planarization layer 209 may also include contact holes HC. The pixel electrodes 210-1, 210-2, and 210-3 may be connected to the connection metal layer CM through the contact holes HC formed in the planarization layer 209, or may be connected to the connection metal layer CM within the contact holes HC. That is, the pixel electrodes 210-1, 210-2, and 210-3 may be electrically connected to the thin film transistors TFT through the contact holes HC, the connection metal layer CM, and the contact holes formed in the organic insulating layer 208, which are formed in the planarization layer 209.

[0086] The inner side surface HCa (e.g., a first inner side surface) of the planarization layer 209 defining the contact holes HC also includes a forward tapered inclined surface. The fact that an inner side surface of a layer defining a certain hole includes a forward tapered inclined surface means that the width of the portion of the hole in the direction opposite to the substrate 100 (+z direction) is wider than the width of the portion of the hole in the direction toward the substrate 100 (-z direction). That is, the width of each hole decreases (e.g., along a plane) as the distance along the z direction relative to the substrate 100 decreases, while the width of each hole increases as the distance along the z direction relative to the substrate 100 increases. In contrast, the fact that an inner side surface of a layer defining a certain hole includes a reverse tapered inclined surface means that the width of the portion of the hole in the direction opposite to the substrate 100 (+z direction) is narrower than the width of the portion of the hole in the direction toward the substrate 100 (-z direction). That is, as the distance along the z-direction relative to the substrate 100 decreases, the width of each hole increases (e.g., along a plane), while as the distance along the z-direction relative to the substrate 100 increases, the width of each hole decreases.

[0087] The inner side surface HCa of such a layer defining the contact hole HC includes a forward tapered inclined surface, which can improve step coverage of the pixel electrodes 210-1, 210-2, and 210-3 formed on the planarization layer 209. That is, the pixel electrodes 210-1, 210-2, and 210-3 formed on the planarization layer 209 are accurately connected to the connection metal layer CM through the contact hole HC.

[0088] As shown in FIG. 7, which is an enlarged cross-sectional view of part B in FIG. 5, the planarization layer 209 also includes a pad hole HP. The upper surface of the pad 400 may be exposed to the outside (e.g., to the outside of the planarization layer 209) through the pad hole HP. The inner side surface HPa (e.g., the second inner side surface) of the planarization layer 209 defining the pad hole HP also includes a forward tapered inclined surface. If the inner side surface HPa of such a layer defining the pad hole HP includes a reverse tapered inclined surface, moisture or the like may exist between the pad 400 and the inner side surface HPa of the pad hole HP. As a result, even if an electrical signal is applied only to a specific pad 400 among the multiple pads 400, the electrical signal may be unintentionally applied to a pad 400 adjacent to the specific pad 400 through moisture or the like existing between the pad 400 and the inner side surface HPa of such a layer defining the pad hole HP. However, in the case of the display device 1 according to this embodiment, since the inner surface HPa of such a layer defining the pad hole HP includes a forward tapered inclined surface as shown in FIG. 7, there is no moisture or the like between the pad 400 and the inner surface HPa of such a layer defining the pad hole HP, or the moisture or the like can be minimized.

[0089] The pad 400 exposed through the pad hole HP may be electrically connected to a driving chip (not shown) included in the display device 1 via an anisotropic conductive film or the like. The driving chip may be, for example, an IC chip, and the driving chip may have a body and output terminals and input terminals located on both sides of the body. That is, the pad 400 may be electrically connected to the driving chip by pressing down the anisotropic conductive film placed between the pad 400 and the input terminal and / or output terminal of the driving chip.

[0090] The thickness of one layer is also the maximum thickness at a position of one layer. The thickness t2 of the planarization layer 209 on the pad 400 (or corresponding to the pad 400) may be different from the thickness t1 of the planarization layer 209 on the display area DA. Specifically, the thickness t2 of the planarization layer 209 on the pad 400 is thinner than the thickness t1 of the planarization layer 209 on the display area DA. If the thickness t2 of the planarization layer 209 on the pad 400 is thick, pressure may not be applied sufficiently to the output terminal and / or input terminal of the driver chip, and the pad 400 may not be electrically connected to the driver chip. However, the thickness t2 of the planarization layer 209 on the pad 400 of the display device 1 according to the present embodiment is thinner than the thickness t1 on the display area DA. In such a case, pressure may be applied sufficiently to the output terminal and / or input terminal of the driver chip, so that the pad 400 may be stably connected to the driver chip. Therefore, there is no failure in the driver chip connection or it may be minimized.

[0091] Hereinafter, the laminated structure of the intermediate layers 220-1, 220-2, and 220-3 of the organic light emitting elements OLED1, OLED2, and OLED3 will be described in detail with reference to FIG.

[0092] The first intermediate layer 220-1 may include a first common layer 221, a first light emitting layer 222-1, and a second common layer 227. The first light emitting layer 222-1 may include a polymer organic material or a low molecular weight organic material that emits a predetermined color light. That is, the first light emitting layer 222-1 may emit light in a predetermined wavelength band. The second light emitting layer 222-2 of the second organic light emitting element OLED2 may emit light in a different wavelength band from the first light emitting layer 222-1 of the first organic light emitting element OLED1. The third light emitting layer 222-3 of the third organic light emitting element OLED3 may emit light in a different wavelength band from the first light emitting layer 222-1 of the first organic light emitting element OLED1 and the second light emitting layer 222-2 of the second organic light emitting element OLED2. For example, the first light emitting layer 222-1, the second light emitting layer 222-2, and the third light emitting layer 222-3 may emit green light, red light, and blue light, respectively. Green light is light that belongs to a wavelength band of about 495 nm to about 580 nm, red light is light that belongs to a wavelength band of about 580 nm to about 780 nm, and blue light is light that belongs to a wavelength band of about 400 nm to about 495 nm.

[0093] 5, the first organic light emitting element OLED1 may have a tandem structure. Specifically, the first organic light emitting element OLED1 may include a first lower light emitting layer 222L-1 and a first upper light emitting layer 222U-1, and the first upper light emitting layer 222U-1 may be disposed on the first lower light emitting layer 222L-1 so as to overlap with the first lower light emitting layer 222L-1. Similarly, the second organic light emitting element OLED2 may include a second lower light emitting layer 222L-2 and a second upper light emitting layer 222U-2, and the second upper light emitting layer 222U-2 may be disposed on the second lower light emitting layer 222L-2 so as to overlap with the second lower light emitting layer 222L-2. Similarly, the third organic light emitting element OLED3 may include a third lower light emitting layer 222L-3 and a third upper light emitting layer 222U-3, and the third upper light emitting layer 222U-3 may be disposed on the third lower light emitting layer 222L-3 so as to overlap with the third lower light emitting layer 222L-3. That is, the first light emitting layer 222-1 may include the first lower light emitting layer 222L-1 and the first upper light emitting layer 222U-1, the second light emitting layer 222-2 may include the second lower light emitting layer 222L-2 and the second upper light emitting layer 222U-2, and the third light emitting layer 222-3 may include the third lower light emitting layer 222L-3 and the third upper light emitting layer 222U-3.

[0094] A first common layer 221 may be interposed between the first pixel electrode 210-1 and the first lower light emitting layer 222L-1, between the second pixel electrode 210-2 and the second lower light emitting layer 222L-2, and between the third pixel electrode 210-3 and the third lower light emitting layer 222L-3. The first common layer 221 may have a single layer structure or a multi-layer structure. For example, when the first common layer 221 is formed of a polymer material, the first common layer 221 is a hole transport layer (HTL) having a single layer structure, and may be formed of polyethylenedioxythiophene (PEDOT), polyaniline (PANI), TPD (N,N'-diphenyl-N,N'-bis(3-methylphenyl)-1,1'-bi-phenyl-4,4'-diamine), or NPB (N,N'-di(naphthalen-1-yl)-N,N'-diphenyl-benzidine). When the first common layer 221 is formed of a low molecular weight material, the first common layer 221 also includes a hole injection layer (HIL) and a hole transport layer (HTL).

[0095] A second common layer 227 may be disposed on the first upper light emitting layer 222U-1, the second upper light emitting layer 222U-2, and the third upper light emitting layer 222U-3. The second common layer 227 is not always provided. For example, when the first common layer 221, the first light emitting layer 222-1, the second light emitting layer 222-2, and the third light emitting layer 222-3 are formed of a polymer material, it is preferable to form the second common layer 227. The second common layer 227 may have a single layer structure or a multilayer structure. The second common layer 227 may also include an electron transport layer (ETL) and / or an electron injection layer (EIL). A counter electrode 230 may be disposed on the second common layer 227.

[0096] The first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 may further include a charge generation layer 224. The charge generation layer 224 may be located between the first lower light emitting layer 222L-1 and the first upper light emitting layer 222U-1, between the second lower light emitting layer 222L-2 and the second upper light emitting layer 222U-2, and between the third lower light emitting layer 222L-3 and the third upper light emitting layer 222U-3. The charge generation layer 224 may serve to supply charges to a first stack including the first lower light emitting layer 222L-1, the second lower light emitting layer 222L-2, and the third lower light emitting layer 222L-3, and a second stack including the first upper light emitting layer 222U-1, the second upper light emitting layer 222U-2, and the third upper light emitting layer 222U-3.

[0097] The first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 may further include a third common layer 223 and a fourth common layer 225. The third common layer 223 may be located between the first lower light emitting layer 222L-1 and the charge generation layer 224, between the second lower light emitting layer 222L-2 and the charge generation layer 224, and between the third lower light emitting layer 222L-3 and the charge generation layer 224. The fourth common layer 225 may be located between the charge generation layer 224 and the first upper light emitting layer 222U-1, between the charge generation layer 224 and the second upper light emitting layer 222U-2, and between the charge generation layer 224 and the third upper light emitting layer 222U-3. The third common layer 223 may include an electron transport layer, and the fourth common layer 225 may include a hole transport layer.

[0098] For example, the first intermediate layer 220-1 includes the first common layer 221, the first lower light-emitting layer 222L-1, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the first upper light-emitting layer 222U-1, and the second common layer 227. Similarly, the second intermediate layer 220-2 includes the first common layer 221, the second lower light-emitting layer 222L-2, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second upper light-emitting layer 222U-2, and the second common layer 227. Similarly, the third intermediate layer 220-3 includes the first common layer 221, the third lower light-emitting layer 222L-3, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the third upper light-emitting layer 222U-3, and the second common layer 227.

[0099] As shown in FIG. 8, which is a schematic enlarged cross-sectional view of part C of FIG. 5, the display device 1 also includes a first hole H1. Specifically, the planarization layer 209 includes a 1-1 hole H1-1 disposed between the first pixel region PXA1 and the second pixel region PXA2, and the pixel defining film 215 also includes a 1-2 hole H1-2 overlapping with the 1-1 hole H1-1. The first hole H1 also includes a 1-1 hole H1-1 and a 1-2 hole H1-2 overlapping (or aligned) with the 1-1 hole H1-1. The organic insulating layer 208 may be exposed to the outside of the planarization layer 209, the pixel defining film 215, each intermediate layer, and the counter electrode 230.

[0100] The inner side H1-2a (e.g., the fifth inner side) of the 1-2 hole H1-2 (e.g., the layer defining the 1-2 hole H1-2) also includes a forward tapered inclined surface. Since the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227, and the counter electrode 230 are integrally formed across a plurality of organic light-emitting elements OLED, such layers may cover a portion of the 1-2 hole H1-2 (e.g., the sidewall of the layer defining the 1-2 hole H1-2). Specifically, the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227, and the counter electrode 230 may cover the inner side H1-2a of the 1-2 hole H1-2.

[0101] In addition, the inner side surface H1-1a (e.g., the third inner side surface) of the planarization layer 209 defining the 1-1 hole H1-1 also includes an inclined surface having an inverse tapered shape. As a result, among the layers disposed on the planarization layer 209, layers integrally formed in the first organic light emitting element OLED1 and the second organic light emitting element OLED2, such as the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227, and the counter electrode 230, may be disconnected or separated on the 1-1 hole H1-1.

[0102] Specifically, in the first pixel region PXA1, the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227, and the counter electrode 230 are located on the pixel defining film 215. In the second pixel region PXA2, the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227, and the counter electrode 230 are also located on the pixel defining film 215, but in the 1-1 hole H1-1, the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227, and a part of the counter electrode 230 may be located on the organic insulating layer 208. That is, the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227 and the counter electrode 230 located in the first pixel region PXA1 are each connected to the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227 and the counter electrode 230 located in the second pixel region PXA2, but are separated from each other in a portion of the boundary between the first pixel region PXA1 and the second pixel region PXA2, i.e., the 1-1 hole H1-1. Since the inner side surface H1-1a of the 1-1 hole H1-1 includes an inverted tapered inclined surface, the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227 and the counter electrode 230 do not cover or extend along the inner side surface H1-1a of the 1-1 hole H1-1.

[0103] For the sake of convenience, the layer located in the 1-1 hole H1-1 will be referred to as the first remaining layer 310. Therefore, the first remaining layer 310 also includes the 1-1 remaining common layer 221a, the 1-3 remaining common layer 223a, the first remaining charge generation layer 224a, the 1-4 remaining common layer 225a, the 1-2 remaining common layer 227a, and the first remaining counter electrode 230a, which correspond to the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227, and the counter electrode 230, respectively. That is, the first remaining layer 310 includes at least a part of the same material as the intermediate layers 220-1, 220-2, and 220-3, and also includes the same material as the counter electrode 230. In one embodiment, the organic insulating layer 208 faces the pixel defining film 215 with the planarization layer 209 interposed therebetween, the organic insulating layer 208 is exposed to the outside of the planarization layer 209 through the 1-1 hole H1-1, and the first remaining layer 310 is located inside the 1-1 hole H1-1 of the planarization layer 209. The intermediate layer and the counter electrode 230 are both disconnected at the 1-1 hole H1-1 of the planarization layer 209, and the first remaining layer 310 includes the disconnected portion of the intermediate layer as well as the disconnected portion of the counter electrode 230. Since the inner side surface H1-1a of the 1-1 hole H1-1 includes a reverse tapered inclined surface, the width of the 1-1 hole H1-1 in the substrate 100 direction (-z direction) is wider than the width in the opposite direction (+z direction), so that the first remaining layer 310 does not contact the inner side surface H1-1a of the 1-1 hole H1-1.

[0104] Since there are layers integrally formed between the first organic light emitting element OLED1 and the second organic light emitting element OLED2, a leakage current may flow between the first organic light emitting element OLED1 and the second organic light emitting element OLED2 through such layers. For example, even when a current is supplied only to the first organic light emitting element OLED1 emitting green light, a current may also be supplied to the adjacent second organic light emitting element OLED2 through layers integrally formed between the first organic light emitting element OLED1 and the second organic light emitting element OLED2, such as the first common layer 221, the second common layer 227, the charge generation layer 224, the third common layer 223, and / or the fourth common layer 225. As a result, not only green light is emitted from the first organic light emitting element OLED1, but also red light is emitted from the second organic light emitting element OLED2, which may cause a problem of degraded display quality such as a decrease in color purity.

[0105] However, in the case of the display device 1 of this embodiment, as described above, the planarization layer 209 provides a 1-1 hole H1-1 arranged between the first pixel area PXA1 and the second pixel area PXA2, and the inner surface H1-1a of the planarization layer 209 from the 1-1 hole H1-1 also includes an inverted tapered inclined surface. As a result, the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227 and the counter electrode 230 located in the first pixel region PXA1 are each connected to the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227 and the counter electrode 230 located in the second pixel region PXA2 in the surrounding areas of various holes (see Figure 4), but are separated from each other in a portion of the boundary between the first pixel region PXA1 and the second pixel region PXA2, i.e., the 1-1 hole H1-1.

[0106] As a result, even if a layer disposed on the planarization layer 209 is integrally formed over the first organic light emitting element OLED1 and the second organic light emitting element OLED2, no current leaks between the first organic light emitting element OLED1 and the second organic light emitting element OLED2 through such a layer, or even if a current leaks, the amount of current is minimized. In other words, even if a layer disposed on the planarization layer 209 is integrally formed over a plurality of organic light emitting elements OLEDs, no current leaks between the organic light emitting elements OLEDs through such a layer, or even if a current leaks, the amount of current is minimized.

[0107] In order to prevent current from leaking between the organic light emitting devices OLED or to minimize the amount of current leakage, if any, it is possible to separately form a separator including an inclined surface with an inverse tapered shape. In such a case, an additional manufacturing process is required to form the separator. However, in the case of the display device 1 according to the present embodiment, the existing planarization layer 209 is formed to include the 1-1 hole H1-1 whose inner side surface H1-1a is inverse tapered and the 2-1 hole H2-1 whose inner side surface H2-1a (e.g., the fourth inner side surface) of the planarization layer 209 is inverse tapered, and the existing pixel definition film 215 is formed to include the 1-2 hole H1-2 and the 2-2 hole H2-2 corresponding to the 1-1 hole H1-1 and the 2-1 hole H2-1, respectively, so that no additional manufacturing process is required. Therefore, in the case of the display device 1 according to the present embodiment, it is possible to prevent current from leaking between the organic light emitting devices OLED or to minimize the amount of current leakage, if any, while maintaining the manufacturing cost.

[0108] In addition, since such an organic light emitting element OLED may be easily damaged by moisture or oxygen from the outside, the organic light emitting element OLED may be covered with a sealing layer (not shown) to protect them. The sealing layer may include a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer, and may cover the display area DA and extend to the outside of the display area DA. Since the display device 1 according to the present embodiment includes the holes H1 and H2, the counter electrode 230 may be formed to be curved, and the surface area of ​​the counter electrode 230 may be increased. Therefore, since the sealing layer is formed on the counter electrode 230, the bonding strength between the sealing layer and the counter electrode 230 may be increased.

[0109] As shown in Fig. 9, which is an enlarged cross-sectional view of part D in Fig. 5, the display device 1 further includes a second hole H2. Specifically, the planarization layer 209 includes a 2-1 hole H2-1 disposed between the first pixel region PXA1 and the third pixel region PXA3, and the pixel defining film 215 includes a 2-2 hole H2-2 overlapping with the 2-1 hole H2-1. The second hole H2 also includes a 2-1 hole H2-1 and a 2-2 hole H2-2 overlapping with the 2-1 hole H2-1. An inner side H2-2a (e.g., a sixth inner side) of the 2-2 hole H2-2 includes a forward tapered inclined surface, and an inner side H2-1a of the 2-1 hole H2-1 also includes a reverse tapered inclined surface. The second remaining layer 320 is located in the 2-1 hole H2-1, and the second remaining layer 320 may include a 2-1 remaining common layer 221b, a 2-3 remaining common layer 223b, a second remaining charge generation layer 224b, a 2-4 remaining common layer 225b, a 2-2 remaining common layer 227b, and a second remaining counter electrode 230b, which correspond to the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227, and the counter electrode 230, respectively. The contents described for the first hole H1 and the first remaining layer 310 may also be applied to the second hole H2 and the second remaining layer 320, so that the duplicated description thereof will be omitted.

[0110] In the display device 1 according to the present embodiment, as described above, the planarization layer 209 includes the 2-1 hole H2-1 disposed between the first pixel region PXA1 and the third pixel region PXA3, and the inner side surface H2-1a of the 2-1 hole H2-1 also includes an inverted tapered inclined surface. As a result, the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227, and the counter electrode 230 located in the first pixel region PXA1 are connected to the first common layer 221, the third common layer 223, the charge generation layer 224, the fourth common layer 225, the second common layer 227, and the counter electrode 230 located in the third pixel region PXA3 in the peripheral regions of the various holes (see FIG. 4), but are separated from each other in a part of the boundary between the first pixel region PXA1 and the third pixel region PXA3, i.e., in the 2-1 hole H2-1.

[0111] As a result, even if a layer disposed on the planarization layer 209 is integrally formed over the first organic light emitting element OLED1 and the third organic light emitting element OLED3, no current leaks between the first organic light emitting element OLED1 and the third organic light emitting element OLED3 through such a layer, or even if a current leaks, the amount of current is minimized. In other words, even if a layer disposed on the planarization layer 209 is integrally formed over a plurality of organic light emitting elements OLEDs, no current leaks between the organic light emitting elements OLEDs through such a layer, or even if a current leaks, the amount of current is minimized.

[0112] In Fig. 4, the first hole H1 and the second hole H2 are illustrated as being spaced apart from each other, but the present invention is not limited thereto. For example, as illustrated in Fig. 10, which is a plan view that illustrates a part of a display device 1 according to an embodiment of the present invention, the first hole H1 and the second hole H2 may be connected to each other. That is, the 1-1 hole H1-1 of the first hole H1 and the 2-1 hole H2-1 of the second hole H2 may be connected to each other, and the 1-2 hole H1-2 of the first hole H1 and the 2-2 hole H2-2 of the second hole H2 may be connected to each other.

[0113] Although the display device 1 has been described above, the present invention is not limited thereto. A method for manufacturing (or providing) such a display device 1 will be described below.

[0114] 11 to 15 are cross-sectional views that diagrammatically illustrate a process for manufacturing the display device 1 of FIG 1. Specifically, FIG 11 to 15 are cross-sectional views that diagrammatically illustrate a process for forming (or providing) the planarization layer 209 and the pixel defining layer 215 of the display device 1 of FIG 1.

[0115] 11, a connection metal layer CM and a pad 400 may be formed on the substrate 100. Specifically, a connection metal layer forming material may be deposited on the entire surface of the substrate 100 using a sputtering method or the like, and then the connection metal layer CM and the pad 400 may be patterned to form the connection metal layer CM and the pad 400. That is, the connection metal layer CM and the pad 400 are patterns of the same material layer and may be considered to be in the same layer on the substrate 100. The connection metal layer forming material may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc.

[0116] Next, as shown in FIG. 12, a planarization layer forming layer 260 may be formed to cover the connection metal layer CM and the pad 400. In this specification, the "planarization layer forming layer 260" refers to a layer (e.g., a preliminary planarization layer) that is not patterned into the shape of the planarization layer 209 after applying a planarization layer forming material. Specifically, the planarization layer forming layer 260 may be formed to cover the connection metal layer CM and the pad 400 by applying a negative photoresist to the entire surface of the substrate 100. Photoresists may be classified into positive photoresists and negative photoresists. The positive photoresist refers to a photoresist that is increased in solubility in a developer by exposure, and the negative photoresist refers to a photoresist that is decreased in solubility in a developer by exposure. As a result, when a partially exposed positive photoresist is developed, a pattern in which the exposed portions are removed is generated, and when a partially exposed negative photoresist is developed, a pattern in which the unexposed portions are removed is generated.

[0117] 13, a half-tone mask M may be positioned on the planarization layer forming layer 260. The half-tone mask M may include a first shielding portion SU1, a first semi-transmitting portion SPU1 surrounding the first shielding portion SU1, a second-first shielding portion SU2-1 (e.g., a first sub-portion), a second-second shielding portion SU2-2 (e.g., a second sub-portion), a third shielding portion SU3, a second semi-transmitting portion SPU2 surrounding the third shielding portion SU3, and a transmissive portion PU. The second-first shielding portion SU2-1 may be positioned away from the first shielding portion SU1 and the first semi-transmitting portion SPU1 in a first direction (D1), and the second-second shielding portion SU2-2 may be positioned away from the first shielding portion SU1 and the first semi-transmitting portion SPU1 in a second direction (D2) intersecting the first direction (D1). A portion of the mask surrounding another portion of the mask may form an interface between the two portions, but is not limited to this. For example, the first semi-transparent portion SPU1 surrounding the first shielding portion SU1 may be formed immediately adjacent to the first shielding portion SU1.

[0118] Specifically, the first shielding portion SU1 may be positioned together with the first semi-transparent portion SPU1 on the connecting metal layer CM or to correspond to the connecting metal layer CM, the 2-1 shielding portion SU2-1 may be positioned away from the connecting metal layer CM in a first direction (D1), the 2-2 shielding portion SU2-2 may be positioned away from the connecting metal layer CM in a second direction (D2) intersecting the first direction (D1), and the third shielding portion SU3 may be positioned together with the second semi-transparent portion SPU2 surrounding the third shielding portion SU3 on the pad 400 or to correspond to the pad 400.

[0119] After the halftone mask M is positioned to face the planarization layer forming layer 260, an exposure process may be performed in which the planarization layer forming layer 260 is irradiated with light such as ultraviolet light through the halftone mask M. After the exposure process of the planarization layer forming layer 260, a development process may be performed in which a preset portion of the planarization layer forming layer 260 is removed, thereby forming a planarization layer 209 having a specific pattern. That is, as shown in FIG. 14, a contact hole HC having an inner surface HCa including a forward tapered inclined surface defined along the sidewall of the planarization layer 209 is formed in a portion of the planarization layer 209 located under the first shielding portion SU1 and the first semi-transmitting portion SPU1, and a 1-1 hole H1-1 having an inner surface H1-1a including a reverse tapered inclined surface defined along the sidewall of the planarization layer 209 is formed in a portion of the planarization layer 209 located under the 2-1 shielding portion SU2-1. In a portion of the planarization layer 209 located below the 2-2 shielding unit SU2-2, a 2-1 hole H2-1 is formed, the inner side surface H2-1a of which includes a reverse tapered inclined surface defined along the sidewall of the planarization layer 209, and in a portion of the planarization layer 209 located below the third shielding unit SU3 and the second semi-transmitting unit SPU2, a pad hole HP is formed, the inner side surface HPa of which includes a forward tapered inclined surface. The connection metal layer CM and the pad 400 are exposed to the outside of the planarization layer 209 through the respective holes defined by the planarization layer 209.

[0120] As shown in Figs. 16 to 18, which are diagrams for explaining the taper angle of the negative photoresist, the taper direction of the negative photoresist may vary depending on the exposure dose. In Figs. 16 to 18, a half-tone mask M' is also shown for convenience. The half-tone mask M' also includes a shielding portion SU', a semi-transmitting portion SPU', and a transmitting portion PU'. The negative photoresist patterns P1, P2, and P3 of Figs. 16 to 18 are formed using the half-tone mask M', and during exposure, the transmitting portion PU' of the half-tone mask M' may be located on the portions corresponding to the central portions P1C, P2C, and P3C of the pattern, and the semi-transmitting portion SPU' of the half-tone mask M' may be located on the portions corresponding to the edges P1E, P2E, and P3E of the pattern. Here, it goes without saying that the shielding portion SU' of the halftone mask M' may be located on the outside of the pattern edges P1E, P2E, P3E or on the portion adjacent to the pattern edges P1E, P2E, P3E.

[0121] When the negative photoresist pattern P1 of Fig. 16 was exposed using a halftone mask M', the central part P1C of the pattern was irradiated with light having an amount of 80 mJ, and the edge P1E of the pattern was irradiated with light having an amount of 16 mJ. When the negative photoresist pattern P2 of Fig. 17 was exposed using a halftone mask M', the central part P2C of the pattern was irradiated with light having an amount of 60 mJ, and the edge P2E of the pattern was irradiated with light having an amount of 12 mJ. When the negative photoresist pattern P3 of Fig. 18 was exposed using a halftone mask M', the central part P3C of the pattern was irradiated with light having an amount of 40 mJ, and the edge P3E of the pattern was irradiated with light having an amount of 8 mJ.

[0122] The negative photoresist is photocured by exposure, and the solubility of the exposed portion in a developer is reduced. When the negative photoresist is exposed using the halftone mask M', if light having a sufficient amount of light is irradiated to completely photocure the negative photoresist, not only the portion located under the transmissive portion PU' but also the portion adjacent to the lower portion of the transmissive portion PU' may be exposed. As a result, the solubility of the portion adjacent to the lower portion of the transmissive portion PU' in a developer may also be reduced. Therefore, a pattern having a reverse tapered inclined surface may be formed, such as the negative photoresist pattern P1 in FIG. 16.

[0123] However, if the amount of light irradiated to the negative photoresist is not sufficient to completely photo-cure the negative photoresist, the irradiated portion may also be dissolved by the developer. Therefore, the inclination angle of the edge P2E of the pattern may be almost a right angle, as in the negative photoresist pattern P2 of Fig. 17. Furthermore, if the amount of light irradiated to the negative photoresist is smaller than that of the negative photoresist pattern P2 of Fig. 17, a pattern having a forward tapered inclined surface may be formed, as in the negative photoresist pattern P3 of Fig. 18.

[0124] As described above, the taper angle and direction of the negative photoresist may vary depending on the exposure dose. The planarization layer 209 portion located under the 2-1 shielding portion SU2-1 or the 2-2 shielding portion SU2-2 of the halftone mask M is irradiated with light sufficient to be photocured through the 2-1 shielding portion SU2-1 and the 2-2 shielding portion SU2-2 of the halftone mask M, so that the planarization layer 209 may include the 1-1 hole H1-1 having an inclined surface with an inverse tapered inner side H1-1a and the 2-1 hole H2-1 having an inclined surface with an inverse tapered inner side H2-1a. The amount of light irradiated to the planarization layer 209 may be adjusted by the first semi-transmitting portion SPU1 and the second semi-transmitting portion SPU2 of the halftone mask M. As a result, the planarization layer 209 can include a contact hole HC whose inner side surface HCa includes an inclined surface having a forward tapered shape, and a pad hole HP whose inner side surface HPa includes an inclined surface having a forward tapered shape. Furthermore, since the amount of light irradiated to the planarization layer 209 is adjusted by the second semi-transmissive unit SPU2, a part of the planarization layer 209 disposed on the pad 400 can be removed, so that the planarization layer 209 can be formed such that the thickness t2 of the planarization layer 209 disposed on the pad 400 is thinner than the thickness t1 of the planarization layer 209 disposed on the display area DA.

[0125] In one embodiment, the 2-1 shielding portion SU2-1 and the 2-2 shielding portion SU2-2 of the half-tone mask M may be connected to each other in the half-tone mask M. As a result, the inverse tapered 1-1 hole H1-1 and the inverse tapered 2-1 hole H2-1 may also be connected to each other (see FIG. 10).

[0126] 15, pixel electrodes 210-1, 210-2, and 210-3 are formed on the planarization layer 209, and then a pixel defining layer 215 including a 1-2 hole H1-2 overlapping with a 1-1 hole H1-1 and a 2-2 hole H2-2 overlapping with a 2-1 hole H2-1 may be formed. Specifically, a positive photoresist is applied, exposed to light using a mask, and then developed, so that the pixel defining layer 215 includes a 1-2 hole H1-2 and a 2-2 hole H2-2, and the inner side H1-2a of the 1-2 hole H1-2 and the inner side H2-2a of the 2-2 hole H2-2 include forward tapered inclined surfaces. However, the present invention is not limited thereto. For example, the pixel defining film 215 may be formed using a negative photoresist, and in this case, the inner side surface H1-2a of the 1-2 hole H1-2 and / or the inner side surface H2-2a of the 2-2 hole H2-2 may include an inverted tapered inclined surface. Here, it goes without saying that the pixel defining film 215 may define an opening 215OP that exposes the center portion of each of the pixel electrodes 210-1, 210-2, and 210-3 to the outside of the pixel defining film 215.

[0127] As described above, the present invention has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will understand that modifications and equivalent embodiments are possible therefrom. Therefore, the true technical scope of the present invention is defined by the technical ideas of the appended claims.

Claims

1. a substrate having a display area including a first pixel area and a second pixel area adjacent to each other along a first direction, and a peripheral area outside the display area; an organic insulating layer disposed on the substrate; a connecting metal layer disposed on the organic insulating layer; a planarization layer covering the connecting metal layer; The planarization layer is a first inner surface that defines a contact hole corresponding to the first pixel region and exposing at least a portion of the connection metal layer to an outside of the planarization layer, the first inner surface being a forward tapered inclined surface; a second inner surface that is an inverted tapered surface and that defines a 1-1 hole that is located between the first pixel region and the second pixel region along the first direction and exposes a portion of the organic insulating layer to the outside of the planarization layer.

2. 2. The display device of claim 1, wherein the 1-1 holes extend along a second direction intersecting the first direction.

3. the display region further includes a third pixel region arranged adjacent to the first pixel region along the second direction, the planarization layer further includes a third inner surface disposed between the first pixel region and the third pixel region along the second direction and defining a 2-1 hole extending along the first direction; The display device according to claim 2 , wherein the third inner side surface is an inverted tapered inclined surface.

4. The display device of claim 3, wherein the first-1 hole and the second-1 hole of the planarization layer are connected to each other.

5. The pixel defining layer is disposed on the planarization layer.

2. The display device of claim 1, wherein the pixel defining layer comprises a third inner surface defining a first-2 hole overlapping the first-1 hole.

6. The display device according to claim 5 , wherein the third inner side surface of the first-2 hole includes a forward tapered inclined surface.

7. the display region further includes a third pixel region arranged adjacent to the first pixel region along a second direction intersecting the first direction, the planarization layer further includes a fourth inner surface that is located between the first pixel region and the third pixel region along the second direction and defines a 2-1 hole that is extended along the first direction; The fourth inner surface includes a reverse tapered inclined surface, the pixel defining layer further includes a fifth inner surface defining a 2-2 hole overlapping the 2-1 hole, The display device according to claim 6 , wherein the fifth inner side surface includes a forward tapered inclined surface.

8. The display device of claim 7, wherein the first-2 hole and the second-2 hole of the pixel defining layer are connected to each other.

9. The display device according to claim 5 , further comprising a pad disposed in the peripheral region.

10. the planarization layer includes a fourth inner surface covering the pad and defining a pad hole exposing the pad to an outside of the planarization layer; The display device according to claim 9 , wherein the fourth inner side surface includes a forward tapered inclined surface.

11. The display device according to claim 10 , wherein a thickness of the planarization layer corresponding to the pads is smaller than a thickness of the planarization layer corresponding to the display area.

12. a pixel electrode interposed between the planarization layer and the pixel definition film; A counter electrode disposed to cover the pixel defining film; The display device according to claim 5 , further comprising an intermediate layer interposed between the pixel electrode and the counter electrode.

13. The display device of claim 12, wherein the intermediate layer and the counter electrode cover a third inner side surface that defines the first and second holes of the pixel defining layer.

14. The display device according to claim 13, wherein the intermediate layer and the counter electrode are located outside the 1-1 hole of the planarizing layer.

15. a residual layer located inside the first-1 hole of the planarization layer, the intermediate layer and the counter electrode are both disconnected at the 1-1 hole in the planarization layer, The display device according to claim 13 , wherein the remaining layer includes the interrupted portion of the intermediate layer together with the interrupted portion of the counter electrode.

16. The display device of claim 15, wherein the residual layer is disposed to be spaced apart from the second inner surface that defines the 1-1 hole.

17. forming a connection metal layer on a substrate; forming a pre-planarization layer overlying the interconnect metal layer, the pre-planarization layer comprising a negative photoresist; exposing the pre-planarization layer through a half-tone mask to form a planarization layer including a plurality of inner surfaces; The half-tone mask comprises: a first shielding portion corresponding to a first inner side surface of the planarization layer, the first shielding portion being a forward tapered inclined surface; a first semi-transparent portion surrounding the first shielding portion; a second inner side surface of the planarization layer, the second inner side surface being an inversely tapered inclined surface, and a second-1 shielding portion spaced apart from the first shielding portion and the first semi-transmitting portion.

18. The step of exposing the pre-planarization layer includes: forming the first shielding portion and the first semi-transmitting portion corresponding to the connecting metal layer; 20. The method of claim 17, further comprising: forming the second-first shielding portion spaced apart from the connection metal layer in one direction along the preliminary planarization layer.

19. the half-tone mask further includes a second-second shielding portion that corresponds to a third inner side surface of the planarization layer, the third inner side surface being an inclined surface having an inverse tapered shape, and is spaced apart from the first shielding portion and the first semi-transmitting portion; The step of exposing the pre-planarization layer includes: forming the first shielding portion and the first semi-transmitting portion corresponding to the connecting metal layer; forming the second-first shielding portion spaced apart from the connection metal layer along a first direction; 20. The method of claim 17, further comprising: forming the second-2 shielding portion spaced apart from the connection metal layer along a second direction intersecting the first direction.

20. 20. The method of claim 19, wherein the second-1 shielding portion and the second-2 shielding portion are connected to each other in the half-tone mask.

21. forming a connection metal layer in a display area and a pad in a non-display area; forming a pre-planarization layer overlying the interconnect metal layer, the pre-planarization layer comprising a negative photoresist; exposing the pre-planarization layer through a half-tone mask to form a planarization layer including a plurality of inner surfaces; The half-tone mask comprises: a first shielding portion corresponding to a first inner side surface of the planarization layer, the first shielding portion being a forward tapered inclined surface; a first semi-transparent portion surrounding the first shielding portion; a second-1 shielding portion corresponding to a second inner side surface of the planarization layer, the second inner side surface being an inversely tapered inclined surface, and spaced apart from the first shielding portion and the first semi-transmitting portion; a third shielding portion corresponding to a third inner side surface of the planarizing layer, the third inner side surface being a forward tapered inclined surface; and a second semi-transmissive portion surrounding the third shielding portion.

22. The step of exposing the preliminary planarization layer is forming the first shielding portion and the first semi-transmitting portion corresponding to the connecting metal layer; forming the second-first shielding portion spaced apart from the connection metal layer in one direction along the preliminary planarization layer; The method of claim 21 , further comprising forming the third shielding portion and the second semi-transmitting portion corresponding to the pad.

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