DUAL DRIVE DOHERTY POWER AMPLIFIER AND RELATED SYSTEMS AND METHODS - Patent application

Abstract

A dual-drive based Doherty amplifier is provided that includes a first power amplifier and a second power amplifier in parallel with the first power amplifier. The first power amplifier is configured to receive a first portion of a signal having a first phase, and the second power amplifier is configured to receive a second portion of a signal having a second phase that has a phase difference from the first phase. At least one of the first power amplifier or the second power amplifier includes a dual-drive power amplifier core.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent claims the benefit of U.S. Provisional Patent Application No. 63 / 319,930, entitled "Dual Drive Doherty Power Amplifiers and Related Systems and Methods," filed March 15, 2022, the entire contents of which are incorporated herein by reference for all purposes.

[0002] The present disclosure relates generally to power amplifier architectures, and more particularly to a combination of a Doherty load modulation power combining network and a main / auxiliary power amplifier core that uses a dual drive configuration to increase achievable communication modulation efficiency. [Background technology]

[0003] Doherty amplifiers have been around for decades. In recent years, Doherty amplifiers have been making a comeback. For example, modern communication systems use Doherty amplifiers in massive multiple-input multiple-output (mMIMO) based base stations. Modern communication systems use complex signal modulation schemes such as OFDM (orthogonal frequency division multiplexing) with high peak-to-average power ratios (PAPR), making the probability of a power amplifier operating at maximum efficiency at peak power very low. The property of Doherty amplifiers of exhibiting multiple efficiency peaks at various low power levels makes them an attractive choice to increase the average efficiency of modern transmitters. Doherty amplifiers are able to achieve this by using a technique called "dynamic load modulation," in which the load seen by the main amplifier varies with the power level in order to increase efficiency at low power levels. Summary of the Invention

[0004] Below is a non-exhaustive list of some aspects of the present technology. These and other aspects are described in the subsequent disclosure.

[0005] Some aspects include a power divider, a first power amplifier coupled to a first output of the power divider, and a second power amplifier coupled to a second output of the power divider and arranged in parallel with the first power amplifier, the second power amplifier receiving a second output signal from the second output that is out of phase with a first output signal from the first output, and at least one of the first power amplifier or the second power amplifier includes a dual-drive based Doherty amplifier including a dual-drive power amplifier core.

[0006] Some aspects comprise a first power amplifier and a second power amplifier in parallel with the first power amplifier, the first power amplifier configured to receive a first portion of a signal having a first phase and the second power amplifier configured to receive a second portion of the signal having a second phase having a phase difference from the first phase, and at least one of the first power amplifier or the second power amplifier comprises a dual-drive based Doherty amplifier including a dual-drive power amplifier core.

[0007] Some aspects include a method of amplifying power using a dual-drive based Doherty amplifier that includes a dual-drive power amplifier core. [Brief description of the drawings]

[0008] The above and other aspects of the present technology will be better understood when this application is read in conjunction with the following figures, in which like numbers indicate similar or identical elements, and in which: [Figure 1] FIG. 2 is a block diagram of a Doherty load modulation power combining network in accordance with various embodiments of the present disclosure. [Diagram 2] 1 is a schematic diagram of a dual-drive power amplifier (PA) core in accordance with various embodiments of the present disclosure. [Diagram 3] FIG. 1 illustrates a coupled transmission line pair that enables passive generation of a signal αVin+ from Vin+ and a signal αVin− from Vin− in accordance with various embodiments of the present disclosure. [Figure 4] FIG. 3 is a detailed schematic diagram of the Doherty load modulation power combining network of FIG. 1 utilizing the dual drive core of FIG. 2 in accordance with various embodiments of the present disclosure. [Diagram 5] 2 is a block diagram of an in-phase / quadrature (IQ) network of the Doherty load modulation power combining network of FIG. 1 in accordance with various embodiments of the present disclosure. [Figure 6] FIG. 2 is a block diagram of a phase-matched secondary network of the Doherty load modulation power combining network of FIG. 1 in accordance with various embodiments of the present disclosure. [Figure 7] FIG. 1 is an example block diagram of a power amplifier utilizing a dual drive core, in accordance with various embodiments of the present disclosure. [Figure 8A] 4 illustrates a graph of input impedance of a common source power amplifier in accordance with various embodiments of the present disclosure. [Figure 8B] 4A-4C are diagrams illustrating input impedances of a dual drive power amplifier core in accordance with various embodiments of the present disclosure. [Figure 9] FIG. 3 is a schematic diagram of a small signal dual drive transistor model used to derive the input impedance of the dual drive power amplifier (PA) core of FIG. 2 in accordance with various embodiments of the present disclosure.

[0009] While the technology of the present invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. The drawings may not be to scale. It should be understood, however, that the drawings and the detailed description thereunder are not intended to limit the technology to the particular forms disclosed, but on the contrary, are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the technology as defined by the appended claims. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] To alleviate the problems described herein, the inventors have had to devise solutions and, in some cases equally important, recognize problems that others in the fields of wireless communications, Doherty amplifiers, and power amplifiers have overlooked (or have not yet foreseen). Indeed, the inventors wish to emphasize the difficulty of recognizing problems in their infancy. These problems will become much more evident in the future if industry trends continue as the inventors expect. Furthermore, because there are multiple problems addressed, it should be understood that some embodiments are specialized to one problem or another, and that not all embodiments address all of the problems of conventional systems described herein or provide all of the advantages described herein. In short, improvements that solve various permutations of these problems are described below.

[0011] Conventional power amplifiers (PAs) are limited in efficiency, output power, and gain due to low device breakdown voltage, limited fmax, poor quality on-chip passive elements, and limited voltage swing. Furthermore, complex modulation schemes (e.g., QAM / OFDM) are used to be spectrally efficient, but with the consequent cost of reduced peak-to-average power ratio (PAPR). This forces the power amplifier to operate, on average, away from its most efficient peak output power, resulting in a significant reduction in average modulation efficiency.

[0012] To increase efficiency during power back-off (PBO) and therefore modulation, designers have employed complex design techniques such as load modulation (Doherty power amplifiers and out-phased power amplifiers). However, these techniques sacrifice gain, linearity, and peak efficiency due to the loss of power combining / phase shifter networks. Harmonically tuned power amplifiers improve peak efficiency, but at the expense of reduced linearity and bandwidth due to harmonic termination. Dual-drive topologies also increase the peak efficiency and linearity achievable in the power amplifier core by coupling the gate and source out of phase, increasing the total swing, but do not improve efficiency under power back-off conditions.

[0013] The disclosed technology relates to a new power amplifier (PA) architecture that dramatically improves achievable communications modulation efficiency. To achieve this, the disclosed system and method uses a combination of a Doherty load modulation power combining network and a primary / auxiliary power amplifier core that utilizes a dual drive configuration described in U.S. Patent No. 11,469,726, filed March 3, 2022, entitled "Highly Efficient Dual Drive Power Amplifier for High Reliability Applications," which is incorporated herein by reference for all purposes. The dual drive input coupling network supports driving the gate and source terminals of the differential pair out of phase while providing proper DC bias to both terminals. This coupling network ensures that the source and drain of the transistor oscillate in phase, artificially lowering the knee voltage of the transistor and increasing the total swing of the output voltage. The increased voltage swing improves the peak output power, linearity, and efficiency of the power amplifier. Additionally, due to the coupling to the source, the input impedance of the dual drive power amplifier core is significantly reduced, minimizing the required impedance transformation ratio and supporting a wideband, low loss matching network.

[0014] The Doherty power combining network supports power combining for high power applications and active load modulation for improved power back-off (PBO) efficiency. The combination of the Doherty network with a dual-drive power amplifier core supports high PBO efficiency peaks for efficient communication under modulation, high gain with low matching losses in the input / interstage networks, and wideband operation with minimal impedance transformation required.

[0015] In addition, conventional power amplifiers (PAs) have low device voltage resistance, max They are limited in efficiency, output power, and gain due to limited power distribution, poor quality on-chip passive elements, and limited voltage swing. In addition, complex modulation schemes such as QAMs / OFDM are used to be spectrally efficient at the expense of high peak-to-average power ratio (PAPR). This forces the power amplifier to operate, on average, away from its most efficient peak output power, significantly reducing the average modulation efficiency. To increase efficiency during power back-off (PBO) and therefore modulation, designers have employed complex design techniques such as load modulation (Doherty power amplifiers and out-phased power amplifiers). However, these techniques sacrifice gain, linearity, and peak efficiency due to loss of power combining / phase shifter networks. Harmonic tuned power amplifiers improve peak efficiency, but at the expense of reduced linearity and bandwidth due to harmonic termination. Dual drive topologies also increase the peak efficiency and linearity achievable in the power amplifier core by coupling the gate and source out of phase, increasing the total swing. However, they do not improve efficiency under power back-off conditions.

[0016] To overcome these challenges, the disclosed system and method propose a new power amplifier architecture that employs Doherty power combining and a main / auxiliary power amplifier core utilizing a dual drive configuration. The Doherty power amplifier architecture may support PBO efficiency improvement through active load modulation. However, the peak efficiency of the Doherty power amplifier architecture may be limited due to gain limitations and losses in the power combining / IQ power splitting network, whereas the disclosed technology uses a dual drive power amplifier core for the main / auxiliary power amplifier to mitigate these issues.

[0017] According to some embodiments of the disclosed technology, a dual-drive power amplifier core used in a main / auxiliary power amplifier contributes to alleviating these problems. The dual-drive active core delivers the input signal to the source and gate of the power amplifier in different phases via a multi-feed coupling network. The dual-drive power amplifier core employs a differential pair consisting of M1 and M2 and a multi-feed network to couple the gate of M1 to the source of M2 and the gate of M2 to the source of M1 while ensuring a proper DC bias point (gate at a non-zero DC voltage, source at DC ground). The coupling network swings the source of the transistor in phase with its drain, reducing the effective voltage knee and improving the output swing, thereby improving the linearity, output power, and power-added efficiency of the dual-drive power amplifier core compared to conventional common source (CS) or cascode.

[0018] Thus, according to aspects of the present disclosure, the peak efficiency improvement from the primary / auxiliary dual drive power amplifier cores can compensate for the peak efficiency reduction from the Doherty power combining network while maintaining the improved PBO efficiency, significantly improving the average efficiency achievable under modulation. Furthermore, since the dual drive topology is a combination of a common gate amplifier and a common source amplifier, the input impedance of the power amplifier cores is significantly reduced. This minimizes the impedance transformation required for the matching network interfacing with the dual drive core input, increasing the achievable bandwidth of the Doherty power amplifier and minimizing losses in the matching network. The reduced losses in the matching network improve the overall gain of the power amplifier, further improving the peak efficiency and improving the modulation efficiency achievable with the Doherty power amplifier. This superior performance perfectly positions the power amplifier architecture as a high efficiency topology for commercial applications.

[0019] FIG. 1 is a block diagram of a Doherty load modulation power combining network 100 in accordance with various embodiments of the present disclosure. In various embodiments, the Doherty load modulation power combining network 100 may include a Doherty power amplifier architecture. Although a particular Doherty power amplifier architecture is illustrated in FIG. 1, one of ordinary skill in the art having access to this disclosure will recognize that other circuits that may be classified as a Doherty power amplifier may be considered and are within the scope of the present disclosure. The Doherty power amplifier architecture may include a driver 102 including a driver input 102a and a driver output 102b. The driver input 102a may receive an input signal RF in In various embodiments, the driver 102 may include a dual drive power amplifier core, as described in more detail below.

[0020] In various embodiments, the driver output 102b can provide a driver output signal to an in-phase quadrature (IQ) network 104. The IQ network 104 can include a power splitter and a phase shifter. The power splitter can split the driver output signal into a main signal line and an auxiliary signal line. The phase shifter can be coupled to the auxiliary signal line and shift the signal on that auxiliary signal line (e.g., a line that provides a signal to an auxiliary power amplifier). Although a power splitter is shown splitting the signal into two lines, other splitter configurations (e.g., 3-way, 4-way, or other configurations that would be apparent to one of ordinary skill in the art) can be envisioned. In some embodiments, the phase shifter can perform a quadrature (90 degree) phase shift. However, other phase shifts can be envisioned. The phase shifter can include a quadrature hybrid coupler, a Lange coupler, a polyphase filter quadrature phase splitter, a Schiffman phase shifter, a branch line coupler, a power split with delay lines, or any other phase shifter that would be apparent to one of ordinary skill in the art having access to this disclosure. In various embodiments, the phase shifter outputs to the auxiliary power amplifier input 108a, while the main power amplifier input 106a does not include a phase shifter and receives a portion of the driver output signal without any phase shifting.

[0021] As mentioned above, the IQ network 104 is coupled to a main power amplifier input 106a of the main power amplifier 106. The main power amplifier 106 may include a main power amplifier output 106b. The main power amplifier 106 may be biased in class AB, although other classes may be envisioned. In various embodiments, the main power amplifier 106 may include a dual drive power amplifier core, as described in more detail below. The IQ network 104 is also coupled to an auxiliary power amplifier input 108a of the auxiliary power amplifier 108. The auxiliary power amplifier 108 may include an auxiliary power amplifier output 108b. The auxiliary power amplifier 108 may be biased in class C. This biasing scheme means that when the input drive level is low, the main power amplifier 106 conducts and the auxiliary power amplifier 108 is off. As the input level increases, the drive level of the main power amplifier 106 also increases, and when the output power is approximately one quarter of the maximum of the main power amplifier, the auxiliary power amplifier 108 begins to conduct current. In various embodiments, the auxiliary power amplifier 108 may include a dual drive power amplifier core, as described in further detail below.

[0022] In various embodiments, the main power amplifier output 106b may be coupled to a second phase shifter 110 (e.g., an impedance inverter) that shifts the phase of the main power amplifier output signal to match the phase of the auxiliary power amplifier output signal from the auxiliary power amplifier output 108b. Thus, in various embodiments, the phase shifter 110 may include a quarter wave impedance inverter to match the 90 degree phase shift of the auxiliary power amplifier 108. The signals from the phase shifter 110 and the auxiliary power amplifier output 108b are combined in an output matching network 112 to produce an output signal RF out As load Z L 1, one of ordinary skill in the art having the benefit of this disclosure will recognize that other Doherty power amplifiers including other components and configurations are contemplated and are also within the scope of the present disclosure.

[0023] 2 is a schematic diagram of a dual drive power amplifier (PA) core 200 according to an embodiment of the present disclosure that may be provided as at least one of the main power amplifier 106 or the auxiliary power amplifier 108 of the Doherty load modulation power combining network 100 of FIG. 1. In some embodiments, the driver 102 may also include the dual drive power amplifier core 200. The dual drive power amplifier core 200 may utilize a transistor differential pair including a first transistor M1 202 and a second transistor M2 204 with a dual drive coupling network 206. The dual drive coupling network 206 may include transmission line segments T1 208, T2 210, T3 212, and T4 214, of which T1 208 and T2 210 are electromagnetically coupled and T3 212 and T4 214 are electromagnetically coupled. The dual drive coupling network 206 allows for a first portion of the balanced input signal Vin− to be applied via T4 214 to drive the gate of M1 202, while a version of Vin− may be coupled via T3 212 to drive the source terminal of M2 204. At the same time, a second portion of the balanced input signal Vin+ may be applied via T2 210 to drive the gate of M2 204, while a version of Vin+ may be coupled via T1 208 to drive the source terminal of M1 202. The embodiments disclosed herein further allow for providing the correct DC bias point, such as providing a non-zero DC voltage on the gate and a DC ground on the source. With this power amplifier topology, the sources of transistors 202 and 204 can swing in phase with the drains, thus extending the voltage knee / output swing, allowing for linear increases in output power and power-added efficiency while using low supply voltages.

[0024] 3 is an illustration of a coupling network 300 that may provide the dual drive coupling network 206 of FIG. 2. The coupling network 300 includes a pair of transmission line based couplers T1 208 and T2 210, T3 212 and T4 214, where T1 208 is coupled to T2 210 (S 302) and T3 212 is coupled to T4 214 (S 304). Although each of T1 208, T2 210, T3 212 and T4 214 may be considered an independent transmission line (separately), T1 208 and T2 210 may form a first transmission line based coupler due to their proximity and the possibility of electromagnetic coupling therebetween. Similarly, T3 212 and T4 214 may form a second transmission line based coupler. The couplings 302-304 allow for passive generation of signals αVin+ and αVin− from Vin+ and Vin−, respectively. In some embodiments, the coupling network 300 may introduce an inductive reactance source degeneration that reduces the overall power gain of the device. In certain embodiments, the even mode impedance Z 0e and odd-mode impedance Z 0o Inductive reactance may be reduced by selecting a transmission line geometry that gives a reasonably low value for . According to certain embodiments of the present disclosure, the coupling coefficient α may be set by the transmission line geometry.

[0025] In some embodiments of the present disclosure, the coupling coefficient α may be set in the range of about 0.1 to about 0.9. In other embodiments, the coupling coefficient α may be set in the range between about 0.2 to about 0.8. In yet other embodiments, the coupling coefficient α may be set in the range of about 0.3 to about 0.7. In yet other embodiments, the coupling coefficient α may be set in the range of about 0.4 to about 0.6. In yet other embodiments, the coupling coefficient α may be set in the range of about 0.3 to about 0.4.

[0026] 2 and 3, the dual drive power amplifier core 200 may include a first transistor M1 202 having at least three terminals including an M1 gate terminal, an M1 drain terminal, and an M1 source terminal. The dual drive power amplifier core 200 may include a second transistor M2 204 having at least three terminals including an M2 gate terminal, an M2 drain terminal, and an M2 source terminal.

[0027] The dual drive power amplifier core 200 may include a first transmission line coupler including a first transmission line section T1 208 having a first end and a second end, the first end being grounded and the second end being connected to the M1 source terminal.

[0028] The dual drive power amplifier core 200 may include a first transmission line coupler including a second transmission line section T2 210 having a first end and a second end, the first end may be configured to receive one or more of the core's first input signal and / or a first bias voltage. The second end of the second transmission line section T2 210 may be connected to the M2 gate terminal and capacitively coupled to the M1 drain terminal. As described above, the first transmission line section T1 208 may be electromagnetically coupled to the second transmission line section T2 210.

[0029] The dual drive power amplifier core 200 may include a second transmission line coupler including a third transmission line section T3 212 having a first end and a second end, where the first end may be grounded and the second end may be connected to the M2 source terminal.

[0030] The dual drive power amplifier core 200 may include a fourth transmission line section T4 214 having a first end and a second end, the first end may be configured to receive one or more of the core's second input signal and / or the first bias voltage. The second end of the fourth transmission line section T4 214 may be connected to the M1 gate terminal and, in certain embodiments, capacitively coupled to the M2 drain terminal. As described above, the third transmission line section T3 212 may be electromagnetically coupled to the fourth transmission line section T4 214.

[0031] Figure 4 illustrates a Doherty load modulation power combining network 400 that includes the dual drive power amplifier core 200 of Figure 2 used in the power amplifiers and drivers of the Doherty load modulation power combining network 100 of Figure 1. For example, the driver 102 includes the dual drive power amplifier core 200, the main power amplifier 106 includes the dual drive power amplifier core 200, and the auxiliary power amplifier 108 can include the dual drive power amplifier core 200. In the example illustrated in Figure 4, the main power amplifier 106 and the auxiliary power amplifier 108 can include a matching network 402 and a matching network 404. The driver 102 can include a matching network 406 and a matching network 408.

[0032] FIG. 5 illustrates an IQ network 500 that may provide the IQ network 104 of FIG. 1 according to various embodiments of the present disclosure. As described above, the IQ network 500 may include a power divider 502 and a phase shifter 504. The power divider 502 may divide a driver output signal or other input signal, and the phase shifter 504 may shift the signal on the line to which it is coupled (e.g., the line that supplies the signal to the auxiliary power amplifier 108). Although a power divider 502 is illustrated that splits the signal into two lines, other divider configurations (e.g., 3-way, 4-way, or other configurations that would be apparent to one of ordinary skill in the art) may be envisioned. In some embodiments, the phase shifter 504 may perform a quadrature (90 degree) phase shift; however, other phase shifts may be envisioned. The phase shifter 504 may include a quadrature hybrid coupler, a Lange coupler, a polyphase filter quadrature phase splitter, a Schiffman phase shifter, a branch line coupler, a power split with a delay line, or any other phase shifter that would be apparent to one of ordinary skill in the art having access to this disclosure. In various embodiments, a phase shifter is located at the auxiliary power amplifier input 108a, while the main power amplifier input 106a does not include a phase shifter. Figure 6 shows an IQ network 600 as another embodiment of the IQ network 104 of Figure 1.

[0033] 7 is a block diagram of an example power amplifier 700 that can utilize the dual drive power amplifier core 200 (described above) in accordance with various embodiments of the present disclosure. Various arrangements can be configured to utilize the dual drive power amplifier core 200 without departing from the scope of the present disclosure. FIG. 7 illustrates one practical example of how other stages (such as an input matching network 702, a driver 704, an inter-stage matching network 706, and / or an output network 708) can be utilized with the dual drive power amplifier core 200. The power amplifier 700 can be utilized as at least one of the main power amplifier 106 or the auxiliary power amplifier 108.

[0034] FIG. 8A shows a graph 800a of the input impedance of a common source power amplifier, and FIG. 8B shows a graph 800b of the input impedance of the dual drive power amplifier core 200 of FIG. 2, where α is 0.3. One advantage of a dual drive based Doherty power amplifier is that the input impedance of the transistor is reduced because the gate impedance of the device is combined in parallel with the low source impedance of the device. The source impedance can also be designed to be mitigated by source coupling α without the need to implement a Q elimination resistor in the design of a wideband, low loss interstage matching network. FIG. 9 shows a small signal dual drive transistor model 900 used to derive the input impedance, including the dual drive coupling network and inductive degeneration. The input impedance of the dual drive power amplifier core 200 can be expressed as follows:

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[0046] Thus, a system and method for providing a dual-drive Doherty power amplifier has been described. A Doherty power combining with a main / auxiliary power amplifier core utilizing a dual-drive configuration is employed. A conventional Doherty power amplifier architecture may support PBO efficiency enhancement with active load modulation. However, a conventional Doherty power amplifier architecture has limited peak efficiency due to gain limitations and losses in the power combining / IQ power splitting network. The dual-drive power amplifier core used for the main / auxiliary power amplifier contributes to alleviating these issues. The peak efficiency enhancement with the dual-drive power amplifier core for the main / auxiliary can compensate for the peak efficiency reduction due to the Doherty power combining network while maintaining the PBO efficiency enhancement, and significantly improve the achievable average efficiency under modulation. Furthermore, since the dual-drive topology is a combination of a common-gate amplifier and a common-source amplifier, the input impedance of the power amplifier core is significantly reduced. This minimizes the impedance transformation required for the matching network interfacing with the dual-drive core input, increasing the achievable bandwidth of the Doherty power amplifier and minimizing losses in the matching network. The reduced losses in the matching network improve the overall power amplifier gain, further increasing the peak efficiency and improving the modulation efficiency achievable with the Doherty power amplifier. This superior performance perfectly positions the power amplifier architecture as a highly efficient topology for commercial applications such as wireless communications, radar, satellite communications, and other applications that will be apparent to those skilled in the art having access to this disclosure.

[0047] Although the block diagram depicts the illustrated components as separate functional blocks, embodiments are not limited to a system in which the functions described herein are organized as illustrated. The functionality provided by each component may be provided by software or hardware modules organized in a manner different from that currently illustrated, for example, such software or hardware may be mixed, combined, replicated, split, distributed (e.g., in a data center or geographically), or otherwise organized in a different manner. The functionality described herein may be provided by one or more processors of one or more computers executing code stored on a tangible, non-transitory, machine-readable medium. In some cases, despite the use of the singular term "medium," the instructions may be distributed on different storage devices associated with different computing devices, where each computing device may have a different subset of the instructions, for example. This is an implementation that is consistent with the use of the singular term "medium" herein. In some cases, a third-party content delivery network may host some or all of the information communicated over the network, in which case, to the extent that information (e.g., content) can be described as being provided or otherwise provided, the information may be provided by sending instructions to obtain the information from the content delivery network.

[0048] The reader should understand that this application describes several separately useful technologies. Applicant has grouped these technologies together in one document, rather than separating them into multiple independent patent applications, because the subject matter of the technologies is related, leading to economies of scale in the filing process. However, separate advantages or aspects of such technologies should not be confused. In some cases, while an embodiment addresses all of the deficiencies noted herein, it should be understood that the technologies are independently useful, and that some embodiments address only a subset of such problems or provide other unmentioned advantages that would be apparent to one of ordinary skill in the art viewing this disclosure. Due to cost constraints, some technologies disclosed herein may not be currently claimed, and may be claimed in a later application, such as a continuation application, or by amending the present claims. Similarly, for the sake of space, the "Abstract" and / or "Summary" sections of this document should not be considered as comprehensive descriptions of all such technologies, or all aspects of such technologies.

[0049] It should be understood that the detailed description and drawings are not intended to limit the technology to the particular forms disclosed, but on the contrary, are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the technology as defined by the appended claims. Further modifications and alternative embodiments of various aspects of the technology will be apparent to those skilled in the art upon reading this description. Thus, this description and drawings are to be construed as illustrative only and are intended to teach those skilled in the art the general manner of carrying out the technology. It should be understood that the forms of the technology shown and described herein should be considered as exemplary embodiments. Various elements and materials may be substituted for those shown and described herein, parts and processes may be reversed or omitted, and certain features of the technology may be utilized independently, all of which will become apparent to those skilled in the art after having the benefit of this description of the technology. Changes may be made to the elements described herein without departing from the spirit and scope of the technology as set forth in the following claims. The headings used herein are for organizational purposes only and are not intended to be used to limit the scope of the description.

[0050] As used throughout this application, the word "may" is used in a permissive sense (i.e., may) rather than a required sense (i.e., must). Words such as "include," "including," "includes," and the like mean including but not limited to. In this application, the singular forms "a," "an," and "the" include plurals unless the content clearly indicates otherwise. Thus, for example, reference to "an element" or "a element" includes a combination of two or more elements, regardless of the use of other terms and phrases for one or more elements, such as "one or more." The term "or" is non-exclusive unless otherwise specified, i.e., it encompasses both "and" and "or." Terms expressing conditional relationships, such as "depending on X, Y," "upon X, Y," "if X, Y," and "in the event of X, Y," imply a causal relationship where the antecedent is a necessary causal condition, where the antecedent is a sufficient causal condition, or where the antecedent is a contributory causal condition of the consequent, etc. For example, "When condition Y is satisfied, state X occurs" means either "X occurs only because of Y" or "X occurs because of Y and Z." Such conditional relations are not limited to the consequent being immediately entailed by the occurrence of the antecedent, but may occur later depending on the consequent. Also, in a conditional statement, the antecedent is connected to its consequent such that it is related to the possibility of the consequent occurring. A statement that multiple attributes or features are mapped to multiple objects (e.g., one or more processors performing steps A, B, C, and D) encompasses both all of those attributes or features being mapped to all of those objects and a subset of those attributes or features being mapped to a subset of those attributes or features (e.g., both when all processors perform steps A through D, and when processor 1 performs step A, processor 2 performs step B and part of step C, and processor 3 performs part of step C and step D), unless otherwise indicated.Similarly, a "computer system" that performs step A and a "computer system" that performs step B can include the same computing device in the computer system that performs both steps, or different computing devices in the computer system that perform steps A and B. Furthermore, a statement that a value or action is "based on" another condition or value encompasses both cases where that condition or value is the only factor and cases where that condition or value is one factor among multiple factors, unless otherwise indicated. A statement that "each" instance of a collection has a characteristic should not be read to exclude cases where the same or similar member of other properties of the larger collection does not have that characteristic, unless otherwise indicated. That is, "each" does not necessarily mean all. No limitations on the order of the recited steps should be read into the claims unless expressly specified, such as "perform X, then perform Y." In contrast, statements that could be improperly argued to imply an order restriction, such as "perform X on an item, then perform Y on the item that has been X," are used for the purpose of making the claims easier to read, rather than specifying an order. Also, statements such as "at least Z of A, B, and C" (e.g., "at least Z of A, B, or C") refer to at least Z of each of the listed categories (A, B, and C) and do not require at least Z units in each category. As is apparent from the description, discussions herein utilizing terms such as "processing," "computing," "calculating," "determining," and the like are understood to refer to specific apparatus operations or processes, such as a special purpose computer or similar special purpose electronic processing / computing device, unless otherwise indicated. Features described with reference to geometric constructs such as "parallel," "perpendicular / orthogonal," "square," "cylindrical," and the like, should be construed to encompass items that substantially embody the properties of that geometric construct; for example, reference to "parallel" surfaces encompasses surfaces that are substantially parallel.The permissible range of deviations from the Platonic notion of these geometric constructs should be determined by reference to the ranges in the specification, and if no such range is stated, reference should be made to industry norms in the field of use, and if no such range is defined, reference should be made to industry norms in the field of manufacture of the specified feature, and if no such range is defined, features that substantially embody a geometric construct should be construed to include features that are within 15% of the defining attributes of the geometric construct. The terms "first," "second," "third," "predetermined," and the like, used in the claims are used to distinguish or identify, and do not indicate sequential or numerical limitations. As is common practice in the art, data structures and formats described with reference to uses prominent to humans need not be presented in a human-understandable form to constitute said data structures or formats. For example, text does not need to be rendered or encoded in Unicode or ASCII to constitute text, images, maps, and data visualizations do not need to be displayed or decoded to constitute images, maps, and data visualizations, and voice, music, and other sounds do not need to be emitted from a speaker or decoded to constitute voice, music, and other sounds. Computer-implemented instructions, commands, and the like are not limited to executable code, but may be implemented in the form of data that provides a function, e.g., arguments to a function or API call. To the extent that purpose-built noun phrases (and other coined terms) are used in the claims and lack obvious interpretation, definitions of such phrases may be set forth in the claims themselves, in which case the use of such noun phrases should not be deemed to confer additional limitations by reference to the specification or extrinsic evidence.

[0051] If any U.S. patents, U.S. patent applications, or other materials (such as articles) are incorporated by reference in this patent, the text of such materials is incorporated by reference only to the extent that there is no conflict between such materials and the description and drawings set forth herein. In the event of such a conflict, the text of this specification shall control, and a term in this specification should not be construed narrower because of the use of that term in other materials incorporated by reference.

[0052] The present technology will be better understood with reference to the embodiments listed below. [Embodiment 1] 1. A dual-drive based Doherty amplifier comprising: a power divider; a first power amplifier coupled to a first output of the power divider; and a second power amplifier coupled to a second output of the power divider and arranged in parallel with the first power amplifier, the second power amplifier receiving a second output signal from the second output that is out of phase with a first output signal from the first output, and at least one of the first power amplifier or the second power amplifier comprising a dual-drive power amplifier core. [Embodiment 2] 2. The dual-drive-based Doherty amplifier of embodiment 1, wherein the dual-drive power amplifier core includes: a transistor differential pair, each transistor having a gate terminal, a drain terminal, and a source terminal; and a multi-feed coupling network configured to drive the transistor differential pair with different phases at the gate terminal and the source terminal, thereby driving the dual-drive power amplifier core with different phases at the gate terminal and the source terminal and vibrating the source terminal and the drain terminal in phase. [Embodiment 3] 3. The dual-drive-based Doherty amplifier of any one of claims 1 to 2, wherein the dual-drive power amplifier core includes a core first output terminal Vout+ configured to be connected to a drain terminal of a first transistor, a core second output terminal Vout- configured to be connected to a drain terminal of a second transistor, and a plurality of transmission line couplers including a first transmission line coupler having a transmission line section having a first termination configured to receive a core first input signal Vin+, and a second transmission line coupler having a transmission line section having a first termination configured to receive a core first input signal Vin-, and the core first output terminal and the core second output terminal are configured to output an amplified differential signal corresponding to a difference between the core first input signal Vin+ and the core second input signal Vin-. [Embodiment 4] the dual drive power amplifier core includes a first transistor M1 having an M1 gate terminal, the drain terminal being the M1 drain terminal, and an M1 source terminal, and the second transistor M2 having an M2 gate terminal, the drain terminal being the M2 drain terminal, and an M2 source terminal, the first transmission line coupler further comprising a first transmission line section T1 having a first end and a second end, the first end being connected to ground and the second end being connected to the M1 source terminal, the transmission line section having the first end configured to receive the core first input signal Vin+ includes a second transmission line section T2 of the first transmission line coupler, the second transmission line section T2 having a first end connected to ground and the second end being connected to the M1 source terminal, 4. The dual-drive-based Doherty amplifier of embodiment 3, wherein the first transmission line section T1 is electromagnetically coupled to the second transmission line section T2, the second transmission line coupler further comprises a third transmission line section T3 having a first end and a second end, the first end being grounded and the second end being connected to the M2 source terminal, the transmission line section having the first end configured to receive the core first input signal Vin− includes a fourth transmission line section T4, the fourth transmission line section T4 further having a second end connected to the M1 gate terminal and coupled to the M2 drain terminal, the third transmission line section T3 being electromagnetically coupled to the fourth transmission line section T4. [Embodiment 5] 5. A dual-drive-based Doherty amplifier as in any one of embodiments 1 to 4, further comprising a driver including a driver input and a driver output, the driver output being coupled to the input of the power divider. [Embodiment 6] 6. A dual-drive-based Doherty amplifier as recited in embodiment 5, wherein the driver includes a dual-drive power amplifier core. [Embodiment 7] 7. The dual-drive-based Doherty amplifier of any one of embodiments 1 to 6, wherein the dual-drive power amplifier core improves wideband operation of the dual-drive-based Doherty amplifier due to a reduction in input impedance at the dual-drive power amplifier core. [Embodiment 8] 8. A dual-drive-based Doherty amplifier as in any one of embodiments 1 to 7, wherein the first amplifier is a class AB amplifier and the second amplifier is a class C amplifier. [Embodiment 9] 9. The dual-drive-based Doherty amplifier of any one of embodiments 1 to 8, further comprising an impedance inverter coupled to a power amplifier output of the first power amplifier. [Embodiment 10] 10. The dual drive-based Doherty amplifier of embodiment 9, further comprising an output matching network coupled to the impedance inverter and a power amplifier output of the second power amplifier, the output of the output matching network being supplied to a load. [Embodiment 11] 1. A dual-drive based Doherty amplifier comprising: a first power amplifier; and a second power amplifier in parallel with the first power amplifier, the first power amplifier configured to receive a first portion of a signal having a first phase, and the second power amplifier configured to receive a second portion of the signal having a second phase having a phase difference from the first phase, and at least one of the first power amplifier or the second power amplifier includes a dual-drive power amplifier core. [Embodiment 12] 12. The dual-drive-based Doherty amplifier of embodiment 11, wherein the dual-drive power amplifier core includes a transistor differential pair, each transistor having a gate terminal, a drain terminal, and a source terminal, and a multi-feed coupling network configured to drive the transistor differential pair with different phases at the gate terminals and the source terminals, thereby driving the core with different phases at the gate terminals and the source terminals and vibrating the source terminals and the drain terminals in phase. [Embodiment 13] 13. The dual drive-based Doherty amplifier of embodiment 12, wherein the multi-feed coupling network couples the input signal from the gate terminal of a first transistor of the transistor differential pair to the source terminal of a second transistor of the transistor differential pair, couples the input signal from the gate terminal of the second transistor to the source terminal of the first transistor, provides a non-zero DC voltage to the gate terminal, and provides DC ground to the source terminal. [Embodiment 14] 14. A dual-drive-based Doherty amplifier as described in any one of embodiments 11 to 13, further comprising an in-phase quadrature (IQ) network including a power divider configured to receive an input signal and divide the input signal into a first portion of the signal and a second portion of the signal. [Embodiment 15] 15. A dual-drive-based Doherty amplifier as described in any one of embodiments 11 to 14, further comprising a driver including a driver input and a driver output, the driver output being coupled to the input of the power divider. [Embodiment 16] 16. The dual-drive-based Doherty amplifier of embodiment 15, wherein the driver includes a dual-drive power amplifier core. [Embodiment 17] 17. A dual-drive-based Doherty amplifier as described in any one of embodiments 11 to 16, wherein the dual-drive power amplifier core improves wideband operation of the dual-drive-based Doherty amplifier due to a reduction in input impedance at the dual-drive power amplifier core. [Embodiment 18] 18. A dual-drive-based Doherty amplifier as in any one of embodiments 11 to 17, wherein the first amplifier is a class AB amplifier and the second amplifier is a class C amplifier. [Embodiment 19] 19. The dual-drive-based Doherty amplifier of any one of embodiments 11 to 18, further comprising an impedance inverter coupled to a power amplifier output of the first power amplifier. [Embodiment 20] 20. The dual drive-based Doherty amplifier of embodiment 19, further comprising an output matching network coupled to the impedance inverter and a power amplifier output of the second power amplifier, the output of the output matching network being supplied to a load.

Claims

1. A power divider; a first power amplifier coupled to a first output of the power divider; a second power amplifier coupled to a second output of the power divider and arranged in parallel with the first power amplifier; Equipped with the second power amplifier receives a second output signal from the second output that is out of phase with a first output signal from the first output, and at least one of the first power amplifier or the second power amplifier includes a dual drive power amplifier core. Dual drive based Doherty amplifier.

2. said dual drive power amplifier core a differential pair of transistors, each transistor having a gate terminal, a drain terminal, and a source terminal; A multi-feed coupling network comprising: driving the transistor differential pair with out-of-phase at the gate and source terminals, thereby driving the dual drive power amplifier core with out-of-phase at the gate and source terminals; The source terminal and the drain terminal are vibrated in the same phase. A multi-feed coupling network configured as follows:

2. The dual-drive-based Doherty amplifier of claim 1 , comprising:

3. said dual drive power amplifier core a core first output terminal Vout+ configured to be connected to the drain terminal of the first transistor; a core second output terminal Vout− configured to be connected to the drain terminal of the second transistor; a plurality of transmission line couplers including a first transmission line coupler having a transmission line section with a first end configured to receive the core first input signal Vin+; and a second transmission line coupler having a transmission line section with a first end configured to receive the core first input signal Vin−; Including, the core first output terminal and the core second output terminal are configured to output an amplified differential signal corresponding to a difference between the core first input signal Vin+ and the core second input signal Vin−; 2. The dual-drive-based Doherty amplifier of claim 1.

4. said dual drive power amplifier core the first transistor comprising a first transistor M1 having an M1 gate terminal, a drain terminal comprising an M1 drain terminal, and an M1 source terminal; the second transistor comprising a second transistor M2 having an M2 gate terminal, a M2 drain terminal, the drain terminal being an M2 drain terminal, and an M2 source terminal; Including, the first transmission line coupler further comprises a first transmission line section T1 having a first end and a second end, the first end being grounded and the second end being connected to the M1 source terminal; the transmission line section having the first termination configured to receive the core first input signal Vin+ includes a second transmission line section T2 of the first transmission line coupler, the second transmission line section T2 further having a second termination connected to the M2 gate terminal and coupled to the M1 drain terminal; the first transmission line portion T1 is electromagnetically coupled to the second transmission line portion T2, the second transmission line coupler further comprises a third transmission line section T3 having a first end and a second end, the first end being grounded and the second end being connected to the M2 source terminal; the transmission line section having the first termination configured to receive the core first input signal Vin− includes a fourth transmission line section T4, the fourth transmission line section T4 further having a second termination connected to the M1 gate terminal and coupled to the M2 drain terminal; the third transmission line portion T3 is electromagnetically coupled to the fourth transmission line portion T4; 4. The dual-drive based Doherty amplifier of claim 3.

5. 10. The dual-drive-based Doherty amplifier of claim 1, further comprising a driver including a driver input and a driver output, the driver output coupled to an input of the power divider.

6. The dual-drive-based Doherty amplifier of claim 5 , wherein the driver comprises a second dual-drive power amplifier core.

7. The dual-drive-based Doherty amplifier of claim 1 , wherein the dual-drive power amplifier core improves wideband operation of the dual-drive-based Doherty amplifier due to a reduction in input impedance at the dual-drive power amplifier core.

8. 2. The dual-drive-based Doherty amplifier of claim 1, wherein the first power amplifier is a class AB amplifier and the second power amplifier is a class C amplifier.

9. The dual-drive-based Doherty amplifier of claim 1 , further comprising an impedance inverter coupled to a power amplifier output of the first power amplifier.

10. 10. The dual-drive-based Doherty amplifier of claim 9, further comprising an output matching network coupled to the impedance inverter and to a power amplifier output of the second power amplifier, an output of the output matching network being provided to a load.

11. a first power amplifier; a second power amplifier in parallel with the first power amplifier; Equipped with the first power amplifier is configured to receive a first portion of a signal having a first phase and the second power amplifier is configured to receive a second portion of the signal having a second phase having a phase difference from the first phase, and at least one of the first power amplifier or the second power amplifier includes a dual drive power amplifier core. Dual drive based Doherty amplifier.

12. said dual drive power amplifier core a differential pair of transistors, each transistor having a gate terminal, a drain terminal, and a source terminal; A multi-feed coupling network comprising: driving the transistor differential pair with out-of-phase at the gate and source terminals, thereby driving the dual drive power amplifier core with out-of-phase at the gate and source terminals; The source terminal and the drain terminal are vibrated in the same phase. A multi-feed coupling network configured as follows:

12. The dual-drive-based Doherty amplifier of claim 11, comprising:

13. The multi-feed coupling network coupling an input signal from the gate terminal of a first transistor of the differential pair of transistors to the source terminal of a second transistor of the differential pair of transistors; coupling an input signal from the gate terminal of the second transistor to the source terminal of the first transistor, providing a non-zero DC voltage to the gate terminal and providing a DC ground to the source terminal; 13. The dual-drive-based Doherty amplifier of claim 12.

14. 1. An in-phase quadrature (IQ) network, the IQ network including a power divider configured to receive an input signal and divide the input signal into a first portion of the signal and a second portion of the signal. The dual-drive-based Doherty amplifier of claim 11 further comprising:

15. a driver including a driver input and a driver output, the driver output being coupled to the input of the power divider; 15. The dual-drive-based Doherty amplifier of claim 14, further comprising:

16. The dual-drive-based Doherty amplifier of claim 15 , wherein the driver comprises a second dual-drive power amplifier core.

17. 12. The dual-drive-based Doherty amplifier of claim 11, wherein the dual-drive power amplifier core improves wideband operation of the dual-drive-based Doherty amplifier due to a reduction in input impedance at the dual-drive power amplifier core.

18. 12. The dual-drive-based Doherty amplifier of claim 11, wherein the first power amplifier is a class AB amplifier and the second power amplifier is a class C amplifier.

19. 12. The dual-drive-based Doherty amplifier of claim 11, further comprising an impedance inverter coupled to a power amplifier output of the first power amplifier.

20. 20. The dual-drive-based Doherty amplifier of claim 19, further comprising an output matching network coupled to the impedance inverter and to a power amplifier output of the second power amplifier, an output of the output matching network being provided to a load.

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