Systems and methods for reducing the effects of noise on solid-state quantum processors - Patents.com

Abstract

Systems and methods are disclosed for reducing the effects of high-energy radiation or charge noise on solid-state quantum processors. According to one aspect of the disclosure, a quantum computing system is provided that includes a semiconductor substrate including a bulk layer and a qubit layer, and a dielectric forming an interface with the semiconductor substrate. One or more qubits are formed in the qubit layer. The system further includes a shielding structure formed between the bulk layer and the qubit layer or between the qubit layer and the interface. The shielding structure is configured to shield the qubit layer from an electric field generated in the bulk layer due to high-energy radiation, or to shield the qubit layer from charge noise generated at the interface.

Description

[Technical field]

[0001] Aspects of the present disclosure relate generally to quantum computing, and more particularly to reducing the effects of high-energy radiation noise on solid-state quantum processors.

[0002] Another aspect of the present disclosure relates to reducing the effects of charge noise on solid-state processors. [Background technology]

[0003] Quantum computers perform calculations that classical supercomputers cannot perform, such as efficiently factoring integers or figuring out how molecules bond together using quantum chemistry. Such difficult problems can only be solved by incorporating algorithms into large quantum computers that perform quantum error correction. However, when physical quantum bit (qubit) errors are large or correlated, error correction fails.

[0004] Quantum computers have inherent errors and can typically only natively run algorithms with hundreds to thousands of logical operations. To run the most powerful and useful algorithms (e.g., those with millions to billions of logical gates), errors must be reduced to the parts per million or billion range or below. This is possible using quantum error correction. The basic idea of ​​quantum error correction is to redundantly encode the qubit state onto many physical qubits, similar to classical error correction, so that errors in the physical qubit states can be selectively measured, decoded, and corrected. For example, a surface code error correction scheme encodes a protected "logical" state on about 1000 physical qubits. If the physical errors are small (about 0.1%) and occur randomly and independently among these 1000 qubits, logical errors can be reduced to less than 0.1 parts per billion. However, if the errors are large or correlated, occurring in clusters in time or clusters across the chip in space, error correction fails. If the logical errors are large, the quantum computer loses memory and the algorithms fail.

[0005] It is therefore desirable to reduce large or correlated errors in quantum computers. Summary of the Invention [Means for solving the problem]

[0006] According to one aspect of the disclosure, a quantum computing system is provided that includes a semiconductor substrate including a bulk layer and a qubit layer, one or more qubits formed in the qubit layer, and a shielding structure formed between the bulk layer and the qubit layer, the shielding structure configured to shield the qubit layer from electric fields generated in the bulk layer due to high-energy radiation.

[0007] The shielding structure is further configured to recombine, absorb or extract electron-hole pairs that are generated in the bulk layer due to the high-energy radiation.

[0008] In some embodiments, the shielding structure includes a single layer of an n-type semiconductor. Further, in some examples, the n-type semiconductor is phosphorus-doped silicon. In such examples, the concentration of dopant in the n-type semiconductor is between approximately 30% and 50%.

[0009] In some embodiments, the thickness of the shielding structure is in the range of 10 nanometers to 500 nanometers.

[0010] In some other embodiments, the shielding structure includes multiple layers of n-type semiconductor material interposed with one or more spacer layers of intrinsic silicon material. In such embodiments, the shielding structure includes from 2 to 50 layers of n-type semiconductor material. The thickness of each shielding layer may be about 10 to 500 nanometers.

[0011] In some embodiments, the shielding structure further comprises an electrode disposed on a bottom of the bulk layer, the electrode being negatively charged to attract the hole of the electron-hole pair.

[0012] In some other embodiments, the shielding structure further comprises a metal plate disposed at the bottom of the bulk layer to attract the hole of the electron-hole pair.

[0013] According to another aspect of the present disclosure, there is provided a method of fabricating a quantum processing device, the method including the steps of preparing a bulk layer of a semiconductor substrate, preparing a clean crystalline surface of the bulk layer, exposing the clean crystalline surface of the bulk layer to dopant molecules to form a layer of dopant molecules on the exposed surface, annealing the exposed surface to incorporate at least some dopant atoms of the dopant molecules into the semiconductor to form a ground plane, and preparing a qubit layer formed of isotopically inert silicon and including a plurality of qubits.

[0014] In some embodiments, generating the ground plane further includes creating a plurality of ground plane layers interspersed with one or more spacer layers of undoped semiconductor.

[0015] The ground plane may be between 10 nanometers and 500 nanometers thick, and the dopant may be one of phosphorus or aluminum, and the concentration of the dopant in the ground plane may be between approximately 30% and 50%.

[0016] In some embodiments, the method of manufacture further comprises adding a negatively charged electrode to the bottom of the bulk layer, hi other embodiments, the method of manufacture may further comprise placing a metal plate on the bottom of the bulk layer.

[0017] According to yet another aspect of the present disclosure, a quantum processor is provided that includes a semiconductor substrate including a qubit layer, a dielectric material forming an interface with the semiconductor substrate, one or more qubits formed in the qubit layer, and a shielding structure formed between the interface and the qubit layer, the shielding structure being configured to shield the qubit layer from charge noise generated at the interface between the dielectric material and the semiconductor substrate.

[0018] In some embodiments, the shielding structure comprises a single layer of n-type semiconductor, hi other embodiments, the shielding structure comprises multiple layers of n-type semiconductor material interposed with one or more spacer layers of intrinsic silicon material.

[0019] The n-type semiconductor may be phosphorus-doped silicon. In some embodiments, the concentration of phosphorus in the n-type semiconductor is approximately 30% to 50%. Further, the thickness of the shielding structure may be within a range of 10 nanometers to 500 nanometers.

[0020] When the shielding structure includes multiple layers, the shielding structure may include from 2 to 50 layers of n-type semiconductor material, and each shielding layer may have a thickness of about 10 to 500 nanometers.

[0021] According to yet another aspect of the present disclosure, there is provided a method of fabricating a quantum processing device, the method including the steps of providing a bulk layer of a semiconductor substrate, creating a clean crystalline surface of the bulk layer, creating a qubit layer, the qubit layer being formed of isotopically inert silicon and including a plurality of qubits, growing a semiconductor layer on the qubit layer, exposing the semiconductor layer to dopant molecules to produce a layer of dopant molecules on the exposed surface, and annealing the exposed surface to incorporate at least some dopant atoms of the dopant molecules into the semiconductor and form a ground plane.

[0022] Producing the ground plane may further include creating a plurality of ground plane layers interposed with one or more spacer layers of undoped semiconductor, hi some embodiments, the ground plane is between the qubit layer and an interface formed between the semiconductor substrate and the dielectric.

[0023] The ground plane can be from one atomic layer to 500 nanometers in thickness.

[0024] Further aspects of the invention and further embodiments of the aspects described in the previous paragraphs will become apparent from the following description, given by way of example and referring to the accompanying drawings, in which: [Brief description of the drawings]

[0025] [Figure 1] 1 is a cross-sectional view of a typical quantum processor. [Diagram 2] FIG. 1 illustrates a cross-sectional view of a quantum processing device having a ground plane to mitigate the effects of cosmic ray / gamma ray events, according to one embodiment of the present disclosure. [Diagram 3] 3 is a flow chart illustrating an example of a method for fabricating the quantum processing device of FIG. 2. [Figure 4] 1 illustrates a cross-sectional view of a quantum processing device having multiple ground planes according to one embodiment of the present disclosure. [Figure 5A] 1 is a cross-sectional view of a quantum processing device having negatively charged electrodes according to some embodiments of the present disclosure. [Figure 5B] 1 is a cross-sectional view of a quantum processing device having a metal plate according to some embodiments of the present disclosure. [Figure 6] FIG. 2 is a cross-sectional view of a quantum processing device having a ground plane to reduce the effects of charge noise, according to one embodiment of the present disclosure. [Figure 7] 7 is a flow chart illustrating an example of a method for fabricating the quantum processing device of FIG. 6. [Figure 8] 1 illustrates a cross-sectional view of a quantum processing device having multiple ground planes according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The figures depict various embodiments of the present invention for purposes of example only. Those skilled in the art will readily appreciate from the following description that alternative embodiments of the structures and methods described herein may be used without departing from the principles of the invention described herein.

[0027] Reducing the effects of high-energy radiation High-energy radiation, such as cosmic rays, occurs naturally when high-energy particles bombard the atmosphere from space, where they are converted into muon particles and penetrate deep into all materials on the Earth's surface. For typical electronic devices, the effects of high-energy radiation are well known: in such devices, radiation creates charge carriers that move within the device and change its electrical properties, producing both temporary (pulsed) and permanent changes.

[0028] It has been found that high energy radiation can cause large correlated errors in quantum computing chips, especially superconducting quantum chips. When a cosmic ray muon passes through a superconducting quantum chip, it deposits a large amount of energy (~200 keV) in the substrate of the superconducting quantum processor, briefly "heating" the chip. In currently designed superconducting quantum chips, this shortens the memory time of the qubits (~1-10% of the normal memory time) both spatially (across the chip) and for a long period of time (~10 ms). Thus, the qubit errors during this event are so large and correlated that error correction fails and the stored logical qubit state is destroyed. Cosmic ray muons strike the quantum chip every few seconds, which can render some fairly powerful algorithms running on superconducting quantum computers inoperable.

[0029] Several techniques have been proposed to mitigate the effects of cosmic rays on quantum chips, especially superconducting quantum chips. For example, one proposed technique is to operate the quantum computer deep underground or in a specially constructed laboratory. However, this is not a good commercial solution. Also, there is always natural background radiation (from the decay of heavy elements such as uranium) which generates similar energetic events that deposit energy in the quantum chip and destroy the state of the qubits. Another technique has been proposed to shield the quantum chip using thick lead blocks (about 10 cm thick) outside the cryostat to reduce the effects of external radiation on the quantum chip and improve the coherence time of the qubits. Although this shielding technique may protect the chip from cosmic rays, it is not very useful for shielding against background radiation. Furthermore, this technique would not be practical for future scalable quantum computers.

[0030] Therefore, solid-state quantum chips will need to be redesigned.

[0031] The inventors of the present invention have found that, unlike superconducting qubits / processors, solid-state qubits / processors are less susceptible to phonon energy generated by background radiation events and are less adversely affected by "heat pulses" of phonon energy. Instead, in solid-state quantum processors (e.g., those made using semiconductors such as silicon and / or germanium), background radiation events such as cosmic rays and gamma rays generate electron-hole pairs within the device. Over time, these electron-hole pairs become trapped and accumulate within the semiconductor substrate, causing a charged background (also called a "charge offset"). The charge offset / background charge affects qubits (e.g., during initialization, operation, and readout) and gate operations, causing correlated qubit errors. As more electron-hole pairs are generated, this effect becomes more pronounced.

[0032] Furthermore, solid-state quantum chips require cooling at millikelvin temperatures for optimal operation. At such low temperatures, electron-hole pairs (or charge offsets) created by cosmic / gamma ray events become even more problematic (compared to room temperature) because at such low temperatures the electron-hole pairs tend to freeze out, making it less likely that they can move around or recombine within the semiconductor substrate.

[0033] The problem of electron-hole pair accumulation is known in classical electronic transistors at room temperature but has not been discussed or addressed in solid-state quantum systems, and it is desirable to eliminate correlated qubit errors caused by electron-hole accumulation from solid-state quantum processors containing large numbers of qubits.

[0034] Embodiments of the present disclosure attempt to address this problem. Specifically, some embodiments of the present disclosure provide new solid-state quantum processor chip architectures that help reduce or eliminate the effects of cosmic rays, gamma rays, or other background radiation on the qubits / gates of a solid-state quantum processor.

[0035] Typically, a solid-state quantum processor includes a semiconductor substrate, such as a silicon substrate. Qubits are typically disposed / fabricated on top of the semiconductor substrate. FIG. 1 illustrates one such semiconductor-based quantum processing device 100. The device 100 includes a semiconductor substrate 102 and a dielectric 104. In this example, the semiconductor substrate is silicon 28 and the dielectric is silicon dioxide. In other embodiments, the semiconductor substrate can be natural silicon, or isotopically purified silicon 28, or any other semiconductor material, such as germanium. The semiconductor substrate 102 and the dielectric 104 form an interface 105, which in this example is a Si / SiO2 interface. Additionally, the device 100 includes a number of qubits formed in the semiconductor substrate 102 below the interface 105. In this example, the device 100 includes five qubits 106A-106E. Gates 108A-108E that control the qubits 106A-106E are fabricated on top of the dielectric 104.

[0036] In this disclosure, the portion of semiconductor substrate 102 in which the qubits are formed is referred to as qubit layer 103, and the remaining portion of the semiconductor substrate is referred to as bulk layer 107. The thickness of qubit layer 103 may depend on the size of the qubits, the depth from interface 105 at which the qubits are formed, etc. It will be understood that the layers of device 100 in this figure are not drawn to scale, and that in actual implementations the scale of the layers may vary significantly. For example, the ratio of semiconductor bulk layer to qubit layer may be 49:1 in some examples.

[0037] Furthermore, although five qubits and five gates are shown in FIG. 1 and in the rest of the device diagrams of this disclosure, in actual implementations the number of qubits and gates may vary significantly from these numbers. In some cases, quantum processing device 100 may include tens, hundreds, or even thousands of qubits. Furthermore, quantum processing device 100 may be a node of a larger quantum processor that includes multiple interconnected nodes 100.

[0038] As shown in FIG. 1, a cosmic / gamma ray event can create clusters 112 of electron-hole pairs in the silicon substrate, which can lead to correlated errors over time.

[0039] Typically, cosmic rays and gamma rays have energies in the range of about 1 MeV. When a cosmic ray / gamma ray event occurs in a semiconductor substrate 102 such as silicon, approximately 10% of the cosmic ray / gamma ray energy is utilized to generate electron-hole pairs in the silicon substrate. The generation of electron-hole pairs may require approximately 3.6 eV of energy, resulting in a total of approximately 60,000 electron (negative charge) hole (positive charge) pairs being generated in a single cosmic ray event. These positive and negative charges are randomly distributed throughout the electron-hole cloud 112. If the volume of the cloud 112 is approximately 100 cubic micrometers, then the density of excitations within the cloud will be approximately one excitation every 2 micrometers.

[0040] Therefore, we can assume that the average distance between the electrons and holes is about 1 micrometer. With these distances, the electrons and holes can generate a voltage V given by:

[0041]

number

[0042] Since electrons and holes generate negative and positive voltages, respectively, these voltages are randomly added in sign and magnitude to distant voltages. Summing the random positive and negative voltages results in an average voltage of zero. However, the net squared voltage is proportional to the number of voltage sums. In this example, the voltage decreases inversely proportional to the distance, but the average voltage variation can be calculated as an integral over all particle voltages. In this example, the distance is approximated with a continuous distribution over a radius given by the dimensionless distance Rcloud / 2d, where Rcloud is the radius of the electron-hole cloud 112.

[0043]

number

[0044] For the above values ​​of voltage, Rcloud and d,

[0045]

number

[0046] Thus, in some instances, the charge offset voltage due to a single cosmic ray / gamma ray event can be approximately 2.9 meV.

[0047] Generally speaking, a change in the potential of the donor atom (of a qubit) of about 50 meV can change its charge state. To maintain the charge state of the qubit, the potential of the donor needs to be kept constant (e.g., a voltage stability of 5 μeV). This stability value is 600 times smaller than the above calculated charge offset voltage of 2.9 meV produced by a cosmic / gamma ray event. Therefore, this gamma or cosmic ray event will have a large effect on the qubit.

[0048] To mitigate the effects of such cosmic rays / gamma rays on the semiconductor substrate 102, the solid-state quantum device of the present disclosure is designed such that the bulk layer 107 is shielded from the effects of cosmic rays / gamma rays.

[0049] By shielding the bulk layer 107 (the thickest layer in the quantum processing device 100), the majority of the semiconductor 102 is protected. With a bulk to qubit layer ratio of 49:1, roughly 98% of the semiconductor 102 can be shielded from the mitigating effects of high energy radiation. The depth of the qubit layer 103 is typically about 10-500 nanometers (and may be up to 1000 nanometers in some embodiments), and since this layer is unshielded, it may be subject to cosmic / gamma radiation, i.e., electron-hole pairs may be formed in this layer. However, given the thinness of this layer, the likelihood of a cosmic / gamma ray event occurring in the qubit layer 103 is very low. Furthermore, the accumulation of electron-hole pairs in this layer 103 is limited and not enough to generate a charge offset that would cause significant correlated errors in the quantum processing device.

[0050] FIG. 2 illustrates an example of a quantum processing device 200 according to some embodiments of the present disclosure.

[0051] Similar to device 100 shown in FIG. 1, quantum processing device 200 includes a semiconductor substrate 102 and a dielectric 104. In this example, the semiconductor substrate is silicon and the dielectric is silicon dioxide. Semiconductor substrate 102 and dielectric 104 form interface 105, which in this example is a Si / SiO2 interface. Additionally, device 100 includes a plurality of qubits formed in semiconductor substrate 102 below interface 105. In this example, device 100 includes five qubits 106A-106E. It will be appreciated that this is merely an example and that in an actual implementation, a quantum processing device may include hundreds, if not thousands, of qubits. Additionally, the qubits may be formed using any known solid-state technology. For example, qubits 106 may be charge-based or spin-based qubits, i.e., quantum information is encoded into the charge or spin of the qubit, respectively. Examples of such qubits include donor-based phosphorus atomic qubits, silicon MOS qubits, silicon spin qubits, ion traps, topological qubits, gate-patterned quantum dots, and gated semiconductor quantum dots.

[0052] Gates 108A-108E, which control qubits 106A-106E, are fabricated on dielectric 104. It will be understood that, as with the device shown in Figure 1, the layers of device 100 in this figure are not drawn to scale.

[0053] Quantum processing device 200 also includes a ground plane layer 202. In some examples, ground plane 202 can be an n-type semiconductor layer, such as an n-type silicon semiconductor doped with a Group V element, such as phosphorus, arsenic, or antimony. In a preferred embodiment, ground plane 202 is formed of phosphorus-doped silicon epitaxially fabricated on bulk layer 107 of silicon substrate 102.

[0054] Ground plane 202 may shield the top of silicon substrate 102 from cosmic rays / gamma rays coming from the environment / space. Generally speaking, even with ground plane 202, cosmic rays can enter silicon substrate 102 from the bottom or sides of the quantum processing chip and generate electron-hole pairs in the silicon substrate. However, ground plane 202 is more conductive than the silicon substrate, and therefore shields qubit layer 103 from electric fields generated by stationary or moving trapped charges in bulk layer 107 and / or qubit layer 103.

[0055] In some examples, the thickness of ground plane 202 is in the range of 10-50 nm. Additionally, ground plane 202 may be electrically connected to the electrical ground of a measurement setup used to operate quantum processing device 200.

[0056] 3 is a flow chart illustrating an example of a fabrication procedure for fabricating quantum processing device 200. Method 300 describes a process for fabricating quantum processing device 200 having donor atom based qubits. However, it will be understood that this is merely an example and that the process may be performed to fabricate quantum processing device 200 having any other type of qubit 106 without departing from the scope of the present disclosure.

[0057] In step 302, a semiconductor substrate surface is prepared. If the substrate is silicon, this step involves forming a clean silicon substrate surface in ultra-high-vacuum (UHV) by heating it to near its melting point. The surface has a 2×1 unit cell and is composed of rows of σ-bonded Si dimers, with the remaining dangling bond of each Si atom forming a weak π bond with the other Si atom of the dimer that contains it.

[0058] Next, in step 304, a ground plane is formed on the prepared bulk layer 107. This can be done using a variety of techniques. For example, in one example, the ground plane layer can be formed by ion implantation. In another example, the ground plane layer can be formed by diffusion. In either case, a ground plane is formed that includes a layer or blanket of metal atoms (e.g., phosphorus or aluminum). The depth of the ground plane can be between one atomic layer and up to 500 nanometers. Additionally, the concentration of dopants can be between 20-50%.

[0059] If the ground plane is phosphorus-doped silicon, phosphine (PH3) gas is introduced into the vacuum system through a controlled leak valve connected to a specially designed phosphine dosing system. The phosphine molecules bind strongly to the exposed silicon 2x1 surface. Subsequent heating of the surface dissociates the phosphine molecules and incorporates the phosphorus atoms into the silicon. In some embodiments, a blanket layer of phosphorus atoms can be created in this manner. Additional layers of phosphorus atoms can then be created depending on the depth of the ground plane required. A similar process can also be used to create boron or aluminum doped ground planes.

[0060] Next, in step 306, the ground plane layer 202 is encapsulated with a silicon layer. The silicon layer can be tens of nm. In one example, the ground plane layer 202 is encapsulated using state-of-the-art molecular beam epitaxy. This step is called encapsulation.

[0061] In step 308, the surface of the encapsulated ground plane layer is prepared, similar to the process of step 302. However, this step and all subsequent surface preparation steps are performed at a lower temperature to avoid diffusion of dopants patterned underneath.

[0062] Then, in step 310, qubits 106 are patterned on the silicon substrate. Specifically, an STM tip is used to selectively desorb H atoms from the passivated surface by applying appropriate voltages and tunneling currents to pattern the H resist. In this way, areas of bare reactive Si atoms are exposed, allowing the reactive species to then be directly adsorbed onto the Si surface. Phosphine (PH3) gas is introduced into the vacuum system through a controlled leak valve connected to a specially designed phosphine microdosing system. The phosphine molecules bind strongly to the exposed silicon 2x1 surface through holes in the hydrogen resist. Subsequently, heating the STM-patterned surface for crystal growth dissociates the phosphine molecules and incorporates P into the silicon. Therefore, to generate the required donor atomic arrangement, the STM-patterned H-passivated surface is exposed to PH3. After the hydrogen is desorbed, silicon is then overgrown at room temperature, and the surface can be rapidly annealed. Silicon is then grown on the surface at elevated temperatures.

[0063] A dielectric layer may then be formed on the qubit layer 103. The dielectric layer may be formed by exposing the device to ambient air or by growing a dielectric layer over the qubit layer. Finally, in some embodiments, a conductive gate 108 may be aligned on the surface.

[0064] In some cases, the gate may be aligned directly on top of the silicon substrate of quantum processing device 200. In such cases, there is no dielectric layer between the silicon substrate and the gate.

[0065] Further, it will be appreciated that gate 108 need not be aligned on the surface of the device in all implementations. In some embodiments, gate 108 may be "flush" with qubit layer 103. In such cases, the gate may be patterned in step 310.

[0066] It will be understood that the layer thicknesses and interlayer distances described in method 300 are merely exemplary, and the actual layer thicknesses and interlayer distances will vary depending on the qubit technology selected for the quantum computer, the number of electrons, and the static magnetic field value selected.

[0067] It is often difficult to fabricate thick layers of ground planes. This is because if the concentration of dopants is high, it becomes difficult for subsequent layers of dopants to "stick" or adhere to the previous layers, because the previous layers are also doped. Furthermore, if the dopant atoms are very close to each other, a thick ground plane with a high concentration can become electrically inactive. To address one or more of these issues, the ground plane can be split. FIG. 4 illustrates another embodiment of a quantum processing system 400. Specifically, in this embodiment, instead of a single ground plane 202, the shielding structure includes multiple ground plane layers 404 between the bulk layer 107 and the qubit layer 103. The layers of ground planes (formed of n-type semiconductors) are separated by undoped semiconductor spacer layers 406.

[0068] Each ground plane can be between 10 and 500 nanometers, with 10 nanometers representing a single layer of doped silicon and 500 nanometers representing about 50 layers of doped silicon (if the dopant is phosphorus). Above each layer of ground plane, a spacer layer of undoped silicon is fabricated. The thickness of the spacer layer can also be between 10 and 500 nanometers.

[0069] In the example shown in FIG. 4, the shielding structure includes three ground plane layers 404 with two spacer layers 406 interposed. However, in other examples, the number of ground plane layers and spacer layers may be varied without departing from the scope of the present disclosure. For example, in one embodiment, each ground plane layer may be 10 nanometers and the device may include 50 such ground plane layers with interposed spacer layers. Furthermore, it will be understood that the thickness of each ground plane layer or the dopant concentration of each layer need not be the same. The thickness of the ground plane layers may vary, and the dopant concentrations of the various ground plane layers may also vary.

[0070] Two other variations of quantum processing systems according to embodiments of the present disclosure are shown in Figures 5A and 5B. Figure 5A shows a quantum processing system 500 including a negatively charged electrode 502 disposed at the bottom of the bulk layer. A conductive ground plane (either a single layer (as shown in Figure 2) or multiple layers (as shown in Figure 3)) shields the qubit layer from charges generated by stationary or moving charges in the bulk layer. Additionally, the ground plane 202, 404 attracts the electrons of the electron-hole pairs from the substrate. In this example, the electrode 502 may attract the holes. By including the negative electrode 502 in combination with the ground plane 202, 404, the device structure shown in Figure 5A may be capable of absorbing / extracting electron-hole pairs faster than the structures shown in Figures 2 and 4.

[0071] 5B, quantum processing system 510 replaces negatively charged electrode 502 with a metal plate 512 (e.g., copper, aluminum, or any other metal). In this case, the metal plate is more conductive than semiconductor ground plane 202, so holes are attracted to metal plate 512 and background electrons of the electron-hole pair are repelled away from metal plate 512 into ground plane 202 and extracted out of substrate 202.

[0072] Although method 300 describes a process for fabricating quantum processing device 200 of Figure 2, it may also be used to fabricate quantum processing devices 400, 500, and 510 of Figures 4, 5A, and 510, respectively. For example, to fabricate quantum processing device 400 of Figure 4, method step 304 is modified to grow multiple ground plane layers 404 alternating with undoped silicon layers 406.

[0073] Similarly, an additional method step may be performed at the end of method 300 to add a negatively charged electrode 502 to the bottom of bulk layer 107 to produce quantum processing device 500 of Figure 5A. Alternatively, an additional method step may be performed to place a metal plate 512 on the bottom of bulk layer 107 to produce quantum processing device 510 of Figure 5B.

[0074] The above embodiments describe structures sufficient to keep the energy of muons away from the semiconductor bulk layer 107 and to shield the qubit layer from trapped charges in the bulk layer.

[0075] Reducing the effects of charge noise on quantum computers Charge noise is another type of noise that can cause errors in quantum computers. Charge noise is usually caused by imperfections at the interface 105 between the semiconductor substrate 102 and the dielectric 104. Defects at the Si / SiO2 interface 105 or in the dielectric layer 104 can be described as a bistable system known as a two-level fluctuator (TLF). Each TLF has its own Lorentzian spectrum. When all the random distributions of TLFs are added together, 1 / f noise occurs.

[0076] Some aspects of the present disclosure attempt to address this problem. In particular, some embodiments of the present disclosure provide a new solid-state quantum processor chip architecture that helps reduce or eliminate the impact of charge noise caused by the interface 105 between the silicon substrate 102 and the dielectric 104 on the qubits / gates of the solid-state quantum processor.

[0077] To mitigate the effects of charge at interface 105 or dielectric 104, some of the solid-state quantum devices of the present disclosure are designed such that qubit layer 103 is shielded from interface 105 and therefore shielded from the effects of charge noise.

[0078] FIG. 6 illustrates an example of a quantum processing device 600 according to some embodiments of the present disclosure.

[0079] Similar to device 100 shown in FIG. 1, quantum processing device 600 includes a semiconductor substrate 102 and a dielectric 104. In this example, the semiconductor substrate is silicon and the dielectric is silicon dioxide. Semiconductor substrate 102 and dielectric 104 form interface 105, which in this example is a Si / SiO2 interface. Additionally, device 600 includes a plurality of qubits formed in semiconductor substrate 102 below interface 105. In this example, device 600 includes five qubits 106A-106E. It will be appreciated that this is merely an example and that in an actual implementation, quantum processing device 600 may include hundreds, if not thousands, of qubits. Additionally, the qubits may be formed using any known solid-state technology. For example, qubits 106 may be charge-based or spin-based qubits, i.e., quantum information is encoded into the charge or spin of the qubit, respectively. Examples of such qubits include donor-based phosphorus atomic qubits, silicon MOS qubits, silicon spin qubits, ion traps, topological qubits, gate-patterned quantum dots, and gated semiconductor quantum dots.

[0080] Gates 108A-108E, which control qubits 106A-106E, are fabricated on dielectric 104. It will be understood that, as with the device shown in Figure 1, the layers of device 100 in this figure are not drawn to scale.

[0081] Quantum processing device 200 also includes a ground plane layer 602 between qubit layer 103 and interface 105. In some examples, ground plane 602 can be an n-type semiconductor layer, such as an n-type silicon semiconductor doped with a Group V element, such as phosphorus, arsenic, or antimony. In a preferred embodiment, ground plane 602 is formed of phosphorus-doped silicon epitaxially fabricated between qubit layer 103 and interface 105.

[0082] Ground plane 602 may shield qubit layer 103 from charge noise generated at interface 105 or dielectric 104. In some examples, ground plane 602 has a thickness in the range of 10-50 nm. Additionally, the ground plane may be electrically connected to an electrical ground of a measurement setup used to operate quantum processing device 600.

[0083] 7 is a flow chart illustrating an example of a fabrication procedure for fabricating quantum processing device 600. Method 700 describes a process for fabricating quantum processing device 600 having donor atom based qubits. However, it will be understood that this is merely an example and that the process may be performed to fabricate quantum processing device 600 having any other type of qubits 106 without departing from the scope of the present disclosure.

[0084] In step 702, a semiconductor substrate surface is prepared. If the substrate is silicon, this step involves forming a clean silicon substrate surface in ultra-high vacuum (UHV) by heating it to near its melting point. The surface has a 2×1 unit cell and is composed of rows of σ-bonded Si dimers, with the remaining dangling bond of each Si atom forming a weak π bond with the other Si atom of the dimer that contains it.

[0085] Then, in step 704, qubits 106 are patterned on the silicon substrate. Specifically, the STM tip is used to selectively desorb H atoms from the passivated surface by applying appropriate voltages and tunneling currents to form patterns in the H resist. In this way, areas of bare reactive Si atoms are exposed, which then allow for direct adsorption of reactive species onto the Si surface. Phosphine (PH3) gas is introduced into the vacuum system through a controlled leak valve connected to a specially designed phosphine microdosing system. The phosphine molecules bind strongly to the exposed silicon 2x1 surface through holes in the hydrogen resist. Subsequently, heating the STM-patterned surface for crystal growth dissociates the phosphine molecules and incorporates P into the silicon. Therefore, to generate the required donor atomic arrangement, the STM-patterned H-passivated surface is exposed to PH3. After the hydrogen is desorbed, silicon can be overgrown at room temperature and the surface can be rapidly annealed. Silicon is then grown on the surface at elevated temperatures. In some embodiments, 10-1000 nanometers of silicon may be grown on the qubit layer 103 .

[0086] Next, in step 706, a ground plane 602 is formed on the grown silicon. This can be done using a variety of techniques. For example, in one example, the ground plane layer 602 can be formed by ion implantation. In another example, the ground plane layer 602 can be formed by diffusion. In either case, a ground plane is formed that includes a layer or blanket of metal atoms (e.g., phosphorus or aluminum). The depth of the ground plane 602 can be between one atomic layer and up to 500 nanometers. Additionally, the concentration of dopants can be between 20-50%.

[0087] If the ground plane 602 is phosphorus-doped silicon, phosphine (PH3) gas is introduced into the vacuum system through a controlled leak valve connected to a specially designed phosphine dosing system. The phosphine molecules bind strongly to the exposed silicon 2x1 surface. Subsequent heating of the surface dissociates the phosphine molecules and incorporates the phosphorus atoms into the silicon. In some embodiments, a blanket layer of phosphorus atoms may be created in this manner. Additional layers of phosphorus atoms may then be created depending on the depth of the ground plane 602 required. A similar process may also be used to create boron or aluminum doped ground planes.

[0088] Next, in step 708, the ground plane layer 202 is encapsulated with a silicon layer. The silicon layer can be tens of nm. In one example, the ground plane layer 202 is encapsulated using state-of-the-art molecular beam epitaxy. This step is called encapsulation.

[0089] In step 710, the surface of the encapsulated ground plane layer is prepared, similar to the process of step 702. However, this step and all subsequent surface preparation steps are performed at a lower temperature to avoid diffusion of dopants patterned underneath.

[0090] A dielectric layer may then be formed on the qubit layer 103. The dielectric layer may be formed by exposing the device to ambient air or by growing a dielectric layer over the qubit layer. Finally, in some embodiments, a conductive gate 108 may be aligned on the surface.

[0091] In some cases, the gate may be aligned directly on top of the silicon substrate of quantum processing device 200. In such cases, there is no dielectric layer between the silicon substrate and the gate.

[0092] Further, it will be appreciated that gate 108 need not be aligned on the surface of the device in all implementations. In some embodiments, gate 108 may be "flush" with qubit layer 103. In such cases, the gate may be patterned in step 704 as qubit layer 103 is formed.

[0093] The layer thicknesses and interlayer distances described in method 700 are merely examples. The actual layer thicknesses and interlayer distances will vary depending on the qubit technology selected for the quantum computer, the number of electrons, and the static magnetic field value selected.

[0094] It is often difficult to fabricate thick layers of ground planes. This is because if the concentration of dopants is high, it becomes difficult for subsequent layers of dopants to "stick" or bond to the previous layers, because the previous layers are also doped. Furthermore, if the dopant atoms are very close to each other, a thick ground plane with a high concentration can become electrically inactive. To address one or more of these issues, the ground plane can be split. FIG. 8 illustrates another embodiment of a quantum processing system 800. Specifically, in this embodiment, instead of a single ground plane 602, the shielding structure includes multiple ground plane layers 804 between the qubit layer 103 and the interface 105. The layers of ground planes (formed of n-type semiconductors) are separated by undoped semiconductor spacer layers 806.

[0095] Each ground plane can be between 10 and 500 nanometers, with 10 nanometers representing a single layer of doped silicon and 500 nanometers representing about 50 layers of doped silicon (if the dopant is phosphorus). Above each layer of ground plane, a spacer layer of undoped silicon is fabricated. The thickness of the spacer layer can also be between 10 and 500 nanometers.

[0096] In the example shown in FIG. 8, the shielding structure includes three ground plane layers 804 with two spacer layers 806 interposed. However, in other examples, the number of ground plane layers and spacer layers may be varied without departing from the scope of the present disclosure. For example, in one embodiment, each ground plane layer may be 10 nanometers and the device may include 50 such ground plane layers with interposed spacer layers. Furthermore, it will be understood that the thickness of each ground plane layer or the dopant concentration of each layer need not be the same. The thickness of the ground plane layers may vary, and the dopant concentrations of the various ground plane layers may also vary.

[0097] Although method 700 describes a process for fabricating quantum processing device 600 of Figure 6, it can also be used to fabricate quantum processing device 800 of Figure 8. For example, to fabricate quantum processing device 800 of Figure 8, method step 706 is modified to grow multiple ground plane 804 layers alternating with undoped silicon 806 layers.

[0098] The above embodiments describe structures that shield the qubit layer 103 from charge noise at the interface, allowing the qubit layer to be fabricated close to the interface 105, eliminating the need to embed the qubit layer 103 deep (e.g., hundreds of nanometers) in the semiconductor substrate.

[0099] Although this specification contains many specific details of implementation, these are not intended to limit the scope of the invention or what may be claimed, but are instead presented as descriptions of features specific to particular embodiments. Certain features described in this specification in the context of a particular embodiment can also be implemented in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any combination.

[0100] The foregoing description of embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or to limit the invention to the precise form disclosed. Those skilled in the art will recognize that many modifications and variations are possible in light of the above disclosure.

[0101] Finally, the language used herein has been selected primarily for purposes of readability and explanation, and may not have been selected to delineate or delineate the subject matter of the invention. Accordingly, it is intended that the scope of the invention be limited not by this detailed description, but rather by the claims that issue on an application based thereon. Accordingly, the disclosure of embodiments of the invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

[0102] As used herein, the term "comprise" and variations of that term, such as "comprising", "comprises" and "comprised", are not intended to exclude further additional elements, components, integers or steps unless the context requires.

Claims

1. a semiconductor substrate including a bulk layer and a qubit layer; one or more qubits formed in the qubit layer; a shielding structure formed between the bulk layer and the qubit layer, the shielding structure being configured to shield the qubit layer from an electric field generated in the bulk layer due to high-energy radiation; A quantum processing device comprising:

2. The quantum processing device of claim 1 , wherein the shielding structure is further configured to recombine, absorb or extract electron-hole pairs generated in the bulk layer due to high-energy radiation.

3. The quantum processing device of claim 1 , wherein the shielding structure comprises a single layer of an n-type semiconductor.

4. The quantum processing device of claim 3 , wherein the n-type semiconductor is phosphorus-doped silicon.

5. The quantum processing device of claim 4 , wherein the concentration of phosphorus in the n-type semiconductor is between approximately 30% and 50%.

6. The quantum processing device of any one of claims 1 to 5, wherein the shielding structure has a thickness in the range of 10 nanometers to 500 nanometers.

7. 3. The quantum processing device of claim 1, wherein the shielding structure comprises multiple layers of n-type semiconductor material interposed with one or more spacer layers of intrinsic silicon material.

8. The quantum processing device of claim 7 , wherein the shielding structure includes between 2 and 50 layers of n-type semiconductor material.

9. The quantum processing device of claim 8, wherein each shielding layer has a thickness of about 10 to 500 nanometers.

10. The quantum processing device of any one of claims 1 to 9, wherein the shielding structure further comprises an electrode disposed at a bottom of the bulk layer, the electrode being negatively charged to attract holes of the electron-hole pair.

11. The quantum processing device of claim 1 , wherein the shielding structure further comprises a metal plate disposed at a bottom of the bulk layer to attract the hole of the electron-hole pair.

12. 1. A method of manufacturing a quantum processing device, comprising: Providing a bulk layer of a semiconductor substrate; preparing a clean crystalline surface of the bulk layer; exposing the clean crystalline surface of the bulk layer to dopant molecules to produce a layer of dopant molecules on the exposed surface; annealing the surface to incorporate at least some of the dopant atoms of the dopant molecules into the semiconductor to form a ground plane; creating a qubit layer, the qubit layer being formed of isotopically inert silicon and including a plurality of qubits; A method comprising:

13. generating the ground plane Creating multiple ground plane layers with one or more spacer layers of undoped semiconductor interposed therebetween. The method of claim 12 further comprising:

14. The method of claim 12 or 13, wherein the ground plane is between the bulk layer and the qubit layer.

15. The method of any one of claims 12 to 14, wherein the ground plane has a thickness of from one atomic layer to 500 nanometers.

16. The method according to any one of claims 12 to 15, wherein the dopant is one of phosphorus or aluminium.

17. The method of any one of claims 12 to 16, wherein the concentration of dopant in the ground plane is between approximately 20% and 50%.

18. The method of any one of claims 12 to 17, further comprising the step of adding a negatively charged electrode to the bottom of the bulk layer.

19. The method of any one of claims 12 to 17, further comprising the step of placing a metal plate on the bottom of the bulk layer.

20. a semiconductor substrate including a qubit layer; a dielectric material forming an interface with the semiconductor substrate; one or more qubits formed in the qubit layer; a shielding structure formed between the interface and the qubit layer, the shielding structure being configured to shield the qubit layer from charge noise generated at the interface between the dielectric material and the semiconductor substrate; A quantum processor comprising:

21. 21. The quantum processor of claim 20, wherein the shielding structure comprises a single layer of an n-type semiconductor.

22. 22. The quantum processor of claim 21, wherein the n-type semiconductor is phosphorus-doped silicon.

23. 23. The quantum processor of claim 22, wherein a concentration of phosphorus in the n-type semiconductor is approximately 30% to 50%.

24. 24. The quantum processor of claim 20, wherein the shielding structure has a thickness in the range of 10 nanometers to 500 nanometers.

25. 21. The quantum processor of claim 20, wherein the shielding structure includes multiple layers of n-type semiconductor material interposed with one or more spacer layers of intrinsic silicon material.

26. 26. The quantum processor of claim 25, wherein the shielding structure includes between 2 and 50 layers of n-type semiconductor material.

27. 27. The quantum processor of claim 25 or claim 26, wherein each shielding layer has a thickness of about 10 to 500 nanometers.

28. 1. A method of manufacturing a quantum processing device, comprising: Providing a bulk layer of a semiconductor substrate; preparing a clean crystalline surface of the bulk layer; creating a qubit layer, the qubit layer being formed of isotopically inert silicon and including a plurality of qubits; growing a semiconductor layer over the qubit layer; exposing the semiconductor layer to dopant molecules to produce a layer of dopant molecules on the exposed surface; annealing the exposed surface to incorporate at least some of the dopant atoms of the dopant molecules into the semiconductor to form a ground plane; A method comprising:

29. generating the ground plane Creating multiple ground plane layers with one or more spacer layers of undoped semiconductor interposed therebetween.

30. The method of claim 28, further comprising:

30. 30. The method of claim 28 or 29, wherein the ground plane is between the qubit layer and an interface formed between the semiconductor substrate and a dielectric.

31. The method of any one of claims 28 to 30, wherein the ground plane has a thickness of from one atomic layer to 500 nanometers.

32. A method according to any one of claims 28 to 31, wherein the dopant is one of phosphorus or aluminium.

33. The method of any one of claims 28 to 32, wherein the concentration of dopant in the ground plane is between approximately 20% and 50%.

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