Substrate preparation for GaN growth

Abstract

An exemplary semiconductor structure may include a silicon-containing substrate. The structure may include a first layer of a first metal nitride overlying the silicon-containing substrate. The structure may include a second layer of a second metal nitride overlying the first layer of the first metal nitride. The structure may include a gallium nitride structure overlying the layer of metal nitride.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Provisional Application No. 17 / 695,206, entitled "SUBSTRATE PROCESSING FOR GaN GROWTH," filed on March 15, 2022, the entire contents of which are incorporated herein by reference for all purposes.

[0002]

[0002] The present technology relates to semiconductor processing and materials. More specifically, the present technology relates to forming processes and materials for light emitting diode structures and components. [Background technology]

[0003]

[0003] An LED panel or device may be formed from a number of light sources that act as pixels on the device. A pixel may be formed with a monochromatic light source that is then passed through a conversion layer to produce color. Alternatively, individual color light sources may be formed at the pixel. In either case, up to millions of light sources may be formed and connected for operation. The light sources used in LED panels are well developed, but the manufacturing of the structure may be prone to defects that may degrade performance.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technique addresses these and other needs. Summary of the Invention

[0005]

[0005] An exemplary semiconductor structure may include a silicon-containing substrate. The structure may include a first layer of a first metal nitride overlying the silicon-containing substrate. The structure may include a second layer of a second metal nitride overlying the first layer of the first metal nitride. The structure may include a gallium nitride structure overlying the first layer of the first metal nitride.

[0006]

[0006] In some embodiments, the silicon-containing substrate may or may not include silicon. The first metal nitride and the second metal nitride may be selected from the group consisting of aluminum nitride, hafnium nitride, and niobium nitride. The first metal nitride may be or may include aluminum nitride, and the second metal nitride may be or may include hafnium nitride. The structure may include a dielectric material layer covering at least a portion of the second layer of the second metal nitride. The dielectric material layer may be or may include silicon nitride. The dielectric material layer may be discontinuous.

[0007]

[0007] Some embodiments of the present technology may include a semiconductor processing method. The method may include forming a first layer of a first metal nitride material on a substrate. The method may include forming a second layer of a second metal nitride on the first layer of the first metal nitride. The method may include annealing the first layer of the first metal nitride and the second layer of the second metal nitride. The method may include forming a gallium-containing material on the second layer of the second metal nitride.

[0008] In some embodiments, the first metal nitride may be selected from the group consisting of aluminum nitride and niobium nitride. The second metal nitride may be or may include hafnium nitride. The first layer of the first metal nitride and the second layer of the second metal nitride may be formed by physical vapor deposition. The first layer of the first metal nitride and the second layer of the second metal nitride may be formed at a temperature of 1000° C. or less. Annealing the first layer of the first metal nitride and the second layer of the second metal nitride may include annealing at a temperature of about 800° C. or more. A surface of the second layer of the second metal nitride opposite the first layer of the first metal nitride may be characterized by a maximum roughness of about 1.0 μm or less. The gallium-containing material may be characterized by a pyramidal structure. The gallium-containing material may be or may include gallium nitride.

[0009]

[0009] Some embodiments of the present technology may include a semiconductor processing method. The method may include forming a first layer of a first metal nitride material on a silicon substrate. The method may include forming a second layer of a second metal nitride on the first layer of the first metal nitride. The method may include annealing the first layer of the first metal nitride and the second layer of the second metal nitride at a temperature of about 800° C. or greater. The method may include forming a dielectric material on the second layer of the second metal nitride. The dielectric material may be discontinuous. The method may include forming a gallium-containing material on the second layer of the second metal nitride between portions of the dielectric material.

[0010] In some embodiments, the second layer of the second metal nitride may be formed at a lower temperature than the first layer of the first metal nitride. The first layer of the first metal nitride and the second layer of the second metal nitride may be formed by physical vapor deposition. The first metal nitride may be or may include aluminum nitride, and the second metal nitride may be or may include hafnium nitride. The gallium-containing material may be or may include gallium nitride.

[0011]

[0011] Such techniques can provide numerous advantages over conventional systems and techniques. For example, the techniques can provide a method for forming gallium-containing materials characterized by reduced dislocations or defects propagating throughout the material. Additionally, the techniques can enable the ability to utilize physical vapor deposition to fabricate seed layers for growing gallium nitride materials. These and other embodiments, along with their many advantages and features, are described in more detail in the following description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed techniques may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0013] [Figure 1] 1 shows a top view of an embodiment of an exemplary processing system, in accordance with some embodiments of the present technique. [Diagram 2] 1 illustrates selected steps of a method for forming a semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3A-D] 1 shows a schematic diagram of a device developed in accordance with some embodiments of the present technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]

[0016] Some drawings are included as schematics. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematics, the drawings are provided to aid in understanding and may not include all aspects or information compared to a realistic depiction and may include material that is emphasized for illustrative purposes.

[0015]

[0017] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any of the similar components having the same first reference number, regardless of the letter.

[0016]

[0018] An LED may include a semiconductor structure that emits light when a current is passed through the structure. Electrons in the semiconductor recombine with holes, releasing energy in the form of photons. Many conventional LEDs are formed of a thick (e.g., greater than a micron) film that may define a quantum well. Dislocations, such as threading dislocations or defects, may propagate, for example, from the underlying substrate through the material in the quantum well, resulting in non-radiative recombination in the quantum well region, causing the LED to emit phonons rather than photons. In conventional techniques, threading dislocations may easily pass to the surface of the quantum well, undesirably increasing non-radiative recombination. These dislocations may be formed or present due to a number of factors associated with the growth or structure formation process, and may penetrate subsequent device layers formed, including the LED active region, further reducing the efficiency of the device.

[0017]

[0019] Conventional techniques may utilize complex and expensive processing steps to develop quantum well materials in an attempt to reduce dislocations, and may be limited to certain materials and processes for the structure. For example, metal oxide chemical vapor deposition may be used to form both the seed layer on the substrate and the subsequent material used for the quantum well. This process may be expensive and time consuming. However, conventional techniques do not allow for alternative techniques to be used to produce the seed layer, and dislocation densities may still be disadvantageously high. For example, physical vapor deposition may produce films characterized by reduced structure or film properties, which may prevent sufficient growth of quantum well materials. As a non-limiting example, gallium nitride may be used as a quantum well material in some devices, and conventional techniques have not allowed this material to be grown on a metal nitride seed layer produced by physical vapor deposition, and have been characterized by poorer crystal structure orientation. Due to the structure of the metal nitride produced, polar gallium nitride materials may form crystals characterized by mixed polarity, with regions of gallium polar growth and regions of nitrogen polar growth. This can prevent proper fusion of the structures to form the quantum wells and can cause the device to fail.

[0018]

[0020] The present technology overcomes the challenges associated with conventional techniques and overcomes or otherwise overcomes the conventional limitations of physical vapor deposition nitride materials. Using physical vapor deposition to form two metal nitride layers according to embodiments of the present technology can facilitate improved throughput of gallium-containing materials and improved growth of gallium. Thus, dislocations or defects can be controlled or minimized, thereby improving device quality and performance. While the remaining disclosure routinely identifies specific LED materials and processes utilizing the disclosed technology, it will be readily understood that these systems and methods are equally applicable to a variety of materials and processes that may be used in the manufacture of displays. Thus, the present technology should not be considered limited to use with LED processes alone. After describing an exemplary chamber system that may be used according to some embodiments of the present technology, a method for producing high quality structures is described.

[0019]

[0021] 1 shows a top view of a multi-chamber processing system 100 that may be specifically configured to implement aspects or operations according to some embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on individual substrates, such as any number of semiconductor substrates, to form semiconductor devices. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single wafer load locks 110 and 112 (which may also include dual load locks), processing chambers 114, 116, 118, 120, 122, and 124, preheat chambers 123 and 125, and robots 126 and 128. The single wafer load locks 110 and 112 may include a heating element 113 and may be attached to the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. The processing chambers 122 and 124 may be attached to the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be disposed between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between the robots 126 and 128. The platforms 102, 104 may be open to the transfer and buffer chambers, or the platforms may be selectively isolated or sealed from the chambers such that different operating pressures are maintained between the transfer chamber 106 and the buffer chamber 108. The transfer platforms 102 and 104 may each include one or more tools 105, such as for orientation or measurement operations.

[0020]

[0022] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to implement the operations described below. Thus, the computer system 130 may be a general-purpose computer configured with a controller or an array of controllers and / or software stored on a non-transitory computer-readable medium that, when executed, may perform the operations described in connection with the methods according to embodiments of the present technology. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in the manufacture of semiconductor structures. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a number of substrate processing steps, including dry etching processes, cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, pre-cleaning, degassing, and orientation, among any number of other substrate processes.

[0021]

[0023] FIG. 2 illustrates selected steps of a semiconductor processing method 200. Method 200 may include one or more steps prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed prior to the steps described. For example, in some embodiments, degassing or other preparatory steps may be performed on a substrate, such as a silicon or sapphire substrate, to prepare the substrate for deposition. The method may include a number of optional steps, which may or may not be particularly relevant to some embodiments of the method according to the present technology. For example, many of the steps are described to provide a broader scope for structural configurations, but may not be critical to the present technology or may be implemented by alternative methods described in more detail below. Method 200 describes steps shown generally in FIG. 3A-3D, examples of which are described in conjunction with the steps of method 200. It should be understood that the figures are only partial schematic views and that the substrate may include any number of portions having the aspects as shown in the figures, as well as alternative structural aspects that may still benefit from aspects of the present technology.

[0022]

[0024] The method 200 may include any steps for developing the structure into a particular manufacturing process. As shown in FIG. 3A, the semiconductor structure 300 may include a substrate 305 that may be used to facilitate the formation of a number of structures utilized in LED formation or other semiconductor processing. The substrate 305 may be any substrate upon which a structure may be formed, such as a silicon-containing material, an aluminum material including sapphire, or any other material that may be used in display or semiconductor manufacturing. The substrate 305 may have a variety of dimensions, such as 200 mm or 300 mm diameter wafers, and rectangular or square panels. The substrate 305 may be cleaned or processed in preparation for depositing one or more layers of material thereon to fabricate structures such as LEDs, although any number of other semiconductor structures may benefit from aspects of the present technology as well.

[0023]

[0025] In step 205, a first layer of a first metal nitride 310 may be formed over the substrate 305. In step 210, a second layer of a second metal nitride 315 may be formed over the first layer of the first metal nitride 310. The first layer of the first metal nitride 310 and the second layer of the second metal nitride 315 together may form a nitrogen-containing nucleation layer or seed layer. The first metal nitride and the second metal nitride may be or may include various metal nitrides. In some embodiments, each of the first layer and the second layer of the nucleation layer or seed layer may include aluminum nitride, hafnium nitride, niobium nitride, gallium nitride, or any other metal nitride from which a gallium-containing material or other material may be formed. In an exemplary embodiment, the first metal nitride may include aluminum nitride and the second metal nitride may include hafnium nitride. In such an embodiment, when the first metal nitride comprises hafnium nitride, the hafnium nitride may interact with the silicon substrate to form a silicide, which may inhibit the growth of subsequent materials, such as gallium nitride, and affect the final device performance. Therefore, the present technology can avoid interactions between certain metal nitrides, such as hafnium nitride, and the substrate by providing an intermediate metal nitride, such as aluminum nitride, between the substrate and the second metal nitride. This configuration allows for improved throughput and reduced wait times, while at the same time allowing for ideal material growth on the seed layer.

[0024]

[0026] The first layer of the first metal nitride 310 and the second layer of the second metal nitride 315 may be formed in any number of ways, such as by metal oxide chemical vapor deposition, but in some embodiments the seed layer may be formed by physical vapor deposition. It is believed that the layers may be formed using the same or different deposition or growth methods. The first layer of the first metal nitride 310 and the second layer of the second metal nitride 315 may be formed at a temperature of about 1000° C. or less, about 950° C. or less, about 900° C. or less, about 850° C. or less, about 800° C. or less, about 750° C. or less. In embodiments, the second layer of the second metal nitride 315 may be formed at a lower temperature than the first layer of the first metal nitride 310. However, it is believed that the two layers may be formed at the same temperature, or the second layer of the second metal nitride 315 may be formed at a higher temperature than the first layer of the first metal nitride 310.

[0025]

[0027] As mentioned above, the conventional techniques have not been able to utilize physical vapor deposition for seed layer formation, as the resulting material typically has the characteristic of losing structural orientation. Physical vapor deposition formation of the seed layer can result in undesirable kinetics for gallium nitride growth, which can cause a number of problems. The resulting interface between the seed layer and the subsequently formed gallium material can promote more defect transfer, resulting in mixed polarity gallium nitride, which can detrimentally reduce the efficiency and quality of the quantum well. Thus, the conventional techniques have been limited to utilizing more expensive techniques such as electron beam or metal oxide chemical vapor deposition. In addition, the present technique may allow for higher throughput and lower temperatures in forming the seed layer. The conventional techniques required the formation of a thicker buffer layer, which took a longer time to form. In the present technique, the metal nitride seed bilayer formed using physical vapor deposition at a lower temperature than the conventional techniques can eliminate the need for a thicker buffer layer to grow the gallium-containing material.

[0026]

[0028] The method 200 may include annealing the seed layer at step 220. The annealing may be performed at high temperatures, which may improve the crystal structure of the seed layer, including the exposed surfaces, and help reduce or limit the propagation of dislocations through subsequently formed layers, facilitating improved growth of the gallium material. The annealing may be performed at a temperature of about 800° C. or higher, and may be performed at a temperature of about 850° C. or higher, about 900° C. or higher, about 950° C. or higher, about 1000° C. or higher, about 1150° C. or higher, about 1200° C. or higher, about 1250° C. or higher, about 1300° C. or higher, about 1350° C. or higher, about 1400° C. or higher, about 1450° C. or higher, about 1500° C. or higher, about 1550° C. or higher, or about 1600° C. or higher. However, depending on the material of the substrate, lower temperatures may be used, which may facilitate processing of the seed layer, but may protect the substrate. For example, in some embodiments, the substrate may be silicon, which may be damaged or melted at high temperatures. Thus, in some embodiments, depending on the substrate, the temperature may be maintained at about 1500° C., or may be maintained at or below about 1400° C., or at or below about 1300° C., or even lower.

[0027]

[0029] The annealing may be performed for a time sufficient to improve the seed layer, and the annealing may be performed for about 30 minutes or more, about 60 minutes or more, about 90 minutes or more, about 120 minutes or more, about 150 minutes or more, about 180 minutes or more, or more. This time may be related to the annealing temperature, and higher temperature anneals may be performed for shorter times while producing similar effects. For example, anneals at about 1600° C. or more may be performed for about 30 minutes or less, while anneals performed at temperatures of about 1200° C. or less may be performed for about 90 minutes or more. The annealing may be performed in any process atmosphere, but in some embodiments, the annealing may be performed in an inert atmosphere, such as a nitrogen atmosphere, an argon atmosphere, a helium atmosphere, or other non-reactive, oxygen-depleted, or other inert material.

[0028]

[0030] After the annealing step, the surface of the second layer of the second metal nitride 315 opposite the first layer of the first metal nitride 310 may be characterized by a maximum roughness of about 1.0 μm or less. An increase in roughness may indicate that the quality of the seed layer has changed during annealing (e.g., a change in crystal structure from single crystal to polycrystalline), which may affect subsequent gallium growth on the seed layer. The present technique may maintain a maximum roughness of 1.0 μm or less due in part to the seed layer including a first metal nitride and a second metal nitride on the first metal nitride. The presence of two metal nitrides may reduce or eliminate the occurrence of any silicidation during the annealing step. In an embodiment, the surface of the second layer of the second metal nitride 315 opposite the first layer of the first metal nitride 310 may be characterized by a maximum roughness of about 950 nm or less, and may be characterized by a maximum roughness of about 900 nm or less, about 850 nm or less, about 800 nm or less, about 750 nm or less, about 700 nm or less, about 650 nm or less, about 600 nm or less, about 550 nm or less, about 500 nm or less, about 450 nm or less, about 400 nm or less, about 350 nm or less, about 300 nm or less, about 250 nm or less, 200 nm or less, about 150 nm or less, about 100 nm or less, about 50 nm or less, or less than that.

[0029]

[0031] In step 220, a dielectric material 320 may be formed on the second layer of the second metal nitride. The dielectric material 320 may be or include any dielectric material, such as silicon nitride, silicon oxide, aluminum nitride, aluminum oxide, or boron nitride. As shown in FIG. 3B, the dielectric material 320 may be formed and patterned over the second layer 315 of the second metal nitride 315 such that the dielectric material 320 is discontinuous or gaps or windows are created between the dielectric material 320 to expose portions of the underlying second layer of the second metal nitride 315. These gaps or windows may be formed by patterning the dielectric material 320 to expose one or more areas of the second layer of the second metal nitride 315. Although only two gaps or windows are shown here, it should be understood that the substrate may have hundreds, thousands, millions, or more gaps or windows, and they may be of any size.

[0030]

[0032] In step 225, a gallium-containing material 325 may be grown. For example, the gallium-containing material 325, which may include gallium nitride, may be grown by metal oxide chemical vapor deposition or by any other deposition or formation process. The gallium-containing material 325 may be selectively grown on the second layer of the second metal nitride 315 of the seed layer. The gallium-containing material 325 and the dielectric material 320 may overlap slightly, but these two portions may be distinct from each other. For example, the gallium-containing material 325 may be epitaxially grown extending from the exposed seed layer, which may allow selective formation in the open areas of the dielectric material 320 while limiting or preventing growth on the dielectric material 320.

[0031]

[0033] As shown in Figure 3C, the gallium-containing material 325 may be characterized by discrete regions of pyramidal structures as the material grows. Upon further growth, the gallium-containing material 325 fuses together to form a single pyramidal structure as shown in Figure 3D. However, the process can facilitate the growth of any structure that includes a continuous layer of gallium-containing material. The pyramidal structure shown in Figure 3D can be further processed to form an LED structure.

[0032]

[0034] After forming the gallium-containing material 325, the method 200 may further include forming an LED structure in optional step 230, such as in an embodiment where the gallium-nitride material may be used as a quantum well for the LED structure. The embodiment of forming the LED structure may include forming a p-type doped layer on the gallium-containing material 325. The p-type doped layer may be made of one or more of gallium nitride, aluminum-indium-gallium-nitride, nitride-gallium-nitride, and aluminum-gallium-nitride. In some embodiments, the p-type doped layer may include gallium-free indium and nitride materials (e.g., indium nitride), and aluminum-indium-nitride, among other gallium-free nitride materials. Forming the LED structure may further include forming contact pads on the layer of the structure. The contact pads may be formed from one or more conductive materials, such as copper, aluminum, tungsten, chromium, nickel, silver, gold, platinum, palladium, titanium, tin, and / or indium, among other dielectric materials. Any additional or alternative steps or processes for forming the LED structure may be included, as would be understood by one of ordinary skill in the art.

[0033]

[0035] The LED formation may further include forming a light conversion region in the LED structure. The light conversion region may absorb light emitted by the LED structure and emit longer wavelength light from the LED display. In some embodiments, the light conversion region may be a quantum dot layer that may be operable to convert shorter wavelength light from the LED structure to either red, green, or blue light. Additional quantum dot layers may be formed on other LED structures to convert shorter wavelength light emitted from the LED structure to another red, green, or blue light. In some embodiments, a combination of three quantum dot layers on three LED structures may form an LED pixel that includes subpixels operable to emit red, green, and blue light. In some embodiments, a sequential process may form a red quantum dot layer in one of the subpixels of each LED pixel, a green quantum dot layer in another one of the subpixels, and a blue quantum dot layer in yet another one of the subpixels. After formation of the blue quantum dots, each LED pixel in the array of LED pixels may include red, green, and blue sub-pixels.

[0034]

[0036] Embodiments of the present technology include processes and structures that reduce or limit the amount of threading dislocations that thread through the quantum wells. If such threading dislocations are present, the efficiency and performance of the resulting structure may be reduced. By forming a seed layer as described above, the present technology can increase throughput and improve the growth of gallium-containing materials, thereby limiting the propagation and propagation of dislocations through the material. Thus, embodiments of the present technology may provide fabrication methods and resulting structures that feature a reduced amount of threading dislocations to improve the efficiency of light emitting diodes or other semiconductor structures.

[0035]

[0037] In the above description, for purposes of explanation, numerous details are presented in order to facilitate an understanding of various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details or with additional details.

[0036]

[0038] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Moreover, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Thus, the above description should not be considered as limiting the scope of the technology.

[0037]

[0039] Where a range of values ​​is provided, unless the context clearly indicates otherwise, each intervening value between the upper and lower limits of that range is understood to be specifically disclosed to the smallest unit of the lower limit. Any narrower ranges between any stated or unstated intervening value in a stated range, as well as any other stated or intervening value in that stated range, are also encompassed. The upper and lower limits of such narrower ranges may be individually included or excluded from the range, and each range in which the narrower range includes any limit within the range or both limits within the range, or does not include any limit within the range, is further encompassed by this technology, subject to the specifically excluded limit in the stated range. Where a stated range includes one or both limits, ranges excluding either or both of those included limits are also included.

[0038]

[0040] As used in the specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a layer" includes a plurality of such layers, a reference to "the structure" includes a reference to one or more structures and equivalents thereof known to those skilled in the art, and so forth.

[0039]

[0041] Additionally, the terms "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. a silicon-containing substrate; a first layer of a first metal nitride overlying the silicon-containing substrate; a second layer of a second metal nitride overlying the first layer of the first metal nitride; and a gallium nitride structure overlying the second layer of the second metal nitride; 1. A semiconductor structure comprising:

2. 10. The semiconductor structure of claim 1 wherein said silicon-containing substrate is silicon.

3. 2. The semiconductor structure of claim 1 wherein said first metal nitride and said second metal nitride are selected from the group consisting of aluminum nitride, hafnium nitride, and niobium nitride.

4. 2. The semiconductor structure of claim 1 wherein said first metal nitride comprises aluminum nitride and said second metal nitride comprises hafnium nitride.

5. 10. The semiconductor structure of claim 1 further comprising a layer of dielectric material overlying at least a portion of said second layer of second metal nitride.

6. 6. The semiconductor structure of claim 5 wherein said dielectric material layer comprises silicon nitride.

7. 6. The semiconductor structure of claim 5 wherein said dielectric material layer is discontinuous.

8. 1. A method of semiconductor processing comprising the steps of: forming a first layer of a first metal nitride material on a substrate; forming a second layer of a second metal nitride material on the first layer of the first metal nitride material; annealing the first layer of the first metal nitride and the second layer of the second metal nitride; forming a gallium-containing material on the second layer of the second metal nitride; The method includes:

9. 9. The method of semiconductor processing of claim 8, wherein said first metal nitride is selected from the group consisting of aluminum nitride and niobium nitride, and said second metal nitride comprises hafnium nitride.

10. 9. The method of semiconductor processing of claim 8, wherein the first layer of the first metal nitride and the second layer of the second metal nitride are formed by physical vapor deposition.

11. 9. The method of semiconductor processing of claim 8, wherein said first layer of said first metal nitride and said second layer of said second metal nitride are formed at a temperature of about 1000° C. or less.

12. 9. The method of semiconductor processing of claim 8, wherein annealing the first layer of the first metal nitride and the second layer of the second metal nitride comprises annealing at a temperature of about 800° C. or greater.

13. 13. The method of semiconductor processing of claim 12, wherein a surface of the second layer of the second metal nitride opposite the first layer of the first metal nitride is characterized by a maximum roughness of about 1.0 μm or less.

14. 9. The method of semiconductor processing of claim 8, wherein said gallium-containing material is characterized by a pyramidal structure.

15. The method of semiconductor processing of claim 8 , wherein said gallium-containing material comprises gallium nitride.

16. 1. A method of semiconductor processing comprising the steps of: forming a first layer of a first metal nitride material on a silicon substrate; forming a second layer of a second metal nitride on the first layer of the first metal nitride; annealing the first layer of the first metal nitride and the second layer of the second metal nitride at a temperature of about 800° C. or greater; forming a discontinuous dielectric material on the second layer of the second metal nitride; forming a gallium-containing material on the second layer of the second metal nitride between the portions of the dielectric material; and The method includes:

17. 20. The method of semiconductor processing of claim 16, wherein said second layer of said second metal nitride is formed at a lower temperature than said first layer of said first metal nitride.

18. 20. The method of semiconductor processing of claim 16, wherein the first layer of the first metal nitride and the second layer of the second metal nitride are formed by physical vapor deposition.

19. 17. The method of semiconductor processing of claim 16, wherein said first metal nitride comprises aluminum nitride and said second metal nitride comprises hafnium nitride.

20. 20. The method of semiconductor processing of claim 16, wherein said gallium-containing material comprises gallium nitride.

Images