Interconnects for Modular Die Design

Abstract

Interconnects for modular die designs are disclosed. In one aspect, dies that are chiplets are designed and tested for compatibility. After approval of the chiplet design, multiple dies or chiplets can be bonded together in a multi-die package to form a package with a desired computing capability. After assembly, each chiplet is provided with a unique identifier, such as by setting fuses. Based on the unique identifier, each chiplet will know how its interface to other chiplets is configured so that signals can be routed appropriately. Using modular chiplets in this manner increases flexibility of design options while reducing test requirements and non-recurring costs.

Description

Claiming priority

[0001] Priority Application

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 655,823, entitled "INTERCONNECTIONS FOR MODULAR DIE DESIGNS," filed Mar. 22, 2022, the entire contents of which are incorporated by reference into this specification. [Technical field]

[0002] I. Field of Disclosure TECHNICAL FIELD

[0002] The technology of this disclosure relates generally to interconnects for modular integrated circuit (IC) die designs. [Background technology]

[0003] II. Background

[0003] The abundance of computing devices in modern society provides a myriad of functions for different demands. With the increase in functional possibilities, the demand for increased computing requirements (e.g., more processing power) has been met. In the past, such increased computing requirements could be met by increasing the number of transistors in an integrated circuit (IC) die or by increasing the size of the die. As the size of the transistor approaches some theoretical limits at the low nanometer scale, it becomes more difficult to add transistors in a given space. Similarly, the size of the die is reaching some practical limits due to current manufacturing processes. That is, as the size of the die increases, the yield for a given manufacturing run is likely to decrease, and there may be process variations across the die, which may lead to problems in managing internal latency and bias requirements. Therefore, there is still a need for better ways to design dies that allow flexibility in meeting various computational requirements. Summary of the Invention

[0004]

[0004] Aspects disclosed in the detailed description include interconnects for modular die design. In particular, a die, which is a chiplet, is designed and tested for compatibility. After approval of the chiplet design, multiple dies or chiplets can be bonded together in a multi-die package to form a package with the desired computing power. After assembly, each chiplet is provided with a unique identifier, such as by setting fuses. Based on the unique identifier, each chiplet knows how its interface to other chiplets is configured so that signals can be routed appropriately. Using modular chiplets in this manner increases flexibility of design options while reducing test requirements and non-recurring costs.

[0005] In this regard, in one aspect, a method of forming a package is disclosed. The method includes arranging a plurality of chiplets on a substrate. The method also includes setting a unique identifier for each chiplet. The method also includes forming a look-up table (LUT) for each chiplet to route communications between the chiplets based on the unique identifier. The method also includes configuring a port to route communications between the chiplets based on the unique identifier.

[0006] In another aspect, a method of communication between chiplets in a package is disclosed. The method includes generating a signal at a logic block in a first chiplet in the package. The method also includes comparing an address of the signal to a LUT to determine a physical address. The method also includes sending the signal to a port selected based on the LUT.

[0007]

[0007] In another aspect, a package is disclosed. The package includes a substrate. The package also includes a plurality of chiplets mounted on the substrate and interconnected with one another. Each chiplet of the plurality of chiplets includes a unique identifier. Each chiplet also includes a plurality of ports. Each chiplet also includes a LUT. Each chiplet also includes control circuitry configured to distinguish, based on the LUT, whether a signal generated within the chiplet is local or intended for a different chiplet.

[0008]

[0008] In another aspect, a package is disclosed. The package includes a substrate. The package also includes a plurality of chiplets mounted on the substrate and interconnected with one another. Each chiplet of the plurality of chiplets includes a unique identifier. Each chiplet also includes a plurality of ports. Each chiplet also includes control circuitry configured to route a signal generated within the chiplet to a local address or to a different chiplet within the plurality of chiplets based on the chiplet identifier in the signal.

[0009]

[0009] In another aspect, a package is disclosed. The package includes a substrate. The package also includes a plurality of chiplets mounted on the substrate and interconnected with one another. Each chiplet of the plurality of chiplets includes a unique identifier. Each chiplet also includes a plurality of ports. Each chiplet also includes control circuitry configured to route signals generated within the chiplet to a local address or to an outgoing port based on the chiplet identifier. [Brief description of the drawings]

[0010] [Figure 1]

[0010] FIG. 1 is a stylized diagram of an exemplary chiplet incorporated into a multi-chiplet package. [Diagram 2]

[0011] FIG. 2 is a block diagram of an example chiplet having ports for interconnecting with other chiplets, in accordance with an example aspect of the present disclosure. [Diagram 3]

[0012] FIG. 2 is a block diagram of an example package using four homogeneous chiplets with interconnects therebetween, according to an example embodiment of the present disclosure. [Figure 4]

[0013] 1 is a table showing how addressing can work for interconnected chiplets within a die. [Diagram 5]

[0014] 1 is a table showing how memory mapping may work for interconnected chiplets within a die. [Figure 6]

[0015] 4 is a flowchart illustrating an exemplary process for fabricating die from chiplets and making interconnects according to the present disclosure. [Figure 7]

[0016] FIG. 1 is a block diagram of an example processor-based system that may include a die formed from chiplets having interconnects in accordance with the present disclosure. [Figure 8]

[0017] FIG. 2 is a block diagram of an example transceiver circuit that may be present in a processor-based system including a die formed in accordance with the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0018] Several exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0012]

[0019] Aspects disclosed in the detailed description include interconnects for modular die designs. In particular, dies that are chiplets are designed and tested for compatibility. After approval of the chiplet design, multiple dies or chiplets can be bonded together in a multi-die package to form a package with the desired computing power. After assembly, each chiplet is provided with a unique identifier, such as by setting fuses. Based on the unique identifier, each chiplet knows how its interface to other chiplets is configured so that signals can be routed appropriately. Using modular chiplets in this manner increases flexibility of design options while reducing test requirements and non-recurring costs.

[0013]

[0020] In this regard, Figure 1 is a stylized diagram of a package 100 formed from a plurality of homogenous chiplets 102(1)-102(4). The chiplets 102(1)-102(4) may be mounted on a substrate 104, such as a stack (e.g., a printed circuit board (PCB)) having a metallization layer (not shown) therein. The metallization layer may include vias and conductors for interconnecting pins on the chiplets 102(1)-102(4). The package 100 may include a molded overcover (not shown), or the like.

[0014]

[0021] It is further noted that while four chiplets 102(1)-102(4) are shown in package 100, example embodiments of the present disclosure are not limited to only four. For example, a package may be formed using between two and ten (or more) chiplets 102. If the chiplets 102 are homogenous, it may make sense that a geometrically even number of chiplets 102 may be used, or more logically, a power of two (e.g., 2, 4, 8, etc.) chiplets 102.

[0015]

[0022] Although chiplets 102(1)-102(4) are all formed from generic chiplets 102, it should be understood that package 100 may be formed from heterogeneous chiplets (not shown). As yet another possibility, the multiple chiplets 102 may be homogeneous with one or more heterogeneous chiplets on the same package (e.g., three same chiplets and one different chiplet, two sets of two different chiplets, etc.). An advantage of using homogeneous chiplets 102(1)-102(4) is that only a single design and test cycle is required. Each additional possible chiplet design adds an additional design and test cycle, which may increase non-recurring expenses, increase average unit costs, and / or delay time to market.

[0016]

[0023] FIG. 2 provides further details about an example chiplet 200 that may correspond to the chiplet 102 of FIG. Chiplet 200 may include various logic blocks 202(1)-202(N) that couple to an internal interconnect 204. The internal interconnect 204 may be associated with and / or controlled by a control circuit 206 that may control the routing of communications based in part on the contents of a look-up table (LUT) 208. A number of input / output (I / O) ports 210(0)-210(M) may be coupled to the internal interconnect 204 to enable communications from the logic blocks 202(1)-202(N) to external elements, such as logic blocks within another chiplet 102. Fuses 212 may be externally accessible and may be used to help specify a unique identifier for the chiplet 200, as described in more detail below.

[0017]

[0024] When multiple chiplets 102 or 200 are assembled into a package, logic blocks in one chiplet may need to communicate with logic blocks in another chiplet. If there are multiple identical chiplets, they may need to be differentiated for inter-chiplet communication. Exemplary aspects of the present disclosure contemplate using fuses 212 to solve this communication challenge. In particular, fuses 212 may be used to set a unique identifier (e.g., a unique series of bits or bits) for chiplet 200, as better described with reference to FIGS. 3-5.

[0018]

[0025] In this regard, FIG. 3 illustrates a package 300 similar to package 100 of FIG. 1. Package 300 includes four chiplets 200(0)-200(3). Each fuse 212(0)-212(3) may be set to indicate a particular die identifier (Die_ID) during integration into package 300. As shown, chiplet 200(0) has a Die_ID of 00, chiplet 200(1) has a Die_ID of 01, chiplet 200(2) has a Die_ID of 10 (2 in binary), and chiplet 200(3) has a Die_ID of 11 (3 in binary). Each control circuit 206(0)-206(3) may read fuses 212(0)-212(3) and configure ports 302 based on the contents of each respective LUT 208(0)-208(3). Specifically, each chiplet 200(0)-200(3) has three ports 3020(0)-3020(2)-3023(0)-3023(2) (corresponding to ports 210(0)-210(M) of FIG. 2). Before fuses 212(0)-212(3) are set, ports 3020(0)-3020(2)-3023(0)-3023(2) appear the same to their respective internal interconnects 204(0)-204(3). By setting fuses 212(0)-212(3) to provide unique die_IDs, control circuits 206(0)-206(3) now treat ports 3020(0)-3020(2)-3023(0)-3023(2) differently based on the die_ID. Thus, for chiplet 200(0), control circuitry 206(0) knows that port 3020(0) is coupled to chiplet 200(1), port 3020(1) is coupled to chiplet 200(2), and port 3020(2) is coupled to chiplet 200(3). Thus, if a communication from logic blocks 2020(1)-2020(N) in chiplet 200(0) is destined for logic block 2022(3) in chiplet 200(2), control circuitry 206(0) will route the communication through internal interconnect 204(0) to port 3020(1).

[0019]

[0026] For completeness, for chiplet 200(1), control circuitry 206(1) knows that port 3021(0) is coupled to chiplet 200(0), port 3021(1) is coupled to chiplet 200(3), and port 3021(2) is coupled to chiplet 200(2). For chiplet 200(2), control circuitry 206(2) knows that port 3022(0) is coupled to chiplet 200(3), port 3022(1) is coupled to chiplet 200(0), and port 3022(2) is coupled to chiplet 200(1). For chiplet 200(3), control circuitry 206(3) knows that port 3023(0) is coupled to chiplet 200(2), port 3023(1) is coupled to chiplet 200(1), and port 3023(2) is coupled to chiplet 200(0). It should be understood that these connections may in most cases be a function of the positioning of chiplets 200(0)-200(3), which causes chiplets 200(0)-200(3) to be mirrored about different axes. For example, chiplet 200(3) is mirrored about the y-axis relative to chiplet 200(0), and chiplet 200(1) is mirrored about the x-axis relative to chiplet 200(0). This mirroring results in ports 3020(0)-3020(2)-3023(0)-3023(2) being aligned as shown. If chiplets 200(0)-200(3) were rotated or not homogeneous, ports 3020(0)-3020(2)-3023(0)-3023(2) may be aligned differently and have different inter-chiplet connections. Although not required, a typical goal is to minimize the distance of such inter-chiplet connections to reduce latency and potentially reduce the possibility of crosstalk or other forms of electromagnetic interference.

[0020]

[0027] It should be understood that if there are fewer or more chiplets than four, fewer or more bits may be required in fuses 212. Similarly, fewer or more ports 302 with corresponding entries in LUT 208 may be required.

[0021]

[0028] 4 and 5 illustrate further nuances in routing. For purposes of example, assume that each chiplet 200 has sixty-four gigabytes (64 GB) of memory in logic block 202. Referring to FIG. 4 and table 400 therein, control circuitry 206(0)-206(3) can prepend a chiplet identifier 402 to a physical address 404 used by logic block 202, where chiplet identifier 402 can include a number of bits equal to 1 plus the number of bits required to uniquely identify the chiplet. Thus, for four chiplets 200(0)-200(3), chiplet identifier 402 can be three bits (1 plus two bits to identify the four chiplets). If there are additional chiplets, chiplet identifier 402 can be more than three bits. The first bit can be a local or remote identifier. That is, for example, a first bit of 0 can indicate that the communication is local. Thus, as shown by row 404, a chiplet identifier of 000 references a memory element of the local chiplet. Other leading zero chiplet identifiers 402 may be reserved for future use. If the first bit is a 1, then this use may indicate that subsequent bits identify which chiplet (and corresponding port) the communication is addressed to. Note that a chiplet identifier may start with a 1 but still be relative to a local address (generally shown at 406).

[0022]

[0029] FIG. 5 expands on the concept of table 400 of FIG. 4 to show a default configuration memory map 500(0) that is stored for chiplet 200(0) and how modified configurations may exist after setting fuses 212(0)-212(3), as shown by memory maps 500(1)-500(3).

[0023]

[0030] Although fuses are specifically contemplated as a method of setting the configuration of the control circuitry, it should be understood that there may be other ways of achieving the same result. For example, software may reside in firmware that provides the logical-to-physical address mapping function. Still other hardware mechanisms (e.g., jumpers, shorts or opens, etc.) may be used as desired.

[0024]

[0031] FIG. 6 illustrates a flow chart of a process 600 associated with the design and manufacture of a package having multiple modular dies with interconnects according to the present disclosure. Specifically, the process 600 begins with the design of chiplets 200 (block 602). The chiplets 200 are tested and verified (block 604). Computing requirements are then identified and a package is designed using the chiplets 200 (block 606). The designer can then verify whether the package can function as intended with the existing chiplets (block 608). That is, the first chiplet 200 designed may be optimized for a neural processor or a graphics processor, but perhaps not both. If the package cannot be built using the existing chiplets 200, additional chiplets 200 are designed, tested and verified (block 610) and the designer determines whether the package can be built using the existing chiplets 200. In this manner, the package may be a combination of homogenous or heterogeneous chiplets 200.

[0025]

[0032] Once the designer is satisfied with the package design, the package is formed by assembling the chiplets 200 on the substrate 104 (block 612). As part of this step, each chiplet 200 may be assigned and set with a unique identifier (block 612A). Setting the unique identifier may be done by setting fuses 212, grounding certain connections, setting jumpers, via software, etc. The ports on the chiplets 200 are interconnected (block 612B). That is, the chiplets 200 may be soldered to contacts in the metallization layer of the substrate 104 such that the conductors and vias in the metallization layer interconnect the pins of the ports of the chiplets 200. Note that blocks 612A and 612B can be reversed in time to form the interconnects before setting the unique identifiers.

[0026]

[0033] Once the unique identifier is set, the control circuitry may configure the ports using the unique identifier (block 614). That is, the control circuitry 206 may use the LUT 208 to determine which ports are connected to which other chiplets. The control circuitry 206 may also form an address table (e.g., table 400 of FIG. 5 or a memory mapping) that includes local and global addresses based on the unique identifier (block 616).

[0027]

[0034] Interconnects for modular die designs and assembled packages according to aspects disclosed herein may be provided or integrated within any processor-based device, including, but not limited to, set-top boxes, entertainment units, navigation devices, communication devices, stationary data units, mobile data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0028]

[0035] As mentioned, the modular die design of the present disclosure may be incorporated into a processor-based system. In this regard, FIG. 7 illustrates an example of a processor-based system 700 that may employ the package 300 as illustrated in FIG. 3. In this example, the processor-based system 700 includes one or more central processing units (CPUs) 702, each including one or more processors 704. The processor(s) 704 may include the package 300. The CPU(s) 702 may have a cache memory 706 coupled to the processor(s) 704 for quick access to temporarily stored data. The CPU(s) 702 may be coupled to a system bus 708, which may interconnect master and slave devices included in the processor-based system 700. As is well known, the CPU(s) 702 communicate with these other devices by exchanging address, control, and data information via the system bus 708. For example, the CPU(s) 702 may communicate bus transaction requests to a memory controller 710, which is an example of a slave device. Although not shown in FIG.

[0029]

[0036] As shown in FIG. 7, these devices may include, by way of example, a memory system 712, one or more input devices 716, one or more output devices 718, one or more network interface devices 720, and one or more display controllers 722. The input device(s) 716 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. The output device(s) 718 may include any type of output device, including, but not limited to, audio, video, other visual indicators, and the like. The network interface device(s) 720 may be any device configured to enable the exchange of data to and from a network 724. The network 724 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) # may be configured to support any type of communication protocol desired. The memory system 712 may include one or more memory units 714(0-N).

[0030]

[0037] The CPU(s) 702 may also be configured to access display controller(s) 722 via the system bus 708 to control information sent to one or more displays 726. The display controller(s) 722 sends information to be displayed on the display(s) 726 via one or more video processors 728, which process the displayed information into a format suitable for the display(s) 726. The display(s) 726 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0031]

[0038] FIG. 8 illustrates an exemplary wireless communication device 800 including a radio frequency (RF) component formed from one or more ICs 802, any of which may be or include a package including multiple modular dies according to the present disclosure. The wireless communication device 800 may include or be provided within any of the devices described above, as examples. As shown in FIG. 8, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include memory for storing data and program code. The transceiver 804 includes a transmitter 808 and a receiver 810 supporting bidirectional communication. In general, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or a portion of the transceiver 804 may be implemented in one or more analog ICs, RF ICs (RF ICs, RFICs), mixed-signal ICs, and the like.

[0032]

[0039] The transmitter 808 or receiver 810 may be implemented using a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, e.g., from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and / or have different requirements. In the wireless communication device 800 of FIG. 8, the transmitter 808 and receiver 810 are implemented using a direct-conversion architecture.

[0033]

[0040] For the transmit path, the data processor 806 processes data to be transmitted and provides I and Q analog output signals to a transmitter 808. In the example wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1), 812(2) to convert digital signals generated by the data processor 806 into I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0034]

[0041] Within the transmitter 808, low pass filters 814(1), 814(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 816(1), 816(2) amplify the signals from the low pass filters 814(1), 814(2), respectively, and provide I and Q baseband signals. An upconverter 818 upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a transmit (TX) local oscillator (LO) signal generator 622 via mixers 820(1), 820(2) to provide an upconverted signal 824. A filter 826 filters the upconverted signal 824 to remove undesired signals caused by the frequency upconversion as well as noise in the receive frequency band. A power amplifier (PA) 828 amplifies the upconverted signal 824 from filter 826 to obtain a desired output power level and provides a transmit RF signal that is routed through a duplexer or switch 830 and transmitted via an antenna 832.

[0035]

[0042] In the receive path, an antenna 832 receives a signal transmitted by a base station and provides a receive RF signal, which is routed through a duplexer or switch 830 and provided to a low noise amplifier (LNA) 834. The duplexer or switch 830 is designed to operate using a specific RX to TX duplexer frequency separation such that the receive (RX) signal is separated from the TX signal. The receive RF signal is amplified by the LNA 834 and filtered by a filter 836 to obtain a desired RF input signal. Downconversion mixers 838(1), 838(2) mix the output of the filter 836 with I RX LO signals and Q RX LO signals (i.e., LO_I and LO_Q) from a RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 842(1), 842(2) and further filtered by low pass filters 844(1), 844(2) to obtain I and Q analog input signals, which are provided to data processor 806. In this embodiment, data processor 806 includes analog-to-digital converters (ADCs) 846(1), 846(2) for converting the analog input signals to digital signals that can be further processed by data processor 806.

[0036]

[0043] In the wireless communication device 800 of FIG. Y, the TX LO signal generator 822 generates the I TX LO signal and the Q TX LO signal used for frequency up-conversion, while the RX LO signal generator 840 generates the I RX LO signal and the Q RX LO signal used for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. The TX phase-locked loop (PLL) circuit 848 receives timing information from the data processor 806 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 822. Similarly, the RX PLL circuit 850 receives timing information from the data processor 806 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 840.

[0037]

[0044] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, as instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or as a combination of both. The master and slave devices described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. The memories disclosed herein may be of any type and size, and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as a departure from the scope of the present disclosure.

[0038]

[0045] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, individual gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0039]

[0046] Aspects disclosed herein may be embodied in hardware or in instructions stored in hardware, and may reside, for example, in Random Access Memory (RAM), Flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0040]

[0047] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations can be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step can actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps shown in the flow chart diagrams can be subject to numerous different modifications that will be readily apparent to those skilled in the art. Those skilled in the art will also appreciate that information and signals can be represented using any of a wide variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips, which may be referred to throughout the above description, can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0041]

[0048] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the embodiments and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0042]

[0049] The following numbered clauses describe example implementations. 1. A method of forming a package, comprising: disposing a plurality of chiplets on a substrate; establishing a unique identifier for each chiplet; forming a look-up table (LUT) for each chiplet to route communications between the chiplets based on the unique identifier; and configuring the ports to route communications between the chiplets based on the unique identifiers. 2. The method of claim 1, wherein the plurality of chiplets are homogenous. 3. The method of claim 1, wherein the plurality of chiplets are heterogeneous. 4. The method of any one of clauses 1 to 3, wherein setting the unique identifier includes setting at least one fuse. 5. The method of any one of clauses 1 to 3, wherein setting the unique identifier includes grounding the circuit. 6. The method of clauses 1 to 3, wherein setting the unique identifier includes using software to set the unique identifier. 7. The method of any one of the preceding clauses, wherein disposing the plurality of chiplets on the substrate includes forming interconnects between the plurality of chiplets using vias and conductors in a metallization layer in the substrate. 8. The method of any one of the preceding clauses, further comprising assigning a unique identifier to each chiplet prior to configuration. 9. The method of any one of the preceding clauses, further comprising loading global address information versus local address information into a look-up table (LUT) based on the unique identifier. 10. The method of any one of the preceding clauses, wherein arranging the plurality of chiplets on the substrate includes coupling a first port of a first chiplet to a first port of a second chiplet. 11. A method of communication between chiplets in a package, comprising: generating a signal in a logic block in a first chiplet in the package; comparing the address of the signal to a look-up table (LUT) to determine a physical address; and transmitting a signal to a port selected based on the LUT. 12. A package comprising: A substrate; a plurality of chiplets mounted on a substrate and interconnected with one another; Each chiplet of the plurality of chiplets A unique identifier; and Multiple ports and Look-up table (LUT) and and control circuitry configured to distinguish whether a signal generated within a chiplet is local or intended for a different chiplet based on the LUT. 13. The package of claim 12, wherein the plurality of chiplets are of the same type. 14. The package of claim 12, wherein the plurality of chiplets are heterogeneous. 15. The package of any one of clauses 12 to 14, wherein the substrate comprises a metallization layer including conductors and vias, and the multiple chiplets are interconnected using the conductors and vias. 16. A package comprising: A substrate; a plurality of chiplets mounted on a substrate and interconnected with one another; Each chiplet of the plurality of chiplets A unique identifier; and Multiple ports and and control circuitry configured to route signals generated in the chiplets to local addresses or to different chiplets within the plurality of chiplets based on a chiplet identifier in the signal. 17. The package of claim 16, wherein the chiplet identifier is prepended to the address in the signal. 18. The package of clause 16 or 17, wherein the chiplet identifier includes a number of bits equal to 1 plus the number of bits required to uniquely identify multiple chiplets. 19. A package comprising: A substrate; a plurality of chiplets mounted on a substrate and interconnected with one another; Each chiplet of the plurality of chiplets A unique identifier; and Multiple ports and and control circuitry configured to route signals generated within the chiplets to local addresses or to outgoing ports based on the chiplet identifier.

Claims

1. 1. A method of forming a package, comprising: disposing a plurality of chiplets on a substrate; establishing a unique identifier for each chiplet; forming a look-up table (LUT) for each chiplet to route communications between chiplets based on the unique identifier; and configuring a port to route communications between chiplets based on the unique identifier.

2. The method of claim 1 , wherein the plurality of chiplets are homogenous.

3. The method of claim 1 , wherein the plurality of chiplets are heterogeneous.

4. The method of claim 1 , wherein setting the unique identifier comprises setting at least one fuse.

5. The method of claim 1 , wherein setting the unique identifier comprises grounding a circuit.

6. The method of claim 1 , wherein setting the unique identifier comprises setting the unique identifier using software.

7. 10. The method of claim 1, wherein arranging the plurality of chiplets on the substrate comprises forming interconnects between the plurality of chiplets using vias and conductors in a metallization layer in the substrate.

8. The method of claim 1 , further comprising: assigning the unique identifier to each chiplet prior to configuration.

9. 2. The method of claim 1, further comprising loading global address information versus local address information into the look-up table (LUT) based on the unique identifier.

10. The method of claim 1 , wherein arranging the plurality of chiplets on the substrate comprises coupling a first port of a first chiplet to a first port of a second chiplet.

11. 1. A method of communication between chiplets in a package, comprising: generating a signal in a logic block in a first chiplet in the package; comparing the address of the signal with a look-up table (LUT) to determine a physical address; and transmitting the signal to a port selected based on the LUT.

12. A package comprising: A substrate; a plurality of chiplets mounted on the substrate and interconnected with each other; Each chiplet of the plurality of chiplets: A unique identifier; and Multiple ports and A look-up table (LUT); and control circuitry configured to distinguish whether a signal generated within the chiplet is local or intended for a different chiplet based on the LUT.

13. The package of claim 12 , wherein the plurality of chiplets are homogenous.

14. The package of claim 12 , wherein the plurality of chiplets are heterogeneous.

15. The package of claim 12 , wherein the substrate comprises a metallization layer including conductors and vias, and the plurality of chiplets are interconnected using the conductors and the vias.

16. A package comprising: A substrate; a plurality of chiplets mounted on the substrate and interconnected with each other; Each chiplet of the plurality of chiplets: A unique identifier; and Multiple ports and and control circuitry configured to route signals generated within the chiplets to local addresses or to different chiplets within the plurality of chiplets based on a chiplet identifier in the signal.

17. The package of claim 16 , wherein the chiplet identifier is prepended to an address in the signal.

18. 17. The package of claim 16, wherein the chiplet identifier comprises a number of bits equal to one plus a number of bits necessary to uniquely identify the plurality of chiplets.

19. A package comprising: A substrate; a plurality of chiplets mounted on the substrate and interconnected with each other; Each chiplet of the plurality of chiplets: A unique identifier; and Multiple ports and and control circuitry configured to route signals generated within the chiplets to a local address or to an outgoing port based on a chiplet identifier.

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