Semiconductor device operation mode management

Abstract

The present invention relates to a semiconductor device (10) having a plurality of operating modes, a core (12) adapted to execute a software application (14) adapted to select a setting of one or more of peripheral devices (60) and to issue a sleep request, and a power management unit (PMU) (130) having a first input port (132) for receiving a setting of one or more of the peripheral devices, a second input port (134) for receiving a sleep request from the core (12) executing the software application (14), and a control logic module (136) configured to select an operating mode from among the plurality of operating modes depending on the setting of the one or more of the peripheral devices upon receiving the sleep request. The present invention also relates to a method of operating the device.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device having multiple operating modes, the device comprising a power management unit for selecting one of said multiple operating modes depending on the needs of an application, and also to a method for operating said semiconductor device. [Background technology]

[0002] The document US8975916 discloses a core architecture including a digital subsystem, a clock subsystem, and a power management subsystem. Power modes may be implemented and managed by the power management subsystem. Power modes are entered and exited based on the power and processing requirements of the application. Power modes may be controlled by the CPU based on program execution or by an external controller writing to registers in the power subsystem.

[0003] For example, US 2009 / 089599 and US 2019 / 0079573 disclose a microcontroller including a processing unit having a normal power mode and a low power mode of operation, the processing unit further comprising digital circuitry coupled to the processing unit, and a sleep mode initiated by software in which the microcontroller and all components of the microcontroller are disabled.

[0004] Modern semiconductor devices, such as microcontrollers (MCUs), are typically divided into multiple domains containing analog and / or digital circuits that provide different functions. Each domain can typically operate with a clock of different frequencies, can be clock-gated (meaning that the clock signal does not reach the domain), and / or can be power-gated (meaning that power is not provided to the domain). To save power, modern digital semiconductor devices typically have different operation modes, which are implemented using clock scaling, a combination of clock and power scaling and power gating for the different domains. Typically, among the operation modes are an active mode (all domains are active and the highest clock frequency is available), a sleep mode (some domains are clock-gated), and a deep sleep mode (some domains are clock-gated and power-gated and / or some other domains operate at a lower clock frequency). Thus, the available functions and performance of the semiconductor device vary depending on the modes. The user can always select the lowest consumption mode that meets the needs of the application through software. These operating modes are loosely defined by the core IP provider (e.g. ARM) and usually specifically defined by the MCU manufacturer. Usually, the manufacturer defines four or more operating modes to provide more fine-grained power control. As the number of operating modes increases and the MCU becomes more complex, it becomes more difficult for users to write software that sets the MCU to the right mode at the right time. For example, the user usually has to control clock and voltage generators through multiple registers and set them to a state that allows the target operating mode. This is often not easy to understand and apply. This usually leads to suboptimal power consumption because the user cannot write the software properly and the operating modes are not used properly. Summary of the Invention

[0005] It is an object of the present invention to provide a semiconductor device in which the selection and setting of operating modes to minimize power consumption is simple and efficient.

[0006] The invention is defined by the independent claims. The dependent claims define advantageous embodiments.

[0007] According to a first aspect of the present invention, there is provided a semiconductor device having a plurality of operation modes, the semiconductor device comprising: - a plurality of components necessary for operation of the semiconductor device (typically, but not limited to, service components such as voltage regulators or clock generators), each of which has an operational state selectable from a plurality of operational states; - one or more peripheral devices, each configured to provide a function to the semiconductor device (such as, but not limited to, a communication function, a timing function, a sensing function, or a security function) in response to a selected one or more settings; - a core adapted to execute a software application, the software application adapted to select settings for one or more of the peripheral devices and to issue a sleep request. The semiconductor device further includes a power management unit (PMU) having a first input port for receiving a configuration of one or more of the peripheral devices, a second input port for receiving a sleep request from the core executing the software application, and a control logic module configured to select an operating mode from among the plurality of operating modes upon receiving the sleep request depending on a configuration of one or more of the peripheral devices.

[0008] Preferably, in the semiconductor device, one or more of the peripherals include a peripheral control and status register (PCSR) including one or more bits, the one or more bits including bits for setting the peripheral to an operational on or off state and bits for providing status information regarding the peripheral, the semiconductor device includes a first bus for exchanging data between the one or more of the peripherals and the core, and the software application is adapted to select a setting for one or more of the peripherals by sending data via the first bus.

[0009] In a first embodiment of the present invention, in a semiconductor device, one or more of the peripheral devices include a clock input terminal for receiving one or more clocks, and one of the components of the semiconductor device is a clock generator module including one or more clock generators configured to generate and provide clocks to the clock input terminals of the one or more peripheral devices and configured to receive a first command to turn each of the clock generators on or off and / or determine a frequency to be generated, and a PMU is configured to, upon receiving the sleep request, send the first command in response to the selected operating mode to set the semiconductor device to the selected operating mode.

[0010] In a second embodiment of the present invention, a semiconductor device includes one or more power domains, each of which includes one or more of the peripheral devices, one or more of the one or more power domains further including a voltage input terminal for receiving a voltage for powering the power domain, one of the components of the semiconductor device is a voltage generator module including one or more voltage generators and voltage output terminals, each of the one or more voltage generators and voltage output terminals configured to generate and supply a voltage to at least one of the voltage input terminals for powering the one or more power domains, and configured to receive a second command to turn each of the voltage generators on or off and / or determine a voltage to be generated, and a PMU configured to send the second command in response to the selected operating mode upon receiving the sleep request to set the semiconductor device to the selected operating mode.

[0011] In the embodiment of the invention, one wire per clock generator may be provided between the PMU and the clock generators for sending the first command.

[0012] In the embodiment of the present invention, a second bus may be provided for exchanging data between the PMU and the clock generator module, the PMU and the clock generator module being configured to send and receive, respectively, the first commands via the second bus.

[0013] In the second embodiment of the present invention, one wire per voltage generator may be provided between the PMU and the clock generator for sending the second command.

[0014] In the second embodiment of the present invention, a second bus may be provided for exchanging data between the PMU and the voltage generator module, the PMU and the voltage generator module being configured to send and receive, respectively, the second commands via the second bus.

[0015] The first bus and the second bus may advantageously be interconnected to form a single bus.

[0016] In the second embodiment of the present invention, a power gating switch is provided between a voltage output terminal and a voltage input terminal, the power gating switch supplying power to a power domain when the switch is on and gating a voltage supplied to the power domain when the switch is off, the power gating switch (140) being controlled by a third command, and the PMU (130) is configured to, upon receiving the sleep request, send the third command in response to the selected operating mode to set the semiconductor device (10) to the selected operating mode.

[0017] In the second embodiment of the present invention, one or more of the power domains may include a frequency divider module configured to receive a clock from a clock generator module and divide the clock into multiple clocks having different frequencies.

[0018] According to a second aspect of the present invention there is provided a method of operating a semiconductor device according to the present invention comprising the steps of: 1. the software application configuring settings of one or more of the peripheral devices according to the needs of the application; 2. determining, by the software application, to transition to a different mode of operation; 3. A PMU collecting a configuration of at least one of said peripheral devices; 4. The control logic of the PMU selects an operating mode of the semiconductor device in response to a setting of one or more of the peripherals.

[0019] In this method, the PMU preferably sends the first command and / or the second command and / or the third command depending on the selected operating mode.

[0020] FIELD OF THEINVENTION The present invention relates to a semiconductor device comprising one or more power domains, a clock generator module, optionally a voltage generator module and a power management unit. The present invention also relates to a method for managing the operating modes of a semiconductor device. [Brief description of the drawings]

[0021] These and further aspects of the invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which:

[0022] [Figure 1] FIG. 1 illustrates a schematic representation of an embodiment of a semiconductor device according to the invention. [Diagram 2] FIG. 2 illustrates a schematic representation of a portion of another embodiment of a semiconductor device according to the invention. [Diagram 3] FIG. 3 illustrates a schematic representation of a portion of one embodiment of a semiconductor device according to the present invention including a clock generator module. [Figure 4] FIG. 4 illustrates a schematic representation of a portion of an embodiment of a semiconductor device according to the invention including a voltage generator module. [Diagram 5] FIG. 5 shows a schematic representation of a detailed view of a peripheral device in the device according to the invention. [Figure 6] FIG. 6 shows a schematic representation of a detailed view of power domains in a device according to the invention. [Figure 7] FIG. 7 illustrates a flow diagram of a method of operating a semiconductor device according to the present invention.

[0023] The same reference numbers in different drawings indicate the same components or features.

[0024] In the context of the present invention, a control and status register (CSR) of a peripheral device is a register with a number of bits exhibiting logical values ​​0 or 1. The bits may be set to 0 or 1 to control the behavior of the peripheral device with which it is equipped and may also be used and accessed by elements external to the peripheral device to evaluate the status of the peripheral device.

[0025] The figures in the drawings are not drawn to scale or to proportion. Generally, identical components are designated by identical reference numerals in the figures. For clarity, not every component is shown in every figure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] 1 shows a schematic representation of an exemplary embodiment of a semiconductor device 10 according to the invention. As is well known, the power consumption by an electronic circuit increases with the frequency of the clock used in the circuit and with the square of the voltage applied to the circuit. It is therefore known to vary (reduce) the frequency of the clock and the voltage of the power applied to the circuit. The semiconductor device 10 according to the invention is further divided into different parts. These parts include: a core 12, which may be a processing unit having an architecture such as ARMv6, or ARMv7, or ARMv8, or RISC-V, on which a software application 14 may be running. - components 18, which are required and operative during operation of the semiconductor device. These components 18 may include power modules for powering other parts of the device, or clock modules for providing clocks to other parts of the device. - Peripherals 60. These may be active or inactive depending on the needs of the application and may be configured differently in terms of clock frequency and / or voltage to save power. The peripherals may implement functions of semiconductor devices such as Analog to Digital Converter (ADC) functions, Universal Asynchronous Transmitter / Receiver (UART) functions, Universal Serial Bus (USB) functions, True Random Number Generator (TRNG) functions, or other functions commonly known in the field of MCUs and semiconductor devices. - A Power Management Unit (PMU) 130, which is responsible for managing the operating modes.

[0027] In applications where power consumption is critical, the semiconductor device may operate according to different operating modes such as active, run, sleep, deep sleep, standby, stop, idle, off, shutdown, etc. The operating modes may include, for example: - Active mode: In this mode, all parts of the device are powered with the highest voltage and clocked with the fastest clock. - Several operating modes dedicated to the work that the application is currently doing, such as acquiring at high speed when peripherals are enabled and must run at a high speed clock, computing when some peripherals may be disabled, acquiring at low speed when some peripherals may be enabled at low speed, communicating when some communication peripherals are enabled, etc. - Several operating modes dedicated to the lowest possible power consumption, in which most of the peripherals are power gated and only a few are left enabled using a low frequency clock.

[0028] The software application 14 may interact with the peripherals to set them to a particular selected setting by sending peripheral setting signals 62. The peripheral settings may include an operational on or off state, a particular clock frequency to be used, or selecting no clock, or selecting a particular voltage, or selecting no voltage at all. The software application may decide to issue a sleep request 170. In some architectures, the sleep request 170 is part of an instruction set. The sleep request 170 may be sent by the core 12 to the PMU 130. Upon receiving the sleep request 170, the PMU 130 obtains the value of the peripheral's setting. The PMU 130 is provided with an input port 132 to receive the value of the peripheral's 60 setting. The PMU 130 includes a control logic module 136 for receiving the value of the setting and, upon receiving the sleep request, determines a target operating mode to be selected for the semiconductor device 10 depending on the peripheral's 60 setting.

[0029] 2 illustrates a schematic representation of a portion of an exemplary embodiment of a semiconductor device 10 according to the present invention. In this embodiment, a peripheral 60 may include peripheral control and status registers (PCSRs) 30, each of which has a number of bits that allow control of the peripheral, such as enabling or disabling the peripheral, or specifying the clock that should be used to clock the peripheral, or indicating the status of the peripheral.

[0030] The device 10 may include a first bus 16. The PCSR may then be accessed in write mode via the first bus 16, for example, by the core executing an application program and determining to enable or disable one or more of the peripherals, and to select a fast or slow clock based on the needs of the application. The peripheral configuration signal 62 may then be sent via the first bus 16. The PMU 130 may gain access to the values ​​stored in the PCSR via a set of wires 150 that connect the PCSR directly to the input port 132 of the PMU. Those wires 150 may route the contents of the bits of the PCSR or the logical functions of the PCSR to the PMU 130. For clarity, those wires are not shown in FIG. 1 but are represented as arrows 150.

[0031] FIG. 3 is a schematic representation of a portion of an exemplary embodiment of a semiconductor device 10 according to the present invention. In this embodiment, the components 18 include a clock generator module 100 including one or more clock generators 105 configured to provide one or more clocks to a peripheral device 60, with wires connecting the clock output terminal 110 of the clock generator module 100 to the clock input terminal 50 of the peripheral device. Although a single wire is depicted in FIG. 3, multiple wires may be provided depending on the number of clocks generated by the clock generator module 100, and the symbol " / / " represents that multiple wires may be present, with the same number of contacts at the clock input terminal. When the PMU 130 receives the sleep request and obtains the values ​​of the peripheral device settings, the PMU selects an operating mode of the semiconductor device and sends a first command 107 to the clock generator module 100 to set the clock generator 105, for example, to an on or off state or to a specified frequency depending on the selected operating mode. The PMU 130 may be configured to send the first command 107 directly via one or more wires. A wire may be provided to switch the clock generator 105 "off" or "on". The semiconductor device may also include a second bus 17 for exchanging data between the PMU and the components 18. The second bus 17 may be a dedicated bus or the first bus 16. The PMU 130 may then be configured to send the first command 107 directly via the second bus 17. The first command may include a set of operations to safely transition the semiconductor device 10 from one operating mode to another, such as providing a period for an oscillator to settle, providing a period for a voltage regulator to settle, providing a period for data to be saved, or generally allowing a period for the circuit to adapt to the new state.

[0032] 4 illustrates a schematic representation of a portion of an exemplary embodiment of a semiconductor device 10 according to the present invention. In this embodiment, components 18 include a voltage generator module 70 with one or more voltage generators 75. In this embodiment, the semiconductor device includes one or more power domains 20, 20'. A power domain may group one or more peripheral devices 60. Wires are provided to connect a voltage output terminal 80 of the VGM 70 to a voltage input terminal 40 of the power domain 20, 20' to receive a voltage for powering the peripheral devices 60 included in the power domain.

[0033] Each power domain may be provided with a clock input terminal 50 for receiving one or more clocks for clocking the peripheral devices contained within the power domain, as described above.

[0034] For simplicity, the example of Figure 4 depicts two power domains with three peripherals each, however, a device may include any number of power domains, each with any number of peripherals 60 appropriate to the needs of the application.

[0035] Similar to the embodiment of FIG. 3, when the PMU 130 receives the sleep request and obtains the values ​​of the peripheral settings, the PMU selects an operation mode of the semiconductor device and sends a second command 77 to the voltage generator module 70 to set the voltage generator 75, for example, to an “on” or “off” state or to a specified voltage depending on the selected operation mode. The PMU 130 may be configured to send the second command 77 directly via one or more wires. The semiconductor device may include a second bus 17 for exchanging data between the PMU and the components 18. The second bus 17 may be a dedicated bus or the first bus 16. The PMU 130 may then be configured to send the second command 77 directly via the second bus 17.

[0036] As discussed above in connection with the embodiment of FIG. 3, the second command 77 may also include a sequence of actions.

[0037] 4 may additionally include a power gating switch 140 for at least one of the power domains 20, 20′ for enabling power to the power domain in an “on” state and isolating the power domain from the VGM 70 in an “off” state. Upon receiving the sleep request, the PMU 130 may determine a state to which the power gating switch 140 should be set depending on the peripheral device settings and control the power gating switch by sending a third command to configure the semiconductor device into an operation mode depending on the peripheral device settings.

[0038] FIG. 5 shows a schematic representation of a detailed view of a peripheral 60 in a device according to the invention. In this example, the multiple clocks include two clocks, a slow clock and a fast clock. The peripheral 60 includes a PCSR 30 with three bits. Bit 0 is solely for controlling the state of the peripheral, and is disabled when 0 and enabled when 1. Bits 1 and 2 are used to select the clock that will be used by the peripheral. When 00, the clock is gated, i.e., no clock is input to the peripheral. When 01, the slow clock is selected, and when 10, the fast clock is selected. The combination 11 is not used. For example, an application program may determine that a particular peripheral is not needed in the future and set its enable / disable bit to zero. The application program may determine that another peripheral is needed, but its function is not speed critical and may run at a slower speed. Thus, to save power, the application program may set the enable bit and write '01 to bits 1 and 2, selecting the slow clock.

[0039] 6 is a schematic representation of power domain 20 in one embodiment of the invention, including a frequency divider module 65. The frequency divider module may receive a clock from the clock generator module and divide the clock into clocks of different frequencies, for example, clocks divided by 2, 4, 8, or other numbers. Peripheral device 60 may then select one of these divided clocks to clock the peripheral device, depending on PCSR 30.

[0040] Depending on the number of power domains and the nature and number of peripherals in each power domain, several operating modes may be defined. This number of operating modes may be very large, i.e., exceeding a simple active / standby / sleep combination. A control logic module 136 included in the PMU is configured to convert the peripheral settings made by the application program into a selected one of the operating modes and to communicate the required voltage and clock settings to the VGM 70 and / or the clock generator module 100 and / or other necessary components 18. As an example, if all peripherals of a power domain are disabled, the PMU may clock gate all peripherals by shutting off one or more of the clock generators 105, or if power gating is available, the PMU may set the power gating switch 140 to "off" (if this corresponds to the targeted operating mode). EXAMPLES

[0041] We consider a microcontroller with multiple peripherals, namely, communication peripherals like SPI, I2C, UART, timing peripherals like timer, RTC, watchdog, analog sensing peripherals like ADC, comparator, security peripherals like AES, random number generator. The microcontroller is divided into three power domains. Power domain 1 contains the core of the microcontroller. Power domain 2 contains ADC, comparator, SPI, I2C, timer, watchdog, AES, and random number generator. Power domain 3 contains the RTC and UART. The microcontroller has two clock generators that generate high and low frequencies. The microcontroller has two voltage generators that generate high and low voltages. The application program can configure each peripheral to operate at high or low frequency. The core is powered by the low voltage. The other peripherals are powered by the high voltage. The microcontroller has four operating modes: In mode 1, all domains are powered and clocked, all clock generators are active, and all voltage generators are active. In mode 2, domain 1 is powered but clock gated, domains 2 and 3 are powered and clocked, all clock generators are active, and all voltage generators are active. In mode 3, domains 1 and 2 are power gated, domain 3 is powered and clocked, all clock generators are active, and only the high voltage generator is active. In mode 4, domains 1 and 2 are power gated, domain 3 is powered and clocked, only the low frequency clock generator is active, and only the high voltage generator is active.

[0042] On power up, the microcontroller is in mode 1. Then, when the user requests to go to sleep via software, the PMU checks which functionality is required. If SPI is active (and therefore required), the PMU selects mode 2 (since SPI is not available in modes 3 and 4). If only UART is active and high frequency is selected, the PMU selects mode 3 (since a high frequency clock generator is still required). If only UART is active and low frequency is selected, the PMU selects mode 4.

[0043] FIG. 7 illustrates a flow diagram of a method of operating a semiconductor device according to the present invention.

[0044] The semiconductor device of the present invention may operate as follows. - In step 210, the software application 14 configures the peripherals according to the needs of the application, i.e. some peripherals that are used or may be used may be enabled, and those that are not used are disabled. The clock may also be selected according to the needs of the application, i.e. if a short response time or a high throughput is required, a faster clock is selected. This may be done by setting bits in the PCSR. - In step 220, once the application program determines that the conditions are met in the context of the application to go into a "sleep" mode of operation (thereby reducing power requirements), the application program may issue a sleep request and may send or assert that request over a dedicated line to the PMU. - In step 230, the PMU then checks the settings of the peripherals by examining the values ​​contained in the different PCSRs. This is done by accessing the wires that connect each bit of the PCSR to the PMU, or via bus access. - In step 240, the control logic module 136 contained in the PMU then determines the operating mode depending on the settings of the peripherals. - In step 250, the PMU 130 may send the first and second commands and optionally a third command to the clock generator module, the voltage generator module, and the clock gating switch, respectively, thereby transitioning the semiconductor device into a desired operating mode. - When the semiconductor device receives a wake-up condition, it returns to normal mode. This sequence of steps may be repeated depending on the operations performed by the software application.

[0045] By using the semiconductor device and method of the present invention, a simple and efficient method of selecting and configuring the device's operating mode is provided. The application program simply enables or disables peripherals and selects the clock speed and / or voltage to be used, depending on the application's needs. The task of determining how to configure the device is performed by the PMU, and the burden of determining the optimal setting for the operating mode is not placed on the application program.

Claims

1. A semiconductor device (10) having multiple operating modes, - A plurality of components (18) necessary for the operation of the semiconductor device, each of which has an operating state that can be selected from a plurality of operating states, - One or more peripheral devices (60), each configured to provide a certain function to the semiconductor device (10) according to a setting selected from one or more settings, - A core (12) adapted to run a software application (14), wherein the software application (14) is adapted to select the settings of one or more of the peripheral devices (60) and to issue sleep requests, and In a semiconductor device (10) including, The semiconductor device (10) further comprises: A semiconductor device (10) comprising a power management unit (PMU) (130) having a first input port (132) for receiving the settings of one or more of the peripheral devices, a second input port (134) for receiving sleep requests from the core (12) running the software application (14), and a control logic module (136) configured to select an operating mode from among a plurality of operating modes in accordance with the settings of one or more of the peripheral devices upon receiving the sleep request.

2. A semiconductor device (10) according to claim 1, wherein one or more of the peripheral devices (60) include a peripheral device control and status register (PCSR) (30) including one or more bits, the one or more bits including bits for setting the peripheral device (60) to an operational on or off state, and bits for providing status information relating to the peripheral device, the semiconductor device includes a first bus (16) for exchanging data between the one or more of the peripheral devices (60) and the core (12), and the software application (14) is adapted to select the setting of one or more of the peripheral devices by sending data via the first bus (16).

3. In the semiconductor device (10) described in claim 2, - One or more of the peripheral devices (60) have a clock input terminal (50) for receiving one or more clocks. Includes, - One of the components (18) of the semiconductor device (10) is a clock generator module (100) including one or more clock generators (105) configured to generate a clock and provide it to the clock input terminal (50) of the one or more peripheral devices (60), and configured to receive a first command to turn each of the clock generators (105) on or off and / or to determine the frequency to be generated, - The PMU (130) is configured to send the first command according to the selected operating mode in order to set the semiconductor device (10) to the selected operating mode when it receives the sleep request. A semiconductor device (10) characterized by the following features.

4. In the semiconductor device (10) described in claim 2, The semiconductor device (10) includes one or more power domains (20, 20'), each of which includes one or more of the peripheral devices (60). - One or more of the one or more power domains (20, 20') further include a voltage input terminal (40) for receiving a voltage to supply power to the power domains (20, 20'), - One of the components (18) of the semiconductor device (10) is a voltage generator module (70) comprising one or more voltage generators (75) and voltage output terminals (80), each of the one or more voltage generators (75) and voltage output terminals (80) configured to generate a voltage and supply it to at least one of the voltage input terminals (40) for powering the one or more power domains, and configured to receive a second command to turn each of the voltage generators on or off and / or determine the voltage to be generated. - The PMU (130) is configured to send the second command according to the selected operating mode in order to set the semiconductor device (10) to the selected operating mode when it receives the sleep request. A semiconductor device (10) characterized by the following features.

5. The semiconductor device (10) according to claim 3, characterized in that one wire is provided between the PMU (130) and the clock generator for each clock generator (105) in order to send the first command.

6. The semiconductor device (10) according to claim 3, wherein a second bus (17) is provided for exchanging data between the PMU (130) and the clock generator module (100), and the PMU (130) and the clock generator module (100) are configured to send and receive the first command via the second bus (17), respectively.

7. The semiconductor device (10) according to claim 4, characterized in that one wire is provided between the PMU (130) and the clock generator for each voltage generator (75) in order to send the second command.

8. The semiconductor device (10) according to claim 4, wherein a second bus (17) is provided for exchanging data between the PMU (130) and the voltage generator module (70), and the PMU (130) and the voltage generator module (70) are configured to send and receive the second command, respectively, via the second bus (17).

9. A semiconductor device (10) according to claim 6 or 8, characterized in that the first bus (16) and the second bus (17) are interconnected to form a single bus.

10. A semiconductor device (10) according to any one of claims 4, 7, or 8, wherein a power gating switch (140) is provided between a voltage output terminal (80) and a voltage input terminal (40), the power gating switch (140) for supplying power to the power domain when the switch is on and for gating the voltage supplied to the power domain when the switch is off, the power gating switch (140) is controlled by a third command, and the PMU (130) is configured to send the third command according to the selected operating mode in order to set the semiconductor device (10) to the selected operating mode when it receives the sleep request.

11. A semiconductor device (10) according to claim 3 or 4, wherein one or more of the power domains include a frequency divider module (65) configured to receive a clock from the clock generator module and divide the clock into a plurality of clocks having different frequencies.

12. A method for operating a semiconductor device according to claim 1 or 2, 1) The software application (14) sets the settings of one or more of the peripheral devices (60) according to the needs of the application, 2) The software application (14) decides to switch to a different operating mode, 3) The PMU (130) collects the settings of at least one of the peripheral devices (60), 4) The control logic (136) of the PMU selects the operating mode of the semiconductor device according to the settings of one or more of the peripheral devices (60). A method characterized by including

13. The method of claim 12 for operating the semiconductor device of claim 10, 5) The PMU (130) sends the first command and / or the second command and / or the third command according to the selected operating mode. A method characterized by including

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