Semiconductor memory device and its manufacturing method, reading and writing method, electronic device, and memory circuit

Abstract

According to the embodiments of the present disclosure, a semiconductor memory device, a manufacturing method thereof, a read / write method, an electronic device, and a memory circuit are provided. [Solution] A transistor is provided for each memory cell in a semiconductor memory device, a gate and an auxiliary electrode are provided for the transistor, and the auxiliary electrode is electrically connected to the drain. During a write operation, a first voltage is applied to the gate via a word line, and then an electrical signal is applied to the source via a bit line based on external input data. During a read operation, a second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0") is applied to the auxiliary electrode via the word line by utilizing the effect of the voltage on the auxiliary electrode on the threshold voltage of the transistor, and then the magnitude of the output current of the field effect transistor is detected to read data.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly, to dynamic memories, electronic devices, and methods for manufacturing dynamic memories.

Background Art

[0002] This application claims the priority of Chinese Patent Application No. 202210351841.1 filed with the National Intellectual Property Administration on April 2, 2022, the entire content of which is incorporated herein by reference.

[0003] A Dynamic Random Access Memory (DRAM) is a semiconductor Memory device that has the advantages of simple structure, low manufacturing cost, and high capacitance density compared to static Memory devices. With the development of technology, the application of DRAM Memory is becoming increasingly widespread. However, conventional DRAMs Memory have the disadvantages of complex structure and low integration density, which limit the application of DRAMs Memory to some extent.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure aims to reduce the leakage current that may occur in the read / write state while ensuring high integration of the device, Dynamic Memory compact the structure of Dynamic Memory, Electronic Device, and Method for Manufacturing Dynamic Memory and improve the memory performance.

Means for Solving the Problems

[0005] According to an embodiment of the present disclosure, Some Provided is a dynamic memory including a substrate and a plurality of memory cells provided on the substrate, the memory cells including a transistor, a bit line, and a word line, the transistor including a drain provided above the substrate, a main gate provided on a side of the drain far from the substrate, insulated from the drain, and electrically connected to the word line, a back gate provided on a side of the drain far from the substrate, surrounding the main gate, insulated from the main gate, and electrically connected to the drain, an active layer surrounding the main gate, insulated from the main gate and the back gate respectively, and electrically connected to the drain, and a source electrically connected to the active layer and the bit line respectively, and insulated from the main gate and the back gate respectively. In some embodiments, a positive projection of the back gate onto the substrate does not overlap with a positive projection of the main gate onto the substrate. In some embodiments, the back gate is located between the source and the drain. In some embodiments, a positive projection of the back gate onto the substrate overlaps with a positive projection of the drain onto the substrate. In some embodiments, a positive projection of the back gate onto the substrate is located within a positive projection of the drain onto the substrate. In some embodiments, the active layer is provided between the main gate and the back gate. In some embodiments, further comprising a connection portion, the back gate being electrically connected to the drain through the connection portion. In some embodiments, the connection portion surrounds the back gate. In some embodiments, the active layer includes a single-crystalline semiconductor material, a polycrystalline semiconductor material, or a metal oxide semiconductor, the metal oxide semiconductor including IGZO, ITO, or IWO.

[0006] According to some embodiments of the present disclosure, a dynamic memory is provided that includes a substrate and a plurality of memory cells provided on the substrate. The memory cells include a transistor, a bit line, and a word line. The transistor is located above the substrate and includes a main gate connected to the word line, an active layer surrounding the main gate and insulated from the main gate, a source respectively connected to the active layer and the bit line, a drain connected to the active layer and spaced from between the sources, and a back gate located between the source and the drain and insulated from the active layer. The back gate is connected to the drain, and a positive projection of the back gate onto the substrate is located within a positive projection of the drain onto the substrate. In some embodiments, the back gate surrounds the main gate, and the active layer is provided between the main gate and the back gate. In some embodiments, a positive projection of the source onto the substrate and a positive projection of the active layer onto the substrate are respectively located within a positive projection of the drain onto the substrate. In some embodiments, a positive projection of the main gate onto the substrate is located within a positive projection of the drain onto the substrate. In some embodiments, a node capacitance is provided between the back gate and the drain, and the node capacitance constitutes an accumulation capacitance. In some embodiments, a second gate insulating layer is further provided, and the back gate is insulated from the active layer, the source, and the drain by the second gate insulating layer. In some embodiments, a connection portion surrounding the back gate is further provided, and the back gate is electrically connected to the drain through the connection portion. In some embodiments, the drain includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface between the bottom surface and the top surface, and the connection portion is in contact with the side surface.

[0007] According to another embodiment of the present disclosure, an electronic device having the dynamic memory is provided.

[0008] According to some embodiments of the present disclosure, providing a substrate, forming a drain by patterning above the substrate, forming a sacrificial layer covering the drain on a side of the drain far from the substrate, forming a source by patterning on a side of the sacrificial layer far from the substrate, forming a first dielectric layer covering the source on the source, forming a through hole in which the drain is exposed at the bottom and the source is exposed on a wall of the hole, and the through hole penetrates the first dielectric layer, the source, and the sacrificial layer, forming an active layer, a first gate insulating layer, and a main gate that are electrically connected to the source and the drain respectively in the through hole in this order, and forming a back gate and a connection part that are electrically connected to the back gate and the drain respectively on a side of the drain far from the substrate, a method for manufacturing a dynamic memory is provided.

[0009] In some embodiments, forming a back gate and a connection part on a side of the drain far from the substrate includes removing a part of the first dielectric layer and the sacrificial layer by patterning so as to expose the drain, forming an accommodation space by removing the remaining sacrificial layer so as to expose the drain, the source, and the active layer, depositing and forming a second gate insulating layer so as to cover the exposed active layer, the source, and the drain, depositing and forming the back gate on the second gate insulating layer so as to fill the accommodation space, and forming the connection part by deposition so as to connect the drain and the back gate respectively.

[0010] According to an embodiment of the present disclosure, a method for reading and writing the above-mentioned Some is provided. When in the writing state, a first voltage is applied to the gate by a word line to turn on the transistor, and a data signal is applied to the source by a bit line. The data signal is stored in a storage capacitor connected to the drain and the above-mentioned Dynamic memory by the turned-on transistor. When in the reading state, a second voltage is applied to the gate by the word line, and the current at the source is measured by the bit line to read the data signal. Back gate

[0011] The Dynamic memory according to the present disclosure has the following effects.

[0012] In the Dynamic memory of the present disclosure, one transistor is provided for each memory cell, and the transistor has a gate and Back gate is provided, Back gate and the drain are electrically connected. When performing a write operation, a first voltage is applied to the gate via a word line, and then, based on external input data, an electrical signal is applied to the source via a bit line. The source transmits the electrical signal to the drain, and the drain transmits the electrical signal Back gate to, Back gate By using the node capacitor between and the drain as the storage capacitor of the memory cell, data writing is realized. When performing a read operation, Back gate utilize the influence of the voltage on the threshold voltage of the transistor, and via the word line Back gate a second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0") is applied, and then, by detecting the magnitude of the output current of the transistor, data reading is realized. Therefore, data reading and writing can be realized by installing only one transistor in the memory cell, without the need to install separate transistors and capacitor elements, greatly simplifying the structure of the memory cell, Dynamic memory which is beneficial for improving the integration degree and storage density of.

Brief Description of the Drawings

[0013] The above and / or additional aspects and advantages of the present disclosure will become apparent and easier to understand from the description of embodiments with reference to the following drawings.

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Embodiments for Carrying Out the Invention

[0014] Hereinafter, the present disclosure will be described in detail, and examples of embodiments of the present disclosure will be shown in the drawings, where the same or similar reference numerals indicate the same or similar members or members having the same or similar functions. Also, when a detailed description of the known technology is not necessary for the illustrated features of the present invention, the description thereof will be omitted. Hereinafter, the embodiments described with reference to the drawings are exemplary only and are merely for explaining the present disclosure and do not limit the present disclosure.

[0015] Those skilled in the art can understand that, unless otherwise specified, the singular forms "1", "one", "the foregoing", and "said" used herein may include the plural forms. The expression "comprising" used in the specification of the present disclosure means the presence of features, integers, steps, operations, elements, and / or components, but further it should be understood that it does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. When an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. Further, as used herein, "connection" or "coupling" may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit of one or more of the related listed items and all combinations thereof.

[0016] According to the present invention Dynamic memory, electronic device, and method for manufacturing dynamic memory aims to reduce the leakage current while ensuring high integration.

[0017] The present invention is electrically connected to the drain, located on one side of the channel, an insulating layer is provided between it and the channel, and a gate is provided on the other side of the channel Back gate is added. The Back gate functions simultaneously as a back gate and a storage electrode, can control the small off-current of the transistor, and can play a role in storing charges. It can achieve relatively low-frequency refresh without adding an additional capacitor, and can ensure a larger charge storage capacity when an additional capacitor is added.

[0018] Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings. Dynamic memory, electronic device, and method for manufacturing dynamic memory will be described in detail.

[0019] FIG. 1 is a Some cross-sectional view of 10 memory cells according to an embodiment of the present disclosure. In FIG. 1, Dynamic memory 10 memory cells In the direction perpendicular to the substrate is a cross-sectional view. In FIG. 1, Dynamic memoryOf the plurality of memory cells arranged in an array at 10, only one memory cell is shown. FIG. 2 is a plan projection view of a partial region of some components of the storage unit shown in FIG. 1.

[0020] As shown in FIG. 1, Dynamic memory 10 includes a substrate 110 and a plurality of memory cells 101 provided on the substrate 110. The memory cell 101 includes a transistor 11, a bit line 32, and a word line 31. The transistor 11 has a drain 112, Main gate 115, back gate 116, active layer 114, and a source 113.

[0021] The substrate 110 may be a silicon substrate, a glass substrate, a flexible substrate, etc., but is not limited thereto. The substrate 110 may have an upper surface and a lower surface facing each other.

[0022] Main gate 115 is a gate connected to the word line 31 to control the on / off of the transistor 11 Main and Back gate 116 is Main gate 115 with respect to The main gate 115 is the active layer located on the surface of the channel, Back gate 116 is Active layer located on the back surface of the channel. Main gate 115 and Back gate Both 116 are used for controlling the transistor current and both serve as gates. However, Back gate the role of 116 is not to control the on and off of the transistor, but to control the transistor to reduce the leakage current loss, Main gate 115 and controls the on or off of the transistor under the action of the word line voltage.

[0023] In some embodiments, Main gate 115 is provided on the substrate 110, extends in a first direction perpendicular to the upper surface of the substrate 110, and may have a column shape. Main gate 115 may be electrically connected to the word line 31.

[0024] An interlayer insulating layer 111 may be provided on the upper surface of the substrate 110 , and a drain 112 may be provided on the interlayer insulating layer 111 .

[0025] Active layer 114 may be provided on the interlayer insulating layer 111, Active layer At least some of 114 Main gate 115 The side walls of the

[0026] Active layer The semiconductor layer 114 may be formed of a single crystal semiconductor material, a polycrystalline semiconductor material, or a metal oxide semiconductor. The metal oxide semiconductor may contain at least one of In, Ga, Zn, Sn, and W.

[0027] Source 113: Active layer 114, provided to surround the outer wall thereof; Active layer 114. The source 113 may be electrically connected to the bit line 32.

[0028] The drain 112 is Active layer of 114 The side close to the substrate 110 To, Active layer 114. The drain 112 is also spaced apart from the source 113 in the first direction.

[0029] No. 1 Gate The insulating layer 117a is Main gate 115 and Active layer 114 and Main gate 115 and the drain 112.

[0030] Back gate 116 is between the source 113 and the drain 112 in the first direction Active layer It may be provided to surround the outer wall of 114.

[0031] The second gate insulating layer 117b is Back gate 116 Active layer 114 and source 113. Back gate 116 and Active layer 114 andBack gate It may be provided between 116 and the source 113. Also, Back gate 116 may be electrically connected to the drain 112.

[0032] Specifically, Back gate 116 may extend in a first direction from the source 113 toward the drain 112. Some In an embodiment, the Back gate orthogonal projection of 116 onto a plane parallel to the upper surface of the substrate 110 and the orthogonal projection of the drain 112 onto a plane parallel to the upper surface of the substrate 110 may overlap.

[0033] Some In an embodiment, the Back gate orthogonal projection of the outer wall of 116 onto a plane parallel to the upper surface of the substrate 110 may be located outside the orthogonal projection of the source 113 onto the plane and may be located inside the orthogonal projection of the drain 112 onto the plane.

[0034] As shown in FIG. 1, Active layer 114 may Main gate 115 surround the side wall of Main gate 115 and the lower surface of First gate insulating layer 117a in a U shape, and Active layer it may also Main gate 115 be formed in a U shape between 114 and Active layer 114 and Main gate 115 so as to insulate them.

[0035] The drain 112 is provided between the substrate 110 and Active layer 114 and is in contact with the lower surface of Active layer 114, as shown in FIG. 1.

[0036] In FIG. 1, it is illustrated that the drain 112 is provided between the substrate 110 and Active layer 114. However, different from FIG. 1, the drain 112 may Active layer surround the lower part of the outer wall of Active layer 114 and may be provided in contact with the lower part of the outer wall of

[0037] Specifically, as shown in FIG. 1, the drain 112 may include a first portion located between the substrate 110 and Active layer 114, and a second portion extending outward in a second direction parallel to the upper surface of the substrate 110 from the first portion. Also, the second portion of the drain 112 Orthogonal projection onto the substrate 110 may Orthogonal projection of the back gate 116 onto the substrate 110 at least partially overlap with

[0038] Some In an embodiment, although not shown, the second portion of the drain 112 may Back gate be in direct contact with 116.

[0039] In another example, as shown in FIG. 1, Back gate 116 may be spaced apart from the second portion of the drain 112 in a first direction Second gate insulating layer 117b via, and Back gate 116 may Connection part 119 be electrically connected to the second portion of the drain 112 via.

[0040] Specifically, Back gate 116 may be electrically connected to an end of the second portion of the drain 112 via a conductive connector 119.

[0041] Although not shown, Connection part 119 may Active layer surround the outer wall of 116 annularly and extend downward in a first direction so as to be connected to the second portion of the drain 112 (for example, Second gate insulating layer 117b may extend through). Also, the Connection part 119 orthogonal projection of on a plane parallel to the upper surface of the substrate 110 is located within the orthogonal projection of Back gate 116 on the plane.

[0042] In other examples, Connection part 119 may Back gate electrically connect a part of the outer wall of 116 to an end of the second portion of the drain 112. In this case, as shown in FIG. 2, the Connection part 119 orthogonal projection of on a plane parallel to the upper surface of the substrate 110 may be located outside the orthogonal projection of Back gate 116 on the plane.​

[0043] The word line 31 and the bit line 32 are both Main gate 115 located in The side far from the substrate 110 and are insulated from each other in different layers.

[0044] As shown in FIG. 1, the orthographic projection of the source 113 onto a plane parallel to the upper surface of the substrate 110 may overlap the orthographic projection of Back gate 116 onto the plane.

[0045] Also, Dynamic memory 10 may further include an additional electrode (not shown) that at least partially overlaps 116 in the first direction, Back gate and the additional electrode may form two opposing electrodes of a capacitor together with 116. The orthogonal projection of this additional electrode onto the substrate 110 and the orthogonal projection of the back gate 116 onto the substrate 110 overlap at least partially, The additional electrode Back gate may be insulated from 116.

[0046] As shown in FIG. 1, the orthographic projection of Main gate 115 onto a plane parallel to the upper surface of the substrate 110 overlaps the orthographic projection of the drain 112 onto a plane parallel to the upper surface of the substrate 110, Main gate 115 and may be insulated from the drain 112.

[0047] However, in other embodiments, the orthographic projection of Main gate 115 onto the substrate 110 does not overlap the orthographic projection of the drain 112 onto the substrate 110.

[0048] As shown in FIG. 1, Back gate 116 may be provided on the upper surface of the drain 112 away from the substrate 110. The orthographic projection of Back gate 116 onto the substrate 110 may overlap the orthographic projection of the drain 112 onto the substrate 110. Back gate 116 may be Main gate 115 insulated from Back gate The orthographic projection of 116 onto the substrate 110 Main gate 115 may not overlap the orthographic projection of

[0049] Active layer 114 is Main gate 115may surround. As shown in FIG. 1, the Active layer orthogonal projection of 114 onto the substrate 110 overlaps with the orthogonal projection of the drain 112 onto the substrate 110, Active layer 114 is Main gate 115 and Back gate insulated from 116 respectively, Active layer 114 is electrically connected to the drain 112.

[0050] The source 113 may be electrically connected to 114 and the bit line 32 respectively, and the source 113 Active layer may be insulated from 116 respectively. Main gate 115 and Back gate Specifically, as shown in FIGS. 1-5, the substrate 110 may include silicon or glass, and a plurality of memory cells 101 located on the substrate 110 are arranged in an array.

[0051] The drain 112 can be formed by a patterning process. On the upper surface of the drain 112 away from the substrate 110,

[0052] 114, Active layer 114, Main gate 115 , First gate insulating layer 117a, second gate insulating layer 117b, back gate 116 and the source 113 are provided.

[0053] The source 113 may be located on the surface of 116 away from the substrate 110, that is, the drain 112, Back gate 116 and the source 113 are provided by being stacked in order along the first direction in FIG. 1. Back gate 116 and the source 113 are provided by being stacked in order along the first direction in FIG. 1. Main gate 115 and Back gate 116 extends upward along the first direction on the substrate 110. That is, Main gate 115 and Back gate 116 has a longer length in the first direction in FIG. 1 than the lengths in other directions.

[0054] Main gate 115 and active layer Between 114, the source 113 and the drain 112 First gate insulating layer 117a is insulated by Back gate 116 and active layer 114, Between the source 113 and the drain 112 Second gate insulating layer 117bInsulated by, the source 113 and the drain 112 are respectively Active layer electrically connected to 114. The source 113, the drain 112, Main gate 115, back gate 116 and active layer 114 are stacked to form the transistor 11 with a three-dimensional structure ( Active layer 114, Main gate 115 and back gate 116 all extend along the direction perpendicular to the substrate 110), Back gate 116 is electrically connected to the drain 112. The memory cell 101 further includes Main gate 115 a word line 31 electrically connected to, and a bit line 32 electrically connected to the source 113.

[0055] Dynamic memory When 10 is in the write operation mode, a first voltage is applied to Main gate 115 through the word line 31, and the first voltage is an on voltage (for example, +5V). At this time, the channel of the transistor is in the conductive state, and the voltage of the source is approximately equal to the voltage of the drain. At the same time, a voltage input data signal is applied to the source 113 through the bit line 32, and the voltage of the drain 112 is equal to the voltage of the data signal input from the source. Since the drain 112 and Back gate 116 are electrically connected, at this time, the magnitudes of the voltages at the source 113, the drain 112 and Back gate the magnitude of the voltage at 116 are the same (the potentials of the drain 112 and Back gate 116 are the same). Back gate The node capacitor between 116 and the drain 112 constitutes the storage capacitor 103 of the memory cell 101, Back gate the height of the voltage at 116 determines the magnitude of the charge amount in the storage capacitor, and further determines whether the binary of the data signal stored in the memory cell 101 is 0 or 1. When a high voltage (for example, 5V) is applied to the source 113 through the bit line 32, data "1" is written into the memory cell 101, and when a low voltage (for example, 0V) is applied to the source 113 through the bit line 32, data "0" is written into the memory cell 101.

[0056] In the above embodiment, the node capacitor is the Back gateThe potential difference between 116 and infinity, or Back gate it may also be the voltage difference between 116 and peripheral electrodes such as the source and gate.

[0057] Dynamic memory When 10 is in the read operation mode, Main gate 115 a second voltage is applied via the word line 31 so as to have a voltage difference with the source 113, turning on the transistor, Main gate 115 and the charge stored in 116 is sensed by the sense bit line 32, and the magnitude of the current in the bit line 32 (i.e., the output current of the transistor 11) is detected, realizing the reading of data. In some embodiments, the sense bit line 32 may be the above-described bit line, and in this case, the input signal line and the data read line are the same line. Back gate

[0058] Back gate Specifically, when the data stored in front of the memory cell 101 is "1", Back gate 116 and the drain 112 have a high potential (e.g., +5V), and due to the combined action of the first voltage and the second voltage of the gate, the transistor 11 is in the on state, so a significant current can be measured via the bit line 32. When an obvious current is measured, it is determined that the read data is "1". When the data stored in front of the storage unit 101 is "0", Main gate 115 the potentials on 116 and the drain 112 are low, and after applying the second voltage, the transistor 11 is still in the off state, so the current measured via the bit line 32 is very weak, and at this time, it is determined that the read data is "0".

[0059] Back gate Note that the magnitude of the threshold voltage of the transistor 11 Back gate is related to the control of 116. When there is only a gate, Vth is related to factors such as the material and the device structure. When controls the semiconductor channel of the transistor, a negative bias is generated in the Vth of the transistor.

[0060] ​Regarding an N-type field-effect transistor (where carriers are electrons when the transistor is on), Back gate The higher the potential on the gate 116 and the drain 112 (e.g., +5V), the smaller the on-voltage of the transistor gate becomes (i.e., the threshold voltage is negative), that is, Main gate 115 When the pressure difference between the source 113 and the drain 112 is small, the transistor 11 is also turned on, Back gate The lower the potential on the gate 116 and the drain 112, the Back gate by Active layer control of the channel is weak, and the threshold voltage is Back gate not affected by. Therefore, Main gate 115 When the same second voltage is applied to the gate 116, referring to FIG. 6, the horizontal axis in FIG. 6 is the Main gate 115 voltage applied to the gate 116 (i.e., the second voltage), and the vertical axis is the output current of the transistor 11. Main gate 115 When the voltage applied to the gate 116 is a specific value (the position of the dashed line in FIG. 6), Back gate depending on the high or low voltage at the gate 116 and the drain 112 (i.e., whether the data written in the transistor 11 is "1" or "0"), there is a significant difference in the magnitude of the output current of the transistor 11 (i.e., the current measured through the bit line 32). By detecting the current of the bit line 32, the data can be read from the memory cell 101. When the transistor 11 writes the data "1", since the output current of the transistor 11 is large, the read data is also "1". When the data written by the transistor 11 is "0", since the output current of the transistor 11 is extremely weak, the read data is also "0".

[0061] In this case, Back gate By increasing the control of the semiconductor channel by the gate 116, the transistor can obtain a large current with a small on-voltage, and it becomes difficult to turn off when the transistor is on. When the transistor is off, a large voltage is required to turn on, making it difficult to turn on. In this way, the dark current during on or off can be reduced, the ability of the device to accumulate and hold charges can be improved, and in some embodiments, the refresh frequency can be reduced.

[0062] The value of the second voltage may be determined according to the parameters of the transistor and the magnitude of the voltage applied to the drain 112 at the time of the write operation. Note that the value of the second voltage needs to be appropriate (it needs to be between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0"). If the value of the second voltage is not appropriate, when storing data "1" (i.e., the potential on the drain 112 and Back gate 116 is high), the output current of transistor 11 and when storing data "0" (i.e., the potential on the drain 112 and Back gate 116 gate is low), the magnitudes of the output currents of transistor 11 are very close. Therefore, when performing a read operation, it is difficult to determine whether the read data is "0" or "1", which Back gate affects the performance of Dynamic memory 10. The optimal value of the second voltage can be determined by experiments or simulation methods so that the difference in output current is maximized when transistor 11 performs read operations in different states in order to improve the read performance.

[0063] According to the present disclosure Dynamic memory in 10, one transistor 11 is provided for each memory cell 101, and Main gate 115 and back gate 116 is provided for the transistor 11, Back gate and 116 and the drain 112 are electrically connected. During the write operation, Main gate 115 after applying a first voltage to the word line 31, an electrical signal is applied to the source 113 via the bit line 32 according to the external input data. The source 113 transmits the electrical signal to the drain 112, and the drain 112 transmits the electrical signal to Back gate 116, Back gate and the node capacitor between 116 and the drain 112 constitutes the memory capacitor of the memory cell 101 to realize the writing of data ("1" or "0"). When performing a read operation, Back gate the influence of the voltage at 116 on the threshold voltage of transistor 11 is advantageous, and via the word line 31 Main gate 115A second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor 11 stores "1" and the threshold voltage when the transistor 11 stores "0") is applied, and data reading is realized by detecting the magnitude of the output current of the field-effect transistor. Therefore, the memory cell 101 in the embodiment of the present disclosure can realize data reading and writing only by providing one transistor 11, without the need to provide other transistors and capacitive elements, greatly simplifying the structure of the memory cell 101, which is beneficial to improving the integration degree and memory density of the semiconductor memory element 10. Also, it becomes easy to stack the memory cells 101 to form a multi-layer structure of Dynamic memory 10, Dynamic memory and the formation process of 10 is simplified.

[0064] In the embodiment of the present disclosure, Main gate 115, back gate 116, active layer both the gate 114 and the source 113 are provided on the side far from the substrate 110 of the drain 112, Main gate 115, back gate 116, active layer and the specific positions of the gate 114 and the source 113 can be adjusted according to the actual situation. In the embodiment, as shown in FIGS. 1 and 2, in the embodiment of the present disclosure, Main gate 115, back gate the gate 116, the source 113 and Active layer the orthographic projections of the gate 114 on the substrate 110 all fall within the orthographic projection of the drain 112 on the substrate 110, so the area occupied by the transistor 11 can be reduced, Dynamic memory making the structural layout of 10 more compact, which is more beneficial to the integration of the device.

[0065] As shown in FIGS. 1 and 2, in the embodiment, Back gate the gate 116 Main gate 115 surrounds, Active layer 114 is the main gate 115 and the back gate and is provided between the gate 116 and the gate 114. Back gate 116 is the main gate 115 By surrounding the gate 116, Main gate 115, back gate 116 and active layer the area of the overlapping region between the gate 114 and the gate 116 can be maximally increased, thereby Back gate greatly affecting the threshold voltage of the transistor 11 of the gate 116, that is, Back gateWhen the voltages at 116 are different, by applying the same threshold voltage, a large difference can be created in the output current of the transistor. Therefore, it is advantageous for distinguishing the data read during the read operation, improving the accuracy of the read data. Note that in the first direction in FIG. 1 Main gate 115 of the layer and Back gate the thickness of the layer of 116 may be determined according to the actual situation and is not limited here.

[0066] In this embodiment, Active layer the material of 114 includes a metal oxide semiconductor material. Due to the inherent characteristics of the metal oxide semiconductor (factors such as low electron mobility), Active layer when a metal oxide is adopted as the material of 114, the leakage current of the transistor 11 can be reduced, and the speed of the charge flow in the storage capacitor can be decreased. Therefore, Dynamic memory the data retention time of 10 can be lengthened, Dynamic memory which is advantageous for reducing the refresh frequency and power consumption of 10.

[0067] The metal oxide material may be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor 11 is small (the leakage current is less than 10 -15 A), and thereby Dynamic memory the operating performance of can be ensured. Note that the metal oxide material may be ITO, IWO, ZnO x , InO x , In 2 O 3 , InWO, SnO 2 , TiO x , InSnO x , Zn x O y N z , Mg x , Zn y O z , In x , Zn y O z , In x , Ga y , Zn zO a 、 Zr x In y Zn z O a 、 Hf x In y Zn z O a 、 Sn x In y Zn z O a 、 Al x Sn y In z Zn a O d 、 Si x In y Zn z O a 、 Zn x Sn y O z 、 Al x Zn y Sn z O a 、 Ga x Zn y Sn z O a 、 Zr x Zn y Sn z O a Materials such as InGaSiO may also be used, as long as it is guaranteed that the leakage current of the transistor meets the requirements, and specifically, it can be adjusted according to the actual situation.

[0068] Note that Back gate The specific method for realizing the electrical connection between 116 and the drain 112 can be determined according to the actual situation. In the embodiment, as shown in FIGS. 1 and 2, the transistor 11 Connection part 119 further includes Connection part 119 which is provided on the side far from the substrate 110 of the drain 112, Back gate 116 is Connection part 119 electrically connected to the drain 112 through Dynamic memory In the formation process of 10, the drain 112 and Back gateAfter forming 116, a conductive connection member 119 can be formed by depositing a metal material on the drain 112, which is easy in the process. The material of the conductive connection member 119 can be a material having good electrical conductivity such as copper or aluminum, which is not limited herein. The size and position of the conductive connection member 119 can be adjusted according to the actual situation. In the embodiment, as shown in FIGS. 1 and 2, Connection part 119 is Back gate to surround 116, Connection part 119 and back gate the contact area with 116 and the drain 112 can be maximized, Back gate which is advantageous for improving the electrical connection performance between 116 and the drain 112 before.

[0069] In the embodiment, as shown in FIGS. 1-5, in the embodiment of the present disclosure, Dynamic memory 10 includes a plurality of array modules 102 provided in a stacked manner, and the array module 102 includes a plurality of memory units 101 arranged in an array. Specifically, the word lines 31 (not shown in FIG. 3) of the plurality of memory cells 101 are connected to each other, and the bit lines 32 (not shown in FIG. 3) are connected to each other to form one layer of array module 102. The multi-array module 102 has a three-dimensional structure Dynamic memory By being stacked and provided to form 10, Dynamic memory the storage capacity of 10 is improved, and at the same time, Dynamic memory the area occupied by 10 can be reduced, which is advantageous for the integration of the device.

[0070] Based on the same inventive concept, the embodiment of the present disclosure further provides a memory circuit. As shown in FIG. 4, Main gate 115, back gate including 116, a source 113, a drain 112, a word line 31, and a bit line 32, Main gate 115 is electrically connected to the word line 31, the source 113 is electrically connected to the bit line 32, and the drain 112 is Back gate electrically connected to 116, Main gate 115 and back gate 116 is insulated from each other, Main gate 115 is insulated from the source 113 and the drain 112 respectively, Back main gate 115is insulated from the source 113 and the drain 112 respectively, Back gate The node capacitor between 116 and the drain 112 constitutes the storage capacitor 103.

[0071] Based on the same inventive concept, embodiments of the present disclosure further provide an electronic device including the above Dynamic memory 10, or an electronic device including the above storage circuit according to the embodiments of the present disclosure. Since the electronic device includes the above Dynamic memory 10, Dynamic memory it has the same beneficial effects as 10, and the description is omitted here.

[0072] Specifically, the electronic device according to the embodiments of the present disclosure includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, etc., and specifically can be determined according to the actual situation. The storage device may include a memory in a computer, etc., and is not limited here.

[0073] Based on the same inventive concept, embodiments of the present disclosure Dynamic memory further provide a manufacturing method of 10. In S101, a substrate is provided. In S102, a drain is formed on one side of the substrate by a patterning process. In S103, a source Active layer and a gate are sequentially formed on the side of the drain far from the substrate. In S104, on the side of the drain far from the substrate Back gate and a conductive connection member are formed.

[0074] In the forming method according to an embodiment of the present disclosure, by providing one transistor 11 for each memory cell 101, 116 is provided in the transistor 11 Main gate 115 and back gate and Back gate 116 and the drain 112 are electrically connected. When performing a writing operation, via the word line 31 Main gate 115Apply a first voltage, and then, based on external input data, apply an electrical signal to the source 113 via the bit line 32. The source 113 transmits the electrical signal to the drain 112, and the drain 112 transmits the electrical signal to Back gate 116, Back gate By configuring the node capacitance between 116 and the drain 112 to form the storage capacitance of the memory cell 101, data writing is realized. When performing a read operation, via the word line 31 Main gate 115 Apply a second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor 11 stores "1" and the threshold voltage when the transistor 11 stores "0") to, and then, by detecting the magnitude of the output current of the field-effect transistor, realize data reading. Therefore, data reading and writing can be realized by simply installing one transistor 11 in the memory cell 101, without the need to separately install a transistor 11 and a capacitor element, greatly simplifying the structure of the memory cell 101, Dynamic memory which is beneficial for improving the integration degree and storage density of 10.

[0075] In one embodiment, the step of sequentially forming the source 113, Active layer 114 and Main gate 115 on the side of the drain 112 far from the substrate 110 is forming a sacrificial layer on the side of the drain far from the substrate, such that the sacrificial layer covers the drain, forming a source on the side of the sacrificial layer far from the substrate by a patterning process, where the orthogonal projection of the source on the substrate is located within the orthogonal projection of the drain on the substrate, forming a first medium layer on the side of the source far from the substrate, where the first medium layer covers the source and the drain, opening a through hole that sequentially penetrates the first medium layer, the source, and the sacrificial layer, exposing the drain at the bottom of the through hole and exposing the source on the hole wall of the through hole, inside the through hole, Active layer , a first insulating layer, and a gate are sequentially formed, Active layer which are electrically connected to the source and the drain respectively, and includes.

[0076] In one embodiment, on the side of the drain 112 far from the substrate 110 Back gate The steps of forming 116 and the conductive connection member 119 include removing a part of the first dielectric layer and the sacrificial layer by a patterning process to expose the drain, removing the remaining sacrificial layer to form an accommodation space for exposing the drain, the source, and Active layer forming an accommodation space for exposing the drain, the source, and depositing and forming a second insulating layer to cover the exposed Active layer source 113 and the drain with the second insulating layer, depositing Back gate on the surface of the second insulating layer , back gate to fill the accommodation space, depositing and forming conductive connection members at both ends of the exposed drain, and connecting the conductive connection members to the drain and Back gate respectively.

[0077] In an embodiment of the present disclosure, on the side of the drain 112 far from the substrate 110 Back gate 116 and Connection part 119 after forming, further forming a word line by a patterning process and electrically connecting the word line and the gate, forming a bit line by a patterning process and electrically connecting the bit line to the source.

[0078] Hereinafter, the manufacturing process of Dynamic memory 10 according to the embodiments of the present disclosure will be described in detail with reference to the drawings. Specifically, the patterning process in the embodiments of the present disclosure includes some or all of the processes of applying a photoresist, exposing, developing, etching, and removing the photoresist. As shown in FIG. 8a, first, a substrate 110 is provided. The material of the substrate 110 includes silicon or glass. As shown in FIG. 8b, next, an interlayer insulating layer 111 is formed on one side of the substrate 110. As shown in FIG. 8c, next, a drain 112 is formed on the side of the interlayer insulating layer 111 far from the substrate 110 by a patterning process. Next, as shown in FIG. 8d, a sacrificial layer 100 is formed on the side of the drain 112 far from the substrate 110, the sacrificial layer 100 covers the drain 112, and the material of the sacrificial layer 100 includes an organic material or an inorganic material. Next, as shown in FIG. 8e, a source 113 is formed on the side of the sacrificial layer 100 far from the substrate 110 by a patterning process, and the orthographic projection of the source 113 on the substrate 110 is positioned within the orthographic projection of the drain 112 on the substrate 110. Next, as shown in FIG. 8f, a first medium layer 118a is formed on the side of the source 113 far from the substrate 110 so that the first medium layer 118a covers the source 113. The material of the first medium layer 118a includes an inorganic material such as silicon oxide or silicon nitride. Next, as shown in FIG. 8g, a part of the region on the first medium layer 118a is shielded by a mask 23, a through hole 20 is opened in the first medium layer 118a not shielded by the mask 23, the through hole 20 penetrates the first medium layer 118a, the source 113, and the sacrificial layer 100 in sequence, the drain 112 is exposed at the bottom of the through hole 20, and the source 113 is exposed on the hole wall of the through hole 20. Next, as shown in FIG. 8h, into the via hole 20 by processes such as atomic deposition, chemical vapor deposition, physical vapor deposition Active layer 114, First gate insulating layer 117a and Main gate 115 are formed in sequence, Active layer 114 is electrically connected to the source 113 and the drain 112 respectively. Active layer The material of 114 includes a metal oxide such as IGZO, First gate insulating layer 117a The material of includes a material having good insulation performance such as aluminum oxide. Main gate 115 The material of includes a material having good conductivity such as titanium nitride, tungsten, etc. Then, by a chemical mechanical polishing process Active layer 114, first gate insulating layer 117a and main gate 115 The surface away from the substrate 110 of is polished, Active layer 114, first gate insulating layer 117a, main gate 115 and the first medium layer 118a are made flush. Next, as shown in FIG. 8i, a part of the first medium layer 118a and the sacrificial layer 100 are removed by a patterning process to expose the drain 112. Specifically, using the mask 23 Active layer 114, First gate insulating layer 117aAnd Main Gate 115 Shield the corresponding regions, and etch the portions located at both ends of the first dielectric layer 118a and the sacrificial layer 100. Next, as shown in FIG. 8j, remove the remaining sacrificial layer 100 by an etching process, and form the accommodation space 22 so as to expose the drain 112, the source 113, and Active Layer 114. Next, as shown in FIG. 8k, Second Gate Insulating Layer 117b is formed in the accommodation space 22 by a deposition process, Second Gate Insulating Layer 117b covers the exposed Active Layer 114, the source 113, and the drain 112. Next, as shown in FIG. 8l, Second Gate Insulating Layer 117b on the surface of Back Gate 116 is deposited and formed, Back Gate 116 is filled in the accommodation space 22. Next, by an etching process Back Gate the side surfaces of 116 are etched to ensure that the Back Gate 116s of adjacent memory cells are isolated from each other. Next, as shown in FIG. 8m, Connection Part 119 is deposited and formed at both ends of the exposed drain 112 by a deposition process, Connection Part 119 is connected to the drain 112 and Back Gate 116 respectively to complete the manufacture of the transistor 11. Next, as shown in FIG. 8n, a second dielectric layer 118b is formed on one side of the substrate 110 by a deposition process so that the second dielectric layer 118b covers the transistor 11. Next, as shown in FIG. 8o, a through passage 21 is opened at a position corresponding to the source 113 in the second dielectric layer 118b. Next, as shown in FIG. 8p, a bit line 32 is formed on the side of the second dielectric layer 118b far from the substrate 110 by a patterning process, and the bit line 32 is electrically connected to the source 113 through the through via 21. Next, as shown in FIG. 8q, a third dielectric layer 118c is deposited on the second dielectric layer 118b. Next, as shown in FIG. 8r, Main Gate 115 a through passage 21 is provided at a position corresponding to As shown in FIG. 8s, next, a word line 31 is formed on the side of the third medium layer 118c far from the substrate 110 by a patterning process, and the word line 31 is electrically connected to Main Gate 115 through the through-passage 21. Based on the same inventive concept, the embodiments of the present disclosure further provide Dynamic Memory a reading and writing method of 10. In S201, when in the writing state, a first voltage is applied to the gate by the word line. In S202, based on the external input data, an electrical signal is applied to the source through the bit line, and the data is Dynamic Memory written to, or when in the reading state, a second voltage is applied to the gate through the word line. In S203, the current at the source is measured by the bit line, and the data is Dynamic Memory read from.

[0079] Specifically, as shown in FIGS. 1 and 2 (word lines and bit lines are not shown in FIG. 2), Dynamic Memory when 10 is in the write operation mode, by applying a first voltage (for example, 5V) to Main Gate 115 through the word line 31, the transistor 11 is turned on, and the magnitude of the first voltage is related to factors such as the structure of the transistor 11 and the material of Active Layer 114 in the transistor 11, and specifically, it can be adjusted according to the actual situation. When the transistor 11 is turned on, according to the external input data, a voltage is applied to the source 113 through the bit line 32, and the source 113 and the drain 112 Active Layer are conducted through 114, and the drain 112 and Back Gate 116 are electrically connected, so that the magnitudes of the voltages at the source 113 and the drain 112 and Back Gate the magnitude of the voltage at 116 become the same. Back Gate The node capacitance between 116 and the drain 112 constitutes the storage capacitance of the memory cell 101, Back GateThe height of the gate voltage of 116 determines the magnitude of the charge amount in the storage capacitance, and further determines whether the binary value of the data signal stored in the memory cell 101 is 0 or 1. When a high voltage (for example, when it is 5 V) is applied to the source 113 via the bit line 32, data "1" is written into the memory cell 101, and when a low voltage (for example, 0 V) is applied to the source 113 via the bit line 32, data "0" is written into the memory cell 101.

[0080] Dynamic Memory When 10 is in the read operation mode, Main Gate 115 so as to have a voltage difference with the source 113, via the word line 31 Main Gate 115 a second voltage is applied to, and at the same time, the magnitude of the current flowing through the bit line 32 (that is, the output current of the transistor 11) is detected to realize the reading of data. Specifically, when the data stored in front of the memory cell 101 is "1", Back Gate 116 and the drain 112 have a high potential, and due to the combined action of the first voltage and the second voltage, the transistor 11 is in the on state, so a significant current can be measured via the bit line 32. When an obvious current is measured, it is determined that the read data is "1". When the data stored in front of the storage unit 101 is "0", Back Gate the voltages at 116 and the drain 112 are low, Main Gate 115 after a second voltage is applied to, since the field-effect transistor is still in the off state, the current measured via the bit line 32 is very weak, and at this time, it is determined that the read data is "0".

[0081] Note that the magnitude of the threshold voltage of the transistor 11 is Back Gate related to the magnitudes of the voltages at 116 and the drain 112. For an N-type field-effect transistor (that is, the Active Layer 114 adopts an N-type semiconductor material), Back Gate the higher the potentials at 116 and the drain 112, the smaller the threshold voltage, that is, Main Gate 115When the differential pressure between the source 113 is small, the transistor 11 can have a large output current. Back Gate The lower the potentials at 116 and the drain 112, the higher the threshold voltage. Therefore, Main Gate 115 When a second voltage similar to that in is applied, as shown in FIGS. 1, 4, and 6, Back Gate Depending on the voltage levels at 116 and the drain 112 (i.e., whether the data written by the transistor 11 is "1" or "0"), there is a significant difference in the magnitude of the output current of the transistor 11 (i.e., the current measured by the bit line 32). By detecting the current in the bit line 32, data can be read from the memory cell 101. When writing the data "1" by the transistor 11, the output current of the transistor 11 is "1".

[0082] Note that the numerical value of the second voltage can be determined based on the parameters of the field-effect transistor and the magnitude of the voltage applied to 116 and the drain 112 during the write operation. The value of the second voltage needs to be appropriate (it needs to be between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0"). If the value of the second voltage is not appropriate, when storing the data "1" (i.e., the potential on the drain 112 and Back Gate 116 is high), the output current of the transistor 11 and when storing the data "0" (i.e., the potential on the drain 112 and Back Gate 116 The potential on the gate is low), the magnitudes of the output currents of the transistor 11 are very close. Therefore, when performing the read operation, it is difficult to determine whether the read data is "0" or "1", which Back Gate Affects the performance of 10. In actual applications, the optimal value of the second voltage can be determined by experiments or simulation methods to maximize the difference in output currents when the transistor 11 performs read operations in different states, thereby improving the read performance. Dynamic Memory Applying the embodiments of the present disclosure can achieve at least the following beneficial effects.

[0083] By applying the embodiments of the present disclosure, at least the following beneficial effects can be realized. 1. According to the present disclosure Dynamic Memory 10, one transistor 11 is provided for each memory cell 101, and the transistor 11 Main Gate 115 and Back Gate 116 is provided, Back Gate 116 and the drain 112 are electrically connected. When performing a write operation, via the word line 31 Main Gate 115 a first voltage is applied to, and then, based on the external input data, an electrical signal is applied to the source 113 via the bit line 32, the source 113 transmits the electrical signal to the drain 112, and the drain 112 transmits the electrical signal to Back Gate 116, Back Gate the node capacitance between 116 and the drain 112 constitutes the storage capacitance of the memory cell 101, thereby realizing data writing. When performing a read operation, Back Gate utilizing the influence of the voltage on 116 on the threshold voltage of the transistor 11, via the word line 31 Main Gate 115 a second voltage (the magnitude of the second voltage is between the threshold voltage when the transistor 11 stores "1" and the threshold voltage when the transistor stores "0") is applied to, and then, by detecting the magnitude of the output current of the field effect transistor, data reading is realized. Therefore, data reading and writing can be realized only by installing one transistor 11 in the memory cell 101, and there is no need to separately install a transistor 11 and a capacitor element, greatly simplifying the structure of the memory cell 101, Dynamic Memory which is advantageous for improving the integration degree and storage density of 10. 2. In an embodiment of the present disclosure, Main Gate 115 , by making the orthographic projections of Back Gate 116, the source 113 and Active Layer 114 all fall within the orthographic projection of the drain 112 on the substrate 110, the area occupied by the transistor 11 is reduced, Dynamic Memory the structural layout of 10 is made more compact, which is more advantageous for device integration. 3. In an embodiment of the present disclosure, Back Gate 116 and Main Gate 115 by surrounding, Main Gate 115, Back Gate the area of the overlapping region between 116 and Active Layer 114 can be maximally increased, therebyBack Gate It is possible to significantly affect the threshold voltage of the transistor 11 of 116, that is, Back Gate When the voltages in 116 are different, by applying the same threshold voltage, a large difference can be created in the output current of the field-effect transistor. Therefore, it is advantageous for distinguishing the data read during the read operation, and it improves the accuracy of the read data. 4. Active Layer When a metal oxide is adopted as the material of 114, the leakage current of the transistor 11 can be reduced (when the metal oxide is IGZO, the leakage current is 10 -15 A or less), and since the charge loss rate in the storage capacitor can be reduced, Dynamic Memory the data storage time of 10 can be extended, Dynamic Memory which is advantageous for reducing the refresh frequency and power consumption of 10. 5. In the embodiments of the present disclosure, a plurality of memory cells 101 are arranged in an array to form an array module 102, and then the multilayer array modules 102 are stacked and installed to have a three-dimensional structure Dynamic Memory for forming 10, Dynamic Memory while improving the storage capacity of 10, Dynamic Memory the area occupied by 10 is reduced, which is advantageous for the integration of the device.

[0084] In the description of the present disclosure, the orientation or positional relationship indicated by terms such as "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of description and simplification of the description of the present disclosure, and does not indicate or imply that the specified device or element must have a specific orientation and be configured and operated in a specific orientation. Therefore, it should not be understood as limiting the present disclosure.

[0085] The terms "first" and "second" are for illustrative purposes only and are not to be construed as indicating relative importance or implying or implicitly indicating the number of the indicated technical features. Thus, the features limited to "first" and "second" can explicitly or implicitly include one or more of such features. In the description of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more.

[0086] In the description of this specification, specific features, structures, materials or characteristics can be combined in a suitable manner in any one or more of the embodiments or exemplifications.

[0087] The above are only some embodiments of the present disclosure. For those skilled in the art, without departing from the principles of the present disclosure, some improvements and modifications can be made, and these improvements and modifications should also be regarded as within the protection scope of the present disclosure.

Claims

A dynamic memory comprising a substrate and a plurality of memory cells provided on the substrate, wherein: The memory cells include transistors, bit lines, and word lines. The transistor includes: A drain provided above the substrate; A main gate provided on the side of the drain far from the substrate, insulated from the drain, and electrically connected to the word line; A back gate provided on the side of the drain far from the substrate, surrounding the main gate, insulated from the main gate, and electrically connected to the drain; An active layer surrounding the main gate, insulated from the main gate and the back gate respectively, and electrically connected to the drain; A source electrically connected to the active layer and the bit line respectively, and insulated from the main gate and the back gate respectively. The dynamic memory includes the above components. The dynamic memory according to claim 1, wherein a positive projection of the back gate on the substrate does not overlap with a positive projection of the main gate on the substrate. The dynamic memory according to claim 1, wherein the back gate is located between the source and the drain. The dynamic memory according to claim 1, wherein a positive projection of the back gate on the substrate overlaps with a positive projection of the drain on the substrate. The dynamic memory according to claim 4, wherein a positive projection of the back gate on the substrate is located within a positive projection of the drain on the substrate. The dynamic memory according to claim 1, wherein the active layer is provided between the main gate and the back gate. The dynamic memory according to claim 1, further comprising a connection portion, wherein the back gate is electrically connected to the drain through the connection portion. The dynamic memory according to claim 7, wherein the connection portion surrounds the back gate. The dynamic memory according to claim 1, wherein the active layer includes a single crystal semiconductor material, a polycrystalline semiconductor material, or a metal oxide semiconductor. The dynamic memory according to claim 1, wherein the metal oxide semiconductor includes IGZO, ITO, or IWO. A dynamic memory comprising a substrate and a plurality of memory cells provided on the substrate, wherein: The memory cell includes a transistor, a bit line, and a word line. The transistor includes a main gate located above the substrate and connected to the word line, an active layer surrounding the main gate and insulated from the main gate, a source respectively connected to the active layer and the bit line, a drain connected to the active layer and spaced apart from between the sources, and a back gate located between the source and the drain and insulated from the active layer. The back gate is connected to the drain, and a positive projection of the back gate onto the substrate is located at a positive projection of the drain onto the substrate. It is a dynamic memory. **Claim 11**: The dynamic memory according to claim 10, wherein the back gate surrounds the main gate, and the active layer is provided between the main gate and the back gate. **Claim 12**: The dynamic memory according to claim 10, wherein a positive projection of the source onto the substrate and a positive projection of the active layer onto the substrate are respectively located at a positive projection of the drain onto the substrate. **Claim 13**: The dynamic memory according to claim 10, wherein a positive projection of the main gate onto the substrate is located at a positive projection of the drain onto the substrate. **Claim 14**: The dynamic memory according to claim 10, having a node capacitance between the back gate and the drain, and the node capacitance constitutes a storage capacitance. **Claim 15**: The dynamic memory according to claim 10, further comprising a second gate insulating layer, and the back gate is insulated from the active layer, the source, and the drain by the second gate insulating layer. **Claim 16**: The dynamic memory according to claim 10, further comprising a connection portion surrounding the back gate, and the back gate is electrically connected to the drain through the connection portion. **Claim 17**: The dynamic memory according to claim 16, wherein the drain includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface between the bottom surface and the top surface, and the connection portion is in contact with the side surface. **Claim 18**: An electronic device having the dynamic memory according to claim 1. **Claim 19**: Preparing a substrate, forming a drain by patterning above the substrate, forming a sacrificial layer covering the drain on a side of the drain far from the substrate. forming a source by patterning on the side of the sacrificial layer far from the substrate; forming a first dielectric layer covering the source on the source; forming a through hole in which the drain is exposed at the bottom and the source is exposed on the wall of the hole, the through hole penetrating the first dielectric layer, the source and the sacrificial layer; forming an active layer, a first gate insulating layer and a main gate, which are electrically connected to the source and the drain respectively, in the through hole in sequence; forming a back gate and a connection part electrically connected to the back gate and the drain respectively on the side of the drain far from the substrate; including A method for manufacturing a dynamic memory.

20. Forming the back gate and the connection part on the side of the drain far from the substrate is removing a part of the first dielectric layer and the sacrificial layer by patterning so as to expose the drain; removing the remaining sacrificial layer to form an accommodation space so as to expose the drain, the source and the active layer; depositing and forming a second gate insulating layer so as to cover the exposed active layer, the source and the drain; depositing and forming the back gate on the second gate insulating layer so as to fill the accommodation space; forming the connection part by deposition so as to connect to the drain and the back gate respectively. A method for manufacturing a dynamic memory according to claim 19, including

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