Monolithic complementary field effect transistors with carbon-doped release layers.

Abstract

The embodiments of the present disclosure advantageously provide a semiconductor device CFET having a fully strained superlattice structure with, inter alia, a substantially defect-free channel layer and an exfoliation layer having a reduced selective removal rate, and a method for manufacturing such a device. The CFET described herein includes a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure including a first hGAA structure on the substrate, a sacrificial layer on the top surface of the first hGAA structure, the sacrificial layer including silicon germanium (SiGe) having a germanium content in the range of greater than 0% to 50% on an atomic basis, and a second hGAA structure on the top surface of the sacrificial layer. Each of the first hGAA and the second hGAA includes alternating layers of a nanosheet channel layer including silicon (Si) and a nanosheet exfoliation layer including doped silicon germanium (SiGe).

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0002] Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular to transistors. More particularly, embodiments of the present disclosure relate to complementary field effect transistors (CFETs). [Background technology]

[0002] Transistors are key components of most integrated circuits. A transistor's drive current, and therefore its speed, is proportional to the transistor's gate width, so faster transistors generally require larger gate widths. Thus, there is a tradeoff between transistor size and speed, and to address the conflicting goals of a transistor with maximum drive current and minimum size, "fin" field effect transistors (finFETs) have been developed. FinFETs are characterized by a fin-shaped channel region that significantly increases the size of the transistor without significantly increasing the transistor's footprint, and are currently being applied in many integrated circuits. However, finFETs have their own drawbacks.

[0003] As transistor device feature sizes continue to shrink to achieve greater circuit density and higher performance, there is a need to improve transistor device structures to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field effect transistor (FinFET) structures, and gate-all-around (GAA) structures. GAA device structures include several lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. GAA structures offer good electrostatic control and may find widespread adoption in complementary metal-oxide-semiconductor (CMOS) wafer fabrication.

[0004] One example of a gate-all-around (GAA) technology is the complementary field-effect transistor (CFET), where nFET and pFET nanowires / nanosheets are stacked vertically on top of each other. CFET transistors have increased on-chip device density and reduced area consumption compared to GAA transistors. When stacking nFETs and pFETs monolithically, n and p superlattices are deposited sequentially with intermediate sacrificial layers that are selectively removed during processing and replaced with intermediate dielectric isolation. The intermediate dielectric isolation layer serves to electrically isolate the lower level GAA from the upper level GAA.

[0005] Each n or p superlattice of a CFET includes alternating layers of channel layers and exfoliation layers. The exfoliation layers typically include silicon germanium (SiGe) with a low concentration of germanium (Ge). Due to the etch contrast between the intermediate sacrificial layer and the channel and exfoliation layers, the intermediate sacrificial layer includes SiGe with a high concentration of Ge. However, with such a high concentration of Ge in the intermediate sacrificial layer, the superlattice relaxes, reducing strain and mobility, thereby causing degradation of transistor performance due to reduced drive current.

[0006] Thus, there is a need for semiconductor devices, particularly CFETs, having fully strained superlattice structures with defect-free or substantially defect-free channel layers and exfoliation layers with reduced selective removal rates, and methods for fabricating such devices. Summary of the Invention

[0007] One or more embodiments of the present disclosure relate to a semiconductor device. In one or more embodiments, the semiconductor device includes a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure includes a first horizontal gate-all-around (hGAA) structure on the substrate, a sacrificial layer on an upper surface of the first hGAA structure, the sacrificial layer including silicon germanium (SiGe) having a germanium content in the range of greater than 0% to 50% on an atomic basis, and a second horizontal gate-all-around (hGAA) structure on an upper surface of the sacrificial layer. Each of the first hGAA and the second hGAA includes alternating layers of nanosheet channel layers and nanosheet release layers. The nanosheet channel layer includes silicon (Si), and the nanosheet release layer includes doped silicon germanium (SiGe).

[0008] Additional embodiments of the present disclosure relate to a method for forming a semiconductor device. In one or more embodiments, the method for forming a semiconductor device includes forming a vertically stacked superlattice structure on a substrate by forming a first horizontal gate-all-around (hGAA) structure on the substrate, forming a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in the range of greater than 0% to 50% on an atomic basis, and forming a second horizontal gate-all-around (hGAA) structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprises alternating layers of nanosheet channel layers and nanosheet release layers. The nanosheet channel layers comprise silicon (Si) and the nanosheet release layers comprise doped silicon germanium (SiGe).

[0009] In order to allow the above-described features of the present disclosure to be understood in detail, a more detailed description of the disclosure briefly summarized above can be made with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only illustrate typical embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, since the present disclosure may admit of other equally effective embodiments. The embodiments described herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like references indicate like elements. [Brief description of the drawings]

[0010] [Figure 1] 1 is a process flow diagram of a method of forming a semiconductor device according to one or more embodiments. [Diagram 2] FIG. 1 illustrates a semiconductor structure according to one or more embodiments. [Diagram 3] FIG. 1 illustrates a semiconductor structure according to one or more embodiments. [Figure 4] FIG. 2 illustrates a vertically stacked superlattice structure according to one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Before describing certain example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0012] The term "about" as used herein means approximately or nearly, and in the context of a stated numerical value or range, refers to a variation of no more than ±15% of the numerical value. For example, values ​​that differ by ±14%, ±10%, ±5%, ±2%, or ±1% would meet the definition of about.

[0013] The term "substrate" or "wafer" as used herein and in the appended claims refers to a surface or a portion of a surface on which a process acts. Those skilled in the art will also understand that unless the context indicates otherwise, a reference to a substrate may refer to only a portion of the substrate. In addition, a reference to depositing on a substrate can refer to both a bare substrate and a substrate on which one or more films or features have been deposited or formed.

[0014] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film treatment steps may further be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015] The term "on" indicates that there is direct contact between the elements. The term "directly on" indicates that there is direct contact between the elements, with no intervening elements.

[0016] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0017] "Epitaxy" is a process in which a deposited film is forced into a high degree of crystallographic alignment with the substrate. Epitaxial growth is loosely defined as the condensation of gaseous precursors to form a film on a substrate. Liquid precursors can also be used. Vapor precursors can be obtained by chemical vapor deposition (CVD) and laser ablation. Currently, several epitaxy techniques are available, such as molecular beam epitaxy (MBE), epitaxial CVD, or atomic layer epitaxy (ALE).

[0018] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors are formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is positioned above the channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0019] The term "field effect transistor" or "FET" as used herein refers to a transistor that uses an electric field to control the electrical behavior of the device. A field effect transistor is a voltage-controlled device whose current carrying capability is changed by applying an electric field. Field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, which is generated by the voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), where carriers enter the channel, the drain (D), where carriers exit the channel, and the gate (G), which is the terminal that modulates the channel conductivity. Conventionally, the current entering the channel at the source (S) is called IS, and the current entering the channel at the drain (D) is called ID. The drain-source voltage is called VDS. The current entering the channel at the drain (i.e., ID) can be controlled by applying a voltage to the gate (G).

[0020] A metal oxide semiconductor field effect transistor (MOSFET) is a type of field effect transistor (FET) used in integrated circuits and high speed switching applications. A MOSFET has an insulated gate, the voltage across which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge concentration by metal oxide semiconductor (MOS) capacitance between a body electrode and a gate electrode that is placed above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each connected to an individual highly doped region separated by a body region. These regions can be either p-type or n-type, but both of these regions are the same type, opposite the type of the body region. The source and drain (unlike the body) are highly doped as indicated by a "+" sign after the type of doping.

[0021] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is a p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is an n-type substrate region. The source is so named because it is the source of charge carriers (electrons in n-channel and holes in p-channel) that flow through the channel; similarly, the drain is where the charge carriers exit the channel.

[0022] An nMOS FET consists of an n-type source and drain, and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are repelled away from the gate. This allows an n-type channel to form between the source and drain, and current is carried by electrons from the source to the drain through the induced n-type channel. Logic gates and other digital devices realized using NMOS are said to have NMOS logic. NMOS has three modes of operation called cutoff, triode, and saturation. Circuits with NMOS logic gates waste static power when the circuit is idle because DC current flows through the logic gate when the output is low.

[0023] A pMOS FET consists of a p-type source and drain and an n-type substrate. When a positive voltage is applied between the source and gate (and a negative voltage between the gate and source), a p-type channel of opposite polarity is formed between the source and drain. Current is carried by holes from the source to the drain through the induced p-type channel. When the voltage on the gate is high, the PMOS does not conduct, but when the voltage on the gate is low, the PMOS conducts. Logic gates and other digital devices realized using PMOS are said to have PMOS logic. PMOS technology is low cost and has good noise immunity.

[0024] In NMOS, the carriers are electrons while in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS conducts while PMOS does not. Furthermore, when a low voltage is applied to the gate, NMOS does not conduct and PMOS conducts. NMOS is considered faster than PMOS because the carriers in NMOS, which are electrons, move twice as fast as the holes, which are the carriers in PMOS. However, PMOS devices are less susceptible to noise than NMOS devices. Furthermore, NMOS ICs are smaller than PMOS ICs (giving the same functionality) because NMOS can provide half the impedance provided by PMOS (having the same geometry and operating conditions).

[0025] The term "Fin Field Effect Transistor (FinFET)" as used herein refers to a MOSFET transistor built on a substrate where the gate is located on two, three, or four sides of the channel or wrapped around the channel forming a double-gate structure. FinFET devices are given the collective name FinFET because the source / drain regions form "fins" on the substrate. FinFET devices have fast switching times and high current densities.

[0026] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device, e.g., a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor can include a nanowire or nanoslab or nanosheet, a bar-shaped channel, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has multiple horizontal nanowires or horizontal bars spaced vertically apart, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0027] As used herein, the term "complementary field effect transistor (CFET)" refers to a transistor that includes an NMOS FET device and a PMOS FET device stacked on top of each other. Each of the NMOS FET and PMOS FET devices that form a CFET is a GAA transistor or an hGAA transistor.

[0028] As used herein, the term "nanowire" refers to a wire that is sized to measure 10 nanometers (10 -9 Nanowires refer to nanostructures with diameters on the order of 1000 to 1500 nm (m). Nanowires may also be defined as having a length to width ratio of greater than 1000. Alternatively, nanowires may be defined as structures with a thickness or diameter constrained to tens of nanometers or less and an unconstrained length. Nanowires are used in transistors and some laser applications, and in one or more embodiments are fabricated from semiconducting, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to two-dimensional nanostructures with thicknesses on the scale of about 0.1 nm to about 1000 nm, 0.5 nm to 500 nm, 0.5 nm to 100 nm, 1 nm to 500 nm, 1 nm to 100 nm, or 1 nm to 50 nm.

[0029] Without being bound by theory, it is believed that relaxation of the vertically stacked superlattice structure containing one or more hGAAs induces defects in the nanosheet channel layer within the structure. The embodiments of the present disclosure advantageously provide a semiconductor device including a fully strained vertically stacked superlattice structure having a nanosheet channel layer that is free or substantially free of defects. In some embodiments, the presence of defects in the nanosheet channel layer is determined by a reciprocal space mapping (RSM) method. Without being bound by theory, the RSM method is an X-ray diffraction method that collects diffraction data of the vertically stacked superlattice structure in which the presence of defects may be observed. As used herein, the term "substantially free" means that the nanosheet channel layer is substantially free of defects as determined by the reciprocal space mapping (RSM) method.

[0030] A three-color selectivity of >10:1 is required to remove the sacrificial layer in a CFET superlattice without etching the nanosheet exfoliation layer. In a typical patterned wafer, the SiGe to Si selectivity is very high, meeting the >10:1 requirement. However, the selectivity is very low for SiGe with low germanium content (i.e., 15-20% on an atomic basis) versus high germanium content (i.e., greater than 30% on an atomic basis), not meeting the >10:1 requirement. Without being bound to any particular theory of operation, it is believed that doping the SiGe exfoliation layer with a dopant, e.g., carbon (C), slows the etch rate of the SiGe and thus enhances the differential etch rate of the sacrificial layer from undoped SiGe. Thus, one or more embodiments of the present disclosure advantageously provide differentiation of the SiGe layers (i.e., the sacrificial layer and the nanosheet exfoliation layer) from each other and from the channel layer during etching.

[0031] In one or more embodiments, the release layer is advantageously doped with carbon (C) to improve strain and mobility by reducing relaxation. At the same time, doping the release layer with carbon (C) reduces the etching rate of the release layer compared to the etching rate of the sacrificial layer. In other words, doping the release layer with carbon (C) advantageously increases the etching rate of the intermediate sacrificial layer, facilitating easier removal without damage to the release layer or the channel layer.

[0032] Embodiments of the present disclosure are illustrated by diagrams illustrating devices (e.g., transistors) and processes for forming the transistors according to one or more embodiments of the present disclosure. The processes illustrated are merely exemplary possible uses of the disclosed processes, and one of ordinary skill in the art will recognize that the disclosed processes are not limited to the applications illustrated.

[0033] FIG. 1 illustrates a process flow diagram of a method 100 of fabricating a monolithic CFET device according to one or more embodiments of the present disclosure. More specifically, FIG. 1 illustrates a process flow diagram of a method 100 of fabricating an epitaxially grown superlattice engineered substrate consisting of alternating layers of silicon (Si) and silicon germanium (SiGe) to be used to create a monolithic CFET device. In one or more embodiments, the superlattice is strained and free of crystal lattice defects, allowing for differential selective removal of two or more different compositions of SiGe. With reference to FIG. 1, the method 100 begins in operation 102 by forming a vertically stacked superlattice structure on a substrate. The vertically stacked superlattice structure on the substrate is formed in operation 104 by forming a first horizontal gate-all-around (hGAA) structure on the substrate. In operation 106, a sacrificial layer is formed on a top surface of the first hGAA structure. In operation 108, a second horizontal gate-all-around (hGAA) structure on a top surface of the sacrificial layer. In operation 110, the method 100 optionally includes selectively removing the sacrificial layer so that an intermediate isolation layer can be formed during subsequent processing.

[0034] 2-4 show cross-sectional views of a vertically stacked superlattice structure of a CFET device 200. The CFET device 200 shown in FIGS. 2-4 can be fabricated by the method 100 shown in FIG.

[0035] In one or more embodiments, the CFET device 200 includes a substrate 210 having a top surface 212. The substrate 210 can be any suitable substrate material known to one of ordinary skill in the art. In one or more embodiments, the substrate 210 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 210 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). Although several examples of materials from which substrate 210 can be formed are described herein, any material that can serve as a base upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be built falls within the spirit and scope of the present disclosure.

[0036] In one or more embodiments, the substrate 210 is a p-type substrate or an n-type substrate. The term "n-type" as used herein refers to a semiconductor created by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of the electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. The term "p-type" as used herein refers to the positive charge of the wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration that is greater than the electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers.

[0037] In one or more embodiments, the vertically stacked superlattice structure 260 includes one or more horizontal gate-all-around (hGAA) structures on the substrate 210. In some embodiments, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate-all-around (hGAA) structure 215 on the substrate 210. In some embodiments, in operation 104 of the method 100, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate-all-around (hGAA) structure 215 on the top surface 212 of the substrate 210. In some embodiments, the vertically stacked superlattice structure 260 includes a second or upper horizontal gate-all-around (hGAA) structure 255. Without being bound to any particular theory of operation, the first or lower hGAA 215 and the second or upper hGAA 255 can independently include the same structure having the same layers. In the illustrated embodiment of Figures 3 and 4, the vertically stacked superlattice structure 260 includes a first hGAA structure 215 on an upper surface 212 of the substrate 210, a sacrificial layer 240 on an upper surface 225 of the first hGAA structure 215 formed in operation 106 of method 100, and a second hGAA structure 255 on an upper surface 245 of the sacrificial layer 240 formed in operation 108 of method 100.

[0038] 2-4, in some embodiments, the first hGAA 215 and the second hGAA 255 each include alternating layers of nanosheet channel layer 230 and nanosheet release layer 220. In some embodiments, the plurality of nanosheet release layers 220 and the plurality of nanosheet channel layers 230 can include any number of lattice-matched material pairs suitable for forming a vertically stacked superlattice structure 260. In some embodiments, the first hGAA 215 and the second hGAA 255 each have between 1 and 5 pairs of alternating layers of nanosheet channel layer 230 and nanosheet release layer 220.

[0039] The nanosheet release layers 220 can have any suitable thickness. In one or more embodiments, each nanosheet release layer 220 has a thickness in the range of 5 nm to 15 nm. The nanosheet channel layers 230 can have any suitable thickness. In one or more embodiments, each nanosheet channel layer 230 has a thickness in the range of 5 nm to 15 nm.

[0040] In some embodiments, each of the nanosheet channel layers 230 independently comprises silicon (Si). In some embodiments, each of the nanosheet release layers 220 independently comprises silicon germanium (SiGe) doped with a dopant. In one or more embodiments, the nanosheet release layers 220 comprise silicon germanium (SiGe) having a germanium content in the range of greater than 0% to 30% on an atomic basis. In certain embodiments, the nanosheet release layers 220 comprise silicon germanium (SiGe) having a germanium content in the range of approximately 10% to 25% on an atomic basis.

[0041] The silicon germanium (SiGe) of the nanosheet release layer 220 can be doped with any suitable dopant, including elements having an atomic weight that is less than the atomic weight of silicon (Si). In some embodiments, the silicon germanium (SiGe) of the nanosheet release layer 220 is doped with a dopant that includes one or more of carbon (C) and boron (B). In one or more particular embodiments, the silicon germanium (SiGe) of the nanosheet release layer 220 is doped with carbon (C).

[0042] In one or more embodiments, the dopant in the nanosheet release layer 220 can have any suitable concentration. In some embodiments, the dopant has a concentration in the range of greater than 0% to 2% dopant on an atomic basis. In some embodiments, the dopant has a concentration in the range of 2% dopant on an atomic basis, including a range of 0.1% to 1.99% dopant on an atomic basis. In some embodiments, the dopant has a concentration in the range of 0.1% to 1.99%, including a range of 0.1% to 1.95%, a range of 0.1% to 1.9%, a range of 0.2% to 1.8%, a range of 0.3% to 1.7%, a range of 0.4% to 1.6%, a range of 0.5% to 1.5%, a range of 0.6% to 1.4%, a range of 0.7% to 1.3%, a range of 0.8% to 1.2%, and a range of 0.9% to 1.1% dopant on an atomic basis.

[0043] In certain embodiments, the dopant is carbon (C) and the carbon concentration ranges from greater than 0% to less than 2% carbon (C) on an atomic basis. In some embodiments, the nanosheet release layer 220 is doped with carbon (C) and the carbon (C) concentration of the nanosheet release layer 220 ranges from greater than 0% to less than 2% carbon on an atomic basis. In some embodiments, the carbon concentration of the nanosheet release layer 220 is less than 2% carbon on an atomic basis, including in the range of 0.1% to 1.99% carbon on an atomic basis. In some embodiments, the concentration of carbon in the nanosheet release layer 220 is in the range of 0.1% to 1.99%, including, on an atomic basis, the range of 0.1% to 1.95%, the range of 0.1% to 1.9%, the range of 0.2% to 1.8%, the range of 0.3% to 1.7%, the range of 0.4% to 1.6%, the range of 0.5% to 1.5%, the range of 0.6% to 1.4%, the range of 0.7% to 1.3%, the range of 0.8% to 1.2%, and the range of 0.9% to 1.1% carbon.

[0044] In another embodiment, the dopant of nanosheet release layer 220 is boron (B) and the dopant has a concentration ranging from greater than 0% to less than or equal to 2% boron (B) on an atomic basis.

[0045] In one or more embodiments, the nanosheet release layer 220 can include dopants including one or more of carbon (C) and boron (B), and the total combined dopant concentration can range from greater than 0% to less than or equal to 2%. Thus, in some embodiments, the nanosheet release layer 220 is doped with both carbon (C) and boron (B).

[0046] In one or more embodiments, it has been found that doping of the nanosheet exfoliation layers 220 with silicon germanium (SiGe) advantageously allows for control of the strain in the vertically stacked superlattice structure 260. Embodiments of the present disclosure advantageously provide a fully strained vertically stacked superlattice structure 260 in which each of the nanosheet exfoliation layers 220 comprises independently doped silicon germanium (SiGe). More specifically, embodiments of the present disclosure advantageously provide a fully strained vertically stacked superlattice structure 260 in which each of the nanosheet exfoliation layers 220 comprises independently doped silicon germanium (SiGe) with carbon (C).

[0047] In one or more embodiments, it has been surprisingly discovered that doping the silicon germanium (SiGe) of the nanosheet exfoliation layer 220 with carbon (C) reduces the strain of the vertically stacked superlattice structure 260 and allows for higher growth temperatures, thereby increasing the growth rate of forming the vertically stacked superlattice structure 260. As used herein, "increased growth rate" refers to a decrease in the time to form the layers of the vertically stacked superlattice structure 260. Stated differently, doping the silicon germanium (SiGe) of the nanosheet exfoliation layer 220 with carbon (C) increases the growth rate by at least two or at least three times at a temperature of about 600° C. compared to the growth rate at a temperature of about 560° C. Embodiments of the present disclosure advantageously provide a fully strained vertically stacked superlattice structure 260 in which each of the nanosheet exfoliation layers 220 independently comprises silicon germanium (SiGe) doped with carbon (C).

[0048] In one or more embodiments, the sacrificial layer 240 is formed between the first or lower hGAA and the second or upper hGAA. In one or more embodiments, the intermediate sacrificial layer 240 is selectively removed during subsequent processing and replaced with an intermediate dielectric isolation. The intermediate dielectric isolation layer serves to electrically isolate the source / drain regions of the lower level GAA 215 from the source / drain regions of the upper level GAA 255. In one or more embodiments, the sacrificial layer 240 comprises silicon germanium (SiGe) having a germanium content in the range of greater than 15% to 50% on an atomic basis. In certain embodiments, the nanosheet release layer 220 comprises silicon germanium (SiGe) having a germanium content in the range of approximately 10% to 30% on an atomic basis, and the sacrificial layer 240 comprises silicon germanium (SiGe) having a germanium content in the range of 20% to 40% on an atomic basis. In certain embodiments, the sacrificial layer 240 comprises silicon germanium (SiGe) having a germanium content in the range of approximately 20% to 50%, including, on an atomic basis, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, 45%, 46%, 47%, 48%, 49%, and 50%.

[0049] In one or more embodiments, the sacrificial layer 240 can have any suitable thickness. In some embodiments, the sacrificial layer 240 has a thickness in the range of 15 nm to 90 nm, including in the range of 15 nm to 80 nm, in the range of 20 nm to 75 nm, in the range of 15 nm to 60 nm, in the range of 15 nm to 50 nm, in the range of 15 nm to 75 nm, and in the range of 20 nm to 50 nm. In some embodiments, increasing the thickness of the sacrificial layer 240 to more than 40 nm improves the etch selectivity between the sacrificial layer 240 and the nanosheet release layer 220.

[0050] As will be appreciated by those skilled in the art, during subsequent processing, the sacrificial layer 240 can be removed and replaced with an intermediate separation layer. Thus, in operation 110, the method 100 optionally includes selectively removing the sacrificial layer 240. Selectively removing the sacrificial layer 240 may be performed by any suitable means known to those skilled in the art. In some embodiments, selectively removing the sacrificial layer 240 includes an etching process that removes the sacrificial layer 240 and does not remove the nanosheet release layer 220. In some embodiments, the etching process includes one or more of a wet etching process or a dry etching process. In some embodiments, the etching process is a directional etch.

[0051] Each of the nanosheet release layer 220, the nanosheet channel layer 230, and the sacrificial layer 240 in the vertically stacked superlattice structure 260 has its own selective removal rate. Without being bound by theory, it is believed that a high germanium content (e.g., greater than 30% germanium on an atomic basis) of the sacrificial layer 240 increases the selective removal rate in the vertically stacked superlattice structure, and doping the SiGe of the nanosheet release layer 220 with carbon reduces the etch rate of the nanosheet release layer, thereby providing a selectivity of >10:1 between the sacrificial layer 240 and the nanosheet release layer 220. In one or more embodiments, increasing the thickness of the sacrificial layer 240 to a thickness of greater than 40 nm provides an increased selectivity of greater than 15:1 between the sacrificial layer 240 and the nanosheet release layer 220.

[0052] In one or more embodiments, it has been found that advantageously doping the silicon germanium (SiGe) of the nanosheet release layer 220 with a dopant (e.g., carbon (C)) having a dopant concentration in the range of more than 0% to 2% dopant on an atomic basis allows differentiation of the nanosheet release layer 220, the nanosheet channel layer 230, and the sacrificial layer 240 in the vertically stacked superlattice structure 260. In other words, doping the silicon germanium (SiGe) of the nanosheet release layer 220 with carbon (C) advantageously reduces the selective removal rate of each nanosheet release layer in the vertically stacked superlattice structure 260. The embodiments of the present disclosure advantageously provide a method of selectively removing the sacrificial layer while reducing the selective removal rate of the nanosheet release layer without damaging the nanosheet release layer and the nanosheet channel layer in one or more of the first hGAA 215 or the second hGAA 255.

[0053] In one or more embodiments, it has been found that the nanosheet release layer 220 doped with carbon (C) advantageously has a reduced etch rate compared to a nanosheet release layer that is not doped with carbon (C). In some embodiments, the etch rate is reduced by at least a factor of two.

[0054] Spatially relative terms such as "below," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures for ease of description. It should be understood that the spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in a figure is turned over, an element described as "below" or "below" another element or feature would be oriented "above" the other element or feature. Thus, an exemplary term such as "below" can encompass both an upward and downward orientation. The device may be otherwise oriented (rotated 90 degrees or to other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0055] The use of "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (particularly in the claims below) should be construed to encompass both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The recitation of a range of values ​​herein is merely intended to serve as a shorthand method of individually referring to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated herein as if it were individually recited herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise claimed. No language herein should be construed as indicating that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0056] References throughout this specification to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in one embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0057] Although the disclosure of this specification has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various changes and modifications can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to cover changes and modifications that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming a first horizontal gate-all-around (hGAA) structure on the substrate to form a vertically stacked superlattice structure on the substrate; forming a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in the range of greater than 0% to 50% on an atomic basis; forming a second horizontal gate-all-around (hGAA) structure on a top surface of the sacrificial layer; forming the first hGAA structure and the second hGAA structure, each of which comprises alternating layers of nanosheet channel layers and nanosheet exfoliation layers, the nanosheet channel layers comprising silicon (Si) and each of the nanosheet exfoliation layers independently comprising silicon germanium (SiGe) doped with a dopant; A method comprising:

2. The method of claim 1 , wherein the sacrificial layer comprises silicon germanium (SiGe) having a germanium content in the range of 20% to 50% on an atomic basis.

3. The method of claim 2 , wherein the nanosheet release layer comprises silicon germanium (SiGe) having a germanium content ranging from 10% to 30% on an atomic basis.

4. The method of claim 1 , wherein the sacrificial layer has a thickness in the range of 15 nm to 90 nm.

5. 2. The method of claim 1, wherein each of the first hGAA structure and the second hGAA structure has between 1 and 5 pairs of alternating nanosheet channel layers and nanosheet release layers.

6. The method of claim 1 , wherein the dopant comprises one or more of carbon (C) and boron (B).

7. The method of claim 6, wherein the silicon germanium (SiGe) of the nanosheet release layer is doped with carbon (C).

8. The method of claim 6, wherein the dopant has a concentration ranging from greater than 0% to less than or equal to 2% dopant on an atomic basis.

9. 10. The method of claim 1, wherein the nanosheet release layer has a reduced etch rate compared to the sacrificial layer.

10. The method of claim 9 , wherein the etch rate is reduced by at least a factor of two.

11. 8. The method of claim 7, wherein doping the silicon germanium (SiGe) of the nanosheet exfoliation layer with carbon (C) reduces strain in the vertically stacked superlattice structure, allowing for higher growth temperatures and increased growth rates.

12. 2. The method of claim 1, wherein the vertically stacked superlattice structure is fully strained and each nanosheet channel layer is substantially defect-free.

13. 4. The method of claim 3, wherein the sacrificial layer comprises silicon germanium (SiGe) having a germanium content in the range of greater than 30% to 50% on an atomic basis, and the nanosheet release layer comprises silicon germanium (SiGe) having a concentration in the range of greater than 15% to 20% on an atomic basis doped with carbon having a carbon concentration in the range of greater than 0% to 2% or less on an atomic basis.

14. The method of claim 1 , further comprising selectively removing the sacrificial layer.

15. A vertically stacked superlattice structure on a substrate, comprising: a first horizontal gate-all-around (hGAA) structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in the range of greater than 0% to 50% on an atomic basis; a second horizontal gate-all-around (hGAA) structure on a top surface of the sacrificial layer; a second horizontal gate-all-around (hGAA) structure, each of the first hGAA structure and the second hGAA structure comprising alternating layers of nanosheet channel layers and nanosheet exfoliation layers, the nanosheet channel layers comprising silicon (Si) and the nanosheet exfoliation layers comprising silicon germanium (SiGe) doped with a dopant.

2. A semiconductor device comprising:

16. 16. The semiconductor device of claim 15, wherein the dopant comprises one or more of carbon (C) and boron (B).

17. 17. The semiconductor device of claim 16, wherein the silicon germanium (SiGe) of the nanosheet exfoliation layer is doped with carbon (C).

18. 17. The semiconductor device of claim 16, wherein the dopant has a concentration ranging from greater than 0% to less than or equal to 2% dopant on an atomic basis.

19. 16. The semiconductor device of claim 15, wherein the sacrificial layer comprises silicon germanium (SiGe) having a germanium content in the range of 20% to 50% on an atomic basis, and the nanosheet release layer comprises silicon germanium (SiGe) having a concentration in the range of 10% to 30% on an atomic basis doped with carbon having a carbon concentration in the range of greater than 0% to 2% or less on an atomic basis.

20. 20. The semiconductor device of claim 17, wherein the silicon germanium (SiGe) of the nanosheet exfoliation layer doped with carbon (C) reduces strain in the vertically stacked superlattice structure, allowing for higher growth temperatures and increased growth rates.

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